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7a3f1944 FB |
1 | /* |
2 | SPARC translation | |
3 | ||
4 | Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at> | |
3475187d | 5 | Copyright (C) 2003-2005 Fabrice Bellard |
7a3f1944 FB |
6 | |
7 | This library is free software; you can redistribute it and/or | |
8 | modify it under the terms of the GNU Lesser General Public | |
9 | License as published by the Free Software Foundation; either | |
10 | version 2 of the License, or (at your option) any later version. | |
11 | ||
12 | This library is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | Lesser General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU Lesser General Public | |
18 | License along with this library; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
22 | /* | |
7a3f1944 FB |
23 | TODO-list: |
24 | ||
3475187d | 25 | Rest of V9 instructions, VIS instructions |
bd497938 | 26 | NPC/PC static optimisations (use JUMP_TB when possible) |
7a3f1944 | 27 | Optimize synthetic instructions |
3475187d | 28 | 128-bit float |
bd497938 | 29 | */ |
7a3f1944 FB |
30 | |
31 | #include <stdarg.h> | |
32 | #include <stdlib.h> | |
33 | #include <stdio.h> | |
34 | #include <string.h> | |
35 | #include <inttypes.h> | |
36 | ||
37 | #include "cpu.h" | |
38 | #include "exec-all.h" | |
39 | #include "disas.h" | |
40 | ||
41 | #define DEBUG_DISAS | |
42 | ||
72cbca10 FB |
43 | #define DYNAMIC_PC 1 /* dynamic pc value */ |
44 | #define JUMP_PC 2 /* dynamic pc value which takes only two values | |
45 | according to jump_pc[T2] */ | |
46 | ||
7a3f1944 | 47 | typedef struct DisasContext { |
72cbca10 FB |
48 | target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */ |
49 | target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */ | |
50 | target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */ | |
cf495bcf | 51 | int is_br; |
e8af50a3 | 52 | int mem_idx; |
a80dde08 | 53 | int fpu_enabled; |
cf495bcf | 54 | struct TranslationBlock *tb; |
7a3f1944 FB |
55 | } DisasContext; |
56 | ||
62724a37 BS |
57 | struct sparc_def_t { |
58 | const unsigned char *name; | |
59 | target_ulong iu_version; | |
60 | uint32_t fpu_version; | |
61 | uint32_t mmu_version; | |
62 | }; | |
63 | ||
7a3f1944 FB |
64 | static uint16_t *gen_opc_ptr; |
65 | static uint32_t *gen_opparam_ptr; | |
66 | extern FILE *logfile; | |
67 | extern int loglevel; | |
68 | ||
69 | enum { | |
70 | #define DEF(s,n,copy_size) INDEX_op_ ## s, | |
71 | #include "opc.h" | |
72 | #undef DEF | |
cf495bcf | 73 | NB_OPS |
7a3f1944 FB |
74 | }; |
75 | ||
76 | #include "gen-op.h" | |
77 | ||
3475187d | 78 | // This function uses non-native bit order |
7a3f1944 FB |
79 | #define GET_FIELD(X, FROM, TO) \ |
80 | ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1)) | |
81 | ||
3475187d FB |
82 | // This function uses the order in the manuals, i.e. bit 0 is 2^0 |
83 | #define GET_FIELD_SP(X, FROM, TO) \ | |
84 | GET_FIELD(X, 31 - (TO), 31 - (FROM)) | |
85 | ||
86 | #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1) | |
46d38ba8 | 87 | #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1)) |
3475187d FB |
88 | |
89 | #ifdef TARGET_SPARC64 | |
90 | #define DFPREG(r) (((r & 1) << 6) | (r & 0x1e)) | |
91 | #else | |
c185970a | 92 | #define DFPREG(r) (r & 0x1e) |
3475187d FB |
93 | #endif |
94 | ||
83469015 FB |
95 | #ifdef USE_DIRECT_JUMP |
96 | #define TBPARAM(x) | |
97 | #else | |
98 | #define TBPARAM(x) (long)(x) | |
99 | #endif | |
100 | ||
3475187d FB |
101 | static int sign_extend(int x, int len) |
102 | { | |
103 | len = 32 - len; | |
104 | return (x << len) >> len; | |
105 | } | |
106 | ||
7a3f1944 FB |
107 | #define IS_IMM (insn & (1<<13)) |
108 | ||
cf495bcf | 109 | static void disas_sparc_insn(DisasContext * dc); |
7a3f1944 | 110 | |
a68156d0 | 111 | static GenOpFunc * const gen_op_movl_TN_reg[2][32] = { |
cf495bcf FB |
112 | { |
113 | gen_op_movl_g0_T0, | |
114 | gen_op_movl_g1_T0, | |
115 | gen_op_movl_g2_T0, | |
116 | gen_op_movl_g3_T0, | |
117 | gen_op_movl_g4_T0, | |
118 | gen_op_movl_g5_T0, | |
119 | gen_op_movl_g6_T0, | |
120 | gen_op_movl_g7_T0, | |
121 | gen_op_movl_o0_T0, | |
122 | gen_op_movl_o1_T0, | |
123 | gen_op_movl_o2_T0, | |
124 | gen_op_movl_o3_T0, | |
125 | gen_op_movl_o4_T0, | |
126 | gen_op_movl_o5_T0, | |
127 | gen_op_movl_o6_T0, | |
128 | gen_op_movl_o7_T0, | |
129 | gen_op_movl_l0_T0, | |
130 | gen_op_movl_l1_T0, | |
131 | gen_op_movl_l2_T0, | |
132 | gen_op_movl_l3_T0, | |
133 | gen_op_movl_l4_T0, | |
134 | gen_op_movl_l5_T0, | |
135 | gen_op_movl_l6_T0, | |
136 | gen_op_movl_l7_T0, | |
137 | gen_op_movl_i0_T0, | |
138 | gen_op_movl_i1_T0, | |
139 | gen_op_movl_i2_T0, | |
140 | gen_op_movl_i3_T0, | |
141 | gen_op_movl_i4_T0, | |
142 | gen_op_movl_i5_T0, | |
143 | gen_op_movl_i6_T0, | |
144 | gen_op_movl_i7_T0, | |
145 | }, | |
146 | { | |
147 | gen_op_movl_g0_T1, | |
148 | gen_op_movl_g1_T1, | |
149 | gen_op_movl_g2_T1, | |
150 | gen_op_movl_g3_T1, | |
151 | gen_op_movl_g4_T1, | |
152 | gen_op_movl_g5_T1, | |
153 | gen_op_movl_g6_T1, | |
154 | gen_op_movl_g7_T1, | |
155 | gen_op_movl_o0_T1, | |
156 | gen_op_movl_o1_T1, | |
157 | gen_op_movl_o2_T1, | |
158 | gen_op_movl_o3_T1, | |
159 | gen_op_movl_o4_T1, | |
160 | gen_op_movl_o5_T1, | |
161 | gen_op_movl_o6_T1, | |
162 | gen_op_movl_o7_T1, | |
163 | gen_op_movl_l0_T1, | |
164 | gen_op_movl_l1_T1, | |
165 | gen_op_movl_l2_T1, | |
166 | gen_op_movl_l3_T1, | |
167 | gen_op_movl_l4_T1, | |
168 | gen_op_movl_l5_T1, | |
169 | gen_op_movl_l6_T1, | |
170 | gen_op_movl_l7_T1, | |
171 | gen_op_movl_i0_T1, | |
172 | gen_op_movl_i1_T1, | |
173 | gen_op_movl_i2_T1, | |
174 | gen_op_movl_i3_T1, | |
175 | gen_op_movl_i4_T1, | |
176 | gen_op_movl_i5_T1, | |
177 | gen_op_movl_i6_T1, | |
178 | gen_op_movl_i7_T1, | |
179 | } | |
7a3f1944 FB |
180 | }; |
181 | ||
a68156d0 | 182 | static GenOpFunc * const gen_op_movl_reg_TN[3][32] = { |
cf495bcf FB |
183 | { |
184 | gen_op_movl_T0_g0, | |
185 | gen_op_movl_T0_g1, | |
186 | gen_op_movl_T0_g2, | |
187 | gen_op_movl_T0_g3, | |
188 | gen_op_movl_T0_g4, | |
189 | gen_op_movl_T0_g5, | |
190 | gen_op_movl_T0_g6, | |
191 | gen_op_movl_T0_g7, | |
192 | gen_op_movl_T0_o0, | |
193 | gen_op_movl_T0_o1, | |
194 | gen_op_movl_T0_o2, | |
195 | gen_op_movl_T0_o3, | |
196 | gen_op_movl_T0_o4, | |
197 | gen_op_movl_T0_o5, | |
198 | gen_op_movl_T0_o6, | |
199 | gen_op_movl_T0_o7, | |
200 | gen_op_movl_T0_l0, | |
201 | gen_op_movl_T0_l1, | |
202 | gen_op_movl_T0_l2, | |
203 | gen_op_movl_T0_l3, | |
204 | gen_op_movl_T0_l4, | |
205 | gen_op_movl_T0_l5, | |
206 | gen_op_movl_T0_l6, | |
207 | gen_op_movl_T0_l7, | |
208 | gen_op_movl_T0_i0, | |
209 | gen_op_movl_T0_i1, | |
210 | gen_op_movl_T0_i2, | |
211 | gen_op_movl_T0_i3, | |
212 | gen_op_movl_T0_i4, | |
213 | gen_op_movl_T0_i5, | |
214 | gen_op_movl_T0_i6, | |
215 | gen_op_movl_T0_i7, | |
216 | }, | |
217 | { | |
218 | gen_op_movl_T1_g0, | |
219 | gen_op_movl_T1_g1, | |
220 | gen_op_movl_T1_g2, | |
221 | gen_op_movl_T1_g3, | |
222 | gen_op_movl_T1_g4, | |
223 | gen_op_movl_T1_g5, | |
224 | gen_op_movl_T1_g6, | |
225 | gen_op_movl_T1_g7, | |
226 | gen_op_movl_T1_o0, | |
227 | gen_op_movl_T1_o1, | |
228 | gen_op_movl_T1_o2, | |
229 | gen_op_movl_T1_o3, | |
230 | gen_op_movl_T1_o4, | |
231 | gen_op_movl_T1_o5, | |
232 | gen_op_movl_T1_o6, | |
233 | gen_op_movl_T1_o7, | |
234 | gen_op_movl_T1_l0, | |
235 | gen_op_movl_T1_l1, | |
236 | gen_op_movl_T1_l2, | |
237 | gen_op_movl_T1_l3, | |
238 | gen_op_movl_T1_l4, | |
239 | gen_op_movl_T1_l5, | |
240 | gen_op_movl_T1_l6, | |
241 | gen_op_movl_T1_l7, | |
242 | gen_op_movl_T1_i0, | |
243 | gen_op_movl_T1_i1, | |
244 | gen_op_movl_T1_i2, | |
245 | gen_op_movl_T1_i3, | |
246 | gen_op_movl_T1_i4, | |
247 | gen_op_movl_T1_i5, | |
248 | gen_op_movl_T1_i6, | |
249 | gen_op_movl_T1_i7, | |
250 | }, | |
251 | { | |
252 | gen_op_movl_T2_g0, | |
253 | gen_op_movl_T2_g1, | |
254 | gen_op_movl_T2_g2, | |
255 | gen_op_movl_T2_g3, | |
256 | gen_op_movl_T2_g4, | |
257 | gen_op_movl_T2_g5, | |
258 | gen_op_movl_T2_g6, | |
259 | gen_op_movl_T2_g7, | |
260 | gen_op_movl_T2_o0, | |
261 | gen_op_movl_T2_o1, | |
262 | gen_op_movl_T2_o2, | |
263 | gen_op_movl_T2_o3, | |
264 | gen_op_movl_T2_o4, | |
265 | gen_op_movl_T2_o5, | |
266 | gen_op_movl_T2_o6, | |
267 | gen_op_movl_T2_o7, | |
268 | gen_op_movl_T2_l0, | |
269 | gen_op_movl_T2_l1, | |
270 | gen_op_movl_T2_l2, | |
271 | gen_op_movl_T2_l3, | |
272 | gen_op_movl_T2_l4, | |
273 | gen_op_movl_T2_l5, | |
274 | gen_op_movl_T2_l6, | |
275 | gen_op_movl_T2_l7, | |
276 | gen_op_movl_T2_i0, | |
277 | gen_op_movl_T2_i1, | |
278 | gen_op_movl_T2_i2, | |
279 | gen_op_movl_T2_i3, | |
280 | gen_op_movl_T2_i4, | |
281 | gen_op_movl_T2_i5, | |
282 | gen_op_movl_T2_i6, | |
283 | gen_op_movl_T2_i7, | |
284 | } | |
7a3f1944 FB |
285 | }; |
286 | ||
a68156d0 | 287 | static GenOpFunc1 * const gen_op_movl_TN_im[3] = { |
cf495bcf FB |
288 | gen_op_movl_T0_im, |
289 | gen_op_movl_T1_im, | |
290 | gen_op_movl_T2_im | |
7a3f1944 FB |
291 | }; |
292 | ||
3475187d FB |
293 | // Sign extending version |
294 | static GenOpFunc1 * const gen_op_movl_TN_sim[3] = { | |
295 | gen_op_movl_T0_sim, | |
296 | gen_op_movl_T1_sim, | |
297 | gen_op_movl_T2_sim | |
298 | }; | |
299 | ||
300 | #ifdef TARGET_SPARC64 | |
301 | #define GEN32(func, NAME) \ | |
a68156d0 | 302 | static GenOpFunc * const NAME ## _table [64] = { \ |
3475187d FB |
303 | NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \ |
304 | NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \ | |
305 | NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \ | |
306 | NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \ | |
307 | NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \ | |
308 | NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \ | |
309 | NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \ | |
310 | NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \ | |
311 | NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0, \ | |
312 | NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0, \ | |
313 | NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0, \ | |
314 | NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0, \ | |
315 | }; \ | |
316 | static inline void func(int n) \ | |
317 | { \ | |
318 | NAME ## _table[n](); \ | |
319 | } | |
320 | #else | |
e8af50a3 | 321 | #define GEN32(func, NAME) \ |
a68156d0 | 322 | static GenOpFunc *const NAME ## _table [32] = { \ |
e8af50a3 FB |
323 | NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \ |
324 | NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \ | |
325 | NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \ | |
326 | NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \ | |
327 | NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \ | |
328 | NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \ | |
329 | NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \ | |
330 | NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \ | |
331 | }; \ | |
332 | static inline void func(int n) \ | |
333 | { \ | |
334 | NAME ## _table[n](); \ | |
335 | } | |
3475187d | 336 | #endif |
e8af50a3 FB |
337 | |
338 | /* floating point registers moves */ | |
339 | GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf); | |
340 | GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf); | |
e8af50a3 FB |
341 | GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf); |
342 | GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf); | |
e8af50a3 FB |
343 | |
344 | GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf); | |
345 | GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf); | |
e8af50a3 FB |
346 | GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf); |
347 | GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf); | |
e8af50a3 | 348 | |
3475187d FB |
349 | #ifdef TARGET_SPARC64 |
350 | // 'a' versions allowed to user depending on asi | |
351 | #if defined(CONFIG_USER_ONLY) | |
352 | #define supervisor(dc) 0 | |
e9ebed4d | 353 | #define hypervisor(dc) 0 |
3475187d FB |
354 | #define gen_op_ldst(name) gen_op_##name##_raw() |
355 | #define OP_LD_TABLE(width) \ | |
356 | static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \ | |
357 | { \ | |
358 | int asi, offset; \ | |
359 | \ | |
360 | if (IS_IMM) { \ | |
361 | offset = GET_FIELD(insn, 25, 31); \ | |
362 | if (is_ld) \ | |
363 | gen_op_ld_asi_reg(offset, size, sign); \ | |
364 | else \ | |
365 | gen_op_st_asi_reg(offset, size, sign); \ | |
366 | return; \ | |
367 | } \ | |
368 | asi = GET_FIELD(insn, 19, 26); \ | |
369 | switch (asi) { \ | |
370 | case 0x80: /* Primary address space */ \ | |
371 | gen_op_##width##_raw(); \ | |
372 | break; \ | |
725cb90b FB |
373 | case 0x82: /* Primary address space, non-faulting load */ \ |
374 | gen_op_##width##_raw(); \ | |
375 | break; \ | |
3475187d FB |
376 | default: \ |
377 | break; \ | |
378 | } \ | |
379 | } | |
380 | ||
381 | #else | |
382 | #define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])() | |
383 | #define OP_LD_TABLE(width) \ | |
a68156d0 | 384 | static GenOpFunc * const gen_op_##width[] = { \ |
3475187d FB |
385 | &gen_op_##width##_user, \ |
386 | &gen_op_##width##_kernel, \ | |
387 | }; \ | |
388 | \ | |
389 | static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \ | |
390 | { \ | |
391 | int asi, offset; \ | |
392 | \ | |
393 | if (IS_IMM) { \ | |
394 | offset = GET_FIELD(insn, 25, 31); \ | |
395 | if (is_ld) \ | |
396 | gen_op_ld_asi_reg(offset, size, sign); \ | |
397 | else \ | |
398 | gen_op_st_asi_reg(offset, size, sign); \ | |
399 | return; \ | |
400 | } \ | |
401 | asi = GET_FIELD(insn, 19, 26); \ | |
402 | if (is_ld) \ | |
403 | gen_op_ld_asi(asi, size, sign); \ | |
404 | else \ | |
405 | gen_op_st_asi(asi, size, sign); \ | |
406 | } | |
407 | ||
408 | #define supervisor(dc) (dc->mem_idx == 1) | |
e9ebed4d | 409 | #define hypervisor(dc) (dc->mem_idx == 2) |
3475187d FB |
410 | #endif |
411 | #else | |
e8af50a3 FB |
412 | #if defined(CONFIG_USER_ONLY) |
413 | #define gen_op_ldst(name) gen_op_##name##_raw() | |
0fa85d43 | 414 | #define OP_LD_TABLE(width) |
e8af50a3 FB |
415 | #define supervisor(dc) 0 |
416 | #else | |
417 | #define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])() | |
418 | #define OP_LD_TABLE(width) \ | |
a68156d0 | 419 | static GenOpFunc * const gen_op_##width[] = { \ |
e8af50a3 FB |
420 | &gen_op_##width##_user, \ |
421 | &gen_op_##width##_kernel, \ | |
422 | }; \ | |
423 | \ | |
424 | static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \ | |
425 | { \ | |
426 | int asi; \ | |
427 | \ | |
428 | asi = GET_FIELD(insn, 19, 26); \ | |
429 | switch (asi) { \ | |
430 | case 10: /* User data access */ \ | |
431 | gen_op_##width##_user(); \ | |
432 | break; \ | |
433 | case 11: /* Supervisor data access */ \ | |
434 | gen_op_##width##_kernel(); \ | |
435 | break; \ | |
436 | case 0x20 ... 0x2f: /* MMU passthrough */ \ | |
437 | if (is_ld) \ | |
438 | gen_op_ld_asi(asi, size, sign); \ | |
439 | else \ | |
440 | gen_op_st_asi(asi, size, sign); \ | |
441 | break; \ | |
442 | default: \ | |
443 | if (is_ld) \ | |
444 | gen_op_ld_asi(asi, size, sign); \ | |
445 | else \ | |
446 | gen_op_st_asi(asi, size, sign); \ | |
447 | break; \ | |
448 | } \ | |
449 | } | |
450 | ||
451 | #define supervisor(dc) (dc->mem_idx == 1) | |
452 | #endif | |
3475187d | 453 | #endif |
e8af50a3 FB |
454 | |
455 | OP_LD_TABLE(ld); | |
456 | OP_LD_TABLE(st); | |
457 | OP_LD_TABLE(ldub); | |
458 | OP_LD_TABLE(lduh); | |
459 | OP_LD_TABLE(ldsb); | |
460 | OP_LD_TABLE(ldsh); | |
461 | OP_LD_TABLE(stb); | |
462 | OP_LD_TABLE(sth); | |
463 | OP_LD_TABLE(std); | |
464 | OP_LD_TABLE(ldstub); | |
465 | OP_LD_TABLE(swap); | |
466 | OP_LD_TABLE(ldd); | |
467 | OP_LD_TABLE(stf); | |
468 | OP_LD_TABLE(stdf); | |
469 | OP_LD_TABLE(ldf); | |
470 | OP_LD_TABLE(lddf); | |
471 | ||
3475187d | 472 | #ifdef TARGET_SPARC64 |
dc011987 | 473 | OP_LD_TABLE(lduw); |
3475187d FB |
474 | OP_LD_TABLE(ldsw); |
475 | OP_LD_TABLE(ldx); | |
476 | OP_LD_TABLE(stx); | |
477 | OP_LD_TABLE(cas); | |
478 | OP_LD_TABLE(casx); | |
479 | #endif | |
480 | ||
481 | static inline void gen_movl_imm_TN(int reg, uint32_t imm) | |
7a3f1944 | 482 | { |
83469015 | 483 | gen_op_movl_TN_im[reg](imm); |
7a3f1944 FB |
484 | } |
485 | ||
3475187d | 486 | static inline void gen_movl_imm_T1(uint32_t val) |
7a3f1944 | 487 | { |
cf495bcf | 488 | gen_movl_imm_TN(1, val); |
7a3f1944 FB |
489 | } |
490 | ||
3475187d | 491 | static inline void gen_movl_imm_T0(uint32_t val) |
7a3f1944 | 492 | { |
cf495bcf | 493 | gen_movl_imm_TN(0, val); |
7a3f1944 FB |
494 | } |
495 | ||
3475187d FB |
496 | static inline void gen_movl_simm_TN(int reg, int32_t imm) |
497 | { | |
498 | gen_op_movl_TN_sim[reg](imm); | |
499 | } | |
500 | ||
501 | static inline void gen_movl_simm_T1(int32_t val) | |
502 | { | |
503 | gen_movl_simm_TN(1, val); | |
504 | } | |
505 | ||
506 | static inline void gen_movl_simm_T0(int32_t val) | |
507 | { | |
508 | gen_movl_simm_TN(0, val); | |
509 | } | |
510 | ||
cf495bcf | 511 | static inline void gen_movl_reg_TN(int reg, int t) |
7a3f1944 | 512 | { |
cf495bcf FB |
513 | if (reg) |
514 | gen_op_movl_reg_TN[t][reg] (); | |
515 | else | |
516 | gen_movl_imm_TN(t, 0); | |
7a3f1944 FB |
517 | } |
518 | ||
cf495bcf | 519 | static inline void gen_movl_reg_T0(int reg) |
7a3f1944 | 520 | { |
cf495bcf | 521 | gen_movl_reg_TN(reg, 0); |
7a3f1944 FB |
522 | } |
523 | ||
cf495bcf | 524 | static inline void gen_movl_reg_T1(int reg) |
7a3f1944 | 525 | { |
cf495bcf | 526 | gen_movl_reg_TN(reg, 1); |
7a3f1944 FB |
527 | } |
528 | ||
cf495bcf | 529 | static inline void gen_movl_reg_T2(int reg) |
7a3f1944 | 530 | { |
cf495bcf | 531 | gen_movl_reg_TN(reg, 2); |
7a3f1944 FB |
532 | } |
533 | ||
cf495bcf | 534 | static inline void gen_movl_TN_reg(int reg, int t) |
7a3f1944 | 535 | { |
cf495bcf FB |
536 | if (reg) |
537 | gen_op_movl_TN_reg[t][reg] (); | |
7a3f1944 FB |
538 | } |
539 | ||
cf495bcf | 540 | static inline void gen_movl_T0_reg(int reg) |
7a3f1944 | 541 | { |
cf495bcf | 542 | gen_movl_TN_reg(reg, 0); |
7a3f1944 FB |
543 | } |
544 | ||
cf495bcf | 545 | static inline void gen_movl_T1_reg(int reg) |
7a3f1944 | 546 | { |
cf495bcf | 547 | gen_movl_TN_reg(reg, 1); |
7a3f1944 FB |
548 | } |
549 | ||
3475187d FB |
550 | static inline void gen_jmp_im(target_ulong pc) |
551 | { | |
552 | #ifdef TARGET_SPARC64 | |
553 | if (pc == (uint32_t)pc) { | |
554 | gen_op_jmp_im(pc); | |
555 | } else { | |
556 | gen_op_jmp_im64(pc >> 32, pc); | |
557 | } | |
558 | #else | |
559 | gen_op_jmp_im(pc); | |
560 | #endif | |
561 | } | |
562 | ||
563 | static inline void gen_movl_npc_im(target_ulong npc) | |
564 | { | |
565 | #ifdef TARGET_SPARC64 | |
566 | if (npc == (uint32_t)npc) { | |
567 | gen_op_movl_npc_im(npc); | |
568 | } else { | |
569 | gen_op_movq_npc_im64(npc >> 32, npc); | |
570 | } | |
571 | #else | |
572 | gen_op_movl_npc_im(npc); | |
573 | #endif | |
574 | } | |
575 | ||
6e256c93 FB |
576 | static inline void gen_goto_tb(DisasContext *s, int tb_num, |
577 | target_ulong pc, target_ulong npc) | |
578 | { | |
579 | TranslationBlock *tb; | |
580 | ||
581 | tb = s->tb; | |
582 | if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) && | |
583 | (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) { | |
584 | /* jump to same page: we can use a direct jump */ | |
585 | if (tb_num == 0) | |
586 | gen_op_goto_tb0(TBPARAM(tb)); | |
587 | else | |
588 | gen_op_goto_tb1(TBPARAM(tb)); | |
589 | gen_jmp_im(pc); | |
590 | gen_movl_npc_im(npc); | |
591 | gen_op_movl_T0_im((long)tb + tb_num); | |
592 | gen_op_exit_tb(); | |
593 | } else { | |
594 | /* jump to another page: currently not optimized */ | |
595 | gen_jmp_im(pc); | |
596 | gen_movl_npc_im(npc); | |
597 | gen_op_movl_T0_0(); | |
598 | gen_op_exit_tb(); | |
599 | } | |
600 | } | |
601 | ||
46525e1f BS |
602 | static inline void gen_branch2(DisasContext *dc, target_ulong pc1, |
603 | target_ulong pc2) | |
83469015 FB |
604 | { |
605 | int l1; | |
606 | ||
607 | l1 = gen_new_label(); | |
608 | ||
609 | gen_op_jz_T2_label(l1); | |
610 | ||
6e256c93 | 611 | gen_goto_tb(dc, 0, pc1, pc1 + 4); |
83469015 FB |
612 | |
613 | gen_set_label(l1); | |
6e256c93 | 614 | gen_goto_tb(dc, 1, pc2, pc2 + 4); |
83469015 FB |
615 | } |
616 | ||
46525e1f BS |
617 | static inline void gen_branch_a(DisasContext *dc, target_ulong pc1, |
618 | target_ulong pc2) | |
83469015 FB |
619 | { |
620 | int l1; | |
621 | ||
622 | l1 = gen_new_label(); | |
623 | ||
624 | gen_op_jz_T2_label(l1); | |
625 | ||
6e256c93 | 626 | gen_goto_tb(dc, 0, pc2, pc1); |
83469015 FB |
627 | |
628 | gen_set_label(l1); | |
6e256c93 | 629 | gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8); |
83469015 FB |
630 | } |
631 | ||
46525e1f BS |
632 | static inline void gen_branch(DisasContext *dc, target_ulong pc, |
633 | target_ulong npc) | |
83469015 | 634 | { |
6e256c93 | 635 | gen_goto_tb(dc, 0, pc, npc); |
83469015 FB |
636 | } |
637 | ||
46525e1f | 638 | static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2) |
83469015 FB |
639 | { |
640 | int l1, l2; | |
641 | ||
642 | l1 = gen_new_label(); | |
643 | l2 = gen_new_label(); | |
644 | gen_op_jz_T2_label(l1); | |
645 | ||
646 | gen_movl_npc_im(npc1); | |
647 | gen_op_jmp_label(l2); | |
648 | ||
649 | gen_set_label(l1); | |
650 | gen_movl_npc_im(npc2); | |
651 | gen_set_label(l2); | |
652 | } | |
653 | ||
654 | /* call this function before using T2 as it may have been set for a jump */ | |
655 | static inline void flush_T2(DisasContext * dc) | |
656 | { | |
657 | if (dc->npc == JUMP_PC) { | |
46525e1f | 658 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]); |
83469015 FB |
659 | dc->npc = DYNAMIC_PC; |
660 | } | |
661 | } | |
662 | ||
72cbca10 FB |
663 | static inline void save_npc(DisasContext * dc) |
664 | { | |
665 | if (dc->npc == JUMP_PC) { | |
46525e1f | 666 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]); |
72cbca10 FB |
667 | dc->npc = DYNAMIC_PC; |
668 | } else if (dc->npc != DYNAMIC_PC) { | |
3475187d | 669 | gen_movl_npc_im(dc->npc); |
72cbca10 FB |
670 | } |
671 | } | |
672 | ||
673 | static inline void save_state(DisasContext * dc) | |
674 | { | |
3475187d | 675 | gen_jmp_im(dc->pc); |
72cbca10 FB |
676 | save_npc(dc); |
677 | } | |
678 | ||
0bee699e FB |
679 | static inline void gen_mov_pc_npc(DisasContext * dc) |
680 | { | |
681 | if (dc->npc == JUMP_PC) { | |
46525e1f | 682 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]); |
0bee699e FB |
683 | gen_op_mov_pc_npc(); |
684 | dc->pc = DYNAMIC_PC; | |
685 | } else if (dc->npc == DYNAMIC_PC) { | |
686 | gen_op_mov_pc_npc(); | |
687 | dc->pc = DYNAMIC_PC; | |
688 | } else { | |
689 | dc->pc = dc->npc; | |
690 | } | |
691 | } | |
692 | ||
3475187d FB |
693 | static GenOpFunc * const gen_cond[2][16] = { |
694 | { | |
9bad0425 | 695 | gen_op_eval_bn, |
3475187d FB |
696 | gen_op_eval_be, |
697 | gen_op_eval_ble, | |
698 | gen_op_eval_bl, | |
699 | gen_op_eval_bleu, | |
700 | gen_op_eval_bcs, | |
701 | gen_op_eval_bneg, | |
702 | gen_op_eval_bvs, | |
9bad0425 | 703 | gen_op_eval_ba, |
3475187d FB |
704 | gen_op_eval_bne, |
705 | gen_op_eval_bg, | |
706 | gen_op_eval_bge, | |
707 | gen_op_eval_bgu, | |
708 | gen_op_eval_bcc, | |
709 | gen_op_eval_bpos, | |
710 | gen_op_eval_bvc, | |
711 | }, | |
712 | { | |
713 | #ifdef TARGET_SPARC64 | |
9bad0425 | 714 | gen_op_eval_bn, |
3475187d FB |
715 | gen_op_eval_xbe, |
716 | gen_op_eval_xble, | |
717 | gen_op_eval_xbl, | |
718 | gen_op_eval_xbleu, | |
719 | gen_op_eval_xbcs, | |
720 | gen_op_eval_xbneg, | |
721 | gen_op_eval_xbvs, | |
9bad0425 | 722 | gen_op_eval_ba, |
3475187d FB |
723 | gen_op_eval_xbne, |
724 | gen_op_eval_xbg, | |
725 | gen_op_eval_xbge, | |
726 | gen_op_eval_xbgu, | |
727 | gen_op_eval_xbcc, | |
728 | gen_op_eval_xbpos, | |
729 | gen_op_eval_xbvc, | |
730 | #endif | |
731 | }, | |
732 | }; | |
733 | ||
734 | static GenOpFunc * const gen_fcond[4][16] = { | |
735 | { | |
9bad0425 | 736 | gen_op_eval_bn, |
3475187d FB |
737 | gen_op_eval_fbne, |
738 | gen_op_eval_fblg, | |
739 | gen_op_eval_fbul, | |
740 | gen_op_eval_fbl, | |
741 | gen_op_eval_fbug, | |
742 | gen_op_eval_fbg, | |
743 | gen_op_eval_fbu, | |
9bad0425 | 744 | gen_op_eval_ba, |
3475187d FB |
745 | gen_op_eval_fbe, |
746 | gen_op_eval_fbue, | |
747 | gen_op_eval_fbge, | |
748 | gen_op_eval_fbuge, | |
749 | gen_op_eval_fble, | |
750 | gen_op_eval_fbule, | |
751 | gen_op_eval_fbo, | |
752 | }, | |
753 | #ifdef TARGET_SPARC64 | |
754 | { | |
9bad0425 | 755 | gen_op_eval_bn, |
3475187d FB |
756 | gen_op_eval_fbne_fcc1, |
757 | gen_op_eval_fblg_fcc1, | |
758 | gen_op_eval_fbul_fcc1, | |
759 | gen_op_eval_fbl_fcc1, | |
760 | gen_op_eval_fbug_fcc1, | |
761 | gen_op_eval_fbg_fcc1, | |
762 | gen_op_eval_fbu_fcc1, | |
9bad0425 | 763 | gen_op_eval_ba, |
3475187d FB |
764 | gen_op_eval_fbe_fcc1, |
765 | gen_op_eval_fbue_fcc1, | |
766 | gen_op_eval_fbge_fcc1, | |
767 | gen_op_eval_fbuge_fcc1, | |
768 | gen_op_eval_fble_fcc1, | |
769 | gen_op_eval_fbule_fcc1, | |
770 | gen_op_eval_fbo_fcc1, | |
771 | }, | |
772 | { | |
9bad0425 | 773 | gen_op_eval_bn, |
3475187d FB |
774 | gen_op_eval_fbne_fcc2, |
775 | gen_op_eval_fblg_fcc2, | |
776 | gen_op_eval_fbul_fcc2, | |
777 | gen_op_eval_fbl_fcc2, | |
778 | gen_op_eval_fbug_fcc2, | |
779 | gen_op_eval_fbg_fcc2, | |
780 | gen_op_eval_fbu_fcc2, | |
9bad0425 | 781 | gen_op_eval_ba, |
3475187d FB |
782 | gen_op_eval_fbe_fcc2, |
783 | gen_op_eval_fbue_fcc2, | |
784 | gen_op_eval_fbge_fcc2, | |
785 | gen_op_eval_fbuge_fcc2, | |
786 | gen_op_eval_fble_fcc2, | |
787 | gen_op_eval_fbule_fcc2, | |
788 | gen_op_eval_fbo_fcc2, | |
789 | }, | |
790 | { | |
9bad0425 | 791 | gen_op_eval_bn, |
3475187d FB |
792 | gen_op_eval_fbne_fcc3, |
793 | gen_op_eval_fblg_fcc3, | |
794 | gen_op_eval_fbul_fcc3, | |
795 | gen_op_eval_fbl_fcc3, | |
796 | gen_op_eval_fbug_fcc3, | |
797 | gen_op_eval_fbg_fcc3, | |
798 | gen_op_eval_fbu_fcc3, | |
9bad0425 | 799 | gen_op_eval_ba, |
3475187d FB |
800 | gen_op_eval_fbe_fcc3, |
801 | gen_op_eval_fbue_fcc3, | |
802 | gen_op_eval_fbge_fcc3, | |
803 | gen_op_eval_fbuge_fcc3, | |
804 | gen_op_eval_fble_fcc3, | |
805 | gen_op_eval_fbule_fcc3, | |
806 | gen_op_eval_fbo_fcc3, | |
807 | }, | |
808 | #else | |
809 | {}, {}, {}, | |
810 | #endif | |
811 | }; | |
7a3f1944 | 812 | |
3475187d FB |
813 | #ifdef TARGET_SPARC64 |
814 | static void gen_cond_reg(int cond) | |
e8af50a3 FB |
815 | { |
816 | switch (cond) { | |
e8af50a3 | 817 | case 0x1: |
3475187d | 818 | gen_op_eval_brz(); |
e8af50a3 FB |
819 | break; |
820 | case 0x2: | |
3475187d | 821 | gen_op_eval_brlez(); |
e8af50a3 FB |
822 | break; |
823 | case 0x3: | |
3475187d | 824 | gen_op_eval_brlz(); |
e8af50a3 FB |
825 | break; |
826 | case 0x5: | |
3475187d | 827 | gen_op_eval_brnz(); |
e8af50a3 FB |
828 | break; |
829 | case 0x6: | |
3475187d | 830 | gen_op_eval_brgz(); |
e8af50a3 FB |
831 | break; |
832 | default: | |
3475187d FB |
833 | case 0x7: |
834 | gen_op_eval_brgez(); | |
e8af50a3 FB |
835 | break; |
836 | } | |
837 | } | |
3475187d | 838 | #endif |
cf495bcf | 839 | |
0bee699e | 840 | /* XXX: potentially incorrect if dynamic npc */ |
3475187d | 841 | static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc) |
7a3f1944 | 842 | { |
cf495bcf | 843 | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
af7bf89b | 844 | target_ulong target = dc->pc + offset; |
3475187d | 845 | |
cf495bcf FB |
846 | if (cond == 0x0) { |
847 | /* unconditional not taken */ | |
848 | if (a) { | |
0bee699e | 849 | dc->pc = dc->npc + 4; |
cf495bcf FB |
850 | dc->npc = dc->pc + 4; |
851 | } else { | |
852 | dc->pc = dc->npc; | |
853 | dc->npc = dc->pc + 4; | |
854 | } | |
855 | } else if (cond == 0x8) { | |
856 | /* unconditional taken */ | |
857 | if (a) { | |
72cbca10 | 858 | dc->pc = target; |
cf495bcf FB |
859 | dc->npc = dc->pc + 4; |
860 | } else { | |
861 | dc->pc = dc->npc; | |
72cbca10 | 862 | dc->npc = target; |
cf495bcf FB |
863 | } |
864 | } else { | |
72cbca10 | 865 | flush_T2(dc); |
3475187d | 866 | gen_cond[cc][cond](); |
cf495bcf | 867 | if (a) { |
46525e1f | 868 | gen_branch_a(dc, target, dc->npc); |
cf495bcf | 869 | dc->is_br = 1; |
cf495bcf FB |
870 | } else { |
871 | dc->pc = dc->npc; | |
72cbca10 FB |
872 | dc->jump_pc[0] = target; |
873 | dc->jump_pc[1] = dc->npc + 4; | |
874 | dc->npc = JUMP_PC; | |
cf495bcf FB |
875 | } |
876 | } | |
7a3f1944 FB |
877 | } |
878 | ||
0bee699e | 879 | /* XXX: potentially incorrect if dynamic npc */ |
3475187d | 880 | static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc) |
e8af50a3 FB |
881 | { |
882 | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); | |
af7bf89b FB |
883 | target_ulong target = dc->pc + offset; |
884 | ||
e8af50a3 FB |
885 | if (cond == 0x0) { |
886 | /* unconditional not taken */ | |
887 | if (a) { | |
888 | dc->pc = dc->npc + 4; | |
889 | dc->npc = dc->pc + 4; | |
890 | } else { | |
891 | dc->pc = dc->npc; | |
892 | dc->npc = dc->pc + 4; | |
893 | } | |
894 | } else if (cond == 0x8) { | |
895 | /* unconditional taken */ | |
896 | if (a) { | |
897 | dc->pc = target; | |
898 | dc->npc = dc->pc + 4; | |
899 | } else { | |
900 | dc->pc = dc->npc; | |
901 | dc->npc = target; | |
902 | } | |
903 | } else { | |
904 | flush_T2(dc); | |
3475187d | 905 | gen_fcond[cc][cond](); |
e8af50a3 | 906 | if (a) { |
46525e1f | 907 | gen_branch_a(dc, target, dc->npc); |
e8af50a3 FB |
908 | dc->is_br = 1; |
909 | } else { | |
910 | dc->pc = dc->npc; | |
911 | dc->jump_pc[0] = target; | |
912 | dc->jump_pc[1] = dc->npc + 4; | |
913 | dc->npc = JUMP_PC; | |
914 | } | |
915 | } | |
916 | } | |
917 | ||
3475187d FB |
918 | #ifdef TARGET_SPARC64 |
919 | /* XXX: potentially incorrect if dynamic npc */ | |
920 | static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn) | |
7a3f1944 | 921 | { |
3475187d FB |
922 | unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29)); |
923 | target_ulong target = dc->pc + offset; | |
924 | ||
925 | flush_T2(dc); | |
926 | gen_cond_reg(cond); | |
927 | if (a) { | |
46525e1f | 928 | gen_branch_a(dc, target, dc->npc); |
3475187d FB |
929 | dc->is_br = 1; |
930 | } else { | |
931 | dc->pc = dc->npc; | |
932 | dc->jump_pc[0] = target; | |
933 | dc->jump_pc[1] = dc->npc + 4; | |
934 | dc->npc = JUMP_PC; | |
935 | } | |
7a3f1944 FB |
936 | } |
937 | ||
3475187d FB |
938 | static GenOpFunc * const gen_fcmps[4] = { |
939 | gen_op_fcmps, | |
940 | gen_op_fcmps_fcc1, | |
941 | gen_op_fcmps_fcc2, | |
942 | gen_op_fcmps_fcc3, | |
943 | }; | |
944 | ||
945 | static GenOpFunc * const gen_fcmpd[4] = { | |
946 | gen_op_fcmpd, | |
947 | gen_op_fcmpd_fcc1, | |
948 | gen_op_fcmpd_fcc2, | |
949 | gen_op_fcmpd_fcc3, | |
950 | }; | |
417454b0 BS |
951 | |
952 | static GenOpFunc * const gen_fcmpes[4] = { | |
953 | gen_op_fcmpes, | |
954 | gen_op_fcmpes_fcc1, | |
955 | gen_op_fcmpes_fcc2, | |
956 | gen_op_fcmpes_fcc3, | |
957 | }; | |
958 | ||
959 | static GenOpFunc * const gen_fcmped[4] = { | |
960 | gen_op_fcmped, | |
961 | gen_op_fcmped_fcc1, | |
962 | gen_op_fcmped_fcc2, | |
963 | gen_op_fcmped_fcc3, | |
964 | }; | |
965 | ||
3475187d FB |
966 | #endif |
967 | ||
a80dde08 FB |
968 | static int gen_trap_ifnofpu(DisasContext * dc) |
969 | { | |
970 | #if !defined(CONFIG_USER_ONLY) | |
971 | if (!dc->fpu_enabled) { | |
972 | save_state(dc); | |
973 | gen_op_exception(TT_NFPU_INSN); | |
974 | dc->is_br = 1; | |
975 | return 1; | |
976 | } | |
977 | #endif | |
978 | return 0; | |
979 | } | |
980 | ||
0bee699e | 981 | /* before an instruction, dc->pc must be static */ |
cf495bcf FB |
982 | static void disas_sparc_insn(DisasContext * dc) |
983 | { | |
984 | unsigned int insn, opc, rs1, rs2, rd; | |
7a3f1944 | 985 | |
0fa85d43 | 986 | insn = ldl_code(dc->pc); |
cf495bcf | 987 | opc = GET_FIELD(insn, 0, 1); |
7a3f1944 | 988 | |
cf495bcf FB |
989 | rd = GET_FIELD(insn, 2, 6); |
990 | switch (opc) { | |
991 | case 0: /* branches/sethi */ | |
992 | { | |
993 | unsigned int xop = GET_FIELD(insn, 7, 9); | |
af7bf89b | 994 | int32_t target; |
cf495bcf | 995 | switch (xop) { |
3475187d | 996 | #ifdef TARGET_SPARC64 |
af7bf89b | 997 | case 0x1: /* V9 BPcc */ |
3475187d FB |
998 | { |
999 | int cc; | |
1000 | ||
1001 | target = GET_FIELD_SP(insn, 0, 18); | |
3475187d | 1002 | target = sign_extend(target, 18); |
ee6c0b51 | 1003 | target <<= 2; |
3475187d FB |
1004 | cc = GET_FIELD_SP(insn, 20, 21); |
1005 | if (cc == 0) | |
1006 | do_branch(dc, target, insn, 0); | |
1007 | else if (cc == 2) | |
1008 | do_branch(dc, target, insn, 1); | |
1009 | else | |
1010 | goto illegal_insn; | |
1011 | goto jmp_insn; | |
1012 | } | |
af7bf89b | 1013 | case 0x3: /* V9 BPr */ |
3475187d FB |
1014 | { |
1015 | target = GET_FIELD_SP(insn, 0, 13) | | |
13846e70 | 1016 | (GET_FIELD_SP(insn, 20, 21) << 14); |
3475187d | 1017 | target = sign_extend(target, 16); |
ee6c0b51 | 1018 | target <<= 2; |
3475187d | 1019 | rs1 = GET_FIELD(insn, 13, 17); |
83469015 | 1020 | gen_movl_reg_T0(rs1); |
3475187d FB |
1021 | do_branch_reg(dc, target, insn); |
1022 | goto jmp_insn; | |
1023 | } | |
af7bf89b | 1024 | case 0x5: /* V9 FBPcc */ |
3475187d FB |
1025 | { |
1026 | int cc = GET_FIELD_SP(insn, 20, 21); | |
a80dde08 FB |
1027 | if (gen_trap_ifnofpu(dc)) |
1028 | goto jmp_insn; | |
3475187d | 1029 | target = GET_FIELD_SP(insn, 0, 18); |
3475187d | 1030 | target = sign_extend(target, 19); |
ee6c0b51 | 1031 | target <<= 2; |
3475187d FB |
1032 | do_fbranch(dc, target, insn, cc); |
1033 | goto jmp_insn; | |
1034 | } | |
a4d17f19 BS |
1035 | #else |
1036 | case 0x7: /* CBN+x */ | |
1037 | { | |
1038 | goto ncp_insn; | |
1039 | } | |
3475187d | 1040 | #endif |
cf495bcf | 1041 | case 0x2: /* BN+x */ |
7a3f1944 | 1042 | { |
3475187d | 1043 | target = GET_FIELD(insn, 10, 31); |
cf495bcf | 1044 | target = sign_extend(target, 22); |
ee6c0b51 | 1045 | target <<= 2; |
3475187d | 1046 | do_branch(dc, target, insn, 0); |
cf495bcf | 1047 | goto jmp_insn; |
7a3f1944 | 1048 | } |
e8af50a3 FB |
1049 | case 0x6: /* FBN+x */ |
1050 | { | |
a80dde08 FB |
1051 | if (gen_trap_ifnofpu(dc)) |
1052 | goto jmp_insn; | |
3475187d | 1053 | target = GET_FIELD(insn, 10, 31); |
e8af50a3 | 1054 | target = sign_extend(target, 22); |
ee6c0b51 | 1055 | target <<= 2; |
3475187d | 1056 | do_fbranch(dc, target, insn, 0); |
e8af50a3 FB |
1057 | goto jmp_insn; |
1058 | } | |
cf495bcf | 1059 | case 0x4: /* SETHI */ |
e80cfcfc FB |
1060 | #define OPTIM |
1061 | #if defined(OPTIM) | |
1062 | if (rd) { // nop | |
1063 | #endif | |
3475187d FB |
1064 | uint32_t value = GET_FIELD(insn, 10, 31); |
1065 | gen_movl_imm_T0(value << 10); | |
e80cfcfc FB |
1066 | gen_movl_T0_reg(rd); |
1067 | #if defined(OPTIM) | |
1068 | } | |
1069 | #endif | |
cf495bcf | 1070 | break; |
3475187d FB |
1071 | case 0x0: /* UNIMPL */ |
1072 | default: | |
1073 | goto illegal_insn; | |
cf495bcf FB |
1074 | } |
1075 | break; | |
1076 | } | |
af7bf89b | 1077 | break; |
cf495bcf FB |
1078 | case 1: |
1079 | /*CALL*/ { | |
af7bf89b | 1080 | target_long target = GET_FIELDs(insn, 2, 31) << 2; |
cf495bcf | 1081 | |
83469015 FB |
1082 | #ifdef TARGET_SPARC64 |
1083 | if (dc->pc == (uint32_t)dc->pc) { | |
1084 | gen_op_movl_T0_im(dc->pc); | |
1085 | } else { | |
1086 | gen_op_movq_T0_im64(dc->pc >> 32, dc->pc); | |
1087 | } | |
1088 | #else | |
af7bf89b | 1089 | gen_op_movl_T0_im(dc->pc); |
83469015 | 1090 | #endif |
cf495bcf | 1091 | gen_movl_T0_reg(15); |
af7bf89b | 1092 | target += dc->pc; |
0bee699e | 1093 | gen_mov_pc_npc(dc); |
72cbca10 | 1094 | dc->npc = target; |
cf495bcf FB |
1095 | } |
1096 | goto jmp_insn; | |
1097 | case 2: /* FPU & Logical Operations */ | |
1098 | { | |
1099 | unsigned int xop = GET_FIELD(insn, 7, 12); | |
1100 | if (xop == 0x3a) { /* generate trap */ | |
1101 | int cond; | |
3475187d | 1102 | |
cf495bcf FB |
1103 | rs1 = GET_FIELD(insn, 13, 17); |
1104 | gen_movl_reg_T0(rs1); | |
1105 | if (IS_IMM) { | |
e8af50a3 | 1106 | rs2 = GET_FIELD(insn, 25, 31); |
e80cfcfc | 1107 | #if defined(OPTIM) |
e8af50a3 | 1108 | if (rs2 != 0) { |
e80cfcfc | 1109 | #endif |
3475187d | 1110 | gen_movl_simm_T1(rs2); |
e80cfcfc FB |
1111 | gen_op_add_T1_T0(); |
1112 | #if defined(OPTIM) | |
e8af50a3 | 1113 | } |
e80cfcfc | 1114 | #endif |
cf495bcf FB |
1115 | } else { |
1116 | rs2 = GET_FIELD(insn, 27, 31); | |
e80cfcfc FB |
1117 | #if defined(OPTIM) |
1118 | if (rs2 != 0) { | |
1119 | #endif | |
1120 | gen_movl_reg_T1(rs2); | |
1121 | gen_op_add_T1_T0(); | |
1122 | #if defined(OPTIM) | |
1123 | } | |
1124 | #endif | |
cf495bcf | 1125 | } |
cf495bcf FB |
1126 | cond = GET_FIELD(insn, 3, 6); |
1127 | if (cond == 0x8) { | |
a80dde08 | 1128 | save_state(dc); |
cf495bcf | 1129 | gen_op_trap_T0(); |
af7bf89b | 1130 | } else if (cond != 0) { |
3475187d FB |
1131 | #ifdef TARGET_SPARC64 |
1132 | /* V9 icc/xcc */ | |
1133 | int cc = GET_FIELD_SP(insn, 11, 12); | |
a80dde08 FB |
1134 | flush_T2(dc); |
1135 | save_state(dc); | |
3475187d FB |
1136 | if (cc == 0) |
1137 | gen_cond[0][cond](); | |
1138 | else if (cc == 2) | |
1139 | gen_cond[1][cond](); | |
1140 | else | |
1141 | goto illegal_insn; | |
1142 | #else | |
a80dde08 FB |
1143 | flush_T2(dc); |
1144 | save_state(dc); | |
3475187d FB |
1145 | gen_cond[0][cond](); |
1146 | #endif | |
cf495bcf FB |
1147 | gen_op_trapcc_T0(); |
1148 | } | |
a80dde08 FB |
1149 | gen_op_next_insn(); |
1150 | gen_op_movl_T0_0(); | |
1151 | gen_op_exit_tb(); | |
1152 | dc->is_br = 1; | |
1153 | goto jmp_insn; | |
cf495bcf FB |
1154 | } else if (xop == 0x28) { |
1155 | rs1 = GET_FIELD(insn, 13, 17); | |
1156 | switch(rs1) { | |
1157 | case 0: /* rdy */ | |
65fe7b09 BS |
1158 | #ifndef TARGET_SPARC64 |
1159 | case 0x01 ... 0x0e: /* undefined in the SPARCv8 | |
1160 | manual, rdy on the microSPARC | |
1161 | II */ | |
1162 | case 0x0f: /* stbar in the SPARCv8 manual, | |
1163 | rdy on the microSPARC II */ | |
1164 | case 0x10 ... 0x1f: /* implementation-dependent in the | |
1165 | SPARCv8 manual, rdy on the | |
1166 | microSPARC II */ | |
1167 | #endif | |
1168 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, y)); | |
cf495bcf FB |
1169 | gen_movl_T0_reg(rd); |
1170 | break; | |
3475187d | 1171 | #ifdef TARGET_SPARC64 |
af7bf89b | 1172 | case 0x2: /* V9 rdccr */ |
3475187d FB |
1173 | gen_op_rdccr(); |
1174 | gen_movl_T0_reg(rd); | |
1175 | break; | |
af7bf89b | 1176 | case 0x3: /* V9 rdasi */ |
3475187d FB |
1177 | gen_op_movl_T0_env(offsetof(CPUSPARCState, asi)); |
1178 | gen_movl_T0_reg(rd); | |
1179 | break; | |
af7bf89b | 1180 | case 0x4: /* V9 rdtick */ |
3475187d FB |
1181 | gen_op_rdtick(); |
1182 | gen_movl_T0_reg(rd); | |
1183 | break; | |
af7bf89b | 1184 | case 0x5: /* V9 rdpc */ |
ded3ab80 PB |
1185 | if (dc->pc == (uint32_t)dc->pc) { |
1186 | gen_op_movl_T0_im(dc->pc); | |
1187 | } else { | |
1188 | gen_op_movq_T0_im64(dc->pc >> 32, dc->pc); | |
1189 | } | |
3475187d FB |
1190 | gen_movl_T0_reg(rd); |
1191 | break; | |
af7bf89b | 1192 | case 0x6: /* V9 rdfprs */ |
3475187d FB |
1193 | gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs)); |
1194 | gen_movl_T0_reg(rd); | |
1195 | break; | |
65fe7b09 BS |
1196 | case 0xf: /* V9 membar */ |
1197 | break; /* no effect */ | |
725cb90b FB |
1198 | case 0x13: /* Graphics Status */ |
1199 | if (gen_trap_ifnofpu(dc)) | |
1200 | goto jmp_insn; | |
1201 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr)); | |
1202 | gen_movl_T0_reg(rd); | |
1203 | break; | |
83469015 FB |
1204 | case 0x17: /* Tick compare */ |
1205 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr)); | |
1206 | gen_movl_T0_reg(rd); | |
1207 | break; | |
1208 | case 0x18: /* System tick */ | |
20c9f095 | 1209 | gen_op_rdstick(); |
83469015 FB |
1210 | gen_movl_T0_reg(rd); |
1211 | break; | |
1212 | case 0x19: /* System tick compare */ | |
1213 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr)); | |
1214 | gen_movl_T0_reg(rd); | |
1215 | break; | |
1216 | case 0x10: /* Performance Control */ | |
1217 | case 0x11: /* Performance Instrumentation Counter */ | |
1218 | case 0x12: /* Dispatch Control */ | |
83469015 FB |
1219 | case 0x14: /* Softint set, WO */ |
1220 | case 0x15: /* Softint clear, WO */ | |
1221 | case 0x16: /* Softint write */ | |
3475187d FB |
1222 | #endif |
1223 | default: | |
cf495bcf FB |
1224 | goto illegal_insn; |
1225 | } | |
e8af50a3 | 1226 | #if !defined(CONFIG_USER_ONLY) |
e9ebed4d | 1227 | } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */ |
3475187d | 1228 | #ifndef TARGET_SPARC64 |
e8af50a3 FB |
1229 | if (!supervisor(dc)) |
1230 | goto priv_insn; | |
1231 | gen_op_rdpsr(); | |
e9ebed4d BS |
1232 | #else |
1233 | if (!hypervisor(dc)) | |
1234 | goto priv_insn; | |
1235 | rs1 = GET_FIELD(insn, 13, 17); | |
1236 | switch (rs1) { | |
1237 | case 0: // hpstate | |
1238 | // gen_op_rdhpstate(); | |
1239 | break; | |
1240 | case 1: // htstate | |
1241 | // gen_op_rdhtstate(); | |
1242 | break; | |
1243 | case 3: // hintp | |
1244 | gen_op_movl_T0_env(offsetof(CPUSPARCState, hintp)); | |
1245 | break; | |
1246 | case 5: // htba | |
1247 | gen_op_movl_T0_env(offsetof(CPUSPARCState, htba)); | |
1248 | break; | |
1249 | case 6: // hver | |
1250 | gen_op_movl_T0_env(offsetof(CPUSPARCState, hver)); | |
1251 | break; | |
1252 | case 31: // hstick_cmpr | |
1253 | gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr)); | |
1254 | break; | |
1255 | default: | |
1256 | goto illegal_insn; | |
1257 | } | |
1258 | #endif | |
e8af50a3 FB |
1259 | gen_movl_T0_reg(rd); |
1260 | break; | |
3475187d | 1261 | } else if (xop == 0x2a) { /* rdwim / V9 rdpr */ |
e8af50a3 FB |
1262 | if (!supervisor(dc)) |
1263 | goto priv_insn; | |
3475187d FB |
1264 | #ifdef TARGET_SPARC64 |
1265 | rs1 = GET_FIELD(insn, 13, 17); | |
1266 | switch (rs1) { | |
1267 | case 0: // tpc | |
1268 | gen_op_rdtpc(); | |
1269 | break; | |
1270 | case 1: // tnpc | |
1271 | gen_op_rdtnpc(); | |
1272 | break; | |
1273 | case 2: // tstate | |
1274 | gen_op_rdtstate(); | |
1275 | break; | |
1276 | case 3: // tt | |
1277 | gen_op_rdtt(); | |
1278 | break; | |
1279 | case 4: // tick | |
1280 | gen_op_rdtick(); | |
1281 | break; | |
1282 | case 5: // tba | |
1283 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr)); | |
1284 | break; | |
1285 | case 6: // pstate | |
1286 | gen_op_rdpstate(); | |
1287 | break; | |
1288 | case 7: // tl | |
1289 | gen_op_movl_T0_env(offsetof(CPUSPARCState, tl)); | |
1290 | break; | |
1291 | case 8: // pil | |
1292 | gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil)); | |
1293 | break; | |
1294 | case 9: // cwp | |
1295 | gen_op_rdcwp(); | |
1296 | break; | |
1297 | case 10: // cansave | |
1298 | gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave)); | |
1299 | break; | |
1300 | case 11: // canrestore | |
1301 | gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore)); | |
1302 | break; | |
1303 | case 12: // cleanwin | |
1304 | gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin)); | |
1305 | break; | |
1306 | case 13: // otherwin | |
1307 | gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin)); | |
1308 | break; | |
1309 | case 14: // wstate | |
1310 | gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate)); | |
1311 | break; | |
e9ebed4d BS |
1312 | case 16: // UA2005 gl |
1313 | gen_op_movl_T0_env(offsetof(CPUSPARCState, gl)); | |
1314 | break; | |
1315 | case 26: // UA2005 strand status | |
1316 | if (!hypervisor(dc)) | |
1317 | goto priv_insn; | |
1318 | gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr)); | |
1319 | break; | |
3475187d FB |
1320 | case 31: // ver |
1321 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, version)); | |
1322 | break; | |
1323 | case 15: // fq | |
1324 | default: | |
1325 | goto illegal_insn; | |
1326 | } | |
1327 | #else | |
1328 | gen_op_movl_T0_env(offsetof(CPUSPARCState, wim)); | |
1329 | #endif | |
e8af50a3 FB |
1330 | gen_movl_T0_reg(rd); |
1331 | break; | |
3475187d FB |
1332 | } else if (xop == 0x2b) { /* rdtbr / V9 flushw */ |
1333 | #ifdef TARGET_SPARC64 | |
1334 | gen_op_flushw(); | |
1335 | #else | |
e8af50a3 FB |
1336 | if (!supervisor(dc)) |
1337 | goto priv_insn; | |
3475187d | 1338 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr)); |
e8af50a3 | 1339 | gen_movl_T0_reg(rd); |
3475187d | 1340 | #endif |
e8af50a3 FB |
1341 | break; |
1342 | #endif | |
e80cfcfc | 1343 | } else if (xop == 0x34) { /* FPU Operations */ |
a80dde08 FB |
1344 | if (gen_trap_ifnofpu(dc)) |
1345 | goto jmp_insn; | |
417454b0 | 1346 | gen_op_clear_ieee_excp_and_FTT(); |
e8af50a3 FB |
1347 | rs1 = GET_FIELD(insn, 13, 17); |
1348 | rs2 = GET_FIELD(insn, 27, 31); | |
1349 | xop = GET_FIELD(insn, 18, 26); | |
1350 | switch (xop) { | |
1351 | case 0x1: /* fmovs */ | |
1352 | gen_op_load_fpr_FT0(rs2); | |
1353 | gen_op_store_FT0_fpr(rd); | |
1354 | break; | |
1355 | case 0x5: /* fnegs */ | |
1356 | gen_op_load_fpr_FT1(rs2); | |
1357 | gen_op_fnegs(); | |
1358 | gen_op_store_FT0_fpr(rd); | |
1359 | break; | |
1360 | case 0x9: /* fabss */ | |
1361 | gen_op_load_fpr_FT1(rs2); | |
1362 | gen_op_fabss(); | |
1363 | gen_op_store_FT0_fpr(rd); | |
1364 | break; | |
1365 | case 0x29: /* fsqrts */ | |
1366 | gen_op_load_fpr_FT1(rs2); | |
1367 | gen_op_fsqrts(); | |
1368 | gen_op_store_FT0_fpr(rd); | |
1369 | break; | |
1370 | case 0x2a: /* fsqrtd */ | |
3475187d | 1371 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
e8af50a3 | 1372 | gen_op_fsqrtd(); |
3475187d | 1373 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e8af50a3 | 1374 | break; |
e80cfcfc FB |
1375 | case 0x2b: /* fsqrtq */ |
1376 | goto nfpu_insn; | |
e8af50a3 FB |
1377 | case 0x41: |
1378 | gen_op_load_fpr_FT0(rs1); | |
1379 | gen_op_load_fpr_FT1(rs2); | |
1380 | gen_op_fadds(); | |
1381 | gen_op_store_FT0_fpr(rd); | |
1382 | break; | |
1383 | case 0x42: | |
3475187d FB |
1384 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
1385 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e8af50a3 | 1386 | gen_op_faddd(); |
3475187d | 1387 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e8af50a3 | 1388 | break; |
e80cfcfc FB |
1389 | case 0x43: /* faddq */ |
1390 | goto nfpu_insn; | |
e8af50a3 FB |
1391 | case 0x45: |
1392 | gen_op_load_fpr_FT0(rs1); | |
1393 | gen_op_load_fpr_FT1(rs2); | |
1394 | gen_op_fsubs(); | |
1395 | gen_op_store_FT0_fpr(rd); | |
1396 | break; | |
1397 | case 0x46: | |
3475187d FB |
1398 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
1399 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e8af50a3 | 1400 | gen_op_fsubd(); |
3475187d | 1401 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e8af50a3 | 1402 | break; |
e80cfcfc FB |
1403 | case 0x47: /* fsubq */ |
1404 | goto nfpu_insn; | |
e8af50a3 FB |
1405 | case 0x49: |
1406 | gen_op_load_fpr_FT0(rs1); | |
1407 | gen_op_load_fpr_FT1(rs2); | |
1408 | gen_op_fmuls(); | |
1409 | gen_op_store_FT0_fpr(rd); | |
1410 | break; | |
1411 | case 0x4a: | |
3475187d FB |
1412 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
1413 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e8af50a3 FB |
1414 | gen_op_fmuld(); |
1415 | gen_op_store_DT0_fpr(rd); | |
1416 | break; | |
e80cfcfc FB |
1417 | case 0x4b: /* fmulq */ |
1418 | goto nfpu_insn; | |
e8af50a3 FB |
1419 | case 0x4d: |
1420 | gen_op_load_fpr_FT0(rs1); | |
1421 | gen_op_load_fpr_FT1(rs2); | |
1422 | gen_op_fdivs(); | |
1423 | gen_op_store_FT0_fpr(rd); | |
1424 | break; | |
1425 | case 0x4e: | |
3475187d FB |
1426 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
1427 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e8af50a3 | 1428 | gen_op_fdivd(); |
3475187d | 1429 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e8af50a3 | 1430 | break; |
e80cfcfc FB |
1431 | case 0x4f: /* fdivq */ |
1432 | goto nfpu_insn; | |
e8af50a3 FB |
1433 | case 0x69: |
1434 | gen_op_load_fpr_FT0(rs1); | |
1435 | gen_op_load_fpr_FT1(rs2); | |
1436 | gen_op_fsmuld(); | |
3475187d | 1437 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e8af50a3 | 1438 | break; |
e80cfcfc FB |
1439 | case 0x6e: /* fdmulq */ |
1440 | goto nfpu_insn; | |
e8af50a3 FB |
1441 | case 0xc4: |
1442 | gen_op_load_fpr_FT1(rs2); | |
1443 | gen_op_fitos(); | |
1444 | gen_op_store_FT0_fpr(rd); | |
1445 | break; | |
1446 | case 0xc6: | |
3475187d | 1447 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
e8af50a3 FB |
1448 | gen_op_fdtos(); |
1449 | gen_op_store_FT0_fpr(rd); | |
1450 | break; | |
e80cfcfc FB |
1451 | case 0xc7: /* fqtos */ |
1452 | goto nfpu_insn; | |
e8af50a3 FB |
1453 | case 0xc8: |
1454 | gen_op_load_fpr_FT1(rs2); | |
1455 | gen_op_fitod(); | |
3475187d | 1456 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e8af50a3 FB |
1457 | break; |
1458 | case 0xc9: | |
1459 | gen_op_load_fpr_FT1(rs2); | |
1460 | gen_op_fstod(); | |
3475187d | 1461 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e8af50a3 | 1462 | break; |
e80cfcfc FB |
1463 | case 0xcb: /* fqtod */ |
1464 | goto nfpu_insn; | |
1465 | case 0xcc: /* fitoq */ | |
1466 | goto nfpu_insn; | |
1467 | case 0xcd: /* fstoq */ | |
1468 | goto nfpu_insn; | |
1469 | case 0xce: /* fdtoq */ | |
1470 | goto nfpu_insn; | |
e8af50a3 FB |
1471 | case 0xd1: |
1472 | gen_op_load_fpr_FT1(rs2); | |
1473 | gen_op_fstoi(); | |
1474 | gen_op_store_FT0_fpr(rd); | |
1475 | break; | |
1476 | case 0xd2: | |
1477 | gen_op_load_fpr_DT1(rs2); | |
1478 | gen_op_fdtoi(); | |
1479 | gen_op_store_FT0_fpr(rd); | |
1480 | break; | |
e80cfcfc FB |
1481 | case 0xd3: /* fqtoi */ |
1482 | goto nfpu_insn; | |
3475187d | 1483 | #ifdef TARGET_SPARC64 |
af7bf89b | 1484 | case 0x2: /* V9 fmovd */ |
3475187d FB |
1485 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
1486 | gen_op_store_DT0_fpr(DFPREG(rd)); | |
1487 | break; | |
af7bf89b | 1488 | case 0x6: /* V9 fnegd */ |
3475187d FB |
1489 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
1490 | gen_op_fnegd(); | |
1491 | gen_op_store_DT0_fpr(DFPREG(rd)); | |
1492 | break; | |
af7bf89b | 1493 | case 0xa: /* V9 fabsd */ |
3475187d FB |
1494 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
1495 | gen_op_fabsd(); | |
1496 | gen_op_store_DT0_fpr(DFPREG(rd)); | |
1497 | break; | |
af7bf89b | 1498 | case 0x81: /* V9 fstox */ |
3475187d FB |
1499 | gen_op_load_fpr_FT1(rs2); |
1500 | gen_op_fstox(); | |
1501 | gen_op_store_DT0_fpr(DFPREG(rd)); | |
1502 | break; | |
af7bf89b | 1503 | case 0x82: /* V9 fdtox */ |
3475187d FB |
1504 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
1505 | gen_op_fdtox(); | |
1506 | gen_op_store_DT0_fpr(DFPREG(rd)); | |
1507 | break; | |
af7bf89b | 1508 | case 0x84: /* V9 fxtos */ |
3475187d FB |
1509 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
1510 | gen_op_fxtos(); | |
1511 | gen_op_store_FT0_fpr(rd); | |
1512 | break; | |
af7bf89b | 1513 | case 0x88: /* V9 fxtod */ |
3475187d FB |
1514 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
1515 | gen_op_fxtod(); | |
1516 | gen_op_store_DT0_fpr(DFPREG(rd)); | |
1517 | break; | |
af7bf89b FB |
1518 | case 0x3: /* V9 fmovq */ |
1519 | case 0x7: /* V9 fnegq */ | |
1520 | case 0xb: /* V9 fabsq */ | |
1521 | case 0x83: /* V9 fqtox */ | |
1522 | case 0x8c: /* V9 fxtoq */ | |
3475187d FB |
1523 | goto nfpu_insn; |
1524 | #endif | |
1525 | default: | |
e8af50a3 FB |
1526 | goto illegal_insn; |
1527 | } | |
e80cfcfc | 1528 | } else if (xop == 0x35) { /* FPU Operations */ |
3475187d FB |
1529 | #ifdef TARGET_SPARC64 |
1530 | int cond; | |
1531 | #endif | |
a80dde08 FB |
1532 | if (gen_trap_ifnofpu(dc)) |
1533 | goto jmp_insn; | |
417454b0 | 1534 | gen_op_clear_ieee_excp_and_FTT(); |
cf495bcf | 1535 | rs1 = GET_FIELD(insn, 13, 17); |
e80cfcfc FB |
1536 | rs2 = GET_FIELD(insn, 27, 31); |
1537 | xop = GET_FIELD(insn, 18, 26); | |
3475187d FB |
1538 | #ifdef TARGET_SPARC64 |
1539 | if ((xop & 0x11f) == 0x005) { // V9 fmovsr | |
1540 | cond = GET_FIELD_SP(insn, 14, 17); | |
1541 | gen_op_load_fpr_FT0(rd); | |
1542 | gen_op_load_fpr_FT1(rs2); | |
1543 | rs1 = GET_FIELD(insn, 13, 17); | |
1544 | gen_movl_reg_T0(rs1); | |
1545 | flush_T2(dc); | |
1546 | gen_cond_reg(cond); | |
1547 | gen_op_fmovs_cc(); | |
1548 | gen_op_store_FT0_fpr(rd); | |
1549 | break; | |
1550 | } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr | |
1551 | cond = GET_FIELD_SP(insn, 14, 17); | |
1552 | gen_op_load_fpr_DT0(rd); | |
1553 | gen_op_load_fpr_DT1(rs2); | |
1554 | flush_T2(dc); | |
1555 | rs1 = GET_FIELD(insn, 13, 17); | |
1556 | gen_movl_reg_T0(rs1); | |
1557 | gen_cond_reg(cond); | |
1558 | gen_op_fmovs_cc(); | |
1559 | gen_op_store_DT0_fpr(rd); | |
1560 | break; | |
1561 | } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr | |
1562 | goto nfpu_insn; | |
1563 | } | |
1564 | #endif | |
e80cfcfc | 1565 | switch (xop) { |
3475187d FB |
1566 | #ifdef TARGET_SPARC64 |
1567 | case 0x001: /* V9 fmovscc %fcc0 */ | |
1568 | cond = GET_FIELD_SP(insn, 14, 17); | |
1569 | gen_op_load_fpr_FT0(rd); | |
1570 | gen_op_load_fpr_FT1(rs2); | |
1571 | flush_T2(dc); | |
1572 | gen_fcond[0][cond](); | |
1573 | gen_op_fmovs_cc(); | |
1574 | gen_op_store_FT0_fpr(rd); | |
1575 | break; | |
1576 | case 0x002: /* V9 fmovdcc %fcc0 */ | |
1577 | cond = GET_FIELD_SP(insn, 14, 17); | |
1578 | gen_op_load_fpr_DT0(rd); | |
1579 | gen_op_load_fpr_DT1(rs2); | |
1580 | flush_T2(dc); | |
1581 | gen_fcond[0][cond](); | |
1582 | gen_op_fmovd_cc(); | |
1583 | gen_op_store_DT0_fpr(rd); | |
1584 | break; | |
1585 | case 0x003: /* V9 fmovqcc %fcc0 */ | |
1586 | goto nfpu_insn; | |
1587 | case 0x041: /* V9 fmovscc %fcc1 */ | |
1588 | cond = GET_FIELD_SP(insn, 14, 17); | |
1589 | gen_op_load_fpr_FT0(rd); | |
1590 | gen_op_load_fpr_FT1(rs2); | |
1591 | flush_T2(dc); | |
1592 | gen_fcond[1][cond](); | |
1593 | gen_op_fmovs_cc(); | |
1594 | gen_op_store_FT0_fpr(rd); | |
1595 | break; | |
1596 | case 0x042: /* V9 fmovdcc %fcc1 */ | |
1597 | cond = GET_FIELD_SP(insn, 14, 17); | |
1598 | gen_op_load_fpr_DT0(rd); | |
1599 | gen_op_load_fpr_DT1(rs2); | |
1600 | flush_T2(dc); | |
1601 | gen_fcond[1][cond](); | |
1602 | gen_op_fmovd_cc(); | |
1603 | gen_op_store_DT0_fpr(rd); | |
1604 | break; | |
1605 | case 0x043: /* V9 fmovqcc %fcc1 */ | |
1606 | goto nfpu_insn; | |
1607 | case 0x081: /* V9 fmovscc %fcc2 */ | |
1608 | cond = GET_FIELD_SP(insn, 14, 17); | |
1609 | gen_op_load_fpr_FT0(rd); | |
1610 | gen_op_load_fpr_FT1(rs2); | |
1611 | flush_T2(dc); | |
1612 | gen_fcond[2][cond](); | |
1613 | gen_op_fmovs_cc(); | |
1614 | gen_op_store_FT0_fpr(rd); | |
1615 | break; | |
1616 | case 0x082: /* V9 fmovdcc %fcc2 */ | |
1617 | cond = GET_FIELD_SP(insn, 14, 17); | |
1618 | gen_op_load_fpr_DT0(rd); | |
1619 | gen_op_load_fpr_DT1(rs2); | |
1620 | flush_T2(dc); | |
1621 | gen_fcond[2][cond](); | |
1622 | gen_op_fmovd_cc(); | |
1623 | gen_op_store_DT0_fpr(rd); | |
1624 | break; | |
1625 | case 0x083: /* V9 fmovqcc %fcc2 */ | |
1626 | goto nfpu_insn; | |
1627 | case 0x0c1: /* V9 fmovscc %fcc3 */ | |
1628 | cond = GET_FIELD_SP(insn, 14, 17); | |
1629 | gen_op_load_fpr_FT0(rd); | |
1630 | gen_op_load_fpr_FT1(rs2); | |
1631 | flush_T2(dc); | |
1632 | gen_fcond[3][cond](); | |
1633 | gen_op_fmovs_cc(); | |
1634 | gen_op_store_FT0_fpr(rd); | |
1635 | break; | |
1636 | case 0x0c2: /* V9 fmovdcc %fcc3 */ | |
1637 | cond = GET_FIELD_SP(insn, 14, 17); | |
1638 | gen_op_load_fpr_DT0(rd); | |
1639 | gen_op_load_fpr_DT1(rs2); | |
1640 | flush_T2(dc); | |
1641 | gen_fcond[3][cond](); | |
1642 | gen_op_fmovd_cc(); | |
1643 | gen_op_store_DT0_fpr(rd); | |
1644 | break; | |
1645 | case 0x0c3: /* V9 fmovqcc %fcc3 */ | |
1646 | goto nfpu_insn; | |
1647 | case 0x101: /* V9 fmovscc %icc */ | |
1648 | cond = GET_FIELD_SP(insn, 14, 17); | |
1649 | gen_op_load_fpr_FT0(rd); | |
1650 | gen_op_load_fpr_FT1(rs2); | |
1651 | flush_T2(dc); | |
1652 | gen_cond[0][cond](); | |
1653 | gen_op_fmovs_cc(); | |
1654 | gen_op_store_FT0_fpr(rd); | |
1655 | break; | |
1656 | case 0x102: /* V9 fmovdcc %icc */ | |
1657 | cond = GET_FIELD_SP(insn, 14, 17); | |
1658 | gen_op_load_fpr_DT0(rd); | |
1659 | gen_op_load_fpr_DT1(rs2); | |
1660 | flush_T2(dc); | |
1661 | gen_cond[0][cond](); | |
1662 | gen_op_fmovd_cc(); | |
1663 | gen_op_store_DT0_fpr(rd); | |
1664 | break; | |
1665 | case 0x103: /* V9 fmovqcc %icc */ | |
1666 | goto nfpu_insn; | |
1667 | case 0x181: /* V9 fmovscc %xcc */ | |
1668 | cond = GET_FIELD_SP(insn, 14, 17); | |
1669 | gen_op_load_fpr_FT0(rd); | |
1670 | gen_op_load_fpr_FT1(rs2); | |
1671 | flush_T2(dc); | |
1672 | gen_cond[1][cond](); | |
1673 | gen_op_fmovs_cc(); | |
1674 | gen_op_store_FT0_fpr(rd); | |
1675 | break; | |
1676 | case 0x182: /* V9 fmovdcc %xcc */ | |
1677 | cond = GET_FIELD_SP(insn, 14, 17); | |
1678 | gen_op_load_fpr_DT0(rd); | |
1679 | gen_op_load_fpr_DT1(rs2); | |
1680 | flush_T2(dc); | |
1681 | gen_cond[1][cond](); | |
1682 | gen_op_fmovd_cc(); | |
1683 | gen_op_store_DT0_fpr(rd); | |
1684 | break; | |
1685 | case 0x183: /* V9 fmovqcc %xcc */ | |
1686 | goto nfpu_insn; | |
1687 | #endif | |
1688 | case 0x51: /* V9 %fcc */ | |
e80cfcfc FB |
1689 | gen_op_load_fpr_FT0(rs1); |
1690 | gen_op_load_fpr_FT1(rs2); | |
3475187d FB |
1691 | #ifdef TARGET_SPARC64 |
1692 | gen_fcmps[rd & 3](); | |
1693 | #else | |
e80cfcfc | 1694 | gen_op_fcmps(); |
3475187d | 1695 | #endif |
e80cfcfc | 1696 | break; |
3475187d FB |
1697 | case 0x52: /* V9 %fcc */ |
1698 | gen_op_load_fpr_DT0(DFPREG(rs1)); | |
1699 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
1700 | #ifdef TARGET_SPARC64 | |
1701 | gen_fcmpd[rd & 3](); | |
1702 | #else | |
e80cfcfc | 1703 | gen_op_fcmpd(); |
3475187d | 1704 | #endif |
e80cfcfc FB |
1705 | break; |
1706 | case 0x53: /* fcmpq */ | |
1707 | goto nfpu_insn; | |
3475187d | 1708 | case 0x55: /* fcmpes, V9 %fcc */ |
e80cfcfc FB |
1709 | gen_op_load_fpr_FT0(rs1); |
1710 | gen_op_load_fpr_FT1(rs2); | |
3475187d | 1711 | #ifdef TARGET_SPARC64 |
417454b0 | 1712 | gen_fcmpes[rd & 3](); |
3475187d | 1713 | #else |
417454b0 | 1714 | gen_op_fcmpes(); |
3475187d | 1715 | #endif |
e80cfcfc | 1716 | break; |
3475187d FB |
1717 | case 0x56: /* fcmped, V9 %fcc */ |
1718 | gen_op_load_fpr_DT0(DFPREG(rs1)); | |
1719 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
1720 | #ifdef TARGET_SPARC64 | |
417454b0 | 1721 | gen_fcmped[rd & 3](); |
3475187d | 1722 | #else |
417454b0 | 1723 | gen_op_fcmped(); |
3475187d | 1724 | #endif |
e80cfcfc FB |
1725 | break; |
1726 | case 0x57: /* fcmpeq */ | |
1727 | goto nfpu_insn; | |
1728 | default: | |
1729 | goto illegal_insn; | |
1730 | } | |
1731 | #if defined(OPTIM) | |
1732 | } else if (xop == 0x2) { | |
1733 | // clr/mov shortcut | |
1734 | ||
1735 | rs1 = GET_FIELD(insn, 13, 17); | |
1736 | if (rs1 == 0) { | |
1737 | // or %g0, x, y -> mov T1, x; mov y, T1 | |
1738 | if (IS_IMM) { /* immediate */ | |
1739 | rs2 = GET_FIELDs(insn, 19, 31); | |
3475187d | 1740 | gen_movl_simm_T1(rs2); |
e80cfcfc FB |
1741 | } else { /* register */ |
1742 | rs2 = GET_FIELD(insn, 27, 31); | |
1743 | gen_movl_reg_T1(rs2); | |
1744 | } | |
1745 | gen_movl_T1_reg(rd); | |
1746 | } else { | |
1747 | gen_movl_reg_T0(rs1); | |
1748 | if (IS_IMM) { /* immediate */ | |
1749 | // or x, #0, y -> mov T1, x; mov y, T1 | |
1750 | rs2 = GET_FIELDs(insn, 19, 31); | |
1751 | if (rs2 != 0) { | |
3475187d | 1752 | gen_movl_simm_T1(rs2); |
e80cfcfc FB |
1753 | gen_op_or_T1_T0(); |
1754 | } | |
1755 | } else { /* register */ | |
1756 | // or x, %g0, y -> mov T1, x; mov y, T1 | |
1757 | rs2 = GET_FIELD(insn, 27, 31); | |
1758 | if (rs2 != 0) { | |
1759 | gen_movl_reg_T1(rs2); | |
1760 | gen_op_or_T1_T0(); | |
1761 | } | |
1762 | } | |
1763 | gen_movl_T0_reg(rd); | |
1764 | } | |
83469015 FB |
1765 | #endif |
1766 | #ifdef TARGET_SPARC64 | |
8a08f9a8 | 1767 | } else if (xop == 0x25) { /* sll, V9 sllx */ |
83469015 FB |
1768 | rs1 = GET_FIELD(insn, 13, 17); |
1769 | gen_movl_reg_T0(rs1); | |
1770 | if (IS_IMM) { /* immediate */ | |
1771 | rs2 = GET_FIELDs(insn, 20, 31); | |
1772 | gen_movl_simm_T1(rs2); | |
1773 | } else { /* register */ | |
1774 | rs2 = GET_FIELD(insn, 27, 31); | |
1775 | gen_movl_reg_T1(rs2); | |
1776 | } | |
8a08f9a8 BS |
1777 | if (insn & (1 << 12)) |
1778 | gen_op_sllx(); | |
1779 | else | |
1780 | gen_op_sll(); | |
83469015 FB |
1781 | gen_movl_T0_reg(rd); |
1782 | } else if (xop == 0x26) { /* srl, V9 srlx */ | |
1783 | rs1 = GET_FIELD(insn, 13, 17); | |
1784 | gen_movl_reg_T0(rs1); | |
1785 | if (IS_IMM) { /* immediate */ | |
1786 | rs2 = GET_FIELDs(insn, 20, 31); | |
1787 | gen_movl_simm_T1(rs2); | |
1788 | } else { /* register */ | |
1789 | rs2 = GET_FIELD(insn, 27, 31); | |
1790 | gen_movl_reg_T1(rs2); | |
1791 | } | |
1792 | if (insn & (1 << 12)) | |
1793 | gen_op_srlx(); | |
1794 | else | |
1795 | gen_op_srl(); | |
1796 | gen_movl_T0_reg(rd); | |
1797 | } else if (xop == 0x27) { /* sra, V9 srax */ | |
1798 | rs1 = GET_FIELD(insn, 13, 17); | |
1799 | gen_movl_reg_T0(rs1); | |
1800 | if (IS_IMM) { /* immediate */ | |
1801 | rs2 = GET_FIELDs(insn, 20, 31); | |
1802 | gen_movl_simm_T1(rs2); | |
1803 | } else { /* register */ | |
1804 | rs2 = GET_FIELD(insn, 27, 31); | |
1805 | gen_movl_reg_T1(rs2); | |
1806 | } | |
1807 | if (insn & (1 << 12)) | |
1808 | gen_op_srax(); | |
1809 | else | |
1810 | gen_op_sra(); | |
1811 | gen_movl_T0_reg(rd); | |
e80cfcfc | 1812 | #endif |
fcc72045 | 1813 | } else if (xop < 0x36) { |
e80cfcfc FB |
1814 | rs1 = GET_FIELD(insn, 13, 17); |
1815 | gen_movl_reg_T0(rs1); | |
1816 | if (IS_IMM) { /* immediate */ | |
cf495bcf | 1817 | rs2 = GET_FIELDs(insn, 19, 31); |
3475187d | 1818 | gen_movl_simm_T1(rs2); |
cf495bcf FB |
1819 | } else { /* register */ |
1820 | rs2 = GET_FIELD(insn, 27, 31); | |
1821 | gen_movl_reg_T1(rs2); | |
1822 | } | |
1823 | if (xop < 0x20) { | |
1824 | switch (xop & ~0x10) { | |
1825 | case 0x0: | |
1826 | if (xop & 0x10) | |
1827 | gen_op_add_T1_T0_cc(); | |
1828 | else | |
1829 | gen_op_add_T1_T0(); | |
1830 | break; | |
1831 | case 0x1: | |
1832 | gen_op_and_T1_T0(); | |
1833 | if (xop & 0x10) | |
1834 | gen_op_logic_T0_cc(); | |
1835 | break; | |
1836 | case 0x2: | |
e80cfcfc FB |
1837 | gen_op_or_T1_T0(); |
1838 | if (xop & 0x10) | |
1839 | gen_op_logic_T0_cc(); | |
1840 | break; | |
cf495bcf FB |
1841 | case 0x3: |
1842 | gen_op_xor_T1_T0(); | |
1843 | if (xop & 0x10) | |
1844 | gen_op_logic_T0_cc(); | |
1845 | break; | |
1846 | case 0x4: | |
1847 | if (xop & 0x10) | |
1848 | gen_op_sub_T1_T0_cc(); | |
1849 | else | |
1850 | gen_op_sub_T1_T0(); | |
1851 | break; | |
1852 | case 0x5: | |
1853 | gen_op_andn_T1_T0(); | |
1854 | if (xop & 0x10) | |
1855 | gen_op_logic_T0_cc(); | |
1856 | break; | |
1857 | case 0x6: | |
1858 | gen_op_orn_T1_T0(); | |
1859 | if (xop & 0x10) | |
1860 | gen_op_logic_T0_cc(); | |
1861 | break; | |
1862 | case 0x7: | |
1863 | gen_op_xnor_T1_T0(); | |
1864 | if (xop & 0x10) | |
1865 | gen_op_logic_T0_cc(); | |
1866 | break; | |
1867 | case 0x8: | |
cf495bcf | 1868 | if (xop & 0x10) |
af7bf89b FB |
1869 | gen_op_addx_T1_T0_cc(); |
1870 | else | |
1871 | gen_op_addx_T1_T0(); | |
cf495bcf | 1872 | break; |
ded3ab80 PB |
1873 | #ifdef TARGET_SPARC64 |
1874 | case 0x9: /* V9 mulx */ | |
1875 | gen_op_mulx_T1_T0(); | |
1876 | break; | |
1877 | #endif | |
cf495bcf FB |
1878 | case 0xa: |
1879 | gen_op_umul_T1_T0(); | |
1880 | if (xop & 0x10) | |
1881 | gen_op_logic_T0_cc(); | |
1882 | break; | |
1883 | case 0xb: | |
1884 | gen_op_smul_T1_T0(); | |
1885 | if (xop & 0x10) | |
1886 | gen_op_logic_T0_cc(); | |
1887 | break; | |
1888 | case 0xc: | |
cf495bcf | 1889 | if (xop & 0x10) |
af7bf89b FB |
1890 | gen_op_subx_T1_T0_cc(); |
1891 | else | |
1892 | gen_op_subx_T1_T0(); | |
cf495bcf | 1893 | break; |
ded3ab80 PB |
1894 | #ifdef TARGET_SPARC64 |
1895 | case 0xd: /* V9 udivx */ | |
1896 | gen_op_udivx_T1_T0(); | |
1897 | break; | |
1898 | #endif | |
cf495bcf FB |
1899 | case 0xe: |
1900 | gen_op_udiv_T1_T0(); | |
1901 | if (xop & 0x10) | |
1902 | gen_op_div_cc(); | |
1903 | break; | |
1904 | case 0xf: | |
1905 | gen_op_sdiv_T1_T0(); | |
1906 | if (xop & 0x10) | |
1907 | gen_op_div_cc(); | |
1908 | break; | |
1909 | default: | |
1910 | goto illegal_insn; | |
1911 | } | |
e80cfcfc | 1912 | gen_movl_T0_reg(rd); |
cf495bcf FB |
1913 | } else { |
1914 | switch (xop) { | |
e80cfcfc | 1915 | case 0x20: /* taddcc */ |
e32f879d BS |
1916 | gen_op_tadd_T1_T0_cc(); |
1917 | gen_movl_T0_reg(rd); | |
1918 | break; | |
e80cfcfc | 1919 | case 0x21: /* tsubcc */ |
e32f879d BS |
1920 | gen_op_tsub_T1_T0_cc(); |
1921 | gen_movl_T0_reg(rd); | |
1922 | break; | |
e80cfcfc | 1923 | case 0x22: /* taddcctv */ |
e32f879d BS |
1924 | gen_op_tadd_T1_T0_ccTV(); |
1925 | gen_movl_T0_reg(rd); | |
1926 | break; | |
e80cfcfc | 1927 | case 0x23: /* tsubcctv */ |
e32f879d BS |
1928 | gen_op_tsub_T1_T0_ccTV(); |
1929 | gen_movl_T0_reg(rd); | |
1930 | break; | |
cf495bcf FB |
1931 | case 0x24: /* mulscc */ |
1932 | gen_op_mulscc_T1_T0(); | |
1933 | gen_movl_T0_reg(rd); | |
1934 | break; | |
83469015 FB |
1935 | #ifndef TARGET_SPARC64 |
1936 | case 0x25: /* sll */ | |
3475187d | 1937 | gen_op_sll(); |
cf495bcf FB |
1938 | gen_movl_T0_reg(rd); |
1939 | break; | |
83469015 | 1940 | case 0x26: /* srl */ |
3475187d | 1941 | gen_op_srl(); |
cf495bcf FB |
1942 | gen_movl_T0_reg(rd); |
1943 | break; | |
83469015 | 1944 | case 0x27: /* sra */ |
3475187d | 1945 | gen_op_sra(); |
cf495bcf FB |
1946 | gen_movl_T0_reg(rd); |
1947 | break; | |
83469015 | 1948 | #endif |
cf495bcf FB |
1949 | case 0x30: |
1950 | { | |
cf495bcf | 1951 | switch(rd) { |
3475187d FB |
1952 | case 0: /* wry */ |
1953 | gen_op_xor_T1_T0(); | |
1954 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, y)); | |
cf495bcf | 1955 | break; |
65fe7b09 BS |
1956 | #ifndef TARGET_SPARC64 |
1957 | case 0x01 ... 0x0f: /* undefined in the | |
1958 | SPARCv8 manual, nop | |
1959 | on the microSPARC | |
1960 | II */ | |
1961 | case 0x10 ... 0x1f: /* implementation-dependent | |
1962 | in the SPARCv8 | |
1963 | manual, nop on the | |
1964 | microSPARC II */ | |
1965 | break; | |
1966 | #else | |
af7bf89b | 1967 | case 0x2: /* V9 wrccr */ |
3475187d FB |
1968 | gen_op_wrccr(); |
1969 | break; | |
af7bf89b | 1970 | case 0x3: /* V9 wrasi */ |
3475187d FB |
1971 | gen_op_movl_env_T0(offsetof(CPUSPARCState, asi)); |
1972 | break; | |
af7bf89b | 1973 | case 0x6: /* V9 wrfprs */ |
3299908c | 1974 | gen_op_xor_T1_T0(); |
3475187d | 1975 | gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs)); |
3299908c BS |
1976 | save_state(dc); |
1977 | gen_op_next_insn(); | |
1978 | gen_op_movl_T0_0(); | |
1979 | gen_op_exit_tb(); | |
1980 | dc->is_br = 1; | |
3475187d FB |
1981 | break; |
1982 | case 0xf: /* V9 sir, nop if user */ | |
1983 | #if !defined(CONFIG_USER_ONLY) | |
1984 | if (supervisor(dc)) | |
1985 | gen_op_sir(); | |
1986 | #endif | |
1987 | break; | |
725cb90b FB |
1988 | case 0x13: /* Graphics Status */ |
1989 | if (gen_trap_ifnofpu(dc)) | |
1990 | goto jmp_insn; | |
1991 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr)); | |
1992 | break; | |
83469015 FB |
1993 | case 0x17: /* Tick compare */ |
1994 | #if !defined(CONFIG_USER_ONLY) | |
1995 | if (!supervisor(dc)) | |
1996 | goto illegal_insn; | |
1997 | #endif | |
20c9f095 BS |
1998 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr)); |
1999 | gen_op_wrtick_cmpr(); | |
83469015 FB |
2000 | break; |
2001 | case 0x18: /* System tick */ | |
2002 | #if !defined(CONFIG_USER_ONLY) | |
2003 | if (!supervisor(dc)) | |
2004 | goto illegal_insn; | |
2005 | #endif | |
20c9f095 | 2006 | gen_op_wrstick(); |
83469015 FB |
2007 | break; |
2008 | case 0x19: /* System tick compare */ | |
2009 | #if !defined(CONFIG_USER_ONLY) | |
2010 | if (!supervisor(dc)) | |
2011 | goto illegal_insn; | |
3475187d | 2012 | #endif |
20c9f095 BS |
2013 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr)); |
2014 | gen_op_wrstick_cmpr(); | |
83469015 FB |
2015 | break; |
2016 | ||
3475187d FB |
2017 | case 0x10: /* Performance Control */ |
2018 | case 0x11: /* Performance Instrumentation Counter */ | |
2019 | case 0x12: /* Dispatch Control */ | |
3475187d FB |
2020 | case 0x14: /* Softint set */ |
2021 | case 0x15: /* Softint clear */ | |
2022 | case 0x16: /* Softint write */ | |
83469015 | 2023 | #endif |
3475187d | 2024 | default: |
cf495bcf FB |
2025 | goto illegal_insn; |
2026 | } | |
2027 | } | |
2028 | break; | |
e8af50a3 | 2029 | #if !defined(CONFIG_USER_ONLY) |
af7bf89b | 2030 | case 0x31: /* wrpsr, V9 saved, restored */ |
e8af50a3 FB |
2031 | { |
2032 | if (!supervisor(dc)) | |
2033 | goto priv_insn; | |
3475187d FB |
2034 | #ifdef TARGET_SPARC64 |
2035 | switch (rd) { | |
2036 | case 0: | |
2037 | gen_op_saved(); | |
2038 | break; | |
2039 | case 1: | |
2040 | gen_op_restored(); | |
2041 | break; | |
e9ebed4d BS |
2042 | case 2: /* UA2005 allclean */ |
2043 | case 3: /* UA2005 otherw */ | |
2044 | case 4: /* UA2005 normalw */ | |
2045 | case 5: /* UA2005 invalw */ | |
2046 | // XXX | |
3475187d FB |
2047 | default: |
2048 | goto illegal_insn; | |
2049 | } | |
2050 | #else | |
e8af50a3 FB |
2051 | gen_op_xor_T1_T0(); |
2052 | gen_op_wrpsr(); | |
9e61bde5 FB |
2053 | save_state(dc); |
2054 | gen_op_next_insn(); | |
2055 | gen_op_movl_T0_0(); | |
2056 | gen_op_exit_tb(); | |
2057 | dc->is_br = 1; | |
3475187d | 2058 | #endif |
e8af50a3 FB |
2059 | } |
2060 | break; | |
af7bf89b | 2061 | case 0x32: /* wrwim, V9 wrpr */ |
e8af50a3 FB |
2062 | { |
2063 | if (!supervisor(dc)) | |
2064 | goto priv_insn; | |
2065 | gen_op_xor_T1_T0(); | |
3475187d FB |
2066 | #ifdef TARGET_SPARC64 |
2067 | switch (rd) { | |
2068 | case 0: // tpc | |
2069 | gen_op_wrtpc(); | |
2070 | break; | |
2071 | case 1: // tnpc | |
2072 | gen_op_wrtnpc(); | |
2073 | break; | |
2074 | case 2: // tstate | |
2075 | gen_op_wrtstate(); | |
2076 | break; | |
2077 | case 3: // tt | |
2078 | gen_op_wrtt(); | |
2079 | break; | |
2080 | case 4: // tick | |
2081 | gen_op_wrtick(); | |
2082 | break; | |
2083 | case 5: // tba | |
83469015 | 2084 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr)); |
3475187d FB |
2085 | break; |
2086 | case 6: // pstate | |
2087 | gen_op_wrpstate(); | |
ded3ab80 PB |
2088 | save_state(dc); |
2089 | gen_op_next_insn(); | |
2090 | gen_op_movl_T0_0(); | |
2091 | gen_op_exit_tb(); | |
2092 | dc->is_br = 1; | |
3475187d FB |
2093 | break; |
2094 | case 7: // tl | |
2095 | gen_op_movl_env_T0(offsetof(CPUSPARCState, tl)); | |
2096 | break; | |
2097 | case 8: // pil | |
2098 | gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil)); | |
2099 | break; | |
2100 | case 9: // cwp | |
2101 | gen_op_wrcwp(); | |
2102 | break; | |
2103 | case 10: // cansave | |
2104 | gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave)); | |
2105 | break; | |
2106 | case 11: // canrestore | |
2107 | gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore)); | |
2108 | break; | |
2109 | case 12: // cleanwin | |
2110 | gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin)); | |
2111 | break; | |
2112 | case 13: // otherwin | |
2113 | gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin)); | |
2114 | break; | |
2115 | case 14: // wstate | |
2116 | gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate)); | |
2117 | break; | |
e9ebed4d BS |
2118 | case 16: // UA2005 gl |
2119 | gen_op_movl_env_T0(offsetof(CPUSPARCState, gl)); | |
2120 | break; | |
2121 | case 26: // UA2005 strand status | |
2122 | if (!hypervisor(dc)) | |
2123 | goto priv_insn; | |
2124 | gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr)); | |
2125 | break; | |
3475187d FB |
2126 | default: |
2127 | goto illegal_insn; | |
2128 | } | |
2129 | #else | |
c688a6eb | 2130 | gen_op_wrwim(); |
3475187d | 2131 | #endif |
e8af50a3 FB |
2132 | } |
2133 | break; | |
e9ebed4d | 2134 | case 0x33: /* wrtbr, UA2005 wrhpr */ |
e8af50a3 | 2135 | { |
e9ebed4d | 2136 | #ifndef TARGET_SPARC64 |
e8af50a3 FB |
2137 | if (!supervisor(dc)) |
2138 | goto priv_insn; | |
2139 | gen_op_xor_T1_T0(); | |
e9ebed4d BS |
2140 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr)); |
2141 | #else | |
2142 | if (!hypervisor(dc)) | |
2143 | goto priv_insn; | |
2144 | gen_op_xor_T1_T0(); | |
2145 | switch (rd) { | |
2146 | case 0: // hpstate | |
2147 | // XXX gen_op_wrhpstate(); | |
2148 | save_state(dc); | |
2149 | gen_op_next_insn(); | |
2150 | gen_op_movl_T0_0(); | |
2151 | gen_op_exit_tb(); | |
2152 | dc->is_br = 1; | |
2153 | break; | |
2154 | case 1: // htstate | |
2155 | // XXX gen_op_wrhtstate(); | |
2156 | break; | |
2157 | case 3: // hintp | |
2158 | gen_op_movl_env_T0(offsetof(CPUSPARCState, hintp)); | |
2159 | break; | |
2160 | case 5: // htba | |
2161 | gen_op_movl_env_T0(offsetof(CPUSPARCState, htba)); | |
2162 | break; | |
2163 | case 31: // hstick_cmpr | |
20c9f095 BS |
2164 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, hstick_cmpr)); |
2165 | gen_op_wrhstick_cmpr(); | |
e9ebed4d BS |
2166 | break; |
2167 | case 6: // hver readonly | |
2168 | default: | |
2169 | goto illegal_insn; | |
2170 | } | |
2171 | #endif | |
e8af50a3 FB |
2172 | } |
2173 | break; | |
2174 | #endif | |
3475187d | 2175 | #ifdef TARGET_SPARC64 |
af7bf89b | 2176 | case 0x2c: /* V9 movcc */ |
3475187d FB |
2177 | { |
2178 | int cc = GET_FIELD_SP(insn, 11, 12); | |
2179 | int cond = GET_FIELD_SP(insn, 14, 17); | |
2180 | if (IS_IMM) { /* immediate */ | |
2181 | rs2 = GET_FIELD_SPs(insn, 0, 10); | |
2182 | gen_movl_simm_T1(rs2); | |
2183 | } | |
2184 | else { | |
2185 | rs2 = GET_FIELD_SP(insn, 0, 4); | |
2186 | gen_movl_reg_T1(rs2); | |
2187 | } | |
2188 | gen_movl_reg_T0(rd); | |
2189 | flush_T2(dc); | |
2190 | if (insn & (1 << 18)) { | |
2191 | if (cc == 0) | |
2192 | gen_cond[0][cond](); | |
2193 | else if (cc == 2) | |
2194 | gen_cond[1][cond](); | |
2195 | else | |
2196 | goto illegal_insn; | |
2197 | } else { | |
2198 | gen_fcond[cc][cond](); | |
2199 | } | |
2200 | gen_op_mov_cc(); | |
2201 | gen_movl_T0_reg(rd); | |
2202 | break; | |
2203 | } | |
af7bf89b | 2204 | case 0x2d: /* V9 sdivx */ |
3475187d FB |
2205 | gen_op_sdivx_T1_T0(); |
2206 | gen_movl_T0_reg(rd); | |
2207 | break; | |
af7bf89b | 2208 | case 0x2e: /* V9 popc */ |
3475187d FB |
2209 | { |
2210 | if (IS_IMM) { /* immediate */ | |
2211 | rs2 = GET_FIELD_SPs(insn, 0, 12); | |
2212 | gen_movl_simm_T1(rs2); | |
2213 | // XXX optimize: popc(constant) | |
2214 | } | |
2215 | else { | |
2216 | rs2 = GET_FIELD_SP(insn, 0, 4); | |
2217 | gen_movl_reg_T1(rs2); | |
2218 | } | |
2219 | gen_op_popc(); | |
2220 | gen_movl_T0_reg(rd); | |
2221 | } | |
af7bf89b | 2222 | case 0x2f: /* V9 movr */ |
3475187d FB |
2223 | { |
2224 | int cond = GET_FIELD_SP(insn, 10, 12); | |
2225 | rs1 = GET_FIELD(insn, 13, 17); | |
2226 | flush_T2(dc); | |
2227 | gen_movl_reg_T0(rs1); | |
2228 | gen_cond_reg(cond); | |
2229 | if (IS_IMM) { /* immediate */ | |
46d38ba8 | 2230 | rs2 = GET_FIELD_SPs(insn, 0, 9); |
3475187d FB |
2231 | gen_movl_simm_T1(rs2); |
2232 | } | |
2233 | else { | |
2234 | rs2 = GET_FIELD_SP(insn, 0, 4); | |
2235 | gen_movl_reg_T1(rs2); | |
2236 | } | |
2237 | gen_movl_reg_T0(rd); | |
2238 | gen_op_mov_cc(); | |
2239 | gen_movl_T0_reg(rd); | |
2240 | break; | |
2241 | } | |
3475187d FB |
2242 | #endif |
2243 | default: | |
e80cfcfc FB |
2244 | goto illegal_insn; |
2245 | } | |
2246 | } | |
3299908c BS |
2247 | } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */ |
2248 | #ifdef TARGET_SPARC64 | |
2249 | int opf = GET_FIELD_SP(insn, 5, 13); | |
2250 | rs1 = GET_FIELD(insn, 13, 17); | |
2251 | rs2 = GET_FIELD(insn, 27, 31); | |
e9ebed4d BS |
2252 | if (gen_trap_ifnofpu(dc)) |
2253 | goto jmp_insn; | |
3299908c BS |
2254 | |
2255 | switch (opf) { | |
e9ebed4d BS |
2256 | case 0x000: /* VIS I edge8cc */ |
2257 | case 0x001: /* VIS II edge8n */ | |
2258 | case 0x002: /* VIS I edge8lcc */ | |
2259 | case 0x003: /* VIS II edge8ln */ | |
2260 | case 0x004: /* VIS I edge16cc */ | |
2261 | case 0x005: /* VIS II edge16n */ | |
2262 | case 0x006: /* VIS I edge16lcc */ | |
2263 | case 0x007: /* VIS II edge16ln */ | |
2264 | case 0x008: /* VIS I edge32cc */ | |
2265 | case 0x009: /* VIS II edge32n */ | |
2266 | case 0x00a: /* VIS I edge32lcc */ | |
2267 | case 0x00b: /* VIS II edge32ln */ | |
2268 | // XXX | |
2269 | goto illegal_insn; | |
2270 | case 0x010: /* VIS I array8 */ | |
2271 | gen_movl_reg_T0(rs1); | |
2272 | gen_movl_reg_T1(rs2); | |
2273 | gen_op_array8(); | |
2274 | gen_movl_T0_reg(rd); | |
2275 | break; | |
2276 | case 0x012: /* VIS I array16 */ | |
2277 | gen_movl_reg_T0(rs1); | |
2278 | gen_movl_reg_T1(rs2); | |
2279 | gen_op_array16(); | |
2280 | gen_movl_T0_reg(rd); | |
2281 | break; | |
2282 | case 0x014: /* VIS I array32 */ | |
2283 | gen_movl_reg_T0(rs1); | |
2284 | gen_movl_reg_T1(rs2); | |
2285 | gen_op_array32(); | |
2286 | gen_movl_T0_reg(rd); | |
2287 | break; | |
3299908c | 2288 | case 0x018: /* VIS I alignaddr */ |
3299908c BS |
2289 | gen_movl_reg_T0(rs1); |
2290 | gen_movl_reg_T1(rs2); | |
2291 | gen_op_alignaddr(); | |
2292 | gen_movl_T0_reg(rd); | |
2293 | break; | |
e9ebed4d | 2294 | case 0x019: /* VIS II bmask */ |
3299908c | 2295 | case 0x01a: /* VIS I alignaddrl */ |
3299908c | 2296 | // XXX |
e9ebed4d BS |
2297 | goto illegal_insn; |
2298 | case 0x020: /* VIS I fcmple16 */ | |
2299 | gen_op_load_fpr_DT0(rs1); | |
2300 | gen_op_load_fpr_DT1(rs2); | |
2301 | gen_op_fcmple16(); | |
2302 | gen_op_store_DT0_fpr(rd); | |
2303 | break; | |
2304 | case 0x022: /* VIS I fcmpne16 */ | |
2305 | gen_op_load_fpr_DT0(rs1); | |
2306 | gen_op_load_fpr_DT1(rs2); | |
2307 | gen_op_fcmpne16(); | |
2308 | gen_op_store_DT0_fpr(rd); | |
3299908c | 2309 | break; |
e9ebed4d BS |
2310 | case 0x024: /* VIS I fcmple32 */ |
2311 | gen_op_load_fpr_DT0(rs1); | |
2312 | gen_op_load_fpr_DT1(rs2); | |
2313 | gen_op_fcmple32(); | |
2314 | gen_op_store_DT0_fpr(rd); | |
2315 | break; | |
2316 | case 0x026: /* VIS I fcmpne32 */ | |
2317 | gen_op_load_fpr_DT0(rs1); | |
2318 | gen_op_load_fpr_DT1(rs2); | |
2319 | gen_op_fcmpne32(); | |
2320 | gen_op_store_DT0_fpr(rd); | |
2321 | break; | |
2322 | case 0x028: /* VIS I fcmpgt16 */ | |
2323 | gen_op_load_fpr_DT0(rs1); | |
2324 | gen_op_load_fpr_DT1(rs2); | |
2325 | gen_op_fcmpgt16(); | |
2326 | gen_op_store_DT0_fpr(rd); | |
2327 | break; | |
2328 | case 0x02a: /* VIS I fcmpeq16 */ | |
2329 | gen_op_load_fpr_DT0(rs1); | |
2330 | gen_op_load_fpr_DT1(rs2); | |
2331 | gen_op_fcmpeq16(); | |
2332 | gen_op_store_DT0_fpr(rd); | |
2333 | break; | |
2334 | case 0x02c: /* VIS I fcmpgt32 */ | |
2335 | gen_op_load_fpr_DT0(rs1); | |
2336 | gen_op_load_fpr_DT1(rs2); | |
2337 | gen_op_fcmpgt32(); | |
2338 | gen_op_store_DT0_fpr(rd); | |
2339 | break; | |
2340 | case 0x02e: /* VIS I fcmpeq32 */ | |
2341 | gen_op_load_fpr_DT0(rs1); | |
2342 | gen_op_load_fpr_DT1(rs2); | |
2343 | gen_op_fcmpeq32(); | |
2344 | gen_op_store_DT0_fpr(rd); | |
2345 | break; | |
2346 | case 0x031: /* VIS I fmul8x16 */ | |
2347 | gen_op_load_fpr_DT0(rs1); | |
2348 | gen_op_load_fpr_DT1(rs2); | |
2349 | gen_op_fmul8x16(); | |
2350 | gen_op_store_DT0_fpr(rd); | |
2351 | break; | |
2352 | case 0x033: /* VIS I fmul8x16au */ | |
2353 | gen_op_load_fpr_DT0(rs1); | |
2354 | gen_op_load_fpr_DT1(rs2); | |
2355 | gen_op_fmul8x16au(); | |
2356 | gen_op_store_DT0_fpr(rd); | |
2357 | break; | |
2358 | case 0x035: /* VIS I fmul8x16al */ | |
2359 | gen_op_load_fpr_DT0(rs1); | |
2360 | gen_op_load_fpr_DT1(rs2); | |
2361 | gen_op_fmul8x16al(); | |
2362 | gen_op_store_DT0_fpr(rd); | |
2363 | break; | |
2364 | case 0x036: /* VIS I fmul8sux16 */ | |
2365 | gen_op_load_fpr_DT0(rs1); | |
2366 | gen_op_load_fpr_DT1(rs2); | |
2367 | gen_op_fmul8sux16(); | |
2368 | gen_op_store_DT0_fpr(rd); | |
2369 | break; | |
2370 | case 0x037: /* VIS I fmul8ulx16 */ | |
2371 | gen_op_load_fpr_DT0(rs1); | |
2372 | gen_op_load_fpr_DT1(rs2); | |
2373 | gen_op_fmul8ulx16(); | |
2374 | gen_op_store_DT0_fpr(rd); | |
2375 | break; | |
2376 | case 0x038: /* VIS I fmuld8sux16 */ | |
2377 | gen_op_load_fpr_DT0(rs1); | |
2378 | gen_op_load_fpr_DT1(rs2); | |
2379 | gen_op_fmuld8sux16(); | |
2380 | gen_op_store_DT0_fpr(rd); | |
2381 | break; | |
2382 | case 0x039: /* VIS I fmuld8ulx16 */ | |
2383 | gen_op_load_fpr_DT0(rs1); | |
2384 | gen_op_load_fpr_DT1(rs2); | |
2385 | gen_op_fmuld8ulx16(); | |
2386 | gen_op_store_DT0_fpr(rd); | |
2387 | break; | |
2388 | case 0x03a: /* VIS I fpack32 */ | |
2389 | case 0x03b: /* VIS I fpack16 */ | |
2390 | case 0x03d: /* VIS I fpackfix */ | |
2391 | case 0x03e: /* VIS I pdist */ | |
2392 | // XXX | |
2393 | goto illegal_insn; | |
3299908c | 2394 | case 0x048: /* VIS I faligndata */ |
3299908c BS |
2395 | gen_op_load_fpr_DT0(rs1); |
2396 | gen_op_load_fpr_DT1(rs2); | |
2397 | gen_op_faligndata(); | |
2398 | gen_op_store_DT0_fpr(rd); | |
2399 | break; | |
e9ebed4d BS |
2400 | case 0x04b: /* VIS I fpmerge */ |
2401 | gen_op_load_fpr_DT0(rs1); | |
2402 | gen_op_load_fpr_DT1(rs2); | |
2403 | gen_op_fpmerge(); | |
2404 | gen_op_store_DT0_fpr(rd); | |
2405 | break; | |
2406 | case 0x04c: /* VIS II bshuffle */ | |
2407 | // XXX | |
2408 | goto illegal_insn; | |
2409 | case 0x04d: /* VIS I fexpand */ | |
2410 | gen_op_load_fpr_DT0(rs1); | |
2411 | gen_op_load_fpr_DT1(rs2); | |
2412 | gen_op_fexpand(); | |
2413 | gen_op_store_DT0_fpr(rd); | |
2414 | break; | |
2415 | case 0x050: /* VIS I fpadd16 */ | |
2416 | gen_op_load_fpr_DT0(rs1); | |
2417 | gen_op_load_fpr_DT1(rs2); | |
2418 | gen_op_fpadd16(); | |
2419 | gen_op_store_DT0_fpr(rd); | |
2420 | break; | |
2421 | case 0x051: /* VIS I fpadd16s */ | |
2422 | gen_op_load_fpr_FT0(rs1); | |
2423 | gen_op_load_fpr_FT1(rs2); | |
2424 | gen_op_fpadd16s(); | |
2425 | gen_op_store_FT0_fpr(rd); | |
2426 | break; | |
2427 | case 0x052: /* VIS I fpadd32 */ | |
2428 | gen_op_load_fpr_DT0(rs1); | |
2429 | gen_op_load_fpr_DT1(rs2); | |
2430 | gen_op_fpadd32(); | |
2431 | gen_op_store_DT0_fpr(rd); | |
2432 | break; | |
2433 | case 0x053: /* VIS I fpadd32s */ | |
2434 | gen_op_load_fpr_FT0(rs1); | |
2435 | gen_op_load_fpr_FT1(rs2); | |
2436 | gen_op_fpadd32s(); | |
2437 | gen_op_store_FT0_fpr(rd); | |
2438 | break; | |
2439 | case 0x054: /* VIS I fpsub16 */ | |
2440 | gen_op_load_fpr_DT0(rs1); | |
2441 | gen_op_load_fpr_DT1(rs2); | |
2442 | gen_op_fpsub16(); | |
2443 | gen_op_store_DT0_fpr(rd); | |
2444 | break; | |
2445 | case 0x055: /* VIS I fpsub16s */ | |
2446 | gen_op_load_fpr_FT0(rs1); | |
2447 | gen_op_load_fpr_FT1(rs2); | |
2448 | gen_op_fpsub16s(); | |
2449 | gen_op_store_FT0_fpr(rd); | |
2450 | break; | |
2451 | case 0x056: /* VIS I fpsub32 */ | |
2452 | gen_op_load_fpr_DT0(rs1); | |
2453 | gen_op_load_fpr_DT1(rs2); | |
2454 | gen_op_fpadd32(); | |
2455 | gen_op_store_DT0_fpr(rd); | |
2456 | break; | |
2457 | case 0x057: /* VIS I fpsub32s */ | |
2458 | gen_op_load_fpr_FT0(rs1); | |
2459 | gen_op_load_fpr_FT1(rs2); | |
2460 | gen_op_fpsub32s(); | |
2461 | gen_op_store_FT0_fpr(rd); | |
2462 | break; | |
3299908c | 2463 | case 0x060: /* VIS I fzero */ |
3299908c BS |
2464 | gen_op_movl_DT0_0(); |
2465 | gen_op_store_DT0_fpr(rd); | |
2466 | break; | |
2467 | case 0x061: /* VIS I fzeros */ | |
3299908c BS |
2468 | gen_op_movl_FT0_0(); |
2469 | gen_op_store_FT0_fpr(rd); | |
2470 | break; | |
e9ebed4d BS |
2471 | case 0x062: /* VIS I fnor */ |
2472 | gen_op_load_fpr_DT0(rs1); | |
2473 | gen_op_load_fpr_DT1(rs2); | |
2474 | gen_op_fnor(); | |
2475 | gen_op_store_DT0_fpr(rd); | |
2476 | break; | |
2477 | case 0x063: /* VIS I fnors */ | |
2478 | gen_op_load_fpr_FT0(rs1); | |
2479 | gen_op_load_fpr_FT1(rs2); | |
2480 | gen_op_fnors(); | |
2481 | gen_op_store_FT0_fpr(rd); | |
2482 | break; | |
2483 | case 0x064: /* VIS I fandnot2 */ | |
2484 | gen_op_load_fpr_DT1(rs1); | |
2485 | gen_op_load_fpr_DT0(rs2); | |
2486 | gen_op_fandnot(); | |
2487 | gen_op_store_DT0_fpr(rd); | |
2488 | break; | |
2489 | case 0x065: /* VIS I fandnot2s */ | |
2490 | gen_op_load_fpr_FT1(rs1); | |
2491 | gen_op_load_fpr_FT0(rs2); | |
2492 | gen_op_fandnots(); | |
2493 | gen_op_store_FT0_fpr(rd); | |
2494 | break; | |
2495 | case 0x066: /* VIS I fnot2 */ | |
2496 | gen_op_load_fpr_DT1(rs2); | |
2497 | gen_op_fnot(); | |
2498 | gen_op_store_DT0_fpr(rd); | |
2499 | break; | |
2500 | case 0x067: /* VIS I fnot2s */ | |
2501 | gen_op_load_fpr_FT1(rs2); | |
2502 | gen_op_fnot(); | |
2503 | gen_op_store_FT0_fpr(rd); | |
2504 | break; | |
2505 | case 0x068: /* VIS I fandnot1 */ | |
2506 | gen_op_load_fpr_DT0(rs1); | |
2507 | gen_op_load_fpr_DT1(rs2); | |
2508 | gen_op_fandnot(); | |
2509 | gen_op_store_DT0_fpr(rd); | |
2510 | break; | |
2511 | case 0x069: /* VIS I fandnot1s */ | |
2512 | gen_op_load_fpr_FT0(rs1); | |
2513 | gen_op_load_fpr_FT1(rs2); | |
2514 | gen_op_fandnots(); | |
2515 | gen_op_store_FT0_fpr(rd); | |
2516 | break; | |
2517 | case 0x06a: /* VIS I fnot1 */ | |
2518 | gen_op_load_fpr_DT1(rs1); | |
2519 | gen_op_fnot(); | |
2520 | gen_op_store_DT0_fpr(rd); | |
2521 | break; | |
2522 | case 0x06b: /* VIS I fnot1s */ | |
2523 | gen_op_load_fpr_FT1(rs1); | |
2524 | gen_op_fnot(); | |
2525 | gen_op_store_FT0_fpr(rd); | |
2526 | break; | |
2527 | case 0x06c: /* VIS I fxor */ | |
2528 | gen_op_load_fpr_DT0(rs1); | |
2529 | gen_op_load_fpr_DT1(rs2); | |
2530 | gen_op_fxor(); | |
2531 | gen_op_store_DT0_fpr(rd); | |
2532 | break; | |
2533 | case 0x06d: /* VIS I fxors */ | |
2534 | gen_op_load_fpr_FT0(rs1); | |
2535 | gen_op_load_fpr_FT1(rs2); | |
2536 | gen_op_fxors(); | |
2537 | gen_op_store_FT0_fpr(rd); | |
2538 | break; | |
2539 | case 0x06e: /* VIS I fnand */ | |
2540 | gen_op_load_fpr_DT0(rs1); | |
2541 | gen_op_load_fpr_DT1(rs2); | |
2542 | gen_op_fnand(); | |
2543 | gen_op_store_DT0_fpr(rd); | |
2544 | break; | |
2545 | case 0x06f: /* VIS I fnands */ | |
2546 | gen_op_load_fpr_FT0(rs1); | |
2547 | gen_op_load_fpr_FT1(rs2); | |
2548 | gen_op_fnands(); | |
2549 | gen_op_store_FT0_fpr(rd); | |
2550 | break; | |
2551 | case 0x070: /* VIS I fand */ | |
2552 | gen_op_load_fpr_DT0(rs1); | |
2553 | gen_op_load_fpr_DT1(rs2); | |
2554 | gen_op_fand(); | |
2555 | gen_op_store_DT0_fpr(rd); | |
2556 | break; | |
2557 | case 0x071: /* VIS I fands */ | |
2558 | gen_op_load_fpr_FT0(rs1); | |
2559 | gen_op_load_fpr_FT1(rs2); | |
2560 | gen_op_fands(); | |
2561 | gen_op_store_FT0_fpr(rd); | |
2562 | break; | |
2563 | case 0x072: /* VIS I fxnor */ | |
2564 | gen_op_load_fpr_DT0(rs1); | |
2565 | gen_op_load_fpr_DT1(rs2); | |
2566 | gen_op_fxnor(); | |
2567 | gen_op_store_DT0_fpr(rd); | |
2568 | break; | |
2569 | case 0x073: /* VIS I fxnors */ | |
2570 | gen_op_load_fpr_FT0(rs1); | |
2571 | gen_op_load_fpr_FT1(rs2); | |
2572 | gen_op_fxnors(); | |
2573 | gen_op_store_FT0_fpr(rd); | |
2574 | break; | |
3299908c | 2575 | case 0x074: /* VIS I fsrc1 */ |
3299908c BS |
2576 | gen_op_load_fpr_DT0(rs1); |
2577 | gen_op_store_DT0_fpr(rd); | |
2578 | break; | |
2579 | case 0x075: /* VIS I fsrc1s */ | |
3299908c BS |
2580 | gen_op_load_fpr_FT0(rs1); |
2581 | gen_op_store_FT0_fpr(rd); | |
2582 | break; | |
e9ebed4d BS |
2583 | case 0x076: /* VIS I fornot2 */ |
2584 | gen_op_load_fpr_DT1(rs1); | |
2585 | gen_op_load_fpr_DT0(rs2); | |
2586 | gen_op_fornot(); | |
2587 | gen_op_store_DT0_fpr(rd); | |
2588 | break; | |
2589 | case 0x077: /* VIS I fornot2s */ | |
2590 | gen_op_load_fpr_FT1(rs1); | |
2591 | gen_op_load_fpr_FT0(rs2); | |
2592 | gen_op_fornots(); | |
2593 | gen_op_store_FT0_fpr(rd); | |
2594 | break; | |
3299908c | 2595 | case 0x078: /* VIS I fsrc2 */ |
3299908c BS |
2596 | gen_op_load_fpr_DT0(rs2); |
2597 | gen_op_store_DT0_fpr(rd); | |
2598 | break; | |
2599 | case 0x079: /* VIS I fsrc2s */ | |
3299908c BS |
2600 | gen_op_load_fpr_FT0(rs2); |
2601 | gen_op_store_FT0_fpr(rd); | |
2602 | break; | |
e9ebed4d BS |
2603 | case 0x07a: /* VIS I fornot1 */ |
2604 | gen_op_load_fpr_DT0(rs1); | |
2605 | gen_op_load_fpr_DT1(rs2); | |
2606 | gen_op_fornot(); | |
2607 | gen_op_store_DT0_fpr(rd); | |
2608 | break; | |
2609 | case 0x07b: /* VIS I fornot1s */ | |
2610 | gen_op_load_fpr_FT0(rs1); | |
2611 | gen_op_load_fpr_FT1(rs2); | |
2612 | gen_op_fornots(); | |
2613 | gen_op_store_FT0_fpr(rd); | |
2614 | break; | |
2615 | case 0x07c: /* VIS I for */ | |
2616 | gen_op_load_fpr_DT0(rs1); | |
2617 | gen_op_load_fpr_DT1(rs2); | |
2618 | gen_op_for(); | |
2619 | gen_op_store_DT0_fpr(rd); | |
2620 | break; | |
2621 | case 0x07d: /* VIS I fors */ | |
2622 | gen_op_load_fpr_FT0(rs1); | |
2623 | gen_op_load_fpr_FT1(rs2); | |
2624 | gen_op_fors(); | |
2625 | gen_op_store_FT0_fpr(rd); | |
2626 | break; | |
3299908c | 2627 | case 0x07e: /* VIS I fone */ |
3299908c BS |
2628 | gen_op_movl_DT0_1(); |
2629 | gen_op_store_DT0_fpr(rd); | |
2630 | break; | |
2631 | case 0x07f: /* VIS I fones */ | |
3299908c BS |
2632 | gen_op_movl_FT0_1(); |
2633 | gen_op_store_FT0_fpr(rd); | |
2634 | break; | |
e9ebed4d BS |
2635 | case 0x080: /* VIS I shutdown */ |
2636 | case 0x081: /* VIS II siam */ | |
2637 | // XXX | |
2638 | goto illegal_insn; | |
3299908c BS |
2639 | default: |
2640 | goto illegal_insn; | |
2641 | } | |
2642 | #else | |
2643 | goto ncp_insn; | |
2644 | #endif | |
2645 | } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */ | |
fcc72045 BS |
2646 | #ifdef TARGET_SPARC64 |
2647 | goto illegal_insn; | |
2648 | #else | |
2649 | goto ncp_insn; | |
2650 | #endif | |
3475187d FB |
2651 | #ifdef TARGET_SPARC64 |
2652 | } else if (xop == 0x39) { /* V9 return */ | |
3475187d | 2653 | rs1 = GET_FIELD(insn, 13, 17); |
1ad21e69 | 2654 | save_state(dc); |
3475187d FB |
2655 | gen_movl_reg_T0(rs1); |
2656 | if (IS_IMM) { /* immediate */ | |
2657 | rs2 = GET_FIELDs(insn, 19, 31); | |
2658 | #if defined(OPTIM) | |
2659 | if (rs2) { | |
2660 | #endif | |
2661 | gen_movl_simm_T1(rs2); | |
2662 | gen_op_add_T1_T0(); | |
2663 | #if defined(OPTIM) | |
2664 | } | |
2665 | #endif | |
2666 | } else { /* register */ | |
2667 | rs2 = GET_FIELD(insn, 27, 31); | |
2668 | #if defined(OPTIM) | |
2669 | if (rs2) { | |
2670 | #endif | |
2671 | gen_movl_reg_T1(rs2); | |
2672 | gen_op_add_T1_T0(); | |
2673 | #if defined(OPTIM) | |
2674 | } | |
2675 | #endif | |
2676 | } | |
83469015 | 2677 | gen_op_restore(); |
3475187d FB |
2678 | gen_mov_pc_npc(dc); |
2679 | gen_op_movl_npc_T0(); | |
2680 | dc->npc = DYNAMIC_PC; | |
2681 | goto jmp_insn; | |
2682 | #endif | |
e80cfcfc FB |
2683 | } else { |
2684 | rs1 = GET_FIELD(insn, 13, 17); | |
2685 | gen_movl_reg_T0(rs1); | |
2686 | if (IS_IMM) { /* immediate */ | |
2687 | rs2 = GET_FIELDs(insn, 19, 31); | |
2688 | #if defined(OPTIM) | |
2689 | if (rs2) { | |
e8af50a3 | 2690 | #endif |
3475187d | 2691 | gen_movl_simm_T1(rs2); |
e80cfcfc FB |
2692 | gen_op_add_T1_T0(); |
2693 | #if defined(OPTIM) | |
2694 | } | |
e8af50a3 | 2695 | #endif |
e80cfcfc FB |
2696 | } else { /* register */ |
2697 | rs2 = GET_FIELD(insn, 27, 31); | |
2698 | #if defined(OPTIM) | |
2699 | if (rs2) { | |
2700 | #endif | |
2701 | gen_movl_reg_T1(rs2); | |
2702 | gen_op_add_T1_T0(); | |
2703 | #if defined(OPTIM) | |
2704 | } | |
e8af50a3 | 2705 | #endif |
cf495bcf | 2706 | } |
e80cfcfc FB |
2707 | switch (xop) { |
2708 | case 0x38: /* jmpl */ | |
2709 | { | |
e80cfcfc | 2710 | if (rd != 0) { |
ded3ab80 PB |
2711 | #ifdef TARGET_SPARC64 |
2712 | if (dc->pc == (uint32_t)dc->pc) { | |
2713 | gen_op_movl_T1_im(dc->pc); | |
2714 | } else { | |
2715 | gen_op_movq_T1_im64(dc->pc >> 32, dc->pc); | |
2716 | } | |
2717 | #else | |
0bee699e | 2718 | gen_op_movl_T1_im(dc->pc); |
ded3ab80 | 2719 | #endif |
0bee699e | 2720 | gen_movl_T1_reg(rd); |
e80cfcfc | 2721 | } |
0bee699e FB |
2722 | gen_mov_pc_npc(dc); |
2723 | gen_op_movl_npc_T0(); | |
e80cfcfc FB |
2724 | dc->npc = DYNAMIC_PC; |
2725 | } | |
2726 | goto jmp_insn; | |
3475187d | 2727 | #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) |
af7bf89b | 2728 | case 0x39: /* rett, V9 return */ |
e80cfcfc FB |
2729 | { |
2730 | if (!supervisor(dc)) | |
2731 | goto priv_insn; | |
0bee699e | 2732 | gen_mov_pc_npc(dc); |
e80cfcfc | 2733 | gen_op_movl_npc_T0(); |
0bee699e | 2734 | dc->npc = DYNAMIC_PC; |
e80cfcfc FB |
2735 | gen_op_rett(); |
2736 | } | |
0bee699e | 2737 | goto jmp_insn; |
e80cfcfc FB |
2738 | #endif |
2739 | case 0x3b: /* flush */ | |
2740 | gen_op_flush_T0(); | |
2741 | break; | |
2742 | case 0x3c: /* save */ | |
2743 | save_state(dc); | |
2744 | gen_op_save(); | |
2745 | gen_movl_T0_reg(rd); | |
2746 | break; | |
2747 | case 0x3d: /* restore */ | |
2748 | save_state(dc); | |
2749 | gen_op_restore(); | |
2750 | gen_movl_T0_reg(rd); | |
2751 | break; | |
3475187d | 2752 | #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64) |
af7bf89b | 2753 | case 0x3e: /* V9 done/retry */ |
3475187d FB |
2754 | { |
2755 | switch (rd) { | |
2756 | case 0: | |
2757 | if (!supervisor(dc)) | |
2758 | goto priv_insn; | |
83469015 FB |
2759 | dc->npc = DYNAMIC_PC; |
2760 | dc->pc = DYNAMIC_PC; | |
3475187d | 2761 | gen_op_done(); |
83469015 | 2762 | goto jmp_insn; |
3475187d FB |
2763 | case 1: |
2764 | if (!supervisor(dc)) | |
2765 | goto priv_insn; | |
83469015 FB |
2766 | dc->npc = DYNAMIC_PC; |
2767 | dc->pc = DYNAMIC_PC; | |
3475187d | 2768 | gen_op_retry(); |
83469015 | 2769 | goto jmp_insn; |
3475187d FB |
2770 | default: |
2771 | goto illegal_insn; | |
2772 | } | |
2773 | } | |
2774 | break; | |
2775 | #endif | |
2776 | default: | |
e80cfcfc FB |
2777 | goto illegal_insn; |
2778 | } | |
cf495bcf FB |
2779 | } |
2780 | break; | |
2781 | } | |
af7bf89b | 2782 | break; |
cf495bcf FB |
2783 | case 3: /* load/store instructions */ |
2784 | { | |
2785 | unsigned int xop = GET_FIELD(insn, 7, 12); | |
2786 | rs1 = GET_FIELD(insn, 13, 17); | |
2371aaa2 | 2787 | save_state(dc); |
cf495bcf FB |
2788 | gen_movl_reg_T0(rs1); |
2789 | if (IS_IMM) { /* immediate */ | |
2790 | rs2 = GET_FIELDs(insn, 19, 31); | |
e80cfcfc | 2791 | #if defined(OPTIM) |
e8af50a3 | 2792 | if (rs2 != 0) { |
e80cfcfc | 2793 | #endif |
3475187d | 2794 | gen_movl_simm_T1(rs2); |
e8af50a3 | 2795 | gen_op_add_T1_T0(); |
e80cfcfc | 2796 | #if defined(OPTIM) |
e8af50a3 | 2797 | } |
e80cfcfc | 2798 | #endif |
cf495bcf FB |
2799 | } else { /* register */ |
2800 | rs2 = GET_FIELD(insn, 27, 31); | |
e80cfcfc FB |
2801 | #if defined(OPTIM) |
2802 | if (rs2 != 0) { | |
2803 | #endif | |
2804 | gen_movl_reg_T1(rs2); | |
2805 | gen_op_add_T1_T0(); | |
2806 | #if defined(OPTIM) | |
2807 | } | |
2808 | #endif | |
cf495bcf | 2809 | } |
2f2ecb83 BS |
2810 | if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || |
2811 | (xop > 0x17 && xop <= 0x1d ) || | |
2812 | (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) { | |
cf495bcf FB |
2813 | switch (xop) { |
2814 | case 0x0: /* load word */ | |
dc011987 | 2815 | #ifndef TARGET_SPARC64 |
e8af50a3 | 2816 | gen_op_ldst(ld); |
dc011987 BS |
2817 | #else |
2818 | gen_op_ldst(lduw); | |
2819 | #endif | |
cf495bcf FB |
2820 | break; |
2821 | case 0x1: /* load unsigned byte */ | |
e8af50a3 | 2822 | gen_op_ldst(ldub); |
cf495bcf FB |
2823 | break; |
2824 | case 0x2: /* load unsigned halfword */ | |
e8af50a3 | 2825 | gen_op_ldst(lduh); |
cf495bcf FB |
2826 | break; |
2827 | case 0x3: /* load double word */ | |
d4218d99 BS |
2828 | if (rd & 1) |
2829 | goto illegal_insn; | |
e8af50a3 | 2830 | gen_op_ldst(ldd); |
cf495bcf FB |
2831 | gen_movl_T0_reg(rd + 1); |
2832 | break; | |
2833 | case 0x9: /* load signed byte */ | |
e8af50a3 | 2834 | gen_op_ldst(ldsb); |
cf495bcf FB |
2835 | break; |
2836 | case 0xa: /* load signed halfword */ | |
e8af50a3 | 2837 | gen_op_ldst(ldsh); |
cf495bcf FB |
2838 | break; |
2839 | case 0xd: /* ldstub -- XXX: should be atomically */ | |
e8af50a3 | 2840 | gen_op_ldst(ldstub); |
cf495bcf FB |
2841 | break; |
2842 | case 0x0f: /* swap register with memory. Also atomically */ | |
e80cfcfc | 2843 | gen_movl_reg_T1(rd); |
e8af50a3 FB |
2844 | gen_op_ldst(swap); |
2845 | break; | |
3475187d | 2846 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) |
e8af50a3 | 2847 | case 0x10: /* load word alternate */ |
3475187d | 2848 | #ifndef TARGET_SPARC64 |
d4218d99 BS |
2849 | if (IS_IMM) |
2850 | goto illegal_insn; | |
e8af50a3 FB |
2851 | if (!supervisor(dc)) |
2852 | goto priv_insn; | |
2853 | gen_op_lda(insn, 1, 4, 0); | |
dc011987 BS |
2854 | #else |
2855 | gen_op_lduwa(insn, 1, 4, 0); | |
2856 | #endif | |
e8af50a3 FB |
2857 | break; |
2858 | case 0x11: /* load unsigned byte alternate */ | |
3475187d | 2859 | #ifndef TARGET_SPARC64 |
d4218d99 BS |
2860 | if (IS_IMM) |
2861 | goto illegal_insn; | |
e8af50a3 FB |
2862 | if (!supervisor(dc)) |
2863 | goto priv_insn; | |
3475187d | 2864 | #endif |
e8af50a3 FB |
2865 | gen_op_lduba(insn, 1, 1, 0); |
2866 | break; | |
2867 | case 0x12: /* load unsigned halfword alternate */ | |
3475187d | 2868 | #ifndef TARGET_SPARC64 |
d4218d99 BS |
2869 | if (IS_IMM) |
2870 | goto illegal_insn; | |
e8af50a3 FB |
2871 | if (!supervisor(dc)) |
2872 | goto priv_insn; | |
3475187d | 2873 | #endif |
e8af50a3 FB |
2874 | gen_op_lduha(insn, 1, 2, 0); |
2875 | break; | |
2876 | case 0x13: /* load double word alternate */ | |
3475187d | 2877 | #ifndef TARGET_SPARC64 |
d4218d99 BS |
2878 | if (IS_IMM) |
2879 | goto illegal_insn; | |
e8af50a3 FB |
2880 | if (!supervisor(dc)) |
2881 | goto priv_insn; | |
3475187d | 2882 | #endif |
d4218d99 BS |
2883 | if (rd & 1) |
2884 | goto illegal_insn; | |
e8af50a3 FB |
2885 | gen_op_ldda(insn, 1, 8, 0); |
2886 | gen_movl_T0_reg(rd + 1); | |
2887 | break; | |
2888 | case 0x19: /* load signed byte alternate */ | |
3475187d | 2889 | #ifndef TARGET_SPARC64 |
d4218d99 BS |
2890 | if (IS_IMM) |
2891 | goto illegal_insn; | |
e8af50a3 FB |
2892 | if (!supervisor(dc)) |
2893 | goto priv_insn; | |
3475187d | 2894 | #endif |
e8af50a3 FB |
2895 | gen_op_ldsba(insn, 1, 1, 1); |
2896 | break; | |
2897 | case 0x1a: /* load signed halfword alternate */ | |
3475187d | 2898 | #ifndef TARGET_SPARC64 |
d4218d99 BS |
2899 | if (IS_IMM) |
2900 | goto illegal_insn; | |
e8af50a3 FB |
2901 | if (!supervisor(dc)) |
2902 | goto priv_insn; | |
3475187d | 2903 | #endif |
e8af50a3 FB |
2904 | gen_op_ldsha(insn, 1, 2 ,1); |
2905 | break; | |
2906 | case 0x1d: /* ldstuba -- XXX: should be atomically */ | |
3475187d | 2907 | #ifndef TARGET_SPARC64 |
d4218d99 BS |
2908 | if (IS_IMM) |
2909 | goto illegal_insn; | |
e8af50a3 FB |
2910 | if (!supervisor(dc)) |
2911 | goto priv_insn; | |
3475187d | 2912 | #endif |
e8af50a3 FB |
2913 | gen_op_ldstuba(insn, 1, 1, 0); |
2914 | break; | |
2915 | case 0x1f: /* swap reg with alt. memory. Also atomically */ | |
3475187d | 2916 | #ifndef TARGET_SPARC64 |
d4218d99 BS |
2917 | if (IS_IMM) |
2918 | goto illegal_insn; | |
e8af50a3 FB |
2919 | if (!supervisor(dc)) |
2920 | goto priv_insn; | |
3475187d | 2921 | #endif |
e80cfcfc | 2922 | gen_movl_reg_T1(rd); |
e8af50a3 | 2923 | gen_op_swapa(insn, 1, 4, 0); |
cf495bcf | 2924 | break; |
3475187d FB |
2925 | |
2926 | #ifndef TARGET_SPARC64 | |
fcc72045 BS |
2927 | case 0x30: /* ldc */ |
2928 | case 0x31: /* ldcsr */ | |
2929 | case 0x33: /* lddc */ | |
fcc72045 | 2930 | goto ncp_insn; |
0fa85d43 FB |
2931 | /* avoid warnings */ |
2932 | (void) &gen_op_stfa; | |
2933 | (void) &gen_op_stdfa; | |
2934 | (void) &gen_op_ldfa; | |
2935 | (void) &gen_op_lddfa; | |
3475187d | 2936 | #else |
dc011987 | 2937 | (void) &gen_op_lda; |
3475187d FB |
2938 | #if !defined(CONFIG_USER_ONLY) |
2939 | (void) &gen_op_cas; | |
2940 | (void) &gen_op_casx; | |
e80cfcfc | 2941 | #endif |
3475187d FB |
2942 | #endif |
2943 | #endif | |
2944 | #ifdef TARGET_SPARC64 | |
af7bf89b | 2945 | case 0x08: /* V9 ldsw */ |
3475187d FB |
2946 | gen_op_ldst(ldsw); |
2947 | break; | |
af7bf89b | 2948 | case 0x0b: /* V9 ldx */ |
3475187d FB |
2949 | gen_op_ldst(ldx); |
2950 | break; | |
af7bf89b | 2951 | case 0x18: /* V9 ldswa */ |
3475187d FB |
2952 | gen_op_ldswa(insn, 1, 4, 1); |
2953 | break; | |
af7bf89b | 2954 | case 0x1b: /* V9 ldxa */ |
3475187d FB |
2955 | gen_op_ldxa(insn, 1, 8, 0); |
2956 | break; | |
2957 | case 0x2d: /* V9 prefetch, no effect */ | |
2958 | goto skip_move; | |
af7bf89b | 2959 | case 0x30: /* V9 ldfa */ |
3475187d FB |
2960 | gen_op_ldfa(insn, 1, 8, 0); // XXX |
2961 | break; | |
af7bf89b | 2962 | case 0x33: /* V9 lddfa */ |
3475187d | 2963 | gen_op_lddfa(insn, 1, 8, 0); // XXX |
af7bf89b | 2964 | |
3475187d FB |
2965 | break; |
2966 | case 0x3d: /* V9 prefetcha, no effect */ | |
2967 | goto skip_move; | |
af7bf89b | 2968 | case 0x32: /* V9 ldqfa */ |
3475187d FB |
2969 | goto nfpu_insn; |
2970 | #endif | |
2971 | default: | |
e80cfcfc | 2972 | goto illegal_insn; |
7a3f1944 | 2973 | } |
cf495bcf | 2974 | gen_movl_T1_reg(rd); |
3475187d FB |
2975 | #ifdef TARGET_SPARC64 |
2976 | skip_move: ; | |
2977 | #endif | |
e8af50a3 | 2978 | } else if (xop >= 0x20 && xop < 0x24) { |
a80dde08 FB |
2979 | if (gen_trap_ifnofpu(dc)) |
2980 | goto jmp_insn; | |
e8af50a3 FB |
2981 | switch (xop) { |
2982 | case 0x20: /* load fpreg */ | |
2983 | gen_op_ldst(ldf); | |
2984 | gen_op_store_FT0_fpr(rd); | |
2985 | break; | |
2986 | case 0x21: /* load fsr */ | |
9e61bde5 | 2987 | gen_op_ldst(ldf); |
e8af50a3 FB |
2988 | gen_op_ldfsr(); |
2989 | break; | |
af7bf89b FB |
2990 | case 0x22: /* load quad fpreg */ |
2991 | goto nfpu_insn; | |
e8af50a3 FB |
2992 | case 0x23: /* load double fpreg */ |
2993 | gen_op_ldst(lddf); | |
3475187d | 2994 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e8af50a3 | 2995 | break; |
e80cfcfc FB |
2996 | default: |
2997 | goto illegal_insn; | |
e8af50a3 | 2998 | } |
3475187d FB |
2999 | } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \ |
3000 | xop == 0xe || xop == 0x1e) { | |
cf495bcf FB |
3001 | gen_movl_reg_T1(rd); |
3002 | switch (xop) { | |
3003 | case 0x4: | |
e8af50a3 | 3004 | gen_op_ldst(st); |
cf495bcf FB |
3005 | break; |
3006 | case 0x5: | |
e8af50a3 | 3007 | gen_op_ldst(stb); |
cf495bcf FB |
3008 | break; |
3009 | case 0x6: | |
e8af50a3 | 3010 | gen_op_ldst(sth); |
cf495bcf FB |
3011 | break; |
3012 | case 0x7: | |
d4218d99 BS |
3013 | if (rd & 1) |
3014 | goto illegal_insn; | |
72cbca10 | 3015 | flush_T2(dc); |
cf495bcf | 3016 | gen_movl_reg_T2(rd + 1); |
e8af50a3 FB |
3017 | gen_op_ldst(std); |
3018 | break; | |
3475187d | 3019 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) |
e8af50a3 | 3020 | case 0x14: |
3475187d | 3021 | #ifndef TARGET_SPARC64 |
d4218d99 BS |
3022 | if (IS_IMM) |
3023 | goto illegal_insn; | |
e8af50a3 FB |
3024 | if (!supervisor(dc)) |
3025 | goto priv_insn; | |
3475187d | 3026 | #endif |
e8af50a3 | 3027 | gen_op_sta(insn, 0, 4, 0); |
d39c0b99 | 3028 | break; |
e8af50a3 | 3029 | case 0x15: |
3475187d | 3030 | #ifndef TARGET_SPARC64 |
d4218d99 BS |
3031 | if (IS_IMM) |
3032 | goto illegal_insn; | |
e8af50a3 FB |
3033 | if (!supervisor(dc)) |
3034 | goto priv_insn; | |
3475187d | 3035 | #endif |
e8af50a3 | 3036 | gen_op_stba(insn, 0, 1, 0); |
d39c0b99 | 3037 | break; |
e8af50a3 | 3038 | case 0x16: |
3475187d | 3039 | #ifndef TARGET_SPARC64 |
d4218d99 BS |
3040 | if (IS_IMM) |
3041 | goto illegal_insn; | |
e8af50a3 FB |
3042 | if (!supervisor(dc)) |
3043 | goto priv_insn; | |
3475187d | 3044 | #endif |
e8af50a3 | 3045 | gen_op_stha(insn, 0, 2, 0); |
d39c0b99 | 3046 | break; |
e8af50a3 | 3047 | case 0x17: |
3475187d | 3048 | #ifndef TARGET_SPARC64 |
d4218d99 BS |
3049 | if (IS_IMM) |
3050 | goto illegal_insn; | |
e8af50a3 FB |
3051 | if (!supervisor(dc)) |
3052 | goto priv_insn; | |
3475187d | 3053 | #endif |
d4218d99 BS |
3054 | if (rd & 1) |
3055 | goto illegal_insn; | |
e8af50a3 FB |
3056 | flush_T2(dc); |
3057 | gen_movl_reg_T2(rd + 1); | |
3058 | gen_op_stda(insn, 0, 8, 0); | |
d39c0b99 | 3059 | break; |
e80cfcfc | 3060 | #endif |
3475187d | 3061 | #ifdef TARGET_SPARC64 |
af7bf89b | 3062 | case 0x0e: /* V9 stx */ |
3475187d FB |
3063 | gen_op_ldst(stx); |
3064 | break; | |
af7bf89b | 3065 | case 0x1e: /* V9 stxa */ |
3475187d FB |
3066 | gen_op_stxa(insn, 0, 8, 0); // XXX |
3067 | break; | |
3068 | #endif | |
3069 | default: | |
e80cfcfc | 3070 | goto illegal_insn; |
7a3f1944 | 3071 | } |
e8af50a3 | 3072 | } else if (xop > 0x23 && xop < 0x28) { |
a80dde08 FB |
3073 | if (gen_trap_ifnofpu(dc)) |
3074 | goto jmp_insn; | |
e8af50a3 FB |
3075 | switch (xop) { |
3076 | case 0x24: | |
3077 | gen_op_load_fpr_FT0(rd); | |
3078 | gen_op_ldst(stf); | |
3079 | break; | |
af7bf89b | 3080 | case 0x25: /* stfsr, V9 stxfsr */ |
e8af50a3 | 3081 | gen_op_stfsr(); |
9e61bde5 | 3082 | gen_op_ldst(stf); |
e8af50a3 | 3083 | break; |
9143e598 | 3084 | #if !defined(CONFIG_USER_ONLY) |
af7bf89b | 3085 | case 0x26: /* stdfq */ |
9143e598 BS |
3086 | if (!supervisor(dc)) |
3087 | goto priv_insn; | |
3088 | if (gen_trap_ifnofpu(dc)) | |
3089 | goto jmp_insn; | |
3090 | goto nfq_insn; | |
3091 | #endif | |
e8af50a3 | 3092 | case 0x27: |
3475187d | 3093 | gen_op_load_fpr_DT0(DFPREG(rd)); |
e8af50a3 FB |
3094 | gen_op_ldst(stdf); |
3095 | break; | |
e80cfcfc | 3096 | default: |
3475187d FB |
3097 | goto illegal_insn; |
3098 | } | |
3099 | } else if (xop > 0x33 && xop < 0x3f) { | |
3475187d | 3100 | switch (xop) { |
a4d17f19 | 3101 | #ifdef TARGET_SPARC64 |
af7bf89b | 3102 | case 0x34: /* V9 stfa */ |
3475187d FB |
3103 | gen_op_stfa(insn, 0, 0, 0); // XXX |
3104 | break; | |
af7bf89b | 3105 | case 0x37: /* V9 stdfa */ |
3475187d FB |
3106 | gen_op_stdfa(insn, 0, 0, 0); // XXX |
3107 | break; | |
af7bf89b | 3108 | case 0x3c: /* V9 casa */ |
3475187d FB |
3109 | gen_op_casa(insn, 0, 4, 0); // XXX |
3110 | break; | |
af7bf89b | 3111 | case 0x3e: /* V9 casxa */ |
3475187d FB |
3112 | gen_op_casxa(insn, 0, 8, 0); // XXX |
3113 | break; | |
af7bf89b | 3114 | case 0x36: /* V9 stqfa */ |
3475187d | 3115 | goto nfpu_insn; |
a4d17f19 BS |
3116 | #else |
3117 | case 0x34: /* stc */ | |
3118 | case 0x35: /* stcsr */ | |
3119 | case 0x36: /* stdcq */ | |
3120 | case 0x37: /* stdc */ | |
3121 | goto ncp_insn; | |
3122 | #endif | |
3475187d | 3123 | default: |
e80cfcfc | 3124 | goto illegal_insn; |
e8af50a3 | 3125 | } |
e8af50a3 | 3126 | } |
e80cfcfc FB |
3127 | else |
3128 | goto illegal_insn; | |
7a3f1944 | 3129 | } |
af7bf89b | 3130 | break; |
cf495bcf FB |
3131 | } |
3132 | /* default case for non jump instructions */ | |
72cbca10 FB |
3133 | if (dc->npc == DYNAMIC_PC) { |
3134 | dc->pc = DYNAMIC_PC; | |
3135 | gen_op_next_insn(); | |
3136 | } else if (dc->npc == JUMP_PC) { | |
3137 | /* we can do a static jump */ | |
46525e1f | 3138 | gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1]); |
72cbca10 FB |
3139 | dc->is_br = 1; |
3140 | } else { | |
cf495bcf FB |
3141 | dc->pc = dc->npc; |
3142 | dc->npc = dc->npc + 4; | |
cf495bcf | 3143 | } |
e80cfcfc | 3144 | jmp_insn: |
cf495bcf FB |
3145 | return; |
3146 | illegal_insn: | |
72cbca10 | 3147 | save_state(dc); |
cf495bcf FB |
3148 | gen_op_exception(TT_ILL_INSN); |
3149 | dc->is_br = 1; | |
e8af50a3 | 3150 | return; |
e80cfcfc | 3151 | #if !defined(CONFIG_USER_ONLY) |
e8af50a3 FB |
3152 | priv_insn: |
3153 | save_state(dc); | |
3154 | gen_op_exception(TT_PRIV_INSN); | |
3155 | dc->is_br = 1; | |
e80cfcfc FB |
3156 | return; |
3157 | #endif | |
3158 | nfpu_insn: | |
3159 | save_state(dc); | |
3160 | gen_op_fpexception_im(FSR_FTT_UNIMPFPOP); | |
3161 | dc->is_br = 1; | |
fcc72045 | 3162 | return; |
9143e598 BS |
3163 | #if !defined(CONFIG_USER_ONLY) |
3164 | nfq_insn: | |
3165 | save_state(dc); | |
3166 | gen_op_fpexception_im(FSR_FTT_SEQ_ERROR); | |
3167 | dc->is_br = 1; | |
3168 | return; | |
3169 | #endif | |
fcc72045 BS |
3170 | #ifndef TARGET_SPARC64 |
3171 | ncp_insn: | |
3172 | save_state(dc); | |
3173 | gen_op_exception(TT_NCP_INSN); | |
3174 | dc->is_br = 1; | |
3175 | return; | |
3176 | #endif | |
7a3f1944 FB |
3177 | } |
3178 | ||
cf495bcf | 3179 | static inline int gen_intermediate_code_internal(TranslationBlock * tb, |
e8af50a3 | 3180 | int spc, CPUSPARCState *env) |
7a3f1944 | 3181 | { |
72cbca10 | 3182 | target_ulong pc_start, last_pc; |
cf495bcf FB |
3183 | uint16_t *gen_opc_end; |
3184 | DisasContext dc1, *dc = &dc1; | |
e8af50a3 | 3185 | int j, lj = -1; |
cf495bcf FB |
3186 | |
3187 | memset(dc, 0, sizeof(DisasContext)); | |
cf495bcf | 3188 | dc->tb = tb; |
72cbca10 | 3189 | pc_start = tb->pc; |
cf495bcf | 3190 | dc->pc = pc_start; |
e80cfcfc | 3191 | last_pc = dc->pc; |
72cbca10 | 3192 | dc->npc = (target_ulong) tb->cs_base; |
e8af50a3 FB |
3193 | #if defined(CONFIG_USER_ONLY) |
3194 | dc->mem_idx = 0; | |
a80dde08 | 3195 | dc->fpu_enabled = 1; |
e8af50a3 FB |
3196 | #else |
3197 | dc->mem_idx = ((env->psrs) != 0); | |
a80dde08 FB |
3198 | #ifdef TARGET_SPARC64 |
3199 | dc->fpu_enabled = (((env->pstate & PS_PEF) != 0) && ((env->fprs & FPRS_FEF) != 0)); | |
3200 | #else | |
3201 | dc->fpu_enabled = ((env->psref) != 0); | |
3202 | #endif | |
e8af50a3 | 3203 | #endif |
cf495bcf FB |
3204 | gen_opc_ptr = gen_opc_buf; |
3205 | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; | |
3206 | gen_opparam_ptr = gen_opparam_buf; | |
83469015 | 3207 | nb_gen_labels = 0; |
cf495bcf FB |
3208 | |
3209 | do { | |
e8af50a3 FB |
3210 | if (env->nb_breakpoints > 0) { |
3211 | for(j = 0; j < env->nb_breakpoints; j++) { | |
3212 | if (env->breakpoints[j] == dc->pc) { | |
e80cfcfc FB |
3213 | if (dc->pc != pc_start) |
3214 | save_state(dc); | |
3215 | gen_op_debug(); | |
3216 | gen_op_movl_T0_0(); | |
3217 | gen_op_exit_tb(); | |
3218 | dc->is_br = 1; | |
3219 | goto exit_gen_loop; | |
e8af50a3 FB |
3220 | } |
3221 | } | |
3222 | } | |
3223 | if (spc) { | |
3224 | if (loglevel > 0) | |
3225 | fprintf(logfile, "Search PC...\n"); | |
3226 | j = gen_opc_ptr - gen_opc_buf; | |
3227 | if (lj < j) { | |
3228 | lj++; | |
3229 | while (lj < j) | |
3230 | gen_opc_instr_start[lj++] = 0; | |
3231 | gen_opc_pc[lj] = dc->pc; | |
3232 | gen_opc_npc[lj] = dc->npc; | |
3233 | gen_opc_instr_start[lj] = 1; | |
3234 | } | |
3235 | } | |
cf495bcf FB |
3236 | last_pc = dc->pc; |
3237 | disas_sparc_insn(dc); | |
3475187d | 3238 | |
cf495bcf FB |
3239 | if (dc->is_br) |
3240 | break; | |
3241 | /* if the next PC is different, we abort now */ | |
3242 | if (dc->pc != (last_pc + 4)) | |
3243 | break; | |
d39c0b99 FB |
3244 | /* if we reach a page boundary, we stop generation so that the |
3245 | PC of a TT_TFAULT exception is always in the right page */ | |
3246 | if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0) | |
3247 | break; | |
e80cfcfc FB |
3248 | /* if single step mode, we generate only one instruction and |
3249 | generate an exception */ | |
3250 | if (env->singlestep_enabled) { | |
3475187d | 3251 | gen_jmp_im(dc->pc); |
e80cfcfc FB |
3252 | gen_op_movl_T0_0(); |
3253 | gen_op_exit_tb(); | |
3254 | break; | |
3255 | } | |
cf495bcf FB |
3256 | } while ((gen_opc_ptr < gen_opc_end) && |
3257 | (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32)); | |
e80cfcfc FB |
3258 | |
3259 | exit_gen_loop: | |
72cbca10 FB |
3260 | if (!dc->is_br) { |
3261 | if (dc->pc != DYNAMIC_PC && | |
3262 | (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) { | |
3263 | /* static PC and NPC: we can use direct chaining */ | |
46525e1f | 3264 | gen_branch(dc, dc->pc, dc->npc); |
72cbca10 FB |
3265 | } else { |
3266 | if (dc->pc != DYNAMIC_PC) | |
3475187d | 3267 | gen_jmp_im(dc->pc); |
72cbca10 FB |
3268 | save_npc(dc); |
3269 | gen_op_movl_T0_0(); | |
3270 | gen_op_exit_tb(); | |
3271 | } | |
3272 | } | |
cf495bcf | 3273 | *gen_opc_ptr = INDEX_op_end; |
e8af50a3 FB |
3274 | if (spc) { |
3275 | j = gen_opc_ptr - gen_opc_buf; | |
3276 | lj++; | |
3277 | while (lj <= j) | |
3278 | gen_opc_instr_start[lj++] = 0; | |
3279 | tb->size = 0; | |
3280 | #if 0 | |
3281 | if (loglevel > 0) { | |
3282 | page_dump(logfile); | |
3283 | } | |
3284 | #endif | |
c3278b7b FB |
3285 | gen_opc_jump_pc[0] = dc->jump_pc[0]; |
3286 | gen_opc_jump_pc[1] = dc->jump_pc[1]; | |
e8af50a3 | 3287 | } else { |
e80cfcfc | 3288 | tb->size = last_pc + 4 - pc_start; |
e8af50a3 | 3289 | } |
7a3f1944 | 3290 | #ifdef DEBUG_DISAS |
e19e89a5 | 3291 | if (loglevel & CPU_LOG_TB_IN_ASM) { |
cf495bcf | 3292 | fprintf(logfile, "--------------\n"); |
0fa85d43 FB |
3293 | fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start)); |
3294 | target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0); | |
cf495bcf | 3295 | fprintf(logfile, "\n"); |
e19e89a5 FB |
3296 | if (loglevel & CPU_LOG_TB_OP) { |
3297 | fprintf(logfile, "OP:\n"); | |
3298 | dump_ops(gen_opc_buf, gen_opparam_buf); | |
3299 | fprintf(logfile, "\n"); | |
3300 | } | |
cf495bcf | 3301 | } |
7a3f1944 | 3302 | #endif |
cf495bcf | 3303 | return 0; |
7a3f1944 FB |
3304 | } |
3305 | ||
cf495bcf | 3306 | int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb) |
7a3f1944 | 3307 | { |
e8af50a3 | 3308 | return gen_intermediate_code_internal(tb, 0, env); |
7a3f1944 FB |
3309 | } |
3310 | ||
cf495bcf | 3311 | int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb) |
7a3f1944 | 3312 | { |
e8af50a3 | 3313 | return gen_intermediate_code_internal(tb, 1, env); |
7a3f1944 FB |
3314 | } |
3315 | ||
e80cfcfc | 3316 | extern int ram_size; |
cf495bcf | 3317 | |
e80cfcfc FB |
3318 | void cpu_reset(CPUSPARCState *env) |
3319 | { | |
bb05683b | 3320 | tlb_flush(env, 1); |
cf495bcf FB |
3321 | env->cwp = 0; |
3322 | env->wim = 1; | |
3323 | env->regwptr = env->regbase + (env->cwp * 16); | |
e8af50a3 | 3324 | #if defined(CONFIG_USER_ONLY) |
cf495bcf | 3325 | env->user_mode_only = 1; |
5ef54116 | 3326 | #ifdef TARGET_SPARC64 |
6ef905f6 BS |
3327 | env->cleanwin = NWINDOWS - 2; |
3328 | env->cansave = NWINDOWS - 2; | |
3329 | env->pstate = PS_RMO | PS_PEF | PS_IE; | |
3330 | env->asi = 0x82; // Primary no-fault | |
5ef54116 | 3331 | #endif |
e8af50a3 | 3332 | #else |
32af58f9 | 3333 | env->psret = 0; |
e8af50a3 | 3334 | env->psrs = 1; |
0bee699e | 3335 | env->psrps = 1; |
3475187d | 3336 | #ifdef TARGET_SPARC64 |
83469015 | 3337 | env->pstate = PS_PRIV; |
83469015 | 3338 | env->pc = 0x1fff0000000ULL; |
3475187d | 3339 | #else |
83469015 | 3340 | env->pc = 0xffd00000; |
32af58f9 | 3341 | env->mmuregs[0] &= ~(MMU_E | MMU_NF); |
3475187d | 3342 | #endif |
83469015 | 3343 | env->npc = env->pc + 4; |
e8af50a3 | 3344 | #endif |
e80cfcfc FB |
3345 | } |
3346 | ||
3347 | CPUSPARCState *cpu_sparc_init(void) | |
3348 | { | |
3349 | CPUSPARCState *env; | |
3350 | ||
c68ea704 FB |
3351 | env = qemu_mallocz(sizeof(CPUSPARCState)); |
3352 | if (!env) | |
3353 | return NULL; | |
3354 | cpu_exec_init(env); | |
e80cfcfc | 3355 | cpu_reset(env); |
cf495bcf | 3356 | return (env); |
7a3f1944 FB |
3357 | } |
3358 | ||
62724a37 BS |
3359 | static const sparc_def_t sparc_defs[] = { |
3360 | #ifdef TARGET_SPARC64 | |
3361 | { | |
3362 | .name = "TI UltraSparc II", | |
3363 | .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0 << 24) | |
3364 | | (MAXTL << 8) | (NWINDOWS - 1)), | |
3365 | .fpu_version = 0x00000000, | |
3366 | .mmu_version = 0, | |
3367 | }, | |
3368 | #else | |
3369 | { | |
3370 | .name = "Fujitsu MB86904", | |
3371 | .iu_version = 0x04 << 24, /* Impl 0, ver 4 */ | |
3372 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ | |
3373 | .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ | |
3374 | }, | |
e0353fe2 | 3375 | { |
5ef62c5c BS |
3376 | .name = "Fujitsu MB86907", |
3377 | .iu_version = 0x05 << 24, /* Impl 0, ver 5 */ | |
3378 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ | |
3379 | .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ | |
3380 | }, | |
3381 | { | |
3382 | .name = "TI MicroSparc I", | |
3383 | .iu_version = 0x41000000, | |
3384 | .fpu_version = 4 << 17, | |
3385 | .mmu_version = 0x41000000, | |
3386 | }, | |
3387 | { | |
e0353fe2 BS |
3388 | .name = "TI SuperSparc II", |
3389 | .iu_version = 0x40000000, | |
5ef62c5c BS |
3390 | .fpu_version = 0 << 17, |
3391 | .mmu_version = 0x04000000, | |
3392 | }, | |
3393 | { | |
3394 | .name = "Ross RT620", | |
3395 | .iu_version = 0x1e000000, | |
3396 | .fpu_version = 1 << 17, | |
3397 | .mmu_version = 0x17000000, | |
e0353fe2 | 3398 | }, |
62724a37 BS |
3399 | #endif |
3400 | }; | |
3401 | ||
3402 | int sparc_find_by_name(const unsigned char *name, const sparc_def_t **def) | |
3403 | { | |
3404 | int ret; | |
3405 | unsigned int i; | |
3406 | ||
3407 | ret = -1; | |
3408 | *def = NULL; | |
3409 | for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) { | |
3410 | if (strcasecmp(name, sparc_defs[i].name) == 0) { | |
3411 | *def = &sparc_defs[i]; | |
3412 | ret = 0; | |
3413 | break; | |
3414 | } | |
3415 | } | |
3416 | ||
3417 | return ret; | |
3418 | } | |
3419 | ||
3420 | void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) | |
3421 | { | |
3422 | unsigned int i; | |
3423 | ||
3424 | for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) { | |
3425 | (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x\n", | |
3426 | sparc_defs[i].name, | |
3427 | sparc_defs[i].iu_version, | |
3428 | sparc_defs[i].fpu_version, | |
3429 | sparc_defs[i].mmu_version); | |
3430 | } | |
3431 | } | |
3432 | ||
3433 | int cpu_sparc_register (CPUSPARCState *env, const sparc_def_t *def) | |
3434 | { | |
3435 | env->version = def->iu_version; | |
3436 | env->fsr = def->fpu_version; | |
3437 | #if !defined(TARGET_SPARC64) | |
3438 | env->mmuregs[0] = def->mmu_version; | |
3439 | #endif | |
3440 | return 0; | |
3441 | } | |
3442 | ||
7a3f1944 FB |
3443 | #define GET_FLAG(a,b) ((env->psr & a)?b:'-') |
3444 | ||
7fe48483 FB |
3445 | void cpu_dump_state(CPUState *env, FILE *f, |
3446 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), | |
3447 | int flags) | |
7a3f1944 | 3448 | { |
cf495bcf FB |
3449 | int i, x; |
3450 | ||
af7bf89b | 3451 | cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc); |
7fe48483 | 3452 | cpu_fprintf(f, "General Registers:\n"); |
cf495bcf | 3453 | for (i = 0; i < 4; i++) |
af7bf89b | 3454 | cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); |
7fe48483 | 3455 | cpu_fprintf(f, "\n"); |
cf495bcf | 3456 | for (; i < 8; i++) |
af7bf89b | 3457 | cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); |
7fe48483 | 3458 | cpu_fprintf(f, "\nCurrent Register Window:\n"); |
cf495bcf FB |
3459 | for (x = 0; x < 3; x++) { |
3460 | for (i = 0; i < 4; i++) | |
af7bf89b | 3461 | cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", |
cf495bcf FB |
3462 | (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i, |
3463 | env->regwptr[i + x * 8]); | |
7fe48483 | 3464 | cpu_fprintf(f, "\n"); |
cf495bcf | 3465 | for (; i < 8; i++) |
af7bf89b | 3466 | cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", |
cf495bcf FB |
3467 | (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i, |
3468 | env->regwptr[i + x * 8]); | |
7fe48483 | 3469 | cpu_fprintf(f, "\n"); |
cf495bcf | 3470 | } |
7fe48483 | 3471 | cpu_fprintf(f, "\nFloating Point Registers:\n"); |
e8af50a3 FB |
3472 | for (i = 0; i < 32; i++) { |
3473 | if ((i & 3) == 0) | |
7fe48483 FB |
3474 | cpu_fprintf(f, "%%f%02d:", i); |
3475 | cpu_fprintf(f, " %016lf", env->fpr[i]); | |
e8af50a3 | 3476 | if ((i & 3) == 3) |
7fe48483 | 3477 | cpu_fprintf(f, "\n"); |
e8af50a3 | 3478 | } |
ded3ab80 | 3479 | #ifdef TARGET_SPARC64 |
3299908c BS |
3480 | cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n", |
3481 | env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs); | |
ded3ab80 PB |
3482 | cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n", |
3483 | env->cansave, env->canrestore, env->otherwin, env->wstate, | |
3484 | env->cleanwin, NWINDOWS - 1 - env->cwp); | |
3485 | #else | |
7fe48483 | 3486 | cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env), |
cf495bcf FB |
3487 | GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'), |
3488 | GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'), | |
e8af50a3 FB |
3489 | env->psrs?'S':'-', env->psrps?'P':'-', |
3490 | env->psret?'E':'-', env->wim); | |
ded3ab80 | 3491 | #endif |
3475187d | 3492 | cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env)); |
7a3f1944 | 3493 | } |
edfcbd99 | 3494 | |
e80cfcfc | 3495 | #if defined(CONFIG_USER_ONLY) |
9b3c35e0 | 3496 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
edfcbd99 FB |
3497 | { |
3498 | return addr; | |
3499 | } | |
658138bc | 3500 | |
e80cfcfc | 3501 | #else |
af7bf89b FB |
3502 | extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot, |
3503 | int *access_index, target_ulong address, int rw, | |
0fa85d43 FB |
3504 | int is_user); |
3505 | ||
9b3c35e0 | 3506 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
e80cfcfc | 3507 | { |
af7bf89b | 3508 | target_phys_addr_t phys_addr; |
e80cfcfc FB |
3509 | int prot, access_index; |
3510 | ||
3511 | if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, 0) != 0) | |
6b1575b7 FB |
3512 | if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 0, 0) != 0) |
3513 | return -1; | |
6c36d3fa BS |
3514 | if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED) |
3515 | return -1; | |
e80cfcfc FB |
3516 | return phys_addr; |
3517 | } | |
3518 | #endif | |
3519 | ||
658138bc FB |
3520 | void helper_flush(target_ulong addr) |
3521 | { | |
3522 | addr &= ~7; | |
3523 | tb_invalidate_page_range(addr, addr + 8); | |
3524 | } |