]>
Commit | Line | Data |
---|---|---|
48e06fe0 BK |
1 | /* |
2 | * TriCore emulation for qemu: main translation routines. | |
3 | * | |
4 | * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | ||
21 | #include "cpu.h" | |
22 | #include "disas/disas.h" | |
23 | #include "tcg-op.h" | |
24 | #include "exec/cpu_ldst.h" | |
25 | ||
26 | #include "exec/helper-proto.h" | |
27 | #include "exec/helper-gen.h" | |
28 | ||
7c87d074 | 29 | #include "tricore-opcodes.h" |
0707ec1b | 30 | |
0aaeb118 BK |
31 | /* |
32 | * TCG registers | |
33 | */ | |
34 | static TCGv cpu_PC; | |
35 | static TCGv cpu_PCXI; | |
36 | static TCGv cpu_PSW; | |
37 | static TCGv cpu_ICR; | |
38 | /* GPR registers */ | |
39 | static TCGv cpu_gpr_a[16]; | |
40 | static TCGv cpu_gpr_d[16]; | |
41 | /* PSW Flag cache */ | |
42 | static TCGv cpu_PSW_C; | |
43 | static TCGv cpu_PSW_V; | |
44 | static TCGv cpu_PSW_SV; | |
45 | static TCGv cpu_PSW_AV; | |
46 | static TCGv cpu_PSW_SAV; | |
47 | /* CPU env */ | |
48 | static TCGv_ptr cpu_env; | |
49 | ||
50 | #include "exec/gen-icount.h" | |
48e06fe0 BK |
51 | |
52 | static const char *regnames_a[] = { | |
53 | "a0" , "a1" , "a2" , "a3" , "a4" , "a5" , | |
54 | "a6" , "a7" , "a8" , "a9" , "sp" , "a11" , | |
55 | "a12" , "a13" , "a14" , "a15", | |
56 | }; | |
57 | ||
58 | static const char *regnames_d[] = { | |
59 | "d0" , "d1" , "d2" , "d3" , "d4" , "d5" , | |
60 | "d6" , "d7" , "d8" , "d9" , "d10" , "d11" , | |
61 | "d12" , "d13" , "d14" , "d15", | |
62 | }; | |
63 | ||
0aaeb118 BK |
64 | typedef struct DisasContext { |
65 | struct TranslationBlock *tb; | |
66 | target_ulong pc, saved_pc, next_pc; | |
67 | uint32_t opcode; | |
68 | int singlestep_enabled; | |
69 | /* Routine used to access memory */ | |
70 | int mem_idx; | |
71 | uint32_t hflags, saved_hflags; | |
72 | int bstate; | |
73 | } DisasContext; | |
74 | ||
75 | enum { | |
76 | ||
77 | BS_NONE = 0, | |
78 | BS_STOP = 1, | |
79 | BS_BRANCH = 2, | |
80 | BS_EXCP = 3, | |
81 | }; | |
82 | ||
2e430e1c BK |
83 | enum { |
84 | MODE_LL = 0, | |
85 | MODE_LU = 1, | |
86 | MODE_UL = 2, | |
87 | MODE_UU = 3, | |
88 | }; | |
89 | ||
48e06fe0 BK |
90 | void tricore_cpu_dump_state(CPUState *cs, FILE *f, |
91 | fprintf_function cpu_fprintf, int flags) | |
92 | { | |
93 | TriCoreCPU *cpu = TRICORE_CPU(cs); | |
94 | CPUTriCoreState *env = &cpu->env; | |
45820fcc | 95 | uint32_t psw; |
48e06fe0 BK |
96 | int i; |
97 | ||
45820fcc AZ |
98 | psw = psw_read(env); |
99 | ||
100 | cpu_fprintf(f, "PC: " TARGET_FMT_lx, env->PC); | |
101 | cpu_fprintf(f, " PSW: " TARGET_FMT_lx, psw); | |
102 | cpu_fprintf(f, " ICR: " TARGET_FMT_lx, env->ICR); | |
103 | cpu_fprintf(f, "\nPCXI: " TARGET_FMT_lx, env->PCXI); | |
104 | cpu_fprintf(f, " FCX: " TARGET_FMT_lx, env->FCX); | |
105 | cpu_fprintf(f, " LCX: " TARGET_FMT_lx, env->LCX); | |
106 | ||
48e06fe0 BK |
107 | for (i = 0; i < 16; ++i) { |
108 | if ((i & 3) == 0) { | |
45820fcc | 109 | cpu_fprintf(f, "\nGPR A%02d:", i); |
48e06fe0 | 110 | } |
45820fcc | 111 | cpu_fprintf(f, " " TARGET_FMT_lx, env->gpr_a[i]); |
48e06fe0 BK |
112 | } |
113 | for (i = 0; i < 16; ++i) { | |
114 | if ((i & 3) == 0) { | |
45820fcc | 115 | cpu_fprintf(f, "\nGPR D%02d:", i); |
48e06fe0 | 116 | } |
45820fcc | 117 | cpu_fprintf(f, " " TARGET_FMT_lx, env->gpr_d[i]); |
48e06fe0 | 118 | } |
45820fcc | 119 | cpu_fprintf(f, "\n"); |
48e06fe0 BK |
120 | } |
121 | ||
0707ec1b BK |
122 | /* |
123 | * Functions to generate micro-ops | |
124 | */ | |
125 | ||
9a31922b BK |
126 | /* Makros for generating helpers */ |
127 | ||
128 | #define gen_helper_1arg(name, arg) do { \ | |
129 | TCGv_i32 helper_tmp = tcg_const_i32(arg); \ | |
130 | gen_helper_##name(cpu_env, helper_tmp); \ | |
131 | tcg_temp_free_i32(helper_tmp); \ | |
132 | } while (0) | |
133 | ||
9655b932 BK |
134 | #define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \ |
135 | TCGv arg00 = tcg_temp_new(); \ | |
136 | TCGv arg01 = tcg_temp_new(); \ | |
137 | TCGv arg11 = tcg_temp_new(); \ | |
138 | tcg_gen_sari_tl(arg00, arg0, 16); \ | |
139 | tcg_gen_ext16s_tl(arg01, arg0); \ | |
140 | tcg_gen_ext16s_tl(arg11, arg1); \ | |
141 | gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \ | |
142 | tcg_temp_free(arg00); \ | |
143 | tcg_temp_free(arg01); \ | |
144 | tcg_temp_free(arg11); \ | |
145 | } while (0) | |
146 | ||
147 | #define GEN_HELPER_LU(name, ret, arg0, arg1, n) do { \ | |
148 | TCGv arg00 = tcg_temp_new(); \ | |
149 | TCGv arg01 = tcg_temp_new(); \ | |
150 | TCGv arg10 = tcg_temp_new(); \ | |
151 | TCGv arg11 = tcg_temp_new(); \ | |
152 | tcg_gen_sari_tl(arg00, arg0, 16); \ | |
153 | tcg_gen_ext16s_tl(arg01, arg0); \ | |
154 | tcg_gen_sari_tl(arg11, arg1, 16); \ | |
155 | tcg_gen_ext16s_tl(arg10, arg1); \ | |
156 | gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \ | |
157 | tcg_temp_free(arg00); \ | |
158 | tcg_temp_free(arg01); \ | |
159 | tcg_temp_free(arg10); \ | |
160 | tcg_temp_free(arg11); \ | |
161 | } while (0) | |
162 | ||
163 | #define GEN_HELPER_UL(name, ret, arg0, arg1, n) do { \ | |
164 | TCGv arg00 = tcg_temp_new(); \ | |
165 | TCGv arg01 = tcg_temp_new(); \ | |
166 | TCGv arg10 = tcg_temp_new(); \ | |
167 | TCGv arg11 = tcg_temp_new(); \ | |
168 | tcg_gen_sari_tl(arg00, arg0, 16); \ | |
169 | tcg_gen_ext16s_tl(arg01, arg0); \ | |
170 | tcg_gen_sari_tl(arg10, arg1, 16); \ | |
171 | tcg_gen_ext16s_tl(arg11, arg1); \ | |
172 | gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \ | |
173 | tcg_temp_free(arg00); \ | |
174 | tcg_temp_free(arg01); \ | |
175 | tcg_temp_free(arg10); \ | |
176 | tcg_temp_free(arg11); \ | |
177 | } while (0) | |
178 | ||
179 | #define GEN_HELPER_UU(name, ret, arg0, arg1, n) do { \ | |
180 | TCGv arg00 = tcg_temp_new(); \ | |
181 | TCGv arg01 = tcg_temp_new(); \ | |
182 | TCGv arg11 = tcg_temp_new(); \ | |
183 | tcg_gen_sari_tl(arg01, arg0, 16); \ | |
184 | tcg_gen_ext16s_tl(arg00, arg0); \ | |
185 | tcg_gen_sari_tl(arg11, arg1, 16); \ | |
186 | gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \ | |
187 | tcg_temp_free(arg00); \ | |
188 | tcg_temp_free(arg01); \ | |
189 | tcg_temp_free(arg11); \ | |
190 | } while (0) | |
191 | ||
09532255 BK |
192 | #define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \ |
193 | TCGv_i64 ret = tcg_temp_new_i64(); \ | |
194 | TCGv_i64 arg1 = tcg_temp_new_i64(); \ | |
195 | \ | |
196 | tcg_gen_concat_i32_i64(arg1, al1, ah1); \ | |
197 | gen_helper_##name(ret, arg1, arg2); \ | |
198 | tcg_gen_extr_i64_i32(rl, rh, ret); \ | |
199 | \ | |
200 | tcg_temp_free_i64(ret); \ | |
201 | tcg_temp_free_i64(arg1); \ | |
202 | } while (0) | |
203 | ||
59543d4e | 204 | #define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF)) |
f718b0bb BK |
205 | #define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \ |
206 | ((offset & 0x0fffff) << 1)) | |
59543d4e | 207 | |
d2798210 BK |
208 | /* Functions for load/save to/from memory */ |
209 | ||
210 | static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2, | |
211 | int16_t con, TCGMemOp mop) | |
212 | { | |
213 | TCGv temp = tcg_temp_new(); | |
214 | tcg_gen_addi_tl(temp, r2, con); | |
215 | tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); | |
216 | tcg_temp_free(temp); | |
217 | } | |
218 | ||
219 | static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2, | |
220 | int16_t con, TCGMemOp mop) | |
221 | { | |
222 | TCGv temp = tcg_temp_new(); | |
223 | tcg_gen_addi_tl(temp, r2, con); | |
224 | tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); | |
225 | tcg_temp_free(temp); | |
226 | } | |
227 | ||
59543d4e BK |
228 | static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) |
229 | { | |
230 | TCGv_i64 temp = tcg_temp_new_i64(); | |
231 | ||
232 | tcg_gen_concat_i32_i64(temp, rl, rh); | |
233 | tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEQ); | |
234 | ||
235 | tcg_temp_free_i64(temp); | |
236 | } | |
237 | ||
3a16ecb0 BK |
238 | static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, |
239 | DisasContext *ctx) | |
240 | { | |
241 | TCGv temp = tcg_temp_new(); | |
242 | tcg_gen_addi_tl(temp, base, con); | |
243 | gen_st_2regs_64(rh, rl, temp, ctx); | |
244 | tcg_temp_free(temp); | |
245 | } | |
246 | ||
59543d4e BK |
247 | static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) |
248 | { | |
249 | TCGv_i64 temp = tcg_temp_new_i64(); | |
250 | ||
251 | tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEQ); | |
252 | /* write back to two 32 bit regs */ | |
253 | tcg_gen_extr_i64_i32(rl, rh, temp); | |
254 | ||
255 | tcg_temp_free_i64(temp); | |
256 | } | |
257 | ||
3a16ecb0 BK |
258 | static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, |
259 | DisasContext *ctx) | |
260 | { | |
261 | TCGv temp = tcg_temp_new(); | |
262 | tcg_gen_addi_tl(temp, base, con); | |
263 | gen_ld_2regs_64(rh, rl, temp, ctx); | |
264 | tcg_temp_free(temp); | |
265 | } | |
266 | ||
267 | static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off, | |
268 | TCGMemOp mop) | |
269 | { | |
270 | TCGv temp = tcg_temp_new(); | |
271 | tcg_gen_addi_tl(temp, r2, off); | |
272 | tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); | |
273 | tcg_gen_mov_tl(r2, temp); | |
274 | tcg_temp_free(temp); | |
275 | } | |
276 | ||
277 | static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off, | |
278 | TCGMemOp mop) | |
279 | { | |
280 | TCGv temp = tcg_temp_new(); | |
281 | tcg_gen_addi_tl(temp, r2, off); | |
282 | tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); | |
283 | tcg_gen_mov_tl(r2, temp); | |
284 | tcg_temp_free(temp); | |
285 | } | |
286 | ||
59543d4e BK |
287 | /* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */ |
288 | static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea) | |
289 | { | |
290 | TCGv temp = tcg_temp_new(); | |
291 | TCGv temp2 = tcg_temp_new(); | |
292 | ||
293 | /* temp = (M(EA, word) */ | |
294 | tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); | |
295 | /* temp = temp & ~E[a][63:32]) */ | |
296 | tcg_gen_andc_tl(temp, temp, cpu_gpr_d[ereg+1]); | |
297 | /* temp2 = (E[a][31:0] & E[a][63:32]); */ | |
298 | tcg_gen_and_tl(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg+1]); | |
299 | /* temp = temp | temp2; */ | |
300 | tcg_gen_or_tl(temp, temp, temp2); | |
301 | /* M(EA, word) = temp; */ | |
302 | tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL); | |
303 | ||
304 | tcg_temp_free(temp); | |
305 | tcg_temp_free(temp2); | |
306 | } | |
307 | ||
308 | /* tmp = M(EA, word); | |
309 | M(EA, word) = D[a]; | |
310 | D[a] = tmp[31:0];*/ | |
311 | static void gen_swap(DisasContext *ctx, int reg, TCGv ea) | |
312 | { | |
313 | TCGv temp = tcg_temp_new(); | |
314 | ||
315 | tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); | |
316 | tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL); | |
317 | tcg_gen_mov_tl(cpu_gpr_d[reg], temp); | |
318 | ||
319 | tcg_temp_free(temp); | |
320 | } | |
321 | ||
2b2f7d97 BK |
322 | /* We generate loads and store to core special function register (csfr) through |
323 | the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3 | |
324 | makros R, A and E, which allow read-only, all and endinit protected access. | |
325 | These makros also specify in which ISA version the csfr was introduced. */ | |
326 | #define R(ADDRESS, REG, FEATURE) \ | |
327 | case ADDRESS: \ | |
328 | if (tricore_feature(env, FEATURE)) { \ | |
329 | tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \ | |
330 | } \ | |
331 | break; | |
332 | #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) | |
333 | #define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) | |
334 | static inline void gen_mfcr(CPUTriCoreState *env, TCGv ret, int32_t offset) | |
335 | { | |
336 | /* since we're caching PSW make this a special case */ | |
337 | if (offset == 0xfe04) { | |
338 | gen_helper_psw_read(ret, cpu_env); | |
339 | } else { | |
340 | switch (offset) { | |
341 | #include "csfr.def" | |
342 | } | |
343 | } | |
344 | } | |
345 | #undef R | |
346 | #undef A | |
347 | #undef E | |
348 | ||
349 | #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg, | |
350 | since no execption occurs */ | |
351 | #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \ | |
352 | case ADDRESS: \ | |
353 | if (tricore_feature(env, FEATURE)) { \ | |
354 | tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \ | |
355 | } \ | |
356 | break; | |
357 | /* Endinit protected registers | |
358 | TODO: Since the endinit bit is in a register of a not yet implemented | |
359 | watchdog device, we handle endinit protected registers like | |
360 | all-access registers for now. */ | |
361 | #define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE) | |
362 | static inline void gen_mtcr(CPUTriCoreState *env, DisasContext *ctx, TCGv r1, | |
363 | int32_t offset) | |
364 | { | |
40a1f64b | 365 | if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) { |
2b2f7d97 BK |
366 | /* since we're caching PSW make this a special case */ |
367 | if (offset == 0xfe04) { | |
368 | gen_helper_psw_write(cpu_env, r1); | |
369 | } else { | |
370 | switch (offset) { | |
371 | #include "csfr.def" | |
372 | } | |
373 | } | |
374 | } else { | |
375 | /* generate privilege trap */ | |
376 | } | |
377 | } | |
378 | ||
0707ec1b BK |
379 | /* Functions for arithmetic instructions */ |
380 | ||
381 | static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2) | |
382 | { | |
383 | TCGv t0 = tcg_temp_new_i32(); | |
384 | TCGv result = tcg_temp_new_i32(); | |
385 | /* Addition and set V/SV bits */ | |
386 | tcg_gen_add_tl(result, r1, r2); | |
387 | /* calc V bit */ | |
388 | tcg_gen_xor_tl(cpu_PSW_V, result, r1); | |
389 | tcg_gen_xor_tl(t0, r1, r2); | |
390 | tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); | |
391 | /* Calc SV bit */ | |
392 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
393 | /* Calc AV/SAV bits */ | |
394 | tcg_gen_add_tl(cpu_PSW_AV, result, result); | |
395 | tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); | |
396 | /* calc SAV */ | |
397 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
398 | /* write back result */ | |
399 | tcg_gen_mov_tl(ret, result); | |
400 | ||
401 | tcg_temp_free(result); | |
402 | tcg_temp_free(t0); | |
403 | } | |
404 | ||
2e430e1c BK |
405 | static inline void |
406 | gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2) | |
407 | { | |
408 | TCGv temp = tcg_temp_new(); | |
409 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
410 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
411 | TCGv_i64 result = tcg_temp_new_i64(); | |
412 | ||
413 | tcg_gen_add_i64(result, r1, r2); | |
414 | /* calc v bit */ | |
415 | tcg_gen_xor_i64(t1, result, r1); | |
416 | tcg_gen_xor_i64(t0, r1, r2); | |
417 | tcg_gen_andc_i64(t1, t1, t0); | |
418 | tcg_gen_trunc_shr_i64_i32(cpu_PSW_V, t1, 32); | |
419 | /* calc SV bit */ | |
420 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
421 | /* calc AV/SAV bits */ | |
422 | tcg_gen_trunc_shr_i64_i32(temp, result, 32); | |
423 | tcg_gen_add_tl(cpu_PSW_AV, temp, temp); | |
424 | tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV); | |
425 | /* calc SAV */ | |
426 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
427 | /* write back result */ | |
428 | tcg_gen_mov_i64(ret, result); | |
429 | ||
430 | tcg_temp_free(temp); | |
431 | tcg_temp_free_i64(result); | |
432 | tcg_temp_free_i64(t0); | |
433 | tcg_temp_free_i64(t1); | |
434 | } | |
435 | ||
436 | static inline void | |
437 | gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
438 | TCGv r3, void(*op1)(TCGv, TCGv, TCGv), | |
439 | void(*op2)(TCGv, TCGv, TCGv)) | |
440 | { | |
441 | TCGv temp = tcg_temp_new(); | |
442 | TCGv temp2 = tcg_temp_new(); | |
443 | TCGv temp3 = tcg_temp_new(); | |
444 | TCGv temp4 = tcg_temp_new(); | |
445 | ||
446 | (*op1)(temp, r1_low, r2); | |
447 | /* calc V0 bit */ | |
448 | tcg_gen_xor_tl(temp2, temp, r1_low); | |
449 | tcg_gen_xor_tl(temp3, r1_low, r2); | |
450 | if (op1 == tcg_gen_add_tl) { | |
451 | tcg_gen_andc_tl(temp2, temp2, temp3); | |
452 | } else { | |
453 | tcg_gen_and_tl(temp2, temp2, temp3); | |
454 | } | |
455 | ||
456 | (*op2)(temp3, r1_high, r3); | |
457 | /* calc V1 bit */ | |
458 | tcg_gen_xor_tl(cpu_PSW_V, temp3, r1_high); | |
459 | tcg_gen_xor_tl(temp4, r1_high, r3); | |
460 | if (op2 == tcg_gen_add_tl) { | |
461 | tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, temp4); | |
462 | } else { | |
463 | tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp4); | |
464 | } | |
465 | /* combine V0/V1 bits */ | |
466 | tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp2); | |
467 | /* calc sv bit */ | |
468 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
469 | /* write result */ | |
470 | tcg_gen_mov_tl(ret_low, temp); | |
471 | tcg_gen_mov_tl(ret_high, temp3); | |
472 | /* calc AV bit */ | |
473 | tcg_gen_add_tl(temp, ret_low, ret_low); | |
474 | tcg_gen_xor_tl(temp, temp, ret_low); | |
475 | tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); | |
476 | tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, ret_high); | |
477 | tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); | |
478 | /* calc SAV bit */ | |
479 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
480 | ||
481 | tcg_temp_free(temp); | |
482 | tcg_temp_free(temp2); | |
483 | tcg_temp_free(temp3); | |
484 | tcg_temp_free(temp4); | |
485 | } | |
486 | ||
328f1f0f BK |
487 | /* ret = r2 + (r1 * r3); */ |
488 | static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3) | |
489 | { | |
490 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
491 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
492 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
493 | ||
494 | tcg_gen_ext_i32_i64(t1, r1); | |
495 | tcg_gen_ext_i32_i64(t2, r2); | |
496 | tcg_gen_ext_i32_i64(t3, r3); | |
497 | ||
498 | tcg_gen_mul_i64(t1, t1, t3); | |
499 | tcg_gen_add_i64(t1, t2, t1); | |
500 | ||
501 | tcg_gen_trunc_i64_i32(ret, t1); | |
502 | /* calc V | |
503 | t1 > 0x7fffffff */ | |
504 | tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); | |
505 | /* t1 < -0x80000000 */ | |
506 | tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); | |
507 | tcg_gen_or_i64(t2, t2, t3); | |
508 | tcg_gen_trunc_i64_i32(cpu_PSW_V, t2); | |
509 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); | |
510 | /* Calc SV bit */ | |
511 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
512 | /* Calc AV/SAV bits */ | |
513 | tcg_gen_add_tl(cpu_PSW_AV, ret, ret); | |
514 | tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); | |
515 | /* calc SAV */ | |
516 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
517 | ||
518 | tcg_temp_free_i64(t1); | |
519 | tcg_temp_free_i64(t2); | |
520 | tcg_temp_free_i64(t3); | |
521 | } | |
522 | ||
523 | static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) | |
524 | { | |
525 | TCGv temp = tcg_const_i32(con); | |
526 | gen_madd32_d(ret, r1, r2, temp); | |
527 | tcg_temp_free(temp); | |
528 | } | |
529 | ||
530 | static inline void | |
531 | gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
532 | TCGv r3) | |
533 | { | |
534 | TCGv t1 = tcg_temp_new(); | |
535 | TCGv t2 = tcg_temp_new(); | |
536 | TCGv t3 = tcg_temp_new(); | |
537 | TCGv t4 = tcg_temp_new(); | |
538 | ||
539 | tcg_gen_muls2_tl(t1, t2, r1, r3); | |
540 | /* only the add can overflow */ | |
541 | tcg_gen_add2_tl(t3, t4, r2_low, r2_high, t1, t2); | |
542 | /* calc V bit */ | |
543 | tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high); | |
544 | tcg_gen_xor_tl(t1, r2_high, t2); | |
545 | tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t1); | |
546 | /* Calc SV bit */ | |
547 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
548 | /* Calc AV/SAV bits */ | |
549 | tcg_gen_add_tl(cpu_PSW_AV, t4, t4); | |
550 | tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV); | |
551 | /* calc SAV */ | |
552 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
553 | /* write back the result */ | |
554 | tcg_gen_mov_tl(ret_low, t3); | |
555 | tcg_gen_mov_tl(ret_high, t4); | |
556 | ||
557 | tcg_temp_free(t1); | |
558 | tcg_temp_free(t2); | |
559 | tcg_temp_free(t3); | |
560 | tcg_temp_free(t4); | |
561 | } | |
562 | ||
563 | static inline void | |
564 | gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
565 | TCGv r3) | |
566 | { | |
567 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
568 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
569 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
570 | ||
571 | tcg_gen_extu_i32_i64(t1, r1); | |
572 | tcg_gen_concat_i32_i64(t2, r2_low, r2_high); | |
573 | tcg_gen_extu_i32_i64(t3, r3); | |
574 | ||
575 | tcg_gen_mul_i64(t1, t1, t3); | |
576 | tcg_gen_add_i64(t2, t2, t1); | |
577 | /* write back result */ | |
578 | tcg_gen_extr_i64_i32(ret_low, ret_high, t2); | |
579 | /* only the add overflows, if t2 < t1 | |
580 | calc V bit */ | |
581 | tcg_gen_setcond_i64(TCG_COND_LTU, t2, t2, t1); | |
582 | tcg_gen_trunc_i64_i32(cpu_PSW_V, t2); | |
583 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); | |
584 | /* Calc SV bit */ | |
585 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
586 | /* Calc AV/SAV bits */ | |
587 | tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); | |
588 | tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); | |
589 | /* calc SAV */ | |
590 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
591 | ||
592 | tcg_temp_free_i64(t1); | |
593 | tcg_temp_free_i64(t2); | |
594 | tcg_temp_free_i64(t3); | |
595 | } | |
596 | ||
597 | static inline void | |
598 | gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
599 | int32_t con) | |
600 | { | |
601 | TCGv temp = tcg_const_i32(con); | |
602 | gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); | |
603 | tcg_temp_free(temp); | |
604 | } | |
605 | ||
606 | static inline void | |
607 | gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
608 | int32_t con) | |
609 | { | |
610 | TCGv temp = tcg_const_i32(con); | |
611 | gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); | |
612 | tcg_temp_free(temp); | |
613 | } | |
614 | ||
2e430e1c BK |
615 | static inline void |
616 | gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
617 | TCGv r3, uint32_t n, uint32_t mode) | |
618 | { | |
619 | TCGv temp = tcg_const_i32(n); | |
620 | TCGv temp2 = tcg_temp_new(); | |
621 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
622 | switch (mode) { | |
623 | case MODE_LL: | |
624 | GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); | |
625 | break; | |
626 | case MODE_LU: | |
627 | GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); | |
628 | break; | |
629 | case MODE_UL: | |
630 | GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); | |
631 | break; | |
632 | case MODE_UU: | |
633 | GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); | |
634 | break; | |
635 | } | |
636 | tcg_gen_extr_i64_i32(temp, temp2, temp64); | |
637 | gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, | |
638 | tcg_gen_add_tl, tcg_gen_add_tl); | |
639 | tcg_temp_free(temp); | |
640 | tcg_temp_free(temp2); | |
641 | tcg_temp_free_i64(temp64); | |
642 | } | |
643 | ||
bebe80fc BK |
644 | static inline void |
645 | gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
646 | TCGv r3, uint32_t n, uint32_t mode) | |
647 | { | |
648 | TCGv temp = tcg_const_i32(n); | |
649 | TCGv temp2 = tcg_temp_new(); | |
650 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
651 | switch (mode) { | |
652 | case MODE_LL: | |
653 | GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); | |
654 | break; | |
655 | case MODE_LU: | |
656 | GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); | |
657 | break; | |
658 | case MODE_UL: | |
659 | GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); | |
660 | break; | |
661 | case MODE_UU: | |
662 | GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); | |
663 | break; | |
664 | } | |
665 | tcg_gen_extr_i64_i32(temp, temp2, temp64); | |
666 | gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, | |
667 | tcg_gen_sub_tl, tcg_gen_add_tl); | |
668 | tcg_temp_free(temp); | |
669 | tcg_temp_free(temp2); | |
670 | tcg_temp_free_i64(temp64); | |
671 | } | |
672 | ||
673 | static inline void | |
674 | gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
675 | TCGv r3, uint32_t n, uint32_t mode) | |
676 | { | |
677 | TCGv temp = tcg_const_i32(n); | |
678 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
679 | TCGv_i64 temp64_2 = tcg_temp_new_i64(); | |
680 | TCGv_i64 temp64_3 = tcg_temp_new_i64(); | |
681 | switch (mode) { | |
682 | case MODE_LL: | |
683 | GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); | |
684 | break; | |
685 | case MODE_LU: | |
686 | GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); | |
687 | break; | |
688 | case MODE_UL: | |
689 | GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); | |
690 | break; | |
691 | case MODE_UU: | |
692 | GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); | |
693 | break; | |
694 | } | |
695 | tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high); | |
696 | tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ | |
697 | tcg_gen_ext32s_i64(temp64, temp64); /* low */ | |
698 | tcg_gen_sub_i64(temp64, temp64_2, temp64); | |
699 | tcg_gen_shli_i64(temp64, temp64, 16); | |
700 | ||
701 | gen_add64_d(temp64_2, temp64_3, temp64); | |
702 | /* write back result */ | |
703 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2); | |
704 | ||
705 | tcg_temp_free(temp); | |
706 | tcg_temp_free_i64(temp64); | |
707 | tcg_temp_free_i64(temp64_2); | |
708 | tcg_temp_free_i64(temp64_3); | |
709 | } | |
710 | ||
2e430e1c BK |
711 | static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2); |
712 | ||
713 | static inline void | |
714 | gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
715 | TCGv r3, uint32_t n, uint32_t mode) | |
716 | { | |
717 | TCGv temp = tcg_const_i32(n); | |
718 | TCGv temp2 = tcg_temp_new(); | |
719 | TCGv temp3 = tcg_temp_new(); | |
720 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
721 | ||
722 | switch (mode) { | |
723 | case MODE_LL: | |
724 | GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); | |
725 | break; | |
726 | case MODE_LU: | |
727 | GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); | |
728 | break; | |
729 | case MODE_UL: | |
730 | GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); | |
731 | break; | |
732 | case MODE_UU: | |
733 | GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); | |
734 | break; | |
735 | } | |
736 | tcg_gen_extr_i64_i32(temp, temp2, temp64); | |
737 | gen_adds(ret_low, r1_low, temp); | |
738 | tcg_gen_mov_tl(temp, cpu_PSW_V); | |
739 | tcg_gen_mov_tl(temp3, cpu_PSW_AV); | |
740 | gen_adds(ret_high, r1_high, temp2); | |
741 | /* combine v bits */ | |
742 | tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); | |
743 | /* combine av bits */ | |
744 | tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); | |
745 | ||
746 | tcg_temp_free(temp); | |
747 | tcg_temp_free(temp2); | |
748 | tcg_temp_free(temp3); | |
749 | tcg_temp_free_i64(temp64); | |
750 | ||
751 | } | |
752 | ||
bebe80fc BK |
753 | static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2); |
754 | ||
755 | static inline void | |
756 | gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
757 | TCGv r3, uint32_t n, uint32_t mode) | |
758 | { | |
759 | TCGv temp = tcg_const_i32(n); | |
760 | TCGv temp2 = tcg_temp_new(); | |
761 | TCGv temp3 = tcg_temp_new(); | |
762 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
763 | ||
764 | switch (mode) { | |
765 | case MODE_LL: | |
766 | GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); | |
767 | break; | |
768 | case MODE_LU: | |
769 | GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); | |
770 | break; | |
771 | case MODE_UL: | |
772 | GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); | |
773 | break; | |
774 | case MODE_UU: | |
775 | GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); | |
776 | break; | |
777 | } | |
778 | tcg_gen_extr_i64_i32(temp, temp2, temp64); | |
779 | gen_subs(ret_low, r1_low, temp); | |
780 | tcg_gen_mov_tl(temp, cpu_PSW_V); | |
781 | tcg_gen_mov_tl(temp3, cpu_PSW_AV); | |
782 | gen_adds(ret_high, r1_high, temp2); | |
783 | /* combine v bits */ | |
784 | tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); | |
785 | /* combine av bits */ | |
786 | tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); | |
787 | ||
788 | tcg_temp_free(temp); | |
789 | tcg_temp_free(temp2); | |
790 | tcg_temp_free(temp3); | |
791 | tcg_temp_free_i64(temp64); | |
792 | ||
793 | } | |
794 | ||
795 | static inline void | |
796 | gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
797 | TCGv r3, uint32_t n, uint32_t mode) | |
798 | { | |
799 | TCGv temp = tcg_const_i32(n); | |
800 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
801 | TCGv_i64 temp64_2 = tcg_temp_new_i64(); | |
802 | ||
803 | switch (mode) { | |
804 | case MODE_LL: | |
805 | GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); | |
806 | break; | |
807 | case MODE_LU: | |
808 | GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); | |
809 | break; | |
810 | case MODE_UL: | |
811 | GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); | |
812 | break; | |
813 | case MODE_UU: | |
814 | GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); | |
815 | break; | |
816 | } | |
817 | tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ | |
818 | tcg_gen_ext32s_i64(temp64, temp64); /* low */ | |
819 | tcg_gen_sub_i64(temp64, temp64_2, temp64); | |
820 | tcg_gen_shli_i64(temp64, temp64, 16); | |
821 | tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); | |
822 | ||
823 | gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64); | |
824 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); | |
825 | ||
826 | tcg_temp_free(temp); | |
827 | tcg_temp_free_i64(temp64); | |
828 | tcg_temp_free_i64(temp64_2); | |
829 | } | |
830 | ||
831 | ||
2e430e1c BK |
832 | static inline void |
833 | gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
834 | TCGv r3, uint32_t n, uint32_t mode) | |
835 | { | |
836 | TCGv temp = tcg_const_i32(n); | |
837 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
838 | TCGv_i64 temp64_2 = tcg_temp_new_i64(); | |
839 | TCGv_i64 temp64_3 = tcg_temp_new_i64(); | |
840 | switch (mode) { | |
841 | case MODE_LL: | |
842 | GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp); | |
843 | break; | |
844 | case MODE_LU: | |
845 | GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp); | |
846 | break; | |
847 | case MODE_UL: | |
848 | GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp); | |
849 | break; | |
850 | case MODE_UU: | |
851 | GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp); | |
852 | break; | |
853 | } | |
854 | tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); | |
855 | gen_add64_d(temp64_3, temp64_2, temp64); | |
856 | /* write back result */ | |
857 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3); | |
858 | ||
859 | tcg_temp_free(temp); | |
860 | tcg_temp_free_i64(temp64); | |
861 | tcg_temp_free_i64(temp64_2); | |
862 | tcg_temp_free_i64(temp64_3); | |
863 | } | |
864 | ||
865 | static inline void | |
866 | gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
867 | TCGv r3, uint32_t n, uint32_t mode) | |
868 | { | |
869 | TCGv temp = tcg_const_i32(n); | |
870 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
871 | TCGv_i64 temp64_2 = tcg_temp_new_i64(); | |
872 | switch (mode) { | |
873 | case MODE_LL: | |
874 | GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp); | |
875 | break; | |
876 | case MODE_LU: | |
877 | GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp); | |
878 | break; | |
879 | case MODE_UL: | |
880 | GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp); | |
881 | break; | |
882 | case MODE_UU: | |
883 | GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp); | |
884 | break; | |
885 | } | |
886 | tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); | |
887 | gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64); | |
888 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); | |
889 | ||
890 | tcg_temp_free(temp); | |
891 | tcg_temp_free_i64(temp64); | |
892 | tcg_temp_free_i64(temp64_2); | |
893 | } | |
894 | ||
895 | static inline void | |
896 | gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, | |
897 | uint32_t mode) | |
898 | { | |
899 | TCGv temp = tcg_const_i32(n); | |
900 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
901 | switch (mode) { | |
902 | case MODE_LL: | |
903 | GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); | |
904 | break; | |
905 | case MODE_LU: | |
906 | GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); | |
907 | break; | |
908 | case MODE_UL: | |
909 | GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); | |
910 | break; | |
911 | case MODE_UU: | |
912 | GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); | |
913 | break; | |
914 | } | |
915 | gen_helper_addr_h(ret, cpu_env, temp64, r1_low, r1_high); | |
916 | ||
917 | tcg_temp_free(temp); | |
918 | tcg_temp_free_i64(temp64); | |
919 | } | |
920 | ||
921 | static inline void | |
922 | gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) | |
923 | { | |
924 | TCGv temp = tcg_temp_new(); | |
925 | TCGv temp2 = tcg_temp_new(); | |
926 | ||
927 | tcg_gen_andi_tl(temp2, r1, 0xffff0000); | |
928 | tcg_gen_shli_tl(temp, r1, 16); | |
929 | gen_maddr64_h(ret, temp, temp2, r2, r3, n, mode); | |
930 | ||
931 | tcg_temp_free(temp); | |
932 | tcg_temp_free(temp2); | |
933 | } | |
934 | ||
bebe80fc BK |
935 | static inline void |
936 | gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) | |
937 | { | |
938 | TCGv temp = tcg_const_i32(n); | |
939 | TCGv temp2 = tcg_temp_new(); | |
940 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
941 | switch (mode) { | |
942 | case MODE_LL: | |
943 | GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); | |
944 | break; | |
945 | case MODE_LU: | |
946 | GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); | |
947 | break; | |
948 | case MODE_UL: | |
949 | GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); | |
950 | break; | |
951 | case MODE_UU: | |
952 | GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); | |
953 | break; | |
954 | } | |
955 | tcg_gen_andi_tl(temp2, r1, 0xffff0000); | |
956 | tcg_gen_shli_tl(temp, r1, 16); | |
957 | gen_helper_addsur_h(ret, cpu_env, temp64, temp, temp2); | |
958 | ||
959 | tcg_temp_free(temp); | |
960 | tcg_temp_free(temp2); | |
961 | tcg_temp_free_i64(temp64); | |
962 | } | |
963 | ||
964 | ||
2e430e1c BK |
965 | static inline void |
966 | gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, | |
967 | uint32_t n, uint32_t mode) | |
968 | { | |
969 | TCGv temp = tcg_const_i32(n); | |
970 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
971 | switch (mode) { | |
972 | case MODE_LL: | |
973 | GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); | |
974 | break; | |
975 | case MODE_LU: | |
976 | GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); | |
977 | break; | |
978 | case MODE_UL: | |
979 | GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); | |
980 | break; | |
981 | case MODE_UU: | |
982 | GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); | |
983 | break; | |
984 | } | |
985 | gen_helper_addr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high); | |
986 | ||
987 | tcg_temp_free(temp); | |
988 | tcg_temp_free_i64(temp64); | |
989 | } | |
990 | ||
991 | static inline void | |
992 | gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) | |
993 | { | |
994 | TCGv temp = tcg_temp_new(); | |
995 | TCGv temp2 = tcg_temp_new(); | |
996 | ||
997 | tcg_gen_andi_tl(temp2, r1, 0xffff0000); | |
998 | tcg_gen_shli_tl(temp, r1, 16); | |
999 | gen_maddr64s_h(ret, temp, temp2, r2, r3, n, mode); | |
1000 | ||
1001 | tcg_temp_free(temp); | |
1002 | tcg_temp_free(temp2); | |
1003 | } | |
1004 | ||
bebe80fc BK |
1005 | static inline void |
1006 | gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) | |
1007 | { | |
1008 | TCGv temp = tcg_const_i32(n); | |
1009 | TCGv temp2 = tcg_temp_new(); | |
1010 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
1011 | switch (mode) { | |
1012 | case MODE_LL: | |
1013 | GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); | |
1014 | break; | |
1015 | case MODE_LU: | |
1016 | GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); | |
1017 | break; | |
1018 | case MODE_UL: | |
1019 | GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); | |
1020 | break; | |
1021 | case MODE_UU: | |
1022 | GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); | |
1023 | break; | |
1024 | } | |
1025 | tcg_gen_andi_tl(temp2, r1, 0xffff0000); | |
1026 | tcg_gen_shli_tl(temp, r1, 16); | |
1027 | gen_helper_addsur_h_ssov(ret, cpu_env, temp64, temp, temp2); | |
1028 | ||
1029 | tcg_temp_free(temp); | |
1030 | tcg_temp_free(temp2); | |
1031 | tcg_temp_free_i64(temp64); | |
1032 | } | |
1033 | ||
b00aa8ec BK |
1034 | static inline void |
1035 | gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) | |
1036 | { | |
1037 | TCGv temp = tcg_const_i32(n); | |
1038 | gen_helper_maddr_q(ret, cpu_env, r1, r2, r3, temp); | |
1039 | tcg_temp_free(temp); | |
1040 | } | |
1041 | ||
1042 | static inline void | |
1043 | gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) | |
1044 | { | |
1045 | TCGv temp = tcg_const_i32(n); | |
1046 | gen_helper_maddr_q_ssov(ret, cpu_env, r1, r2, r3, temp); | |
1047 | tcg_temp_free(temp); | |
1048 | } | |
1049 | ||
1050 | static inline void | |
1051 | gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, | |
1052 | uint32_t up_shift, CPUTriCoreState *env) | |
1053 | { | |
1054 | TCGv temp = tcg_temp_new(); | |
1055 | TCGv temp2 = tcg_temp_new(); | |
1056 | TCGv temp3 = tcg_temp_new(); | |
1057 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1058 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1059 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1060 | ||
1061 | tcg_gen_ext_i32_i64(t2, arg2); | |
1062 | tcg_gen_ext_i32_i64(t3, arg3); | |
1063 | ||
1064 | tcg_gen_mul_i64(t2, t2, t3); | |
1065 | tcg_gen_shli_i64(t2, t2, n); | |
1066 | ||
1067 | tcg_gen_ext_i32_i64(t1, arg1); | |
1068 | tcg_gen_sari_i64(t2, t2, up_shift); | |
1069 | ||
1070 | tcg_gen_add_i64(t3, t1, t2); | |
1071 | tcg_gen_trunc_i64_i32(temp3, t3); | |
1072 | /* calc v bit */ | |
1073 | tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); | |
1074 | tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); | |
1075 | tcg_gen_or_i64(t1, t1, t2); | |
1076 | tcg_gen_trunc_i64_i32(cpu_PSW_V, t1); | |
1077 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); | |
1078 | /* We produce an overflow on the host if the mul before was | |
1079 | (0x80000000 * 0x80000000) << 1). If this is the | |
1080 | case, we negate the ovf. */ | |
1081 | if (n == 1) { | |
1082 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); | |
1083 | tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); | |
1084 | tcg_gen_and_tl(temp, temp, temp2); | |
1085 | tcg_gen_shli_tl(temp, temp, 31); | |
1086 | /* negate v bit, if special condition */ | |
1087 | tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); | |
1088 | } | |
1089 | /* Calc SV bit */ | |
1090 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1091 | /* Calc AV/SAV bits */ | |
1092 | tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3); | |
1093 | tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV); | |
1094 | /* calc SAV */ | |
1095 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1096 | /* write back result */ | |
1097 | tcg_gen_mov_tl(ret, temp3); | |
1098 | ||
1099 | tcg_temp_free(temp); | |
1100 | tcg_temp_free(temp2); | |
1101 | tcg_temp_free(temp3); | |
1102 | tcg_temp_free_i64(t1); | |
1103 | tcg_temp_free_i64(t2); | |
1104 | tcg_temp_free_i64(t3); | |
1105 | } | |
1106 | ||
1107 | static inline void | |
1108 | gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) | |
1109 | { | |
1110 | TCGv temp = tcg_temp_new(); | |
1111 | TCGv temp2 = tcg_temp_new(); | |
1112 | if (n == 0) { | |
1113 | tcg_gen_mul_tl(temp, arg2, arg3); | |
1114 | } else { /* n is exspected to be 1 */ | |
1115 | tcg_gen_mul_tl(temp, arg2, arg3); | |
1116 | tcg_gen_shli_tl(temp, temp, 1); | |
1117 | /* catch special case r1 = r2 = 0x8000 */ | |
1118 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); | |
1119 | tcg_gen_sub_tl(temp, temp, temp2); | |
1120 | } | |
1121 | gen_add_d(ret, arg1, temp); | |
1122 | ||
1123 | tcg_temp_free(temp); | |
1124 | tcg_temp_free(temp2); | |
1125 | } | |
1126 | ||
1127 | static inline void | |
1128 | gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) | |
1129 | { | |
1130 | TCGv temp = tcg_temp_new(); | |
1131 | TCGv temp2 = tcg_temp_new(); | |
1132 | if (n == 0) { | |
1133 | tcg_gen_mul_tl(temp, arg2, arg3); | |
1134 | } else { /* n is exspected to be 1 */ | |
1135 | tcg_gen_mul_tl(temp, arg2, arg3); | |
1136 | tcg_gen_shli_tl(temp, temp, 1); | |
1137 | /* catch special case r1 = r2 = 0x8000 */ | |
1138 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); | |
1139 | tcg_gen_sub_tl(temp, temp, temp2); | |
1140 | } | |
1141 | gen_adds(ret, arg1, temp); | |
1142 | ||
1143 | tcg_temp_free(temp); | |
1144 | tcg_temp_free(temp2); | |
1145 | } | |
1146 | ||
1147 | static inline void | |
1148 | gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, | |
1149 | TCGv arg3, uint32_t n) | |
1150 | { | |
1151 | TCGv temp = tcg_temp_new(); | |
1152 | TCGv temp2 = tcg_temp_new(); | |
1153 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1154 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1155 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1156 | ||
1157 | if (n == 0) { | |
1158 | tcg_gen_mul_tl(temp, arg2, arg3); | |
1159 | } else { /* n is exspected to be 1 */ | |
1160 | tcg_gen_mul_tl(temp, arg2, arg3); | |
1161 | tcg_gen_shli_tl(temp, temp, 1); | |
1162 | /* catch special case r1 = r2 = 0x8000 */ | |
1163 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); | |
1164 | tcg_gen_sub_tl(temp, temp, temp2); | |
1165 | } | |
1166 | tcg_gen_ext_i32_i64(t2, temp); | |
1167 | tcg_gen_shli_i64(t2, t2, 16); | |
1168 | tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); | |
1169 | gen_add64_d(t3, t1, t2); | |
1170 | /* write back result */ | |
1171 | tcg_gen_extr_i64_i32(rl, rh, t3); | |
1172 | ||
1173 | tcg_temp_free_i64(t1); | |
1174 | tcg_temp_free_i64(t2); | |
1175 | tcg_temp_free_i64(t3); | |
1176 | tcg_temp_free(temp); | |
1177 | tcg_temp_free(temp2); | |
1178 | } | |
1179 | ||
1180 | static inline void | |
1181 | gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, | |
1182 | TCGv arg3, uint32_t n) | |
1183 | { | |
1184 | TCGv temp = tcg_temp_new(); | |
1185 | TCGv temp2 = tcg_temp_new(); | |
1186 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1187 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1188 | ||
1189 | if (n == 0) { | |
1190 | tcg_gen_mul_tl(temp, arg2, arg3); | |
1191 | } else { /* n is exspected to be 1 */ | |
1192 | tcg_gen_mul_tl(temp, arg2, arg3); | |
1193 | tcg_gen_shli_tl(temp, temp, 1); | |
1194 | /* catch special case r1 = r2 = 0x8000 */ | |
1195 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); | |
1196 | tcg_gen_sub_tl(temp, temp, temp2); | |
1197 | } | |
1198 | tcg_gen_ext_i32_i64(t2, temp); | |
1199 | tcg_gen_shli_i64(t2, t2, 16); | |
1200 | tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); | |
1201 | ||
1202 | gen_helper_add64_ssov(t1, cpu_env, t1, t2); | |
1203 | tcg_gen_extr_i64_i32(rl, rh, t1); | |
1204 | ||
1205 | tcg_temp_free(temp); | |
1206 | tcg_temp_free(temp2); | |
1207 | tcg_temp_free_i64(t1); | |
1208 | tcg_temp_free_i64(t2); | |
1209 | } | |
1210 | ||
1211 | static inline void | |
1212 | gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, | |
1213 | TCGv arg3, uint32_t n, CPUTriCoreState *env) | |
1214 | { | |
1215 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1216 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1217 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1218 | TCGv_i64 t4 = tcg_temp_new_i64(); | |
1219 | TCGv temp, temp2; | |
1220 | ||
1221 | tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); | |
1222 | tcg_gen_ext_i32_i64(t2, arg2); | |
1223 | tcg_gen_ext_i32_i64(t3, arg3); | |
1224 | ||
1225 | tcg_gen_mul_i64(t2, t2, t3); | |
1226 | if (n != 0) { | |
1227 | tcg_gen_shli_i64(t2, t2, 1); | |
1228 | } | |
1229 | tcg_gen_add_i64(t4, t1, t2); | |
1230 | /* calc v bit */ | |
1231 | tcg_gen_xor_i64(t3, t4, t1); | |
1232 | tcg_gen_xor_i64(t2, t1, t2); | |
1233 | tcg_gen_andc_i64(t3, t3, t2); | |
1234 | tcg_gen_trunc_shr_i64_i32(cpu_PSW_V, t3, 32); | |
1235 | /* We produce an overflow on the host if the mul before was | |
1236 | (0x80000000 * 0x80000000) << 1). If this is the | |
1237 | case, we negate the ovf. */ | |
1238 | if (n == 1) { | |
1239 | temp = tcg_temp_new(); | |
1240 | temp2 = tcg_temp_new(); | |
1241 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); | |
1242 | tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); | |
1243 | tcg_gen_and_tl(temp, temp, temp2); | |
1244 | tcg_gen_shli_tl(temp, temp, 31); | |
1245 | /* negate v bit, if special condition */ | |
1246 | tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); | |
1247 | ||
1248 | tcg_temp_free(temp); | |
1249 | tcg_temp_free(temp2); | |
1250 | } | |
1251 | /* write back result */ | |
1252 | tcg_gen_extr_i64_i32(rl, rh, t4); | |
1253 | /* Calc SV bit */ | |
1254 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1255 | /* Calc AV/SAV bits */ | |
1256 | tcg_gen_add_tl(cpu_PSW_AV, rh, rh); | |
1257 | tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); | |
1258 | /* calc SAV */ | |
1259 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1260 | ||
1261 | tcg_temp_free_i64(t1); | |
1262 | tcg_temp_free_i64(t2); | |
1263 | tcg_temp_free_i64(t3); | |
1264 | tcg_temp_free_i64(t4); | |
1265 | } | |
1266 | ||
1267 | static inline void | |
1268 | gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, | |
1269 | uint32_t up_shift) | |
1270 | { | |
1271 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1272 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1273 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1274 | ||
1275 | tcg_gen_ext_i32_i64(t1, arg1); | |
1276 | tcg_gen_ext_i32_i64(t2, arg2); | |
1277 | tcg_gen_ext_i32_i64(t3, arg3); | |
1278 | ||
1279 | tcg_gen_mul_i64(t2, t2, t3); | |
1280 | tcg_gen_sari_i64(t2, t2, up_shift - n); | |
1281 | ||
1282 | gen_helper_madd32_q_add_ssov(ret, cpu_env, t1, t2); | |
1283 | ||
1284 | tcg_temp_free_i64(t1); | |
1285 | tcg_temp_free_i64(t2); | |
1286 | tcg_temp_free_i64(t3); | |
1287 | } | |
1288 | ||
1289 | static inline void | |
1290 | gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, | |
1291 | TCGv arg3, uint32_t n) | |
1292 | { | |
1293 | TCGv_i64 r1 = tcg_temp_new_i64(); | |
1294 | TCGv temp = tcg_const_i32(n); | |
1295 | ||
1296 | tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); | |
1297 | gen_helper_madd64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp); | |
1298 | tcg_gen_extr_i64_i32(rl, rh, r1); | |
2e430e1c | 1299 | |
b00aa8ec BK |
1300 | tcg_temp_free_i64(r1); |
1301 | tcg_temp_free(temp); | |
1302 | } | |
328f1f0f BK |
1303 | /* ret = r2 - (r1 * r3); */ |
1304 | static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3) | |
1305 | { | |
1306 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1307 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1308 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1309 | ||
1310 | tcg_gen_ext_i32_i64(t1, r1); | |
1311 | tcg_gen_ext_i32_i64(t2, r2); | |
1312 | tcg_gen_ext_i32_i64(t3, r3); | |
1313 | ||
1314 | tcg_gen_mul_i64(t1, t1, t3); | |
1315 | tcg_gen_sub_i64(t1, t2, t1); | |
1316 | ||
1317 | tcg_gen_trunc_i64_i32(ret, t1); | |
1318 | /* calc V | |
1319 | t2 > 0x7fffffff */ | |
1320 | tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); | |
1321 | /* result < -0x80000000 */ | |
1322 | tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); | |
1323 | tcg_gen_or_i64(t2, t2, t3); | |
1324 | tcg_gen_trunc_i64_i32(cpu_PSW_V, t2); | |
1325 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); | |
1326 | ||
1327 | /* Calc SV bit */ | |
1328 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1329 | /* Calc AV/SAV bits */ | |
1330 | tcg_gen_add_tl(cpu_PSW_AV, ret, ret); | |
1331 | tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); | |
1332 | /* calc SAV */ | |
1333 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1334 | ||
1335 | tcg_temp_free_i64(t1); | |
1336 | tcg_temp_free_i64(t2); | |
1337 | tcg_temp_free_i64(t3); | |
1338 | } | |
1339 | ||
1340 | static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) | |
1341 | { | |
1342 | TCGv temp = tcg_const_i32(con); | |
1343 | gen_msub32_d(ret, r1, r2, temp); | |
1344 | tcg_temp_free(temp); | |
1345 | } | |
1346 | ||
1347 | static inline void | |
1348 | gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
1349 | TCGv r3) | |
1350 | { | |
1351 | TCGv t1 = tcg_temp_new(); | |
1352 | TCGv t2 = tcg_temp_new(); | |
1353 | TCGv t3 = tcg_temp_new(); | |
1354 | TCGv t4 = tcg_temp_new(); | |
1355 | ||
1356 | tcg_gen_muls2_tl(t1, t2, r1, r3); | |
1357 | /* only the sub can overflow */ | |
1358 | tcg_gen_sub2_tl(t3, t4, r2_low, r2_high, t1, t2); | |
1359 | /* calc V bit */ | |
1360 | tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high); | |
1361 | tcg_gen_xor_tl(t1, r2_high, t2); | |
1362 | tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, t1); | |
1363 | /* Calc SV bit */ | |
1364 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1365 | /* Calc AV/SAV bits */ | |
1366 | tcg_gen_add_tl(cpu_PSW_AV, t4, t4); | |
1367 | tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV); | |
1368 | /* calc SAV */ | |
1369 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1370 | /* write back the result */ | |
1371 | tcg_gen_mov_tl(ret_low, t3); | |
1372 | tcg_gen_mov_tl(ret_high, t4); | |
1373 | ||
1374 | tcg_temp_free(t1); | |
1375 | tcg_temp_free(t2); | |
1376 | tcg_temp_free(t3); | |
1377 | tcg_temp_free(t4); | |
1378 | } | |
1379 | ||
1380 | static inline void | |
1381 | gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
1382 | int32_t con) | |
1383 | { | |
1384 | TCGv temp = tcg_const_i32(con); | |
1385 | gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); | |
1386 | tcg_temp_free(temp); | |
1387 | } | |
1388 | ||
1389 | static inline void | |
1390 | gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
1391 | TCGv r3) | |
1392 | { | |
1393 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1394 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1395 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1396 | ||
1397 | tcg_gen_extu_i32_i64(t1, r1); | |
1398 | tcg_gen_concat_i32_i64(t2, r2_low, r2_high); | |
1399 | tcg_gen_extu_i32_i64(t3, r3); | |
1400 | ||
1401 | tcg_gen_mul_i64(t1, t1, t3); | |
1402 | tcg_gen_sub_i64(t3, t2, t1); | |
1403 | tcg_gen_extr_i64_i32(ret_low, ret_high, t3); | |
1404 | /* calc V bit, only the sub can overflow, if t1 > t2 */ | |
1405 | tcg_gen_setcond_i64(TCG_COND_GTU, t1, t1, t2); | |
1406 | tcg_gen_trunc_i64_i32(cpu_PSW_V, t1); | |
1407 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); | |
1408 | /* Calc SV bit */ | |
1409 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1410 | /* Calc AV/SAV bits */ | |
1411 | tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); | |
1412 | tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); | |
1413 | /* calc SAV */ | |
1414 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1415 | ||
1416 | tcg_temp_free_i64(t1); | |
1417 | tcg_temp_free_i64(t2); | |
1418 | tcg_temp_free_i64(t3); | |
1419 | } | |
1420 | ||
1421 | static inline void | |
1422 | gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
1423 | int32_t con) | |
1424 | { | |
1425 | TCGv temp = tcg_const_i32(con); | |
1426 | gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); | |
1427 | tcg_temp_free(temp); | |
1428 | } | |
1429 | ||
0707ec1b BK |
1430 | static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2) |
1431 | { | |
1432 | TCGv temp = tcg_const_i32(r2); | |
1433 | gen_add_d(ret, r1, temp); | |
1434 | tcg_temp_free(temp); | |
1435 | } | |
0974257e BK |
1436 | /* calculate the carry bit too */ |
1437 | static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2) | |
1438 | { | |
1439 | TCGv t0 = tcg_temp_new_i32(); | |
1440 | TCGv result = tcg_temp_new_i32(); | |
1441 | ||
1442 | tcg_gen_movi_tl(t0, 0); | |
1443 | /* Addition and set C/V/SV bits */ | |
1444 | tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, r2, t0); | |
1445 | /* calc V bit */ | |
1446 | tcg_gen_xor_tl(cpu_PSW_V, result, r1); | |
1447 | tcg_gen_xor_tl(t0, r1, r2); | |
1448 | tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); | |
1449 | /* Calc SV bit */ | |
1450 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1451 | /* Calc AV/SAV bits */ | |
1452 | tcg_gen_add_tl(cpu_PSW_AV, result, result); | |
1453 | tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); | |
1454 | /* calc SAV */ | |
1455 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1456 | /* write back result */ | |
1457 | tcg_gen_mov_tl(ret, result); | |
1458 | ||
1459 | tcg_temp_free(result); | |
1460 | tcg_temp_free(t0); | |
1461 | } | |
1462 | ||
1463 | static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con) | |
1464 | { | |
1465 | TCGv temp = tcg_const_i32(con); | |
1466 | gen_add_CC(ret, r1, temp); | |
1467 | tcg_temp_free(temp); | |
1468 | } | |
1469 | ||
1470 | static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2) | |
1471 | { | |
1472 | TCGv carry = tcg_temp_new_i32(); | |
1473 | TCGv t0 = tcg_temp_new_i32(); | |
1474 | TCGv result = tcg_temp_new_i32(); | |
1475 | ||
1476 | tcg_gen_movi_tl(t0, 0); | |
1477 | tcg_gen_setcondi_tl(TCG_COND_NE, carry, cpu_PSW_C, 0); | |
1478 | /* Addition, carry and set C/V/SV bits */ | |
1479 | tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, carry, t0); | |
1480 | tcg_gen_add2_i32(result, cpu_PSW_C, result, cpu_PSW_C, r2, t0); | |
1481 | /* calc V bit */ | |
1482 | tcg_gen_xor_tl(cpu_PSW_V, result, r1); | |
1483 | tcg_gen_xor_tl(t0, r1, r2); | |
1484 | tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); | |
1485 | /* Calc SV bit */ | |
1486 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1487 | /* Calc AV/SAV bits */ | |
1488 | tcg_gen_add_tl(cpu_PSW_AV, result, result); | |
1489 | tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); | |
1490 | /* calc SAV */ | |
1491 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1492 | /* write back result */ | |
1493 | tcg_gen_mov_tl(ret, result); | |
1494 | ||
1495 | tcg_temp_free(result); | |
1496 | tcg_temp_free(t0); | |
1497 | tcg_temp_free(carry); | |
1498 | } | |
1499 | ||
1500 | static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con) | |
1501 | { | |
1502 | TCGv temp = tcg_const_i32(con); | |
1503 | gen_addc_CC(ret, r1, temp); | |
1504 | tcg_temp_free(temp); | |
1505 | } | |
0707ec1b BK |
1506 | |
1507 | static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, | |
1508 | TCGv r4) | |
1509 | { | |
1510 | TCGv temp = tcg_temp_new(); | |
1511 | TCGv temp2 = tcg_temp_new(); | |
1512 | TCGv result = tcg_temp_new(); | |
1513 | TCGv mask = tcg_temp_new(); | |
1514 | TCGv t0 = tcg_const_i32(0); | |
1515 | ||
1516 | /* create mask for sticky bits */ | |
1517 | tcg_gen_setcond_tl(cond, mask, r4, t0); | |
1518 | tcg_gen_shli_tl(mask, mask, 31); | |
1519 | ||
1520 | tcg_gen_add_tl(result, r1, r2); | |
1521 | /* Calc PSW_V */ | |
1522 | tcg_gen_xor_tl(temp, result, r1); | |
1523 | tcg_gen_xor_tl(temp2, r1, r2); | |
1524 | tcg_gen_andc_tl(temp, temp, temp2); | |
1525 | tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V); | |
1526 | /* Set PSW_SV */ | |
1527 | tcg_gen_and_tl(temp, temp, mask); | |
1528 | tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV); | |
1529 | /* calc AV bit */ | |
1530 | tcg_gen_add_tl(temp, result, result); | |
1531 | tcg_gen_xor_tl(temp, temp, result); | |
1532 | tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV); | |
1533 | /* calc SAV bit */ | |
1534 | tcg_gen_and_tl(temp, temp, mask); | |
1535 | tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV); | |
1536 | /* write back result */ | |
5f30046f | 1537 | tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1); |
0707ec1b BK |
1538 | |
1539 | tcg_temp_free(t0); | |
1540 | tcg_temp_free(temp); | |
1541 | tcg_temp_free(temp2); | |
1542 | tcg_temp_free(result); | |
1543 | tcg_temp_free(mask); | |
1544 | } | |
1545 | ||
1546 | static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2, | |
1547 | TCGv r3, TCGv r4) | |
1548 | { | |
1549 | TCGv temp = tcg_const_i32(r2); | |
1550 | gen_cond_add(cond, r1, temp, r3, r4); | |
1551 | tcg_temp_free(temp); | |
1552 | } | |
1553 | ||
2692802a BK |
1554 | static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2) |
1555 | { | |
1556 | TCGv temp = tcg_temp_new_i32(); | |
1557 | TCGv result = tcg_temp_new_i32(); | |
1558 | ||
1559 | tcg_gen_sub_tl(result, r1, r2); | |
1560 | /* calc V bit */ | |
1561 | tcg_gen_xor_tl(cpu_PSW_V, result, r1); | |
1562 | tcg_gen_xor_tl(temp, r1, r2); | |
1563 | tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); | |
1564 | /* calc SV bit */ | |
1565 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1566 | /* Calc AV bit */ | |
1567 | tcg_gen_add_tl(cpu_PSW_AV, result, result); | |
1568 | tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); | |
1569 | /* calc SAV bit */ | |
1570 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1571 | /* write back result */ | |
1572 | tcg_gen_mov_tl(ret, result); | |
1573 | ||
1574 | tcg_temp_free(temp); | |
1575 | tcg_temp_free(result); | |
1576 | } | |
1577 | ||
d5de7839 BK |
1578 | static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2) |
1579 | { | |
1580 | TCGv result = tcg_temp_new(); | |
1581 | TCGv temp = tcg_temp_new(); | |
1582 | ||
1583 | tcg_gen_sub_tl(result, r1, r2); | |
1584 | /* calc C bit */ | |
1585 | tcg_gen_setcond_tl(TCG_COND_GEU, cpu_PSW_C, r1, r2); | |
1586 | /* calc V bit */ | |
1587 | tcg_gen_xor_tl(cpu_PSW_V, result, r1); | |
1588 | tcg_gen_xor_tl(temp, r1, r2); | |
1589 | tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); | |
1590 | /* calc SV bit */ | |
1591 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1592 | /* Calc AV bit */ | |
1593 | tcg_gen_add_tl(cpu_PSW_AV, result, result); | |
1594 | tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); | |
1595 | /* calc SAV bit */ | |
1596 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1597 | /* write back result */ | |
1598 | tcg_gen_mov_tl(ret, result); | |
1599 | ||
1600 | tcg_temp_free(result); | |
1601 | tcg_temp_free(temp); | |
1602 | } | |
1603 | ||
1604 | static inline void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2) | |
1605 | { | |
1606 | TCGv temp = tcg_temp_new(); | |
1607 | tcg_gen_not_tl(temp, r2); | |
1608 | gen_addc_CC(ret, r1, temp); | |
1609 | tcg_temp_free(temp); | |
1610 | } | |
1611 | ||
09532255 BK |
1612 | static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, |
1613 | TCGv r4) | |
1614 | { | |
1615 | TCGv temp = tcg_temp_new(); | |
1616 | TCGv temp2 = tcg_temp_new(); | |
1617 | TCGv result = tcg_temp_new(); | |
1618 | TCGv mask = tcg_temp_new(); | |
1619 | TCGv t0 = tcg_const_i32(0); | |
1620 | ||
1621 | /* create mask for sticky bits */ | |
1622 | tcg_gen_setcond_tl(cond, mask, r4, t0); | |
1623 | tcg_gen_shli_tl(mask, mask, 31); | |
1624 | ||
1625 | tcg_gen_sub_tl(result, r1, r2); | |
1626 | /* Calc PSW_V */ | |
1627 | tcg_gen_xor_tl(temp, result, r1); | |
1628 | tcg_gen_xor_tl(temp2, r1, r2); | |
1629 | tcg_gen_and_tl(temp, temp, temp2); | |
1630 | tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V); | |
1631 | /* Set PSW_SV */ | |
1632 | tcg_gen_and_tl(temp, temp, mask); | |
1633 | tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV); | |
1634 | /* calc AV bit */ | |
1635 | tcg_gen_add_tl(temp, result, result); | |
1636 | tcg_gen_xor_tl(temp, temp, result); | |
1637 | tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV); | |
1638 | /* calc SAV bit */ | |
1639 | tcg_gen_and_tl(temp, temp, mask); | |
1640 | tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV); | |
1641 | /* write back result */ | |
1642 | tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1); | |
1643 | ||
1644 | tcg_temp_free(t0); | |
1645 | tcg_temp_free(temp); | |
1646 | tcg_temp_free(temp2); | |
1647 | tcg_temp_free(result); | |
1648 | tcg_temp_free(mask); | |
1649 | } | |
1650 | ||
d5de7839 BK |
1651 | static inline void gen_abs(TCGv ret, TCGv r1) |
1652 | { | |
1653 | TCGv temp = tcg_temp_new(); | |
1654 | TCGv t0 = tcg_const_i32(0); | |
1655 | ||
1656 | tcg_gen_neg_tl(temp, r1); | |
1657 | tcg_gen_movcond_tl(TCG_COND_GE, ret, r1, t0, r1, temp); | |
1658 | /* overflow can only happen, if r1 = 0x80000000 */ | |
1659 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000); | |
1660 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); | |
1661 | /* calc SV bit */ | |
1662 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1663 | /* Calc AV bit */ | |
1664 | tcg_gen_add_tl(cpu_PSW_AV, ret, ret); | |
1665 | tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); | |
1666 | /* calc SAV bit */ | |
1667 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1668 | ||
1669 | tcg_temp_free(temp); | |
1670 | tcg_temp_free(t0); | |
1671 | } | |
1672 | ||
0974257e BK |
1673 | static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2) |
1674 | { | |
1675 | TCGv temp = tcg_temp_new_i32(); | |
1676 | TCGv result = tcg_temp_new_i32(); | |
1677 | ||
1678 | tcg_gen_sub_tl(result, r1, r2); | |
1679 | tcg_gen_sub_tl(temp, r2, r1); | |
1680 | tcg_gen_movcond_tl(TCG_COND_GT, result, r1, r2, result, temp); | |
1681 | ||
1682 | /* calc V bit */ | |
1683 | tcg_gen_xor_tl(cpu_PSW_V, result, r1); | |
1684 | tcg_gen_xor_tl(temp, result, r2); | |
1685 | tcg_gen_movcond_tl(TCG_COND_GT, cpu_PSW_V, r1, r2, cpu_PSW_V, temp); | |
1686 | tcg_gen_xor_tl(temp, r1, r2); | |
1687 | tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); | |
1688 | /* calc SV bit */ | |
1689 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1690 | /* Calc AV bit */ | |
1691 | tcg_gen_add_tl(cpu_PSW_AV, result, result); | |
1692 | tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); | |
1693 | /* calc SAV bit */ | |
1694 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1695 | /* write back result */ | |
1696 | tcg_gen_mov_tl(ret, result); | |
1697 | ||
1698 | tcg_temp_free(temp); | |
1699 | tcg_temp_free(result); | |
1700 | } | |
1701 | ||
1702 | static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con) | |
1703 | { | |
1704 | TCGv temp = tcg_const_i32(con); | |
1705 | gen_absdif(ret, r1, temp); | |
1706 | tcg_temp_free(temp); | |
1707 | } | |
1708 | ||
1709 | static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con) | |
1710 | { | |
1711 | TCGv temp = tcg_const_i32(con); | |
1712 | gen_helper_absdif_ssov(ret, cpu_env, r1, temp); | |
1713 | tcg_temp_free(temp); | |
1714 | } | |
1715 | ||
2692802a BK |
1716 | static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2) |
1717 | { | |
1718 | TCGv high = tcg_temp_new(); | |
1719 | TCGv low = tcg_temp_new(); | |
1720 | ||
1721 | tcg_gen_muls2_tl(low, high, r1, r2); | |
1722 | tcg_gen_mov_tl(ret, low); | |
1723 | /* calc V bit */ | |
1724 | tcg_gen_sari_tl(low, low, 31); | |
1725 | tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low); | |
1726 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); | |
1727 | /* calc SV bit */ | |
1728 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1729 | /* Calc AV bit */ | |
1730 | tcg_gen_add_tl(cpu_PSW_AV, ret, ret); | |
1731 | tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); | |
1732 | /* calc SAV bit */ | |
1733 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1734 | ||
1735 | tcg_temp_free(high); | |
1736 | tcg_temp_free(low); | |
1737 | } | |
1738 | ||
0974257e BK |
1739 | static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con) |
1740 | { | |
1741 | TCGv temp = tcg_const_i32(con); | |
1742 | gen_mul_i32s(ret, r1, temp); | |
1743 | tcg_temp_free(temp); | |
1744 | } | |
1745 | ||
1746 | static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2) | |
1747 | { | |
1748 | tcg_gen_muls2_tl(ret_low, ret_high, r1, r2); | |
1749 | /* clear V bit */ | |
1750 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
1751 | /* calc SV bit */ | |
1752 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1753 | /* Calc AV bit */ | |
1754 | tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); | |
1755 | tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); | |
1756 | /* calc SAV bit */ | |
1757 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1758 | } | |
1759 | ||
1760 | static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, | |
1761 | int32_t con) | |
1762 | { | |
1763 | TCGv temp = tcg_const_i32(con); | |
1764 | gen_mul_i64s(ret_low, ret_high, r1, temp); | |
1765 | tcg_temp_free(temp); | |
1766 | } | |
1767 | ||
1768 | static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2) | |
1769 | { | |
1770 | tcg_gen_mulu2_tl(ret_low, ret_high, r1, r2); | |
1771 | /* clear V bit */ | |
1772 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
1773 | /* calc SV bit */ | |
1774 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1775 | /* Calc AV bit */ | |
1776 | tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); | |
1777 | tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); | |
1778 | /* calc SAV bit */ | |
1779 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1780 | } | |
1781 | ||
1782 | static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, | |
1783 | int32_t con) | |
1784 | { | |
1785 | TCGv temp = tcg_const_i32(con); | |
1786 | gen_mul_i64u(ret_low, ret_high, r1, temp); | |
1787 | tcg_temp_free(temp); | |
1788 | } | |
1789 | ||
1790 | static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con) | |
1791 | { | |
1792 | TCGv temp = tcg_const_i32(con); | |
1793 | gen_helper_mul_ssov(ret, cpu_env, r1, temp); | |
1794 | tcg_temp_free(temp); | |
1795 | } | |
1796 | ||
1797 | static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con) | |
1798 | { | |
1799 | TCGv temp = tcg_const_i32(con); | |
1800 | gen_helper_mul_suov(ret, cpu_env, r1, temp); | |
1801 | tcg_temp_free(temp); | |
1802 | } | |
328f1f0f BK |
1803 | /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */ |
1804 | static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) | |
1805 | { | |
1806 | TCGv temp = tcg_const_i32(con); | |
1807 | gen_helper_madd32_ssov(ret, cpu_env, r1, r2, temp); | |
1808 | tcg_temp_free(temp); | |
1809 | } | |
1810 | ||
1811 | static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) | |
1812 | { | |
1813 | TCGv temp = tcg_const_i32(con); | |
1814 | gen_helper_madd32_suov(ret, cpu_env, r1, r2, temp); | |
1815 | tcg_temp_free(temp); | |
1816 | } | |
1817 | ||
f1cc6eaf BK |
1818 | static void |
1819 | gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift) | |
1820 | { | |
1821 | TCGv temp = tcg_temp_new(); | |
1822 | TCGv_i64 temp_64 = tcg_temp_new_i64(); | |
1823 | TCGv_i64 temp2_64 = tcg_temp_new_i64(); | |
1824 | ||
1825 | if (n == 0) { | |
1826 | if (up_shift == 32) { | |
1827 | tcg_gen_muls2_tl(rh, rl, arg1, arg2); | |
1828 | } else if (up_shift == 16) { | |
1829 | tcg_gen_ext_i32_i64(temp_64, arg1); | |
1830 | tcg_gen_ext_i32_i64(temp2_64, arg2); | |
1831 | ||
1832 | tcg_gen_mul_i64(temp_64, temp_64, temp2_64); | |
1833 | tcg_gen_shri_i64(temp_64, temp_64, up_shift); | |
1834 | tcg_gen_extr_i64_i32(rl, rh, temp_64); | |
1835 | } else { | |
1836 | tcg_gen_muls2_tl(rl, rh, arg1, arg2); | |
1837 | } | |
1838 | /* reset v bit */ | |
1839 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
1840 | } else { /* n is exspected to be 1 */ | |
1841 | tcg_gen_ext_i32_i64(temp_64, arg1); | |
1842 | tcg_gen_ext_i32_i64(temp2_64, arg2); | |
1843 | ||
1844 | tcg_gen_mul_i64(temp_64, temp_64, temp2_64); | |
1845 | ||
1846 | if (up_shift == 0) { | |
1847 | tcg_gen_shli_i64(temp_64, temp_64, 1); | |
1848 | } else { | |
1849 | tcg_gen_shri_i64(temp_64, temp_64, up_shift - 1); | |
1850 | } | |
1851 | tcg_gen_extr_i64_i32(rl, rh, temp_64); | |
1852 | /* overflow only occours if r1 = r2 = 0x8000 */ | |
1853 | if (up_shift == 0) {/* result is 64 bit */ | |
1854 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rh, | |
1855 | 0x80000000); | |
1856 | } else { /* result is 32 bit */ | |
1857 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rl, | |
1858 | 0x80000000); | |
1859 | } | |
1860 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); | |
1861 | /* calc sv overflow bit */ | |
1862 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1863 | } | |
1864 | /* calc av overflow bit */ | |
1865 | if (up_shift == 0) { | |
1866 | tcg_gen_add_tl(cpu_PSW_AV, rh, rh); | |
1867 | tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); | |
1868 | } else { | |
1869 | tcg_gen_add_tl(cpu_PSW_AV, rl, rl); | |
1870 | tcg_gen_xor_tl(cpu_PSW_AV, rl, cpu_PSW_AV); | |
1871 | } | |
1872 | /* calc sav overflow bit */ | |
1873 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1874 | tcg_temp_free(temp); | |
1875 | tcg_temp_free_i64(temp_64); | |
1876 | tcg_temp_free_i64(temp2_64); | |
1877 | } | |
1878 | ||
1879 | static void | |
1880 | gen_mul_q_16(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n) | |
1881 | { | |
1882 | TCGv temp = tcg_temp_new(); | |
1883 | if (n == 0) { | |
1884 | tcg_gen_mul_tl(ret, arg1, arg2); | |
1885 | } else { /* n is exspected to be 1 */ | |
1886 | tcg_gen_mul_tl(ret, arg1, arg2); | |
1887 | tcg_gen_shli_tl(ret, ret, 1); | |
1888 | /* catch special case r1 = r2 = 0x8000 */ | |
1889 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80000000); | |
1890 | tcg_gen_sub_tl(ret, ret, temp); | |
1891 | } | |
1892 | /* reset v bit */ | |
1893 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
1894 | /* calc av overflow bit */ | |
1895 | tcg_gen_add_tl(cpu_PSW_AV, ret, ret); | |
1896 | tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); | |
1897 | /* calc sav overflow bit */ | |
1898 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1899 | ||
1900 | tcg_temp_free(temp); | |
1901 | } | |
1902 | ||
1903 | static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n) | |
1904 | { | |
1905 | TCGv temp = tcg_temp_new(); | |
1906 | if (n == 0) { | |
1907 | tcg_gen_mul_tl(ret, arg1, arg2); | |
1908 | tcg_gen_addi_tl(ret, ret, 0x8000); | |
1909 | } else { | |
1910 | tcg_gen_mul_tl(ret, arg1, arg2); | |
1911 | tcg_gen_shli_tl(ret, ret, 1); | |
1912 | tcg_gen_addi_tl(ret, ret, 0x8000); | |
1913 | /* catch special case r1 = r2 = 0x8000 */ | |
1914 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80008000); | |
1915 | tcg_gen_muli_tl(temp, temp, 0x8001); | |
1916 | tcg_gen_sub_tl(ret, ret, temp); | |
1917 | } | |
1918 | /* reset v bit */ | |
1919 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
1920 | /* calc av overflow bit */ | |
1921 | tcg_gen_add_tl(cpu_PSW_AV, ret, ret); | |
1922 | tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); | |
1923 | /* calc sav overflow bit */ | |
1924 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1925 | /* cut halfword off */ | |
1926 | tcg_gen_andi_tl(ret, ret, 0xffff0000); | |
1927 | ||
1928 | tcg_temp_free(temp); | |
1929 | } | |
1930 | ||
2984cfbd BK |
1931 | static inline void |
1932 | gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
1933 | TCGv r3) | |
1934 | { | |
1935 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
1936 | tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); | |
1937 | gen_helper_madd64_ssov(temp64, cpu_env, r1, temp64, r3); | |
1938 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); | |
1939 | tcg_temp_free_i64(temp64); | |
1940 | } | |
1941 | ||
328f1f0f BK |
1942 | static inline void |
1943 | gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
1944 | int32_t con) | |
1945 | { | |
1946 | TCGv temp = tcg_const_i32(con); | |
2984cfbd BK |
1947 | gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp); |
1948 | tcg_temp_free(temp); | |
1949 | } | |
1950 | ||
1951 | static inline void | |
1952 | gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
1953 | TCGv r3) | |
1954 | { | |
328f1f0f BK |
1955 | TCGv_i64 temp64 = tcg_temp_new_i64(); |
1956 | tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); | |
2984cfbd | 1957 | gen_helper_madd64_suov(temp64, cpu_env, r1, temp64, r3); |
328f1f0f | 1958 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); |
328f1f0f BK |
1959 | tcg_temp_free_i64(temp64); |
1960 | } | |
1961 | ||
1962 | static inline void | |
1963 | gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
1964 | int32_t con) | |
1965 | { | |
1966 | TCGv temp = tcg_const_i32(con); | |
2984cfbd | 1967 | gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); |
328f1f0f | 1968 | tcg_temp_free(temp); |
328f1f0f BK |
1969 | } |
1970 | ||
1971 | static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) | |
1972 | { | |
1973 | TCGv temp = tcg_const_i32(con); | |
1974 | gen_helper_msub32_ssov(ret, cpu_env, r1, r2, temp); | |
1975 | tcg_temp_free(temp); | |
1976 | } | |
1977 | ||
1978 | static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) | |
1979 | { | |
1980 | TCGv temp = tcg_const_i32(con); | |
1981 | gen_helper_msub32_suov(ret, cpu_env, r1, r2, temp); | |
1982 | tcg_temp_free(temp); | |
1983 | } | |
1984 | ||
2984cfbd BK |
1985 | static inline void |
1986 | gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
1987 | TCGv r3) | |
1988 | { | |
1989 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
1990 | tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); | |
1991 | gen_helper_msub64_ssov(temp64, cpu_env, r1, temp64, r3); | |
1992 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); | |
1993 | tcg_temp_free_i64(temp64); | |
1994 | } | |
1995 | ||
328f1f0f BK |
1996 | static inline void |
1997 | gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
1998 | int32_t con) | |
1999 | { | |
2000 | TCGv temp = tcg_const_i32(con); | |
2984cfbd BK |
2001 | gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp); |
2002 | tcg_temp_free(temp); | |
2003 | } | |
2004 | ||
2005 | static inline void | |
2006 | gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
2007 | TCGv r3) | |
2008 | { | |
328f1f0f BK |
2009 | TCGv_i64 temp64 = tcg_temp_new_i64(); |
2010 | tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); | |
2984cfbd | 2011 | gen_helper_msub64_suov(temp64, cpu_env, r1, temp64, r3); |
328f1f0f | 2012 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); |
328f1f0f BK |
2013 | tcg_temp_free_i64(temp64); |
2014 | } | |
2015 | ||
2016 | static inline void | |
2017 | gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
2018 | int32_t con) | |
2019 | { | |
2020 | TCGv temp = tcg_const_i32(con); | |
2984cfbd | 2021 | gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); |
328f1f0f | 2022 | tcg_temp_free(temp); |
328f1f0f | 2023 | } |
0974257e | 2024 | |
44ea3430 BK |
2025 | static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low) |
2026 | { | |
2027 | TCGv sat_neg = tcg_const_i32(low); | |
2028 | TCGv temp = tcg_const_i32(up); | |
2029 | ||
2030 | /* sat_neg = (arg < low ) ? low : arg; */ | |
2031 | tcg_gen_movcond_tl(TCG_COND_LT, sat_neg, arg, sat_neg, sat_neg, arg); | |
2032 | ||
2033 | /* ret = (sat_neg > up ) ? up : sat_neg; */ | |
2034 | tcg_gen_movcond_tl(TCG_COND_GT, ret, sat_neg, temp, temp, sat_neg); | |
2035 | ||
2036 | tcg_temp_free(sat_neg); | |
2037 | tcg_temp_free(temp); | |
2038 | } | |
2039 | ||
2040 | static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up) | |
2041 | { | |
2042 | TCGv temp = tcg_const_i32(up); | |
2043 | /* sat_neg = (arg > up ) ? up : arg; */ | |
2044 | tcg_gen_movcond_tl(TCG_COND_GTU, ret, arg, temp, temp, arg); | |
2045 | tcg_temp_free(temp); | |
2046 | } | |
2047 | ||
0707ec1b BK |
2048 | static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count) |
2049 | { | |
2050 | if (shift_count == -32) { | |
2051 | tcg_gen_movi_tl(ret, 0); | |
2052 | } else if (shift_count >= 0) { | |
2053 | tcg_gen_shli_tl(ret, r1, shift_count); | |
2054 | } else { | |
2055 | tcg_gen_shri_tl(ret, r1, -shift_count); | |
2056 | } | |
2057 | } | |
2058 | ||
0974257e BK |
2059 | static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shiftcount) |
2060 | { | |
2061 | TCGv temp_low, temp_high; | |
2062 | ||
2063 | if (shiftcount == -16) { | |
2064 | tcg_gen_movi_tl(ret, 0); | |
2065 | } else { | |
2066 | temp_high = tcg_temp_new(); | |
2067 | temp_low = tcg_temp_new(); | |
2068 | ||
2069 | tcg_gen_andi_tl(temp_low, r1, 0xffff); | |
2070 | tcg_gen_andi_tl(temp_high, r1, 0xffff0000); | |
2071 | gen_shi(temp_low, temp_low, shiftcount); | |
2072 | gen_shi(ret, temp_high, shiftcount); | |
2073 | tcg_gen_deposit_tl(ret, ret, temp_low, 0, 16); | |
2074 | ||
2075 | tcg_temp_free(temp_low); | |
2076 | tcg_temp_free(temp_high); | |
2077 | } | |
2078 | } | |
2079 | ||
0707ec1b BK |
2080 | static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count) |
2081 | { | |
2082 | uint32_t msk, msk_start; | |
2083 | TCGv temp = tcg_temp_new(); | |
2084 | TCGv temp2 = tcg_temp_new(); | |
2085 | TCGv t_0 = tcg_const_i32(0); | |
2086 | ||
2087 | if (shift_count == 0) { | |
2088 | /* Clear PSW.C and PSW.V */ | |
2089 | tcg_gen_movi_tl(cpu_PSW_C, 0); | |
2090 | tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C); | |
2091 | tcg_gen_mov_tl(ret, r1); | |
2092 | } else if (shift_count == -32) { | |
2093 | /* set PSW.C */ | |
2094 | tcg_gen_mov_tl(cpu_PSW_C, r1); | |
2095 | /* fill ret completly with sign bit */ | |
2096 | tcg_gen_sari_tl(ret, r1, 31); | |
2097 | /* clear PSW.V */ | |
2098 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
2099 | } else if (shift_count > 0) { | |
2100 | TCGv t_max = tcg_const_i32(0x7FFFFFFF >> shift_count); | |
2101 | TCGv t_min = tcg_const_i32(((int32_t) -0x80000000) >> shift_count); | |
2102 | ||
2103 | /* calc carry */ | |
2104 | msk_start = 32 - shift_count; | |
2105 | msk = ((1 << shift_count) - 1) << msk_start; | |
2106 | tcg_gen_andi_tl(cpu_PSW_C, r1, msk); | |
2107 | /* calc v/sv bits */ | |
2108 | tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max); | |
2109 | tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min); | |
2110 | tcg_gen_or_tl(cpu_PSW_V, temp, temp2); | |
2111 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); | |
2112 | /* calc sv */ | |
2113 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV); | |
2114 | /* do shift */ | |
2115 | tcg_gen_shli_tl(ret, r1, shift_count); | |
2116 | ||
2117 | tcg_temp_free(t_max); | |
2118 | tcg_temp_free(t_min); | |
2119 | } else { | |
2120 | /* clear PSW.V */ | |
2121 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
2122 | /* calc carry */ | |
2123 | msk = (1 << -shift_count) - 1; | |
2124 | tcg_gen_andi_tl(cpu_PSW_C, r1, msk); | |
2125 | /* do shift */ | |
2126 | tcg_gen_sari_tl(ret, r1, -shift_count); | |
2127 | } | |
2128 | /* calc av overflow bit */ | |
2129 | tcg_gen_add_tl(cpu_PSW_AV, ret, ret); | |
2130 | tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); | |
2131 | /* calc sav overflow bit */ | |
2132 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
2133 | ||
2134 | tcg_temp_free(temp); | |
2135 | tcg_temp_free(temp2); | |
2136 | tcg_temp_free(t_0); | |
2137 | } | |
2138 | ||
0974257e BK |
2139 | static void gen_shas(TCGv ret, TCGv r1, TCGv r2) |
2140 | { | |
2141 | gen_helper_sha_ssov(ret, cpu_env, r1, r2); | |
2142 | } | |
2143 | ||
2144 | static void gen_shasi(TCGv ret, TCGv r1, int32_t con) | |
2145 | { | |
2146 | TCGv temp = tcg_const_i32(con); | |
2147 | gen_shas(ret, r1, temp); | |
2148 | tcg_temp_free(temp); | |
2149 | } | |
2150 | ||
2151 | static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count) | |
2152 | { | |
2153 | TCGv low, high; | |
2154 | ||
2155 | if (shift_count == 0) { | |
2156 | tcg_gen_mov_tl(ret, r1); | |
2157 | } else if (shift_count > 0) { | |
2158 | low = tcg_temp_new(); | |
2159 | high = tcg_temp_new(); | |
2160 | ||
2161 | tcg_gen_andi_tl(high, r1, 0xffff0000); | |
2162 | tcg_gen_shli_tl(low, r1, shift_count); | |
2163 | tcg_gen_shli_tl(ret, high, shift_count); | |
2164 | tcg_gen_deposit_tl(ret, ret, low, 0, 16); | |
2165 | ||
2166 | tcg_temp_free(low); | |
2167 | tcg_temp_free(high); | |
2168 | } else { | |
2169 | low = tcg_temp_new(); | |
2170 | high = tcg_temp_new(); | |
2171 | ||
2172 | tcg_gen_ext16s_tl(low, r1); | |
2173 | tcg_gen_sari_tl(low, low, -shift_count); | |
2174 | tcg_gen_sari_tl(ret, r1, -shift_count); | |
2175 | tcg_gen_deposit_tl(ret, ret, low, 0, 16); | |
2176 | ||
2177 | tcg_temp_free(low); | |
2178 | tcg_temp_free(high); | |
2179 | } | |
2180 | ||
2181 | } | |
2182 | ||
2183 | /* ret = {ret[30:0], (r1 cond r2)}; */ | |
2184 | static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2) | |
2185 | { | |
2186 | TCGv temp = tcg_temp_new(); | |
2187 | TCGv temp2 = tcg_temp_new(); | |
2188 | ||
2189 | tcg_gen_shli_tl(temp, ret, 1); | |
2190 | tcg_gen_setcond_tl(cond, temp2, r1, r2); | |
2191 | tcg_gen_or_tl(ret, temp, temp2); | |
2192 | ||
2193 | tcg_temp_free(temp); | |
2194 | tcg_temp_free(temp2); | |
2195 | } | |
2196 | ||
2197 | static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con) | |
2198 | { | |
2199 | TCGv temp = tcg_const_i32(con); | |
2200 | gen_sh_cond(cond, ret, r1, temp); | |
2201 | tcg_temp_free(temp); | |
2202 | } | |
2203 | ||
2692802a BK |
2204 | static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2) |
2205 | { | |
2206 | gen_helper_add_ssov(ret, cpu_env, r1, r2); | |
2207 | } | |
2208 | ||
0974257e BK |
2209 | static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con) |
2210 | { | |
2211 | TCGv temp = tcg_const_i32(con); | |
2212 | gen_helper_add_ssov(ret, cpu_env, r1, temp); | |
2213 | tcg_temp_free(temp); | |
2214 | } | |
2215 | ||
2216 | static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con) | |
2217 | { | |
2218 | TCGv temp = tcg_const_i32(con); | |
2219 | gen_helper_add_suov(ret, cpu_env, r1, temp); | |
2220 | tcg_temp_free(temp); | |
2221 | } | |
2222 | ||
2692802a BK |
2223 | static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2) |
2224 | { | |
2225 | gen_helper_sub_ssov(ret, cpu_env, r1, r2); | |
2226 | } | |
2227 | ||
0974257e BK |
2228 | static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2) |
2229 | { | |
2230 | gen_helper_sub_suov(ret, cpu_env, r1, r2); | |
2231 | } | |
2232 | ||
b74f2b5b BK |
2233 | static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2, |
2234 | int pos1, int pos2, | |
2235 | void(*op1)(TCGv, TCGv, TCGv), | |
2236 | void(*op2)(TCGv, TCGv, TCGv)) | |
2237 | { | |
2238 | TCGv temp1, temp2; | |
2239 | ||
2240 | temp1 = tcg_temp_new(); | |
2241 | temp2 = tcg_temp_new(); | |
2242 | ||
2243 | tcg_gen_shri_tl(temp2, r2, pos2); | |
2244 | tcg_gen_shri_tl(temp1, r1, pos1); | |
2245 | ||
2246 | (*op1)(temp1, temp1, temp2); | |
2247 | (*op2)(temp1 , ret, temp1); | |
2248 | ||
2249 | tcg_gen_deposit_tl(ret, ret, temp1, 0, 1); | |
2250 | ||
2251 | tcg_temp_free(temp1); | |
2252 | tcg_temp_free(temp2); | |
2253 | } | |
2254 | ||
2255 | /* ret = r1[pos1] op1 r2[pos2]; */ | |
2256 | static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2, | |
2257 | int pos1, int pos2, | |
2258 | void(*op1)(TCGv, TCGv, TCGv)) | |
2259 | { | |
2260 | TCGv temp1, temp2; | |
2261 | ||
2262 | temp1 = tcg_temp_new(); | |
2263 | temp2 = tcg_temp_new(); | |
2264 | ||
2265 | tcg_gen_shri_tl(temp2, r2, pos2); | |
2266 | tcg_gen_shri_tl(temp1, r1, pos1); | |
2267 | ||
2268 | (*op1)(ret, temp1, temp2); | |
2269 | ||
2270 | tcg_gen_andi_tl(ret, ret, 0x1); | |
2271 | ||
2272 | tcg_temp_free(temp1); | |
2273 | tcg_temp_free(temp2); | |
2274 | } | |
2275 | ||
0974257e BK |
2276 | static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2, |
2277 | void(*op)(TCGv, TCGv, TCGv)) | |
2278 | { | |
2279 | TCGv temp = tcg_temp_new(); | |
2280 | TCGv temp2 = tcg_temp_new(); | |
2281 | /* temp = (arg1 cond arg2 )*/ | |
2282 | tcg_gen_setcond_tl(cond, temp, r1, r2); | |
2283 | /* temp2 = ret[0]*/ | |
2284 | tcg_gen_andi_tl(temp2, ret, 0x1); | |
2285 | /* temp = temp insn temp2 */ | |
2286 | (*op)(temp, temp, temp2); | |
2287 | /* ret = {ret[31:1], temp} */ | |
2288 | tcg_gen_deposit_tl(ret, ret, temp, 0, 1); | |
2289 | ||
2290 | tcg_temp_free(temp); | |
2291 | tcg_temp_free(temp2); | |
2292 | } | |
2293 | ||
2294 | static inline void | |
2295 | gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con, | |
2296 | void(*op)(TCGv, TCGv, TCGv)) | |
2297 | { | |
2298 | TCGv temp = tcg_const_i32(con); | |
2299 | gen_accumulating_cond(cond, ret, r1, temp, op); | |
2300 | tcg_temp_free(temp); | |
2301 | } | |
2302 | ||
d5de7839 BK |
2303 | /* ret = (r1 cond r2) ? 0xFFFFFFFF ? 0x00000000;*/ |
2304 | static inline void gen_cond_w(TCGCond cond, TCGv ret, TCGv r1, TCGv r2) | |
2305 | { | |
2306 | tcg_gen_setcond_tl(cond, ret, r1, r2); | |
2307 | tcg_gen_neg_tl(ret, ret); | |
2308 | } | |
2309 | ||
0974257e BK |
2310 | static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con) |
2311 | { | |
2312 | TCGv b0 = tcg_temp_new(); | |
2313 | TCGv b1 = tcg_temp_new(); | |
2314 | TCGv b2 = tcg_temp_new(); | |
2315 | TCGv b3 = tcg_temp_new(); | |
2316 | ||
2317 | /* byte 0 */ | |
2318 | tcg_gen_andi_tl(b0, r1, 0xff); | |
2319 | tcg_gen_setcondi_tl(TCG_COND_EQ, b0, b0, con & 0xff); | |
2320 | ||
2321 | /* byte 1 */ | |
2322 | tcg_gen_andi_tl(b1, r1, 0xff00); | |
2323 | tcg_gen_setcondi_tl(TCG_COND_EQ, b1, b1, con & 0xff00); | |
2324 | ||
2325 | /* byte 2 */ | |
2326 | tcg_gen_andi_tl(b2, r1, 0xff0000); | |
2327 | tcg_gen_setcondi_tl(TCG_COND_EQ, b2, b2, con & 0xff0000); | |
2328 | ||
2329 | /* byte 3 */ | |
2330 | tcg_gen_andi_tl(b3, r1, 0xff000000); | |
2331 | tcg_gen_setcondi_tl(TCG_COND_EQ, b3, b3, con & 0xff000000); | |
2332 | ||
2333 | /* combine them */ | |
2334 | tcg_gen_or_tl(ret, b0, b1); | |
2335 | tcg_gen_or_tl(ret, ret, b2); | |
2336 | tcg_gen_or_tl(ret, ret, b3); | |
2337 | ||
2338 | tcg_temp_free(b0); | |
2339 | tcg_temp_free(b1); | |
2340 | tcg_temp_free(b2); | |
2341 | tcg_temp_free(b3); | |
2342 | } | |
2343 | ||
2344 | static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con) | |
2345 | { | |
2346 | TCGv h0 = tcg_temp_new(); | |
2347 | TCGv h1 = tcg_temp_new(); | |
2348 | ||
2349 | /* halfword 0 */ | |
2350 | tcg_gen_andi_tl(h0, r1, 0xffff); | |
2351 | tcg_gen_setcondi_tl(TCG_COND_EQ, h0, h0, con & 0xffff); | |
2352 | ||
2353 | /* halfword 1 */ | |
2354 | tcg_gen_andi_tl(h1, r1, 0xffff0000); | |
2355 | tcg_gen_setcondi_tl(TCG_COND_EQ, h1, h1, con & 0xffff0000); | |
2356 | ||
2357 | /* combine them */ | |
2358 | tcg_gen_or_tl(ret, h0, h1); | |
2359 | ||
2360 | tcg_temp_free(h0); | |
2361 | tcg_temp_free(h1); | |
2362 | } | |
ed516260 BK |
2363 | /* mask = ((1 << width) -1) << pos; |
2364 | ret = (r1 & ~mask) | (r2 << pos) & mask); */ | |
2365 | static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos) | |
2366 | { | |
2367 | TCGv mask = tcg_temp_new(); | |
2368 | TCGv temp = tcg_temp_new(); | |
2369 | TCGv temp2 = tcg_temp_new(); | |
0974257e | 2370 | |
ed516260 BK |
2371 | tcg_gen_movi_tl(mask, 1); |
2372 | tcg_gen_shl_tl(mask, mask, width); | |
2373 | tcg_gen_subi_tl(mask, mask, 1); | |
2374 | tcg_gen_shl_tl(mask, mask, pos); | |
2375 | ||
2376 | tcg_gen_shl_tl(temp, r2, pos); | |
2377 | tcg_gen_and_tl(temp, temp, mask); | |
2378 | tcg_gen_andc_tl(temp2, r1, mask); | |
2379 | tcg_gen_or_tl(ret, temp, temp2); | |
2380 | ||
2381 | tcg_temp_free(mask); | |
2382 | tcg_temp_free(temp); | |
2383 | tcg_temp_free(temp2); | |
2384 | } | |
0974257e | 2385 | |
e2bed107 BK |
2386 | static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1) |
2387 | { | |
2388 | TCGv_i64 temp = tcg_temp_new_i64(); | |
2389 | ||
2390 | gen_helper_bsplit(temp, r1); | |
2391 | tcg_gen_extr_i64_i32(rl, rh, temp); | |
2392 | ||
2393 | tcg_temp_free_i64(temp); | |
2394 | } | |
2395 | ||
2396 | static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1) | |
2397 | { | |
2398 | TCGv_i64 temp = tcg_temp_new_i64(); | |
2399 | ||
2400 | gen_helper_unpack(temp, r1); | |
2401 | tcg_gen_extr_i64_i32(rl, rh, temp); | |
2402 | ||
2403 | tcg_temp_free_i64(temp); | |
2404 | } | |
2405 | ||
2406 | static inline void | |
2407 | gen_dvinit_b(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2) | |
2408 | { | |
2409 | TCGv_i64 ret = tcg_temp_new_i64(); | |
2410 | ||
2411 | if (!tricore_feature(env, TRICORE_FEATURE_131)) { | |
2412 | gen_helper_dvinit_b_13(ret, cpu_env, r1, r2); | |
2413 | } else { | |
2414 | gen_helper_dvinit_b_131(ret, cpu_env, r1, r2); | |
2415 | } | |
2416 | tcg_gen_extr_i64_i32(rl, rh, ret); | |
2417 | ||
2418 | tcg_temp_free_i64(ret); | |
2419 | } | |
2420 | ||
2421 | static inline void | |
2422 | gen_dvinit_h(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2) | |
2423 | { | |
2424 | TCGv_i64 ret = tcg_temp_new_i64(); | |
2425 | ||
2426 | if (!tricore_feature(env, TRICORE_FEATURE_131)) { | |
2427 | gen_helper_dvinit_h_13(ret, cpu_env, r1, r2); | |
2428 | } else { | |
2429 | gen_helper_dvinit_h_131(ret, cpu_env, r1, r2); | |
2430 | } | |
2431 | tcg_gen_extr_i64_i32(rl, rh, ret); | |
2432 | ||
2433 | tcg_temp_free_i64(ret); | |
2434 | } | |
2435 | ||
9655b932 BK |
2436 | static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg_high) |
2437 | { | |
2438 | TCGv temp = tcg_temp_new(); | |
2439 | /* calc AV bit */ | |
2440 | tcg_gen_add_tl(temp, arg_low, arg_low); | |
2441 | tcg_gen_xor_tl(temp, temp, arg_low); | |
2442 | tcg_gen_add_tl(cpu_PSW_AV, arg_high, arg_high); | |
2443 | tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, arg_high); | |
2444 | tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); | |
2445 | /* calc SAV bit */ | |
2446 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
2447 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
2448 | tcg_temp_free(temp); | |
2449 | } | |
2450 | ||
2451 | static void gen_calc_usb_mulr_h(TCGv arg) | |
2452 | { | |
2453 | TCGv temp = tcg_temp_new(); | |
2454 | /* calc AV bit */ | |
2455 | tcg_gen_add_tl(temp, arg, arg); | |
2456 | tcg_gen_xor_tl(temp, temp, arg); | |
2457 | tcg_gen_shli_tl(cpu_PSW_AV, temp, 16); | |
2458 | tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); | |
2459 | /* calc SAV bit */ | |
2460 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
2461 | /* clear V bit */ | |
2462 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
2463 | tcg_temp_free(temp); | |
2464 | } | |
2465 | ||
9a31922b BK |
2466 | /* helpers for generating program flow micro-ops */ |
2467 | ||
2468 | static inline void gen_save_pc(target_ulong pc) | |
2469 | { | |
2470 | tcg_gen_movi_tl(cpu_PC, pc); | |
2471 | } | |
2472 | ||
2473 | static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) | |
2474 | { | |
2475 | TranslationBlock *tb; | |
2476 | tb = ctx->tb; | |
2477 | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) && | |
2478 | likely(!ctx->singlestep_enabled)) { | |
2479 | tcg_gen_goto_tb(n); | |
2480 | gen_save_pc(dest); | |
2481 | tcg_gen_exit_tb((uintptr_t)tb + n); | |
2482 | } else { | |
2483 | gen_save_pc(dest); | |
2484 | if (ctx->singlestep_enabled) { | |
2485 | /* raise exception debug */ | |
2486 | } | |
2487 | tcg_gen_exit_tb(0); | |
2488 | } | |
2489 | } | |
2490 | ||
2491 | static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1, | |
2492 | TCGv r2, int16_t address) | |
2493 | { | |
2494 | int jumpLabel; | |
2495 | jumpLabel = gen_new_label(); | |
2496 | tcg_gen_brcond_tl(cond, r1, r2, jumpLabel); | |
2497 | ||
2498 | gen_goto_tb(ctx, 1, ctx->next_pc); | |
2499 | ||
2500 | gen_set_label(jumpLabel); | |
2501 | gen_goto_tb(ctx, 0, ctx->pc + address * 2); | |
2502 | } | |
2503 | ||
2504 | static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1, | |
2505 | int r2, int16_t address) | |
2506 | { | |
2507 | TCGv temp = tcg_const_i32(r2); | |
2508 | gen_branch_cond(ctx, cond, r1, temp, address); | |
2509 | tcg_temp_free(temp); | |
2510 | } | |
2511 | ||
a47b50db BK |
2512 | static void gen_loop(DisasContext *ctx, int r1, int32_t offset) |
2513 | { | |
2514 | int l1; | |
2515 | l1 = gen_new_label(); | |
2516 | ||
2517 | tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1); | |
2518 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1); | |
2519 | gen_goto_tb(ctx, 1, ctx->pc + offset); | |
2520 | gen_set_label(l1); | |
2521 | gen_goto_tb(ctx, 0, ctx->next_pc); | |
2522 | } | |
2523 | ||
9a31922b BK |
2524 | static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, |
2525 | int r2 , int32_t constant , int32_t offset) | |
2526 | { | |
a68e0d54 | 2527 | TCGv temp, temp2; |
83c1bb18 | 2528 | int n; |
70b02262 | 2529 | |
9a31922b BK |
2530 | switch (opc) { |
2531 | /* SB-format jumps */ | |
2532 | case OPC1_16_SB_J: | |
2533 | case OPC1_32_B_J: | |
2534 | gen_goto_tb(ctx, 0, ctx->pc + offset * 2); | |
2535 | break; | |
f718b0bb | 2536 | case OPC1_32_B_CALL: |
9a31922b BK |
2537 | case OPC1_16_SB_CALL: |
2538 | gen_helper_1arg(call, ctx->next_pc); | |
2539 | gen_goto_tb(ctx, 0, ctx->pc + offset * 2); | |
2540 | break; | |
2541 | case OPC1_16_SB_JZ: | |
2542 | gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset); | |
2543 | break; | |
2544 | case OPC1_16_SB_JNZ: | |
2545 | gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset); | |
2546 | break; | |
70b02262 BK |
2547 | /* SBC-format jumps */ |
2548 | case OPC1_16_SBC_JEQ: | |
2549 | gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset); | |
2550 | break; | |
2551 | case OPC1_16_SBC_JNE: | |
2552 | gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset); | |
2553 | break; | |
2554 | /* SBRN-format jumps */ | |
2555 | case OPC1_16_SBRN_JZ_T: | |
2556 | temp = tcg_temp_new(); | |
2557 | tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); | |
2558 | gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset); | |
2559 | tcg_temp_free(temp); | |
2560 | break; | |
2561 | case OPC1_16_SBRN_JNZ_T: | |
2562 | temp = tcg_temp_new(); | |
2563 | tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); | |
2564 | gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset); | |
2565 | tcg_temp_free(temp); | |
2566 | break; | |
a47b50db BK |
2567 | /* SBR-format jumps */ |
2568 | case OPC1_16_SBR_JEQ: | |
2569 | gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], | |
2570 | offset); | |
2571 | break; | |
2572 | case OPC1_16_SBR_JNE: | |
2573 | gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], | |
2574 | offset); | |
2575 | break; | |
2576 | case OPC1_16_SBR_JNZ: | |
2577 | gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset); | |
2578 | break; | |
2579 | case OPC1_16_SBR_JNZ_A: | |
2580 | gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset); | |
2581 | break; | |
2582 | case OPC1_16_SBR_JGEZ: | |
2583 | gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset); | |
2584 | break; | |
2585 | case OPC1_16_SBR_JGTZ: | |
2586 | gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset); | |
2587 | break; | |
2588 | case OPC1_16_SBR_JLEZ: | |
2589 | gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset); | |
2590 | break; | |
2591 | case OPC1_16_SBR_JLTZ: | |
2592 | gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset); | |
2593 | break; | |
2594 | case OPC1_16_SBR_JZ: | |
2595 | gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset); | |
2596 | break; | |
2597 | case OPC1_16_SBR_JZ_A: | |
2598 | gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset); | |
2599 | break; | |
2600 | case OPC1_16_SBR_LOOP: | |
2601 | gen_loop(ctx, r1, offset * 2 - 32); | |
2602 | break; | |
44ea3430 BK |
2603 | /* SR-format jumps */ |
2604 | case OPC1_16_SR_JI: | |
2605 | tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe); | |
2606 | tcg_gen_exit_tb(0); | |
2607 | break; | |
2608 | case OPC2_16_SR_RET: | |
2609 | gen_helper_ret(cpu_env); | |
2610 | tcg_gen_exit_tb(0); | |
2611 | break; | |
f718b0bb BK |
2612 | /* B-format */ |
2613 | case OPC1_32_B_CALLA: | |
2614 | gen_helper_1arg(call, ctx->next_pc); | |
2615 | gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); | |
2616 | break; | |
2617 | case OPC1_32_B_JLA: | |
2618 | tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); | |
40a1f64b | 2619 | /* fall through */ |
f718b0bb BK |
2620 | case OPC1_32_B_JA: |
2621 | gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); | |
2622 | break; | |
2623 | case OPC1_32_B_JL: | |
2624 | tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); | |
2625 | gen_goto_tb(ctx, 0, ctx->pc + offset * 2); | |
2626 | break; | |
fc2ef4a3 BK |
2627 | /* BOL format */ |
2628 | case OPCM_32_BRC_EQ_NEQ: | |
2629 | if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JEQ) { | |
2630 | gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], constant, offset); | |
2631 | } else { | |
2632 | gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], constant, offset); | |
2633 | } | |
2634 | break; | |
2635 | case OPCM_32_BRC_GE: | |
2636 | if (MASK_OP_BRC_OP2(ctx->opcode) == OP2_32_BRC_JGE) { | |
2637 | gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], constant, offset); | |
2638 | } else { | |
2639 | constant = MASK_OP_BRC_CONST4(ctx->opcode); | |
2640 | gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant, | |
2641 | offset); | |
2642 | } | |
2643 | break; | |
2644 | case OPCM_32_BRC_JLT: | |
2645 | if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JLT) { | |
2646 | gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset); | |
2647 | } else { | |
2648 | constant = MASK_OP_BRC_CONST4(ctx->opcode); | |
2649 | gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant, | |
2650 | offset); | |
2651 | } | |
2652 | break; | |
2653 | case OPCM_32_BRC_JNE: | |
2654 | temp = tcg_temp_new(); | |
2655 | if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) { | |
2656 | tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); | |
2657 | /* subi is unconditional */ | |
2658 | tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); | |
2659 | gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset); | |
2660 | } else { | |
2661 | tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); | |
2662 | /* addi is unconditional */ | |
2663 | tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); | |
2664 | gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset); | |
2665 | } | |
2666 | tcg_temp_free(temp); | |
2667 | break; | |
83c1bb18 BK |
2668 | /* BRN format */ |
2669 | case OPCM_32_BRN_JTT: | |
2670 | n = MASK_OP_BRN_N(ctx->opcode); | |
2671 | ||
2672 | temp = tcg_temp_new(); | |
2673 | tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n)); | |
2674 | ||
2675 | if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) { | |
2676 | gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset); | |
2677 | } else { | |
2678 | gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset); | |
2679 | } | |
2680 | tcg_temp_free(temp); | |
2681 | break; | |
a68e0d54 BK |
2682 | /* BRR Format */ |
2683 | case OPCM_32_BRR_EQ_NEQ: | |
2684 | if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ) { | |
2685 | gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
2686 | offset); | |
2687 | } else { | |
2688 | gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
2689 | offset); | |
2690 | } | |
2691 | break; | |
2692 | case OPCM_32_BRR_ADDR_EQ_NEQ: | |
2693 | if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ_A) { | |
2694 | gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_a[r1], cpu_gpr_a[r2], | |
2695 | offset); | |
2696 | } else { | |
2697 | gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_a[r1], cpu_gpr_a[r2], | |
2698 | offset); | |
2699 | } | |
2700 | break; | |
2701 | case OPCM_32_BRR_GE: | |
2702 | if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JGE) { | |
2703 | gen_branch_cond(ctx, TCG_COND_GE, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
2704 | offset); | |
2705 | } else { | |
2706 | gen_branch_cond(ctx, TCG_COND_GEU, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
2707 | offset); | |
2708 | } | |
2709 | break; | |
2710 | case OPCM_32_BRR_JLT: | |
2711 | if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JLT) { | |
2712 | gen_branch_cond(ctx, TCG_COND_LT, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
2713 | offset); | |
2714 | } else { | |
2715 | gen_branch_cond(ctx, TCG_COND_LTU, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
2716 | offset); | |
2717 | } | |
2718 | break; | |
2719 | case OPCM_32_BRR_LOOP: | |
2720 | if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) { | |
2721 | gen_loop(ctx, r1, offset * 2); | |
2722 | } else { | |
2723 | /* OPC2_32_BRR_LOOPU */ | |
2724 | gen_goto_tb(ctx, 0, ctx->pc + offset * 2); | |
2725 | } | |
2726 | break; | |
2727 | case OPCM_32_BRR_JNE: | |
2728 | temp = tcg_temp_new(); | |
2729 | temp2 = tcg_temp_new(); | |
2730 | if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRR_JNED) { | |
2731 | tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); | |
2732 | /* also save r2, in case of r1 == r2, so r2 is not decremented */ | |
2733 | tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]); | |
2734 | /* subi is unconditional */ | |
2735 | tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); | |
2736 | gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset); | |
2737 | } else { | |
2738 | tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); | |
2739 | /* also save r2, in case of r1 == r2, so r2 is not decremented */ | |
2740 | tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]); | |
2741 | /* addi is unconditional */ | |
2742 | tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); | |
2743 | gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset); | |
2744 | } | |
2745 | tcg_temp_free(temp); | |
2746 | tcg_temp_free(temp2); | |
2747 | break; | |
2748 | case OPCM_32_BRR_JNZ: | |
2749 | if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JNZ_A) { | |
2750 | gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset); | |
2751 | } else { | |
2752 | gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset); | |
2753 | } | |
2754 | break; | |
9a31922b | 2755 | default: |
a47b50db | 2756 | printf("Branch Error at %x\n", ctx->pc); |
9a31922b BK |
2757 | } |
2758 | ctx->bstate = BS_BRANCH; | |
2759 | } | |
2760 | ||
2761 | ||
0707ec1b BK |
2762 | /* |
2763 | * Functions for decoding instructions | |
2764 | */ | |
2765 | ||
2766 | static void decode_src_opc(DisasContext *ctx, int op1) | |
2767 | { | |
2768 | int r1; | |
2769 | int32_t const4; | |
2770 | TCGv temp, temp2; | |
2771 | ||
2772 | r1 = MASK_OP_SRC_S1D(ctx->opcode); | |
2773 | const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode); | |
2774 | ||
2775 | switch (op1) { | |
2776 | case OPC1_16_SRC_ADD: | |
2777 | gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); | |
2778 | break; | |
2779 | case OPC1_16_SRC_ADD_A15: | |
2780 | gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4); | |
2781 | break; | |
2782 | case OPC1_16_SRC_ADD_15A: | |
2783 | gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4); | |
2784 | break; | |
2785 | case OPC1_16_SRC_ADD_A: | |
2786 | tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4); | |
2787 | break; | |
2788 | case OPC1_16_SRC_CADD: | |
2789 | gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1], | |
2790 | cpu_gpr_d[15]); | |
2791 | break; | |
2792 | case OPC1_16_SRC_CADDN: | |
2793 | gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1], | |
2794 | cpu_gpr_d[15]); | |
2795 | break; | |
2796 | case OPC1_16_SRC_CMOV: | |
2797 | temp = tcg_const_tl(0); | |
2798 | temp2 = tcg_const_tl(const4); | |
2799 | tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, | |
2800 | temp2, cpu_gpr_d[r1]); | |
2801 | tcg_temp_free(temp); | |
2802 | tcg_temp_free(temp2); | |
2803 | break; | |
2804 | case OPC1_16_SRC_CMOVN: | |
2805 | temp = tcg_const_tl(0); | |
2806 | temp2 = tcg_const_tl(const4); | |
2807 | tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, | |
2808 | temp2, cpu_gpr_d[r1]); | |
2809 | tcg_temp_free(temp); | |
2810 | tcg_temp_free(temp2); | |
2811 | break; | |
2812 | case OPC1_16_SRC_EQ: | |
2813 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1], | |
2814 | const4); | |
2815 | break; | |
2816 | case OPC1_16_SRC_LT: | |
2817 | tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1], | |
2818 | const4); | |
2819 | break; | |
2820 | case OPC1_16_SRC_MOV: | |
2821 | tcg_gen_movi_tl(cpu_gpr_d[r1], const4); | |
2822 | break; | |
2823 | case OPC1_16_SRC_MOV_A: | |
2824 | const4 = MASK_OP_SRC_CONST4(ctx->opcode); | |
2825 | tcg_gen_movi_tl(cpu_gpr_a[r1], const4); | |
2826 | break; | |
2827 | case OPC1_16_SRC_SH: | |
2828 | gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); | |
2829 | break; | |
2830 | case OPC1_16_SRC_SHA: | |
2831 | gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); | |
2832 | break; | |
2833 | } | |
2834 | } | |
2835 | ||
2692802a BK |
2836 | static void decode_srr_opc(DisasContext *ctx, int op1) |
2837 | { | |
2838 | int r1, r2; | |
2839 | TCGv temp; | |
2840 | ||
2841 | r1 = MASK_OP_SRR_S1D(ctx->opcode); | |
2842 | r2 = MASK_OP_SRR_S2(ctx->opcode); | |
2843 | ||
2844 | switch (op1) { | |
2845 | case OPC1_16_SRR_ADD: | |
2846 | gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
2847 | break; | |
2848 | case OPC1_16_SRR_ADD_A15: | |
2849 | gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]); | |
2850 | break; | |
2851 | case OPC1_16_SRR_ADD_15A: | |
2852 | gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
2853 | break; | |
2854 | case OPC1_16_SRR_ADD_A: | |
2855 | tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]); | |
2856 | break; | |
2857 | case OPC1_16_SRR_ADDS: | |
2858 | gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
2859 | break; | |
2860 | case OPC1_16_SRR_AND: | |
2861 | tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
2862 | break; | |
2863 | case OPC1_16_SRR_CMOV: | |
2864 | temp = tcg_const_tl(0); | |
2865 | tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, | |
2866 | cpu_gpr_d[r2], cpu_gpr_d[r1]); | |
2867 | tcg_temp_free(temp); | |
2868 | break; | |
2869 | case OPC1_16_SRR_CMOVN: | |
2870 | temp = tcg_const_tl(0); | |
2871 | tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, | |
2872 | cpu_gpr_d[r2], cpu_gpr_d[r1]); | |
2873 | tcg_temp_free(temp); | |
2874 | break; | |
2875 | case OPC1_16_SRR_EQ: | |
2876 | tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1], | |
2877 | cpu_gpr_d[r2]); | |
2878 | break; | |
2879 | case OPC1_16_SRR_LT: | |
2880 | tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1], | |
2881 | cpu_gpr_d[r2]); | |
2882 | break; | |
2883 | case OPC1_16_SRR_MOV: | |
2884 | tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
2885 | break; | |
2886 | case OPC1_16_SRR_MOV_A: | |
2887 | tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]); | |
2888 | break; | |
2889 | case OPC1_16_SRR_MOV_AA: | |
2890 | tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]); | |
2891 | break; | |
2892 | case OPC1_16_SRR_MOV_D: | |
2893 | tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]); | |
2894 | break; | |
2895 | case OPC1_16_SRR_MUL: | |
2896 | gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
2897 | break; | |
2898 | case OPC1_16_SRR_OR: | |
2899 | tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
2900 | break; | |
2901 | case OPC1_16_SRR_SUB: | |
2902 | gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
2903 | break; | |
2904 | case OPC1_16_SRR_SUB_A15B: | |
2905 | gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]); | |
2906 | break; | |
2907 | case OPC1_16_SRR_SUB_15AB: | |
2908 | gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
2909 | break; | |
2910 | case OPC1_16_SRR_SUBS: | |
2911 | gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
2912 | break; | |
2913 | case OPC1_16_SRR_XOR: | |
2914 | tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
2915 | break; | |
2916 | } | |
2917 | } | |
2918 | ||
46aa848f BK |
2919 | static void decode_ssr_opc(DisasContext *ctx, int op1) |
2920 | { | |
2921 | int r1, r2; | |
2922 | ||
2923 | r1 = MASK_OP_SSR_S1(ctx->opcode); | |
2924 | r2 = MASK_OP_SSR_S2(ctx->opcode); | |
2925 | ||
2926 | switch (op1) { | |
2927 | case OPC1_16_SSR_ST_A: | |
2928 | tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); | |
2929 | break; | |
2930 | case OPC1_16_SSR_ST_A_POSTINC: | |
2931 | tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); | |
2932 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); | |
2933 | break; | |
2934 | case OPC1_16_SSR_ST_B: | |
2935 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); | |
2936 | break; | |
2937 | case OPC1_16_SSR_ST_B_POSTINC: | |
2938 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); | |
2939 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1); | |
2940 | break; | |
2941 | case OPC1_16_SSR_ST_H: | |
2942 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW); | |
2943 | break; | |
2944 | case OPC1_16_SSR_ST_H_POSTINC: | |
2945 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW); | |
2946 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2); | |
2947 | break; | |
2948 | case OPC1_16_SSR_ST_W: | |
2949 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); | |
2950 | break; | |
2951 | case OPC1_16_SSR_ST_W_POSTINC: | |
2952 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); | |
2953 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); | |
2954 | break; | |
2955 | } | |
2956 | } | |
2957 | ||
5de93515 BK |
2958 | static void decode_sc_opc(DisasContext *ctx, int op1) |
2959 | { | |
2960 | int32_t const16; | |
2961 | ||
2962 | const16 = MASK_OP_SC_CONST8(ctx->opcode); | |
2963 | ||
2964 | switch (op1) { | |
2965 | case OPC1_16_SC_AND: | |
2966 | tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16); | |
2967 | break; | |
2968 | case OPC1_16_SC_BISR: | |
2969 | gen_helper_1arg(bisr, const16 & 0xff); | |
2970 | break; | |
2971 | case OPC1_16_SC_LD_A: | |
2972 | gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL); | |
2973 | break; | |
2974 | case OPC1_16_SC_LD_W: | |
2975 | gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL); | |
2976 | break; | |
2977 | case OPC1_16_SC_MOV: | |
2978 | tcg_gen_movi_tl(cpu_gpr_d[15], const16); | |
2979 | break; | |
2980 | case OPC1_16_SC_OR: | |
2981 | tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16); | |
2982 | break; | |
2983 | case OPC1_16_SC_ST_A: | |
2984 | gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL); | |
2985 | break; | |
2986 | case OPC1_16_SC_ST_W: | |
2987 | gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL); | |
2988 | break; | |
2989 | case OPC1_16_SC_SUB_A: | |
2990 | tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16); | |
2991 | break; | |
2992 | } | |
2993 | } | |
5a7634a2 BK |
2994 | |
2995 | static void decode_slr_opc(DisasContext *ctx, int op1) | |
2996 | { | |
2997 | int r1, r2; | |
2998 | ||
2999 | r1 = MASK_OP_SLR_D(ctx->opcode); | |
3000 | r2 = MASK_OP_SLR_S2(ctx->opcode); | |
3001 | ||
3002 | switch (op1) { | |
3003 | /* SLR-format */ | |
3004 | case OPC1_16_SLR_LD_A: | |
3005 | tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); | |
3006 | break; | |
3007 | case OPC1_16_SLR_LD_A_POSTINC: | |
3008 | tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); | |
3009 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); | |
3010 | break; | |
3011 | case OPC1_16_SLR_LD_BU: | |
3012 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); | |
3013 | break; | |
3014 | case OPC1_16_SLR_LD_BU_POSTINC: | |
3015 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); | |
3016 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1); | |
3017 | break; | |
3018 | case OPC1_16_SLR_LD_H: | |
3019 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); | |
3020 | break; | |
3021 | case OPC1_16_SLR_LD_H_POSTINC: | |
3022 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); | |
3023 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2); | |
3024 | break; | |
3025 | case OPC1_16_SLR_LD_W: | |
3026 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); | |
3027 | break; | |
3028 | case OPC1_16_SLR_LD_W_POSTINC: | |
3029 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); | |
3030 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); | |
3031 | break; | |
3032 | } | |
3033 | } | |
3034 | ||
3035 | static void decode_sro_opc(DisasContext *ctx, int op1) | |
3036 | { | |
3037 | int r2; | |
3038 | int32_t address; | |
3039 | ||
3040 | r2 = MASK_OP_SRO_S2(ctx->opcode); | |
3041 | address = MASK_OP_SRO_OFF4(ctx->opcode); | |
3042 | ||
3043 | /* SRO-format */ | |
3044 | switch (op1) { | |
3045 | case OPC1_16_SRO_LD_A: | |
3046 | gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL); | |
3047 | break; | |
3048 | case OPC1_16_SRO_LD_BU: | |
3049 | gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB); | |
3050 | break; | |
3051 | case OPC1_16_SRO_LD_H: | |
3052 | gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_LESW); | |
3053 | break; | |
3054 | case OPC1_16_SRO_LD_W: | |
3055 | gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL); | |
3056 | break; | |
3057 | case OPC1_16_SRO_ST_A: | |
3058 | gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL); | |
3059 | break; | |
3060 | case OPC1_16_SRO_ST_B: | |
3061 | gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB); | |
3062 | break; | |
3063 | case OPC1_16_SRO_ST_H: | |
3064 | gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW); | |
3065 | break; | |
3066 | case OPC1_16_SRO_ST_W: | |
3067 | gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL); | |
3068 | break; | |
3069 | } | |
3070 | } | |
3071 | ||
44ea3430 BK |
3072 | static void decode_sr_system(CPUTriCoreState *env, DisasContext *ctx) |
3073 | { | |
3074 | uint32_t op2; | |
3075 | op2 = MASK_OP_SR_OP2(ctx->opcode); | |
3076 | ||
3077 | switch (op2) { | |
3078 | case OPC2_16_SR_NOP: | |
3079 | break; | |
3080 | case OPC2_16_SR_RET: | |
3081 | gen_compute_branch(ctx, op2, 0, 0, 0, 0); | |
3082 | break; | |
3083 | case OPC2_16_SR_RFE: | |
3084 | gen_helper_rfe(cpu_env); | |
3085 | tcg_gen_exit_tb(0); | |
3086 | ctx->bstate = BS_BRANCH; | |
3087 | break; | |
3088 | case OPC2_16_SR_DEBUG: | |
3089 | /* raise EXCP_DEBUG */ | |
3090 | break; | |
3091 | } | |
3092 | } | |
3093 | ||
3094 | static void decode_sr_accu(CPUTriCoreState *env, DisasContext *ctx) | |
3095 | { | |
3096 | uint32_t op2; | |
3097 | uint32_t r1; | |
3098 | TCGv temp; | |
3099 | ||
3100 | r1 = MASK_OP_SR_S1D(ctx->opcode); | |
3101 | op2 = MASK_OP_SR_OP2(ctx->opcode); | |
3102 | ||
3103 | switch (op2) { | |
3104 | case OPC2_16_SR_RSUB: | |
3105 | /* overflow only if r1 = -0x80000000 */ | |
3106 | temp = tcg_const_i32(-0x80000000); | |
3107 | /* calc V bit */ | |
3108 | tcg_gen_setcond_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], temp); | |
3109 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); | |
3110 | /* calc SV bit */ | |
3111 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
3112 | /* sub */ | |
3113 | tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]); | |
3114 | /* calc av */ | |
3115 | tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]); | |
3116 | tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV); | |
3117 | /* calc sav */ | |
3118 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
3119 | tcg_temp_free(temp); | |
3120 | break; | |
3121 | case OPC2_16_SR_SAT_B: | |
3122 | gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80); | |
3123 | break; | |
3124 | case OPC2_16_SR_SAT_BU: | |
3125 | gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff); | |
3126 | break; | |
3127 | case OPC2_16_SR_SAT_H: | |
3128 | gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000); | |
3129 | break; | |
3130 | case OPC2_16_SR_SAT_HU: | |
3131 | gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff); | |
3132 | break; | |
3133 | } | |
3134 | } | |
3135 | ||
0aaeb118 BK |
3136 | static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx) |
3137 | { | |
0707ec1b | 3138 | int op1; |
d2798210 BK |
3139 | int r1, r2; |
3140 | int32_t const16; | |
9a31922b | 3141 | int32_t address; |
d2798210 | 3142 | TCGv temp; |
0707ec1b BK |
3143 | |
3144 | op1 = MASK_OP_MAJOR(ctx->opcode); | |
3145 | ||
d2798210 BK |
3146 | /* handle ADDSC.A opcode only being 6 bit long */ |
3147 | if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) { | |
3148 | op1 = OPC1_16_SRRS_ADDSC_A; | |
3149 | } | |
3150 | ||
0707ec1b BK |
3151 | switch (op1) { |
3152 | case OPC1_16_SRC_ADD: | |
3153 | case OPC1_16_SRC_ADD_A15: | |
3154 | case OPC1_16_SRC_ADD_15A: | |
3155 | case OPC1_16_SRC_ADD_A: | |
3156 | case OPC1_16_SRC_CADD: | |
3157 | case OPC1_16_SRC_CADDN: | |
3158 | case OPC1_16_SRC_CMOV: | |
3159 | case OPC1_16_SRC_CMOVN: | |
3160 | case OPC1_16_SRC_EQ: | |
3161 | case OPC1_16_SRC_LT: | |
3162 | case OPC1_16_SRC_MOV: | |
3163 | case OPC1_16_SRC_MOV_A: | |
3164 | case OPC1_16_SRC_SH: | |
3165 | case OPC1_16_SRC_SHA: | |
3166 | decode_src_opc(ctx, op1); | |
3167 | break; | |
2692802a BK |
3168 | /* SRR-format */ |
3169 | case OPC1_16_SRR_ADD: | |
3170 | case OPC1_16_SRR_ADD_A15: | |
3171 | case OPC1_16_SRR_ADD_15A: | |
3172 | case OPC1_16_SRR_ADD_A: | |
3173 | case OPC1_16_SRR_ADDS: | |
3174 | case OPC1_16_SRR_AND: | |
3175 | case OPC1_16_SRR_CMOV: | |
3176 | case OPC1_16_SRR_CMOVN: | |
3177 | case OPC1_16_SRR_EQ: | |
3178 | case OPC1_16_SRR_LT: | |
3179 | case OPC1_16_SRR_MOV: | |
3180 | case OPC1_16_SRR_MOV_A: | |
3181 | case OPC1_16_SRR_MOV_AA: | |
3182 | case OPC1_16_SRR_MOV_D: | |
3183 | case OPC1_16_SRR_MUL: | |
3184 | case OPC1_16_SRR_OR: | |
3185 | case OPC1_16_SRR_SUB: | |
3186 | case OPC1_16_SRR_SUB_A15B: | |
3187 | case OPC1_16_SRR_SUB_15AB: | |
3188 | case OPC1_16_SRR_SUBS: | |
3189 | case OPC1_16_SRR_XOR: | |
3190 | decode_srr_opc(ctx, op1); | |
3191 | break; | |
46aa848f BK |
3192 | /* SSR-format */ |
3193 | case OPC1_16_SSR_ST_A: | |
3194 | case OPC1_16_SSR_ST_A_POSTINC: | |
3195 | case OPC1_16_SSR_ST_B: | |
3196 | case OPC1_16_SSR_ST_B_POSTINC: | |
3197 | case OPC1_16_SSR_ST_H: | |
3198 | case OPC1_16_SSR_ST_H_POSTINC: | |
3199 | case OPC1_16_SSR_ST_W: | |
3200 | case OPC1_16_SSR_ST_W_POSTINC: | |
3201 | decode_ssr_opc(ctx, op1); | |
3202 | break; | |
d2798210 BK |
3203 | /* SRRS-format */ |
3204 | case OPC1_16_SRRS_ADDSC_A: | |
3205 | r2 = MASK_OP_SRRS_S2(ctx->opcode); | |
3206 | r1 = MASK_OP_SRRS_S1D(ctx->opcode); | |
3207 | const16 = MASK_OP_SRRS_N(ctx->opcode); | |
3208 | temp = tcg_temp_new(); | |
3209 | tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16); | |
3210 | tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp); | |
3211 | tcg_temp_free(temp); | |
3212 | break; | |
3213 | /* SLRO-format */ | |
3214 | case OPC1_16_SLRO_LD_A: | |
3215 | r1 = MASK_OP_SLRO_D(ctx->opcode); | |
3216 | const16 = MASK_OP_SLRO_OFF4(ctx->opcode); | |
3217 | gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); | |
3218 | break; | |
3219 | case OPC1_16_SLRO_LD_BU: | |
3220 | r1 = MASK_OP_SLRO_D(ctx->opcode); | |
3221 | const16 = MASK_OP_SLRO_OFF4(ctx->opcode); | |
3222 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB); | |
3223 | break; | |
3224 | case OPC1_16_SLRO_LD_H: | |
3225 | r1 = MASK_OP_SLRO_D(ctx->opcode); | |
3226 | const16 = MASK_OP_SLRO_OFF4(ctx->opcode); | |
3227 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW); | |
3228 | break; | |
3229 | case OPC1_16_SLRO_LD_W: | |
3230 | r1 = MASK_OP_SLRO_D(ctx->opcode); | |
3231 | const16 = MASK_OP_SLRO_OFF4(ctx->opcode); | |
3232 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); | |
3233 | break; | |
9a31922b BK |
3234 | /* SB-format */ |
3235 | case OPC1_16_SB_CALL: | |
3236 | case OPC1_16_SB_J: | |
3237 | case OPC1_16_SB_JNZ: | |
3238 | case OPC1_16_SB_JZ: | |
3239 | address = MASK_OP_SB_DISP8_SEXT(ctx->opcode); | |
3240 | gen_compute_branch(ctx, op1, 0, 0, 0, address); | |
3241 | break; | |
70b02262 BK |
3242 | /* SBC-format */ |
3243 | case OPC1_16_SBC_JEQ: | |
3244 | case OPC1_16_SBC_JNE: | |
3245 | address = MASK_OP_SBC_DISP4(ctx->opcode); | |
3246 | const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode); | |
3247 | gen_compute_branch(ctx, op1, 0, 0, const16, address); | |
3248 | break; | |
3249 | /* SBRN-format */ | |
3250 | case OPC1_16_SBRN_JNZ_T: | |
3251 | case OPC1_16_SBRN_JZ_T: | |
3252 | address = MASK_OP_SBRN_DISP4(ctx->opcode); | |
3253 | const16 = MASK_OP_SBRN_N(ctx->opcode); | |
3254 | gen_compute_branch(ctx, op1, 0, 0, const16, address); | |
3255 | break; | |
a47b50db BK |
3256 | /* SBR-format */ |
3257 | case OPC1_16_SBR_JEQ: | |
3258 | case OPC1_16_SBR_JGEZ: | |
3259 | case OPC1_16_SBR_JGTZ: | |
3260 | case OPC1_16_SBR_JLEZ: | |
3261 | case OPC1_16_SBR_JLTZ: | |
3262 | case OPC1_16_SBR_JNE: | |
3263 | case OPC1_16_SBR_JNZ: | |
3264 | case OPC1_16_SBR_JNZ_A: | |
3265 | case OPC1_16_SBR_JZ: | |
3266 | case OPC1_16_SBR_JZ_A: | |
3267 | case OPC1_16_SBR_LOOP: | |
3268 | r1 = MASK_OP_SBR_S2(ctx->opcode); | |
3269 | address = MASK_OP_SBR_DISP4(ctx->opcode); | |
3270 | gen_compute_branch(ctx, op1, r1, 0, 0, address); | |
3271 | break; | |
5de93515 BK |
3272 | /* SC-format */ |
3273 | case OPC1_16_SC_AND: | |
3274 | case OPC1_16_SC_BISR: | |
3275 | case OPC1_16_SC_LD_A: | |
3276 | case OPC1_16_SC_LD_W: | |
3277 | case OPC1_16_SC_MOV: | |
3278 | case OPC1_16_SC_OR: | |
3279 | case OPC1_16_SC_ST_A: | |
3280 | case OPC1_16_SC_ST_W: | |
3281 | case OPC1_16_SC_SUB_A: | |
3282 | decode_sc_opc(ctx, op1); | |
3283 | break; | |
5a7634a2 BK |
3284 | /* SLR-format */ |
3285 | case OPC1_16_SLR_LD_A: | |
3286 | case OPC1_16_SLR_LD_A_POSTINC: | |
3287 | case OPC1_16_SLR_LD_BU: | |
3288 | case OPC1_16_SLR_LD_BU_POSTINC: | |
3289 | case OPC1_16_SLR_LD_H: | |
3290 | case OPC1_16_SLR_LD_H_POSTINC: | |
3291 | case OPC1_16_SLR_LD_W: | |
3292 | case OPC1_16_SLR_LD_W_POSTINC: | |
3293 | decode_slr_opc(ctx, op1); | |
3294 | break; | |
3295 | /* SRO-format */ | |
3296 | case OPC1_16_SRO_LD_A: | |
3297 | case OPC1_16_SRO_LD_BU: | |
3298 | case OPC1_16_SRO_LD_H: | |
3299 | case OPC1_16_SRO_LD_W: | |
3300 | case OPC1_16_SRO_ST_A: | |
3301 | case OPC1_16_SRO_ST_B: | |
3302 | case OPC1_16_SRO_ST_H: | |
3303 | case OPC1_16_SRO_ST_W: | |
3304 | decode_sro_opc(ctx, op1); | |
3305 | break; | |
3306 | /* SSRO-format */ | |
3307 | case OPC1_16_SSRO_ST_A: | |
3308 | r1 = MASK_OP_SSRO_S1(ctx->opcode); | |
3309 | const16 = MASK_OP_SSRO_OFF4(ctx->opcode); | |
3310 | gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); | |
3311 | break; | |
3312 | case OPC1_16_SSRO_ST_B: | |
3313 | r1 = MASK_OP_SSRO_S1(ctx->opcode); | |
3314 | const16 = MASK_OP_SSRO_OFF4(ctx->opcode); | |
3315 | gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB); | |
3316 | break; | |
3317 | case OPC1_16_SSRO_ST_H: | |
3318 | r1 = MASK_OP_SSRO_S1(ctx->opcode); | |
3319 | const16 = MASK_OP_SSRO_OFF4(ctx->opcode); | |
3320 | gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW); | |
3321 | break; | |
3322 | case OPC1_16_SSRO_ST_W: | |
3323 | r1 = MASK_OP_SSRO_S1(ctx->opcode); | |
3324 | const16 = MASK_OP_SSRO_OFF4(ctx->opcode); | |
3325 | gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); | |
3326 | break; | |
44ea3430 BK |
3327 | /* SR-format */ |
3328 | case OPCM_16_SR_SYSTEM: | |
3329 | decode_sr_system(env, ctx); | |
3330 | break; | |
3331 | case OPCM_16_SR_ACCU: | |
3332 | decode_sr_accu(env, ctx); | |
3333 | break; | |
3334 | case OPC1_16_SR_JI: | |
3335 | r1 = MASK_OP_SR_S1D(ctx->opcode); | |
3336 | gen_compute_branch(ctx, op1, r1, 0, 0, 0); | |
3337 | break; | |
3338 | case OPC1_16_SR_NOT: | |
3339 | r1 = MASK_OP_SR_S1D(ctx->opcode); | |
3340 | tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]); | |
3341 | break; | |
0707ec1b | 3342 | } |
0aaeb118 BK |
3343 | } |
3344 | ||
59543d4e BK |
3345 | /* |
3346 | * 32 bit instructions | |
3347 | */ | |
3348 | ||
3349 | /* ABS-format */ | |
3350 | static void decode_abs_ldw(CPUTriCoreState *env, DisasContext *ctx) | |
3351 | { | |
3352 | int32_t op2; | |
3353 | int32_t r1; | |
3354 | uint32_t address; | |
3355 | TCGv temp; | |
3356 | ||
3357 | r1 = MASK_OP_ABS_S1D(ctx->opcode); | |
3358 | address = MASK_OP_ABS_OFF18(ctx->opcode); | |
3359 | op2 = MASK_OP_ABS_OP2(ctx->opcode); | |
3360 | ||
3361 | temp = tcg_const_i32(EA_ABS_FORMAT(address)); | |
3362 | ||
3363 | switch (op2) { | |
3364 | case OPC2_32_ABS_LD_A: | |
3365 | tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL); | |
3366 | break; | |
3367 | case OPC2_32_ABS_LD_D: | |
3368 | gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); | |
3369 | break; | |
3370 | case OPC2_32_ABS_LD_DA: | |
3371 | gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); | |
3372 | break; | |
3373 | case OPC2_32_ABS_LD_W: | |
3374 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL); | |
3375 | break; | |
3376 | } | |
3377 | ||
3378 | tcg_temp_free(temp); | |
3379 | } | |
3380 | ||
3381 | static void decode_abs_ldb(CPUTriCoreState *env, DisasContext *ctx) | |
3382 | { | |
3383 | int32_t op2; | |
3384 | int32_t r1; | |
3385 | uint32_t address; | |
3386 | TCGv temp; | |
3387 | ||
3388 | r1 = MASK_OP_ABS_S1D(ctx->opcode); | |
3389 | address = MASK_OP_ABS_OFF18(ctx->opcode); | |
3390 | op2 = MASK_OP_ABS_OP2(ctx->opcode); | |
3391 | ||
3392 | temp = tcg_const_i32(EA_ABS_FORMAT(address)); | |
3393 | ||
3394 | switch (op2) { | |
3395 | case OPC2_32_ABS_LD_B: | |
3396 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB); | |
3397 | break; | |
3398 | case OPC2_32_ABS_LD_BU: | |
3399 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB); | |
3400 | break; | |
3401 | case OPC2_32_ABS_LD_H: | |
3402 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW); | |
3403 | break; | |
3404 | case OPC2_32_ABS_LD_HU: | |
3405 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); | |
3406 | break; | |
3407 | } | |
3408 | ||
3409 | tcg_temp_free(temp); | |
3410 | } | |
3411 | ||
3412 | static void decode_abs_ldst_swap(CPUTriCoreState *env, DisasContext *ctx) | |
3413 | { | |
3414 | int32_t op2; | |
3415 | int32_t r1; | |
3416 | uint32_t address; | |
3417 | TCGv temp; | |
3418 | ||
3419 | r1 = MASK_OP_ABS_S1D(ctx->opcode); | |
3420 | address = MASK_OP_ABS_OFF18(ctx->opcode); | |
3421 | op2 = MASK_OP_ABS_OP2(ctx->opcode); | |
3422 | ||
3423 | temp = tcg_const_i32(EA_ABS_FORMAT(address)); | |
3424 | ||
3425 | switch (op2) { | |
3426 | case OPC2_32_ABS_LDMST: | |
3427 | gen_ldmst(ctx, r1, temp); | |
3428 | break; | |
3429 | case OPC2_32_ABS_SWAP_W: | |
3430 | gen_swap(ctx, r1, temp); | |
3431 | break; | |
3432 | } | |
3433 | ||
3434 | tcg_temp_free(temp); | |
3435 | } | |
3436 | ||
3437 | static void decode_abs_ldst_context(CPUTriCoreState *env, DisasContext *ctx) | |
3438 | { | |
3439 | uint32_t op2; | |
3440 | int32_t off18; | |
3441 | ||
3442 | off18 = MASK_OP_ABS_OFF18(ctx->opcode); | |
3443 | op2 = MASK_OP_ABS_OP2(ctx->opcode); | |
3444 | ||
3445 | switch (op2) { | |
3446 | case OPC2_32_ABS_LDLCX: | |
3447 | gen_helper_1arg(ldlcx, EA_ABS_FORMAT(off18)); | |
3448 | break; | |
3449 | case OPC2_32_ABS_LDUCX: | |
3450 | gen_helper_1arg(lducx, EA_ABS_FORMAT(off18)); | |
3451 | break; | |
3452 | case OPC2_32_ABS_STLCX: | |
3453 | gen_helper_1arg(stlcx, EA_ABS_FORMAT(off18)); | |
3454 | break; | |
3455 | case OPC2_32_ABS_STUCX: | |
3456 | gen_helper_1arg(stucx, EA_ABS_FORMAT(off18)); | |
3457 | break; | |
3458 | } | |
3459 | } | |
3460 | ||
3461 | static void decode_abs_store(CPUTriCoreState *env, DisasContext *ctx) | |
3462 | { | |
3463 | int32_t op2; | |
3464 | int32_t r1; | |
3465 | uint32_t address; | |
3466 | TCGv temp; | |
3467 | ||
3468 | r1 = MASK_OP_ABS_S1D(ctx->opcode); | |
3469 | address = MASK_OP_ABS_OFF18(ctx->opcode); | |
3470 | op2 = MASK_OP_ABS_OP2(ctx->opcode); | |
3471 | ||
3472 | temp = tcg_const_i32(EA_ABS_FORMAT(address)); | |
3473 | ||
3474 | switch (op2) { | |
3475 | case OPC2_32_ABS_ST_A: | |
3476 | tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL); | |
3477 | break; | |
3478 | case OPC2_32_ABS_ST_D: | |
3479 | gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); | |
3480 | break; | |
3481 | case OPC2_32_ABS_ST_DA: | |
3482 | gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); | |
3483 | break; | |
3484 | case OPC2_32_ABS_ST_W: | |
3485 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL); | |
3486 | break; | |
3487 | ||
3488 | } | |
3489 | tcg_temp_free(temp); | |
3490 | } | |
3491 | ||
3492 | static void decode_abs_storeb_h(CPUTriCoreState *env, DisasContext *ctx) | |
3493 | { | |
3494 | int32_t op2; | |
3495 | int32_t r1; | |
3496 | uint32_t address; | |
3497 | TCGv temp; | |
3498 | ||
3499 | r1 = MASK_OP_ABS_S1D(ctx->opcode); | |
3500 | address = MASK_OP_ABS_OFF18(ctx->opcode); | |
3501 | op2 = MASK_OP_ABS_OP2(ctx->opcode); | |
3502 | ||
3503 | temp = tcg_const_i32(EA_ABS_FORMAT(address)); | |
3504 | ||
3505 | switch (op2) { | |
3506 | case OPC2_32_ABS_ST_B: | |
3507 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB); | |
3508 | break; | |
3509 | case OPC2_32_ABS_ST_H: | |
3510 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); | |
3511 | break; | |
3512 | } | |
3513 | tcg_temp_free(temp); | |
3514 | } | |
3515 | ||
b74f2b5b BK |
3516 | /* Bit-format */ |
3517 | ||
3518 | static void decode_bit_andacc(CPUTriCoreState *env, DisasContext *ctx) | |
3519 | { | |
3520 | uint32_t op2; | |
3521 | int r1, r2, r3; | |
3522 | int pos1, pos2; | |
3523 | ||
3524 | r1 = MASK_OP_BIT_S1(ctx->opcode); | |
3525 | r2 = MASK_OP_BIT_S2(ctx->opcode); | |
3526 | r3 = MASK_OP_BIT_D(ctx->opcode); | |
3527 | pos1 = MASK_OP_BIT_POS1(ctx->opcode); | |
3528 | pos2 = MASK_OP_BIT_POS2(ctx->opcode); | |
3529 | op2 = MASK_OP_BIT_OP2(ctx->opcode); | |
3530 | ||
3531 | ||
3532 | switch (op2) { | |
3533 | case OPC2_32_BIT_AND_AND_T: | |
3534 | gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3535 | pos1, pos2, &tcg_gen_and_tl, &tcg_gen_and_tl); | |
3536 | break; | |
3537 | case OPC2_32_BIT_AND_ANDN_T: | |
3538 | gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3539 | pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_and_tl); | |
3540 | break; | |
3541 | case OPC2_32_BIT_AND_NOR_T: | |
3542 | if (TCG_TARGET_HAS_andc_i32) { | |
3543 | gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3544 | pos1, pos2, &tcg_gen_or_tl, &tcg_gen_andc_tl); | |
3545 | } else { | |
3546 | gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3547 | pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_and_tl); | |
3548 | } | |
3549 | break; | |
3550 | case OPC2_32_BIT_AND_OR_T: | |
3551 | gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3552 | pos1, pos2, &tcg_gen_or_tl, &tcg_gen_and_tl); | |
3553 | break; | |
3554 | } | |
3555 | } | |
3556 | ||
3557 | static void decode_bit_logical_t(CPUTriCoreState *env, DisasContext *ctx) | |
3558 | { | |
3559 | uint32_t op2; | |
3560 | int r1, r2, r3; | |
3561 | int pos1, pos2; | |
3562 | r1 = MASK_OP_BIT_S1(ctx->opcode); | |
3563 | r2 = MASK_OP_BIT_S2(ctx->opcode); | |
3564 | r3 = MASK_OP_BIT_D(ctx->opcode); | |
3565 | pos1 = MASK_OP_BIT_POS1(ctx->opcode); | |
3566 | pos2 = MASK_OP_BIT_POS2(ctx->opcode); | |
3567 | op2 = MASK_OP_BIT_OP2(ctx->opcode); | |
3568 | ||
3569 | switch (op2) { | |
3570 | case OPC2_32_BIT_AND_T: | |
3571 | gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3572 | pos1, pos2, &tcg_gen_and_tl); | |
3573 | break; | |
3574 | case OPC2_32_BIT_ANDN_T: | |
3575 | gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3576 | pos1, pos2, &tcg_gen_andc_tl); | |
3577 | break; | |
3578 | case OPC2_32_BIT_NOR_T: | |
3579 | gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3580 | pos1, pos2, &tcg_gen_nor_tl); | |
3581 | break; | |
3582 | case OPC2_32_BIT_OR_T: | |
3583 | gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3584 | pos1, pos2, &tcg_gen_or_tl); | |
3585 | break; | |
3586 | } | |
3587 | } | |
3588 | ||
3589 | static void decode_bit_insert(CPUTriCoreState *env, DisasContext *ctx) | |
3590 | { | |
3591 | uint32_t op2; | |
3592 | int r1, r2, r3; | |
3593 | int pos1, pos2; | |
3594 | TCGv temp; | |
3595 | op2 = MASK_OP_BIT_OP2(ctx->opcode); | |
3596 | r1 = MASK_OP_BIT_S1(ctx->opcode); | |
3597 | r2 = MASK_OP_BIT_S2(ctx->opcode); | |
3598 | r3 = MASK_OP_BIT_D(ctx->opcode); | |
3599 | pos1 = MASK_OP_BIT_POS1(ctx->opcode); | |
3600 | pos2 = MASK_OP_BIT_POS2(ctx->opcode); | |
3601 | ||
3602 | temp = tcg_temp_new(); | |
3603 | ||
3604 | tcg_gen_shri_tl(temp, cpu_gpr_d[r2], pos2); | |
3605 | if (op2 == OPC2_32_BIT_INSN_T) { | |
3606 | tcg_gen_not_tl(temp, temp); | |
3607 | } | |
3608 | tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1); | |
3609 | tcg_temp_free(temp); | |
3610 | } | |
3611 | ||
3612 | static void decode_bit_logical_t2(CPUTriCoreState *env, DisasContext *ctx) | |
3613 | { | |
3614 | uint32_t op2; | |
3615 | ||
3616 | int r1, r2, r3; | |
3617 | int pos1, pos2; | |
3618 | ||
3619 | op2 = MASK_OP_BIT_OP2(ctx->opcode); | |
3620 | r1 = MASK_OP_BIT_S1(ctx->opcode); | |
3621 | r2 = MASK_OP_BIT_S2(ctx->opcode); | |
3622 | r3 = MASK_OP_BIT_D(ctx->opcode); | |
3623 | pos1 = MASK_OP_BIT_POS1(ctx->opcode); | |
3624 | pos2 = MASK_OP_BIT_POS2(ctx->opcode); | |
3625 | ||
3626 | switch (op2) { | |
3627 | case OPC2_32_BIT_NAND_T: | |
3628 | gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3629 | pos1, pos2, &tcg_gen_nand_tl); | |
3630 | break; | |
3631 | case OPC2_32_BIT_ORN_T: | |
3632 | gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3633 | pos1, pos2, &tcg_gen_orc_tl); | |
3634 | break; | |
3635 | case OPC2_32_BIT_XNOR_T: | |
3636 | gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3637 | pos1, pos2, &tcg_gen_eqv_tl); | |
3638 | break; | |
3639 | case OPC2_32_BIT_XOR_T: | |
3640 | gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3641 | pos1, pos2, &tcg_gen_xor_tl); | |
3642 | break; | |
3643 | } | |
3644 | } | |
3645 | ||
3646 | static void decode_bit_orand(CPUTriCoreState *env, DisasContext *ctx) | |
3647 | { | |
3648 | uint32_t op2; | |
3649 | ||
3650 | int r1, r2, r3; | |
3651 | int pos1, pos2; | |
3652 | ||
3653 | op2 = MASK_OP_BIT_OP2(ctx->opcode); | |
3654 | r1 = MASK_OP_BIT_S1(ctx->opcode); | |
3655 | r2 = MASK_OP_BIT_S2(ctx->opcode); | |
3656 | r3 = MASK_OP_BIT_D(ctx->opcode); | |
3657 | pos1 = MASK_OP_BIT_POS1(ctx->opcode); | |
3658 | pos2 = MASK_OP_BIT_POS2(ctx->opcode); | |
3659 | ||
3660 | switch (op2) { | |
3661 | case OPC2_32_BIT_OR_AND_T: | |
3662 | gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3663 | pos1, pos2, &tcg_gen_and_tl, &tcg_gen_or_tl); | |
3664 | break; | |
3665 | case OPC2_32_BIT_OR_ANDN_T: | |
3666 | gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3667 | pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_or_tl); | |
3668 | break; | |
3669 | case OPC2_32_BIT_OR_NOR_T: | |
3670 | if (TCG_TARGET_HAS_orc_i32) { | |
3671 | gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3672 | pos1, pos2, &tcg_gen_or_tl, &tcg_gen_orc_tl); | |
3673 | } else { | |
3674 | gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3675 | pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_or_tl); | |
3676 | } | |
3677 | break; | |
3678 | case OPC2_32_BIT_OR_OR_T: | |
3679 | gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3680 | pos1, pos2, &tcg_gen_or_tl, &tcg_gen_or_tl); | |
3681 | break; | |
3682 | } | |
3683 | } | |
3684 | ||
3685 | static void decode_bit_sh_logic1(CPUTriCoreState *env, DisasContext *ctx) | |
3686 | { | |
3687 | uint32_t op2; | |
3688 | int r1, r2, r3; | |
3689 | int pos1, pos2; | |
3690 | TCGv temp; | |
3691 | ||
3692 | op2 = MASK_OP_BIT_OP2(ctx->opcode); | |
3693 | r1 = MASK_OP_BIT_S1(ctx->opcode); | |
3694 | r2 = MASK_OP_BIT_S2(ctx->opcode); | |
3695 | r3 = MASK_OP_BIT_D(ctx->opcode); | |
3696 | pos1 = MASK_OP_BIT_POS1(ctx->opcode); | |
3697 | pos2 = MASK_OP_BIT_POS2(ctx->opcode); | |
3698 | ||
3699 | temp = tcg_temp_new(); | |
3700 | ||
3701 | switch (op2) { | |
3702 | case OPC2_32_BIT_SH_AND_T: | |
3703 | gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3704 | pos1, pos2, &tcg_gen_and_tl); | |
3705 | break; | |
3706 | case OPC2_32_BIT_SH_ANDN_T: | |
3707 | gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3708 | pos1, pos2, &tcg_gen_andc_tl); | |
3709 | break; | |
3710 | case OPC2_32_BIT_SH_NOR_T: | |
3711 | gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3712 | pos1, pos2, &tcg_gen_nor_tl); | |
3713 | break; | |
3714 | case OPC2_32_BIT_SH_OR_T: | |
3715 | gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3716 | pos1, pos2, &tcg_gen_or_tl); | |
3717 | break; | |
3718 | } | |
3719 | tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1); | |
3720 | tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); | |
3721 | tcg_temp_free(temp); | |
3722 | } | |
3723 | ||
3724 | static void decode_bit_sh_logic2(CPUTriCoreState *env, DisasContext *ctx) | |
3725 | { | |
3726 | uint32_t op2; | |
3727 | int r1, r2, r3; | |
3728 | int pos1, pos2; | |
3729 | TCGv temp; | |
3730 | ||
3731 | op2 = MASK_OP_BIT_OP2(ctx->opcode); | |
3732 | r1 = MASK_OP_BIT_S1(ctx->opcode); | |
3733 | r2 = MASK_OP_BIT_S2(ctx->opcode); | |
3734 | r3 = MASK_OP_BIT_D(ctx->opcode); | |
3735 | pos1 = MASK_OP_BIT_POS1(ctx->opcode); | |
3736 | pos2 = MASK_OP_BIT_POS2(ctx->opcode); | |
3737 | ||
3738 | temp = tcg_temp_new(); | |
3739 | ||
3740 | switch (op2) { | |
3741 | case OPC2_32_BIT_SH_NAND_T: | |
3742 | gen_bit_1op(temp, cpu_gpr_d[r1] , cpu_gpr_d[r2] , | |
3743 | pos1, pos2, &tcg_gen_nand_tl); | |
3744 | break; | |
3745 | case OPC2_32_BIT_SH_ORN_T: | |
3746 | gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3747 | pos1, pos2, &tcg_gen_orc_tl); | |
3748 | break; | |
3749 | case OPC2_32_BIT_SH_XNOR_T: | |
3750 | gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3751 | pos1, pos2, &tcg_gen_eqv_tl); | |
3752 | break; | |
3753 | case OPC2_32_BIT_SH_XOR_T: | |
3754 | gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3755 | pos1, pos2, &tcg_gen_xor_tl); | |
3756 | break; | |
3757 | } | |
3758 | tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1); | |
3759 | tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); | |
3760 | tcg_temp_free(temp); | |
3761 | } | |
3762 | ||
3a16ecb0 BK |
3763 | /* BO-format */ |
3764 | ||
3765 | ||
3766 | static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env, | |
3767 | DisasContext *ctx) | |
3768 | { | |
3769 | uint32_t op2; | |
3770 | uint32_t off10; | |
3771 | int32_t r1, r2; | |
3772 | TCGv temp; | |
3773 | ||
3774 | r1 = MASK_OP_BO_S1D(ctx->opcode); | |
3775 | r2 = MASK_OP_BO_S2(ctx->opcode); | |
3776 | off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); | |
3777 | op2 = MASK_OP_BO_OP2(ctx->opcode); | |
3778 | ||
3779 | switch (op2) { | |
3780 | case OPC2_32_BO_CACHEA_WI_SHORTOFF: | |
3781 | case OPC2_32_BO_CACHEA_W_SHORTOFF: | |
3782 | case OPC2_32_BO_CACHEA_I_SHORTOFF: | |
3783 | /* instruction to access the cache */ | |
3784 | break; | |
3785 | case OPC2_32_BO_CACHEA_WI_POSTINC: | |
3786 | case OPC2_32_BO_CACHEA_W_POSTINC: | |
3787 | case OPC2_32_BO_CACHEA_I_POSTINC: | |
3788 | /* instruction to access the cache, but we still need to handle | |
3789 | the addressing mode */ | |
3790 | tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10); | |
3791 | break; | |
3792 | case OPC2_32_BO_CACHEA_WI_PREINC: | |
3793 | case OPC2_32_BO_CACHEA_W_PREINC: | |
3794 | case OPC2_32_BO_CACHEA_I_PREINC: | |
3795 | /* instruction to access the cache, but we still need to handle | |
3796 | the addressing mode */ | |
3797 | tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10); | |
3798 | break; | |
3799 | case OPC2_32_BO_CACHEI_WI_SHORTOFF: | |
3800 | case OPC2_32_BO_CACHEI_W_SHORTOFF: | |
3801 | /* TODO: Raise illegal opcode trap, | |
47e04430 | 3802 | if !tricore_feature(TRICORE_FEATURE_131) */ |
3a16ecb0 BK |
3803 | break; |
3804 | case OPC2_32_BO_CACHEI_W_POSTINC: | |
3805 | case OPC2_32_BO_CACHEI_WI_POSTINC: | |
47e04430 | 3806 | if (tricore_feature(env, TRICORE_FEATURE_131)) { |
3a16ecb0 BK |
3807 | tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10); |
3808 | } /* TODO: else raise illegal opcode trap */ | |
3809 | break; | |
3810 | case OPC2_32_BO_CACHEI_W_PREINC: | |
3811 | case OPC2_32_BO_CACHEI_WI_PREINC: | |
47e04430 | 3812 | if (tricore_feature(env, TRICORE_FEATURE_131)) { |
3a16ecb0 BK |
3813 | tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10); |
3814 | } /* TODO: else raise illegal opcode trap */ | |
3815 | break; | |
3816 | case OPC2_32_BO_ST_A_SHORTOFF: | |
3817 | gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL); | |
3818 | break; | |
3819 | case OPC2_32_BO_ST_A_POSTINC: | |
3820 | tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
3821 | MO_LESL); | |
3822 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
3823 | break; | |
3824 | case OPC2_32_BO_ST_A_PREINC: | |
3825 | gen_st_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL); | |
3826 | break; | |
3827 | case OPC2_32_BO_ST_B_SHORTOFF: | |
3828 | gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); | |
3829 | break; | |
3830 | case OPC2_32_BO_ST_B_POSTINC: | |
3831 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
3832 | MO_UB); | |
3833 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
3834 | break; | |
3835 | case OPC2_32_BO_ST_B_PREINC: | |
3836 | gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); | |
3837 | break; | |
3838 | case OPC2_32_BO_ST_D_SHORTOFF: | |
3839 | gen_offset_st_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], | |
3840 | off10, ctx); | |
3841 | break; | |
3842 | case OPC2_32_BO_ST_D_POSTINC: | |
3843 | gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx); | |
3844 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
3845 | break; | |
3846 | case OPC2_32_BO_ST_D_PREINC: | |
3847 | temp = tcg_temp_new(); | |
3848 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
3849 | gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); | |
3850 | tcg_gen_mov_tl(cpu_gpr_a[r2], temp); | |
3851 | tcg_temp_free(temp); | |
3852 | break; | |
3853 | case OPC2_32_BO_ST_DA_SHORTOFF: | |
3854 | gen_offset_st_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], | |
3855 | off10, ctx); | |
3856 | break; | |
3857 | case OPC2_32_BO_ST_DA_POSTINC: | |
3858 | gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx); | |
3859 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
3860 | break; | |
3861 | case OPC2_32_BO_ST_DA_PREINC: | |
3862 | temp = tcg_temp_new(); | |
3863 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
3864 | gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); | |
3865 | tcg_gen_mov_tl(cpu_gpr_a[r2], temp); | |
3866 | tcg_temp_free(temp); | |
3867 | break; | |
3868 | case OPC2_32_BO_ST_H_SHORTOFF: | |
3869 | gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); | |
3870 | break; | |
3871 | case OPC2_32_BO_ST_H_POSTINC: | |
3872 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
3873 | MO_LEUW); | |
3874 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
3875 | break; | |
3876 | case OPC2_32_BO_ST_H_PREINC: | |
3877 | gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); | |
3878 | break; | |
3879 | case OPC2_32_BO_ST_Q_SHORTOFF: | |
3880 | temp = tcg_temp_new(); | |
3881 | tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); | |
3882 | gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW); | |
3883 | tcg_temp_free(temp); | |
3884 | break; | |
3885 | case OPC2_32_BO_ST_Q_POSTINC: | |
3886 | temp = tcg_temp_new(); | |
3887 | tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); | |
3888 | tcg_gen_qemu_st_tl(temp, cpu_gpr_a[r2], ctx->mem_idx, | |
3889 | MO_LEUW); | |
3890 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
3891 | tcg_temp_free(temp); | |
3892 | break; | |
3893 | case OPC2_32_BO_ST_Q_PREINC: | |
3894 | temp = tcg_temp_new(); | |
3895 | tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); | |
3896 | gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW); | |
3897 | tcg_temp_free(temp); | |
3898 | break; | |
3899 | case OPC2_32_BO_ST_W_SHORTOFF: | |
3900 | gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); | |
3901 | break; | |
3902 | case OPC2_32_BO_ST_W_POSTINC: | |
3903 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
3904 | MO_LEUL); | |
3905 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
3906 | break; | |
3907 | case OPC2_32_BO_ST_W_PREINC: | |
3908 | gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); | |
3909 | break; | |
3910 | } | |
3911 | } | |
3912 | ||
3913 | static void decode_bo_addrmode_bitreverse_circular(CPUTriCoreState *env, | |
3914 | DisasContext *ctx) | |
3915 | { | |
3916 | uint32_t op2; | |
3917 | uint32_t off10; | |
3918 | int32_t r1, r2; | |
3919 | TCGv temp, temp2, temp3; | |
3920 | ||
3921 | r1 = MASK_OP_BO_S1D(ctx->opcode); | |
3922 | r2 = MASK_OP_BO_S2(ctx->opcode); | |
3923 | off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); | |
3924 | op2 = MASK_OP_BO_OP2(ctx->opcode); | |
3925 | ||
3926 | temp = tcg_temp_new(); | |
3927 | temp2 = tcg_temp_new(); | |
3928 | temp3 = tcg_const_i32(off10); | |
3929 | ||
3930 | tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); | |
3931 | tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); | |
3932 | ||
3933 | switch (op2) { | |
3934 | case OPC2_32_BO_CACHEA_WI_BR: | |
3935 | case OPC2_32_BO_CACHEA_W_BR: | |
3936 | case OPC2_32_BO_CACHEA_I_BR: | |
3937 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
3938 | break; | |
3939 | case OPC2_32_BO_CACHEA_WI_CIRC: | |
3940 | case OPC2_32_BO_CACHEA_W_CIRC: | |
3941 | case OPC2_32_BO_CACHEA_I_CIRC: | |
3942 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
3943 | break; | |
3944 | case OPC2_32_BO_ST_A_BR: | |
3945 | tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); | |
3946 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
3947 | break; | |
3948 | case OPC2_32_BO_ST_A_CIRC: | |
3949 | tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); | |
3950 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
3951 | break; | |
3952 | case OPC2_32_BO_ST_B_BR: | |
3953 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); | |
3954 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
3955 | break; | |
3956 | case OPC2_32_BO_ST_B_CIRC: | |
3957 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); | |
3958 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
3959 | break; | |
3960 | case OPC2_32_BO_ST_D_BR: | |
3961 | gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx); | |
3962 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
3963 | break; | |
3964 | case OPC2_32_BO_ST_D_CIRC: | |
3965 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); | |
3966 | tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); | |
3967 | tcg_gen_addi_tl(temp, temp, 4); | |
3968 | tcg_gen_rem_tl(temp, temp, temp2); | |
3969 | tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); | |
3970 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL); | |
3971 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
3972 | break; | |
3973 | case OPC2_32_BO_ST_DA_BR: | |
3974 | gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx); | |
3975 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
3976 | break; | |
3977 | case OPC2_32_BO_ST_DA_CIRC: | |
3978 | tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); | |
3979 | tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); | |
3980 | tcg_gen_addi_tl(temp, temp, 4); | |
3981 | tcg_gen_rem_tl(temp, temp, temp2); | |
3982 | tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); | |
3983 | tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL); | |
3984 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
3985 | break; | |
3986 | case OPC2_32_BO_ST_H_BR: | |
3987 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); | |
3988 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
3989 | break; | |
3990 | case OPC2_32_BO_ST_H_CIRC: | |
3991 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); | |
3992 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
3993 | break; | |
3994 | case OPC2_32_BO_ST_Q_BR: | |
3995 | tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); | |
3996 | tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW); | |
3997 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
3998 | break; | |
3999 | case OPC2_32_BO_ST_Q_CIRC: | |
4000 | tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); | |
4001 | tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW); | |
4002 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
4003 | break; | |
4004 | case OPC2_32_BO_ST_W_BR: | |
4005 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); | |
4006 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4007 | break; | |
4008 | case OPC2_32_BO_ST_W_CIRC: | |
4009 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); | |
4010 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
4011 | break; | |
4012 | } | |
4013 | tcg_temp_free(temp); | |
4014 | tcg_temp_free(temp2); | |
4015 | tcg_temp_free(temp3); | |
4016 | } | |
4017 | ||
4018 | static void decode_bo_addrmode_ld_post_pre_base(CPUTriCoreState *env, | |
4019 | DisasContext *ctx) | |
4020 | { | |
4021 | uint32_t op2; | |
4022 | uint32_t off10; | |
4023 | int32_t r1, r2; | |
4024 | TCGv temp; | |
4025 | ||
4026 | r1 = MASK_OP_BO_S1D(ctx->opcode); | |
4027 | r2 = MASK_OP_BO_S2(ctx->opcode); | |
4028 | off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); | |
4029 | op2 = MASK_OP_BO_OP2(ctx->opcode); | |
4030 | ||
4031 | switch (op2) { | |
4032 | case OPC2_32_BO_LD_A_SHORTOFF: | |
4033 | gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL); | |
4034 | break; | |
4035 | case OPC2_32_BO_LD_A_POSTINC: | |
4036 | tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
4037 | MO_LEUL); | |
4038 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4039 | break; | |
4040 | case OPC2_32_BO_LD_A_PREINC: | |
4041 | gen_ld_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL); | |
4042 | break; | |
4043 | case OPC2_32_BO_LD_B_SHORTOFF: | |
4044 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB); | |
4045 | break; | |
4046 | case OPC2_32_BO_LD_B_POSTINC: | |
4047 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
4048 | MO_SB); | |
4049 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4050 | break; | |
4051 | case OPC2_32_BO_LD_B_PREINC: | |
4052 | gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB); | |
4053 | break; | |
4054 | case OPC2_32_BO_LD_BU_SHORTOFF: | |
4055 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); | |
4056 | break; | |
4057 | case OPC2_32_BO_LD_BU_POSTINC: | |
4058 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
4059 | MO_UB); | |
4060 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4061 | break; | |
4062 | case OPC2_32_BO_LD_BU_PREINC: | |
4063 | gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB); | |
4064 | break; | |
4065 | case OPC2_32_BO_LD_D_SHORTOFF: | |
4066 | gen_offset_ld_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], | |
4067 | off10, ctx); | |
4068 | break; | |
4069 | case OPC2_32_BO_LD_D_POSTINC: | |
4070 | gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx); | |
4071 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4072 | break; | |
4073 | case OPC2_32_BO_LD_D_PREINC: | |
4074 | temp = tcg_temp_new(); | |
4075 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
4076 | gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); | |
4077 | tcg_gen_mov_tl(cpu_gpr_a[r2], temp); | |
4078 | tcg_temp_free(temp); | |
4079 | break; | |
4080 | case OPC2_32_BO_LD_DA_SHORTOFF: | |
4081 | gen_offset_ld_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], | |
4082 | off10, ctx); | |
4083 | break; | |
4084 | case OPC2_32_BO_LD_DA_POSTINC: | |
4085 | gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx); | |
4086 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4087 | break; | |
4088 | case OPC2_32_BO_LD_DA_PREINC: | |
4089 | temp = tcg_temp_new(); | |
4090 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
4091 | gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); | |
4092 | tcg_gen_mov_tl(cpu_gpr_a[r2], temp); | |
4093 | tcg_temp_free(temp); | |
4094 | break; | |
4095 | case OPC2_32_BO_LD_H_SHORTOFF: | |
4096 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW); | |
4097 | break; | |
4098 | case OPC2_32_BO_LD_H_POSTINC: | |
4099 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
4100 | MO_LESW); | |
4101 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4102 | break; | |
4103 | case OPC2_32_BO_LD_H_PREINC: | |
4104 | gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW); | |
4105 | break; | |
4106 | case OPC2_32_BO_LD_HU_SHORTOFF: | |
4107 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); | |
4108 | break; | |
4109 | case OPC2_32_BO_LD_HU_POSTINC: | |
4110 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
4111 | MO_LEUW); | |
4112 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4113 | break; | |
4114 | case OPC2_32_BO_LD_HU_PREINC: | |
4115 | gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); | |
4116 | break; | |
4117 | case OPC2_32_BO_LD_Q_SHORTOFF: | |
4118 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); | |
4119 | tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); | |
4120 | break; | |
4121 | case OPC2_32_BO_LD_Q_POSTINC: | |
4122 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
4123 | MO_LEUW); | |
4124 | tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); | |
4125 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4126 | break; | |
4127 | case OPC2_32_BO_LD_Q_PREINC: | |
4128 | gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); | |
4129 | tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); | |
4130 | break; | |
4131 | case OPC2_32_BO_LD_W_SHORTOFF: | |
4132 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); | |
4133 | break; | |
4134 | case OPC2_32_BO_LD_W_POSTINC: | |
4135 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
4136 | MO_LEUL); | |
4137 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4138 | break; | |
4139 | case OPC2_32_BO_LD_W_PREINC: | |
4140 | gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); | |
4141 | break; | |
4142 | } | |
4143 | } | |
4144 | ||
4145 | static void decode_bo_addrmode_ld_bitreverse_circular(CPUTriCoreState *env, | |
4146 | DisasContext *ctx) | |
4147 | { | |
4148 | uint32_t op2; | |
4149 | uint32_t off10; | |
4150 | int r1, r2; | |
4151 | ||
4152 | TCGv temp, temp2, temp3; | |
4153 | ||
4154 | r1 = MASK_OP_BO_S1D(ctx->opcode); | |
4155 | r2 = MASK_OP_BO_S2(ctx->opcode); | |
4156 | off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); | |
4157 | op2 = MASK_OP_BO_OP2(ctx->opcode); | |
4158 | ||
4159 | temp = tcg_temp_new(); | |
4160 | temp2 = tcg_temp_new(); | |
4161 | temp3 = tcg_const_i32(off10); | |
4162 | ||
4163 | tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); | |
4164 | tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); | |
4165 | ||
4166 | ||
4167 | switch (op2) { | |
4168 | case OPC2_32_BO_LD_A_BR: | |
4169 | tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); | |
4170 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4171 | break; | |
4172 | case OPC2_32_BO_LD_A_CIRC: | |
4173 | tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); | |
4174 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
4175 | break; | |
4176 | case OPC2_32_BO_LD_B_BR: | |
4177 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB); | |
4178 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4179 | break; | |
4180 | case OPC2_32_BO_LD_B_CIRC: | |
4181 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB); | |
4182 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
4183 | break; | |
4184 | case OPC2_32_BO_LD_BU_BR: | |
4185 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); | |
4186 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4187 | break; | |
4188 | case OPC2_32_BO_LD_BU_CIRC: | |
4189 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); | |
4190 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
4191 | break; | |
4192 | case OPC2_32_BO_LD_D_BR: | |
4193 | gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx); | |
4194 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4195 | break; | |
4196 | case OPC2_32_BO_LD_D_CIRC: | |
4197 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); | |
4198 | tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); | |
4199 | tcg_gen_addi_tl(temp, temp, 4); | |
4200 | tcg_gen_rem_tl(temp, temp, temp2); | |
4201 | tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); | |
4202 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL); | |
4203 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
4204 | break; | |
4205 | case OPC2_32_BO_LD_DA_BR: | |
4206 | gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx); | |
4207 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4208 | break; | |
4209 | case OPC2_32_BO_LD_DA_CIRC: | |
4210 | tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); | |
4211 | tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); | |
4212 | tcg_gen_addi_tl(temp, temp, 4); | |
4213 | tcg_gen_rem_tl(temp, temp, temp2); | |
4214 | tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); | |
4215 | tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL); | |
4216 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
4217 | break; | |
4218 | case OPC2_32_BO_LD_H_BR: | |
4219 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW); | |
4220 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4221 | break; | |
4222 | case OPC2_32_BO_LD_H_CIRC: | |
4223 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW); | |
4224 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
4225 | break; | |
4226 | case OPC2_32_BO_LD_HU_BR: | |
4227 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); | |
4228 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4229 | break; | |
4230 | case OPC2_32_BO_LD_HU_CIRC: | |
4231 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); | |
4232 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
4233 | break; | |
4234 | case OPC2_32_BO_LD_Q_BR: | |
4235 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); | |
4236 | tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); | |
4237 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4238 | break; | |
4239 | case OPC2_32_BO_LD_Q_CIRC: | |
4240 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); | |
4241 | tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); | |
4242 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
4243 | break; | |
4244 | case OPC2_32_BO_LD_W_BR: | |
4245 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); | |
4246 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4247 | break; | |
4248 | case OPC2_32_BO_LD_W_CIRC: | |
4249 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); | |
4250 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
4251 | break; | |
4252 | } | |
4253 | tcg_temp_free(temp); | |
4254 | tcg_temp_free(temp2); | |
4255 | tcg_temp_free(temp3); | |
4256 | } | |
4257 | ||
4258 | static void decode_bo_addrmode_stctx_post_pre_base(CPUTriCoreState *env, | |
4259 | DisasContext *ctx) | |
4260 | { | |
4261 | uint32_t op2; | |
4262 | uint32_t off10; | |
4263 | int r1, r2; | |
4264 | ||
4265 | TCGv temp, temp2; | |
4266 | ||
4267 | r1 = MASK_OP_BO_S1D(ctx->opcode); | |
4268 | r2 = MASK_OP_BO_S2(ctx->opcode); | |
4269 | off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); | |
4270 | op2 = MASK_OP_BO_OP2(ctx->opcode); | |
4271 | ||
4272 | ||
4273 | temp = tcg_temp_new(); | |
4274 | temp2 = tcg_temp_new(); | |
4275 | ||
4276 | switch (op2) { | |
4277 | case OPC2_32_BO_LDLCX_SHORTOFF: | |
4278 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
4279 | gen_helper_ldlcx(cpu_env, temp); | |
4280 | break; | |
4281 | case OPC2_32_BO_LDMST_SHORTOFF: | |
4282 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
4283 | gen_ldmst(ctx, r1, temp); | |
4284 | break; | |
4285 | case OPC2_32_BO_LDMST_POSTINC: | |
4286 | gen_ldmst(ctx, r1, cpu_gpr_a[r2]); | |
4287 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4288 | break; | |
4289 | case OPC2_32_BO_LDMST_PREINC: | |
4290 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4291 | gen_ldmst(ctx, r1, cpu_gpr_a[r2]); | |
4292 | break; | |
4293 | case OPC2_32_BO_LDUCX_SHORTOFF: | |
4294 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
4295 | gen_helper_lducx(cpu_env, temp); | |
4296 | break; | |
4297 | case OPC2_32_BO_LEA_SHORTOFF: | |
4298 | tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10); | |
4299 | break; | |
4300 | case OPC2_32_BO_STLCX_SHORTOFF: | |
4301 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
4302 | gen_helper_stlcx(cpu_env, temp); | |
4303 | break; | |
4304 | case OPC2_32_BO_STUCX_SHORTOFF: | |
4305 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
4306 | gen_helper_stucx(cpu_env, temp); | |
4307 | break; | |
4308 | case OPC2_32_BO_SWAP_W_SHORTOFF: | |
4309 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
4310 | gen_swap(ctx, r1, temp); | |
4311 | break; | |
4312 | case OPC2_32_BO_SWAP_W_POSTINC: | |
4313 | gen_swap(ctx, r1, cpu_gpr_a[r2]); | |
4314 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4315 | break; | |
4316 | case OPC2_32_BO_SWAP_W_PREINC: | |
4317 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4318 | gen_swap(ctx, r1, cpu_gpr_a[r2]); | |
4319 | break; | |
4320 | } | |
4321 | tcg_temp_free(temp); | |
4322 | tcg_temp_free(temp2); | |
4323 | } | |
4324 | ||
4325 | static void decode_bo_addrmode_ldmst_bitreverse_circular(CPUTriCoreState *env, | |
4326 | DisasContext *ctx) | |
4327 | { | |
4328 | uint32_t op2; | |
4329 | uint32_t off10; | |
4330 | int r1, r2; | |
4331 | ||
4332 | TCGv temp, temp2, temp3; | |
4333 | ||
4334 | r1 = MASK_OP_BO_S1D(ctx->opcode); | |
4335 | r2 = MASK_OP_BO_S2(ctx->opcode); | |
4336 | off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); | |
4337 | op2 = MASK_OP_BO_OP2(ctx->opcode); | |
4338 | ||
4339 | temp = tcg_temp_new(); | |
4340 | temp2 = tcg_temp_new(); | |
4341 | temp3 = tcg_const_i32(off10); | |
4342 | ||
4343 | tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); | |
4344 | tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); | |
4345 | ||
4346 | switch (op2) { | |
4347 | case OPC2_32_BO_LDMST_BR: | |
4348 | gen_ldmst(ctx, r1, temp2); | |
4349 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4350 | break; | |
4351 | case OPC2_32_BO_LDMST_CIRC: | |
4352 | gen_ldmst(ctx, r1, temp2); | |
4353 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
4354 | break; | |
4355 | case OPC2_32_BO_SWAP_W_BR: | |
4356 | gen_swap(ctx, r1, temp2); | |
4357 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4358 | break; | |
4359 | case OPC2_32_BO_SWAP_W_CIRC: | |
4360 | gen_swap(ctx, r1, temp2); | |
4361 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
4362 | break; | |
4363 | } | |
4364 | tcg_temp_free(temp); | |
4365 | tcg_temp_free(temp2); | |
4366 | tcg_temp_free(temp3); | |
4367 | } | |
4368 | ||
3fb763cb BK |
4369 | static void decode_bol_opc(CPUTriCoreState *env, DisasContext *ctx, int32_t op1) |
4370 | { | |
4371 | int r1, r2; | |
4372 | int32_t address; | |
4373 | TCGv temp; | |
4374 | ||
4375 | r1 = MASK_OP_BOL_S1D(ctx->opcode); | |
4376 | r2 = MASK_OP_BOL_S2(ctx->opcode); | |
4377 | address = MASK_OP_BOL_OFF16_SEXT(ctx->opcode); | |
4378 | ||
4379 | switch (op1) { | |
4380 | case OPC1_32_BOL_LD_A_LONGOFF: | |
4381 | temp = tcg_temp_new(); | |
4382 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address); | |
4383 | tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL); | |
4384 | tcg_temp_free(temp); | |
4385 | break; | |
af715d98 | 4386 | case OPC1_32_BOL_LD_W_LONGOFF: |
3fb763cb BK |
4387 | temp = tcg_temp_new(); |
4388 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address); | |
4389 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL); | |
4390 | tcg_temp_free(temp); | |
4391 | break; | |
4392 | case OPC1_32_BOL_LEA_LONGOFF: | |
4393 | tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address); | |
4394 | break; | |
4395 | case OPC1_32_BOL_ST_A_LONGOFF: | |
4396 | if (tricore_feature(env, TRICORE_FEATURE_16)) { | |
4397 | gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL); | |
4398 | } else { | |
4399 | /* raise illegal opcode trap */ | |
4400 | } | |
4401 | break; | |
4402 | case OPC1_32_BOL_ST_W_LONGOFF: | |
4403 | gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL); | |
4404 | break; | |
b5fd8fa3 BK |
4405 | case OPC1_32_BOL_LD_B_LONGOFF: |
4406 | if (tricore_feature(env, TRICORE_FEATURE_16)) { | |
4407 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB); | |
4408 | } else { | |
4409 | /* raise illegal opcode trap */ | |
4410 | } | |
4411 | break; | |
4412 | case OPC1_32_BOL_LD_BU_LONGOFF: | |
4413 | if (tricore_feature(env, TRICORE_FEATURE_16)) { | |
4414 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB); | |
4415 | } else { | |
4416 | /* raise illegal opcode trap */ | |
4417 | } | |
4418 | break; | |
4419 | case OPC1_32_BOL_LD_H_LONGOFF: | |
4420 | if (tricore_feature(env, TRICORE_FEATURE_16)) { | |
4421 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW); | |
4422 | } else { | |
4423 | /* raise illegal opcode trap */ | |
4424 | } | |
4425 | break; | |
4426 | case OPC1_32_BOL_LD_HU_LONGOFF: | |
4427 | if (tricore_feature(env, TRICORE_FEATURE_16)) { | |
4428 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW); | |
4429 | } else { | |
4430 | /* raise illegal opcode trap */ | |
4431 | } | |
4432 | break; | |
4433 | case OPC1_32_BOL_ST_B_LONGOFF: | |
4434 | if (tricore_feature(env, TRICORE_FEATURE_16)) { | |
4435 | gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB); | |
4436 | } else { | |
4437 | /* raise illegal opcode trap */ | |
4438 | } | |
4439 | break; | |
4440 | case OPC1_32_BOL_ST_H_LONGOFF: | |
4441 | if (tricore_feature(env, TRICORE_FEATURE_16)) { | |
4442 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW); | |
4443 | } else { | |
4444 | /* raise illegal opcode trap */ | |
4445 | } | |
4446 | break; | |
3fb763cb | 4447 | } |
3fb763cb BK |
4448 | } |
4449 | ||
0974257e BK |
4450 | /* RC format */ |
4451 | static void decode_rc_logical_shift(CPUTriCoreState *env, DisasContext *ctx) | |
4452 | { | |
4453 | uint32_t op2; | |
4454 | int r1, r2; | |
4455 | int32_t const9; | |
4456 | TCGv temp; | |
4457 | ||
4458 | r2 = MASK_OP_RC_D(ctx->opcode); | |
4459 | r1 = MASK_OP_RC_S1(ctx->opcode); | |
4460 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
4461 | op2 = MASK_OP_RC_OP2(ctx->opcode); | |
4462 | ||
4463 | temp = tcg_temp_new(); | |
4464 | ||
4465 | switch (op2) { | |
4466 | case OPC2_32_RC_AND: | |
4467 | tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4468 | break; | |
4469 | case OPC2_32_RC_ANDN: | |
4470 | tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9); | |
4471 | break; | |
4472 | case OPC2_32_RC_NAND: | |
4473 | tcg_gen_movi_tl(temp, const9); | |
4474 | tcg_gen_nand_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); | |
4475 | break; | |
4476 | case OPC2_32_RC_NOR: | |
4477 | tcg_gen_movi_tl(temp, const9); | |
4478 | tcg_gen_nor_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); | |
4479 | break; | |
4480 | case OPC2_32_RC_OR: | |
4481 | tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4482 | break; | |
4483 | case OPC2_32_RC_ORN: | |
4484 | tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9); | |
4485 | break; | |
4486 | case OPC2_32_RC_SH: | |
4487 | const9 = sextract32(const9, 0, 6); | |
4488 | gen_shi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4489 | break; | |
4490 | case OPC2_32_RC_SH_H: | |
4491 | const9 = sextract32(const9, 0, 5); | |
4492 | gen_sh_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4493 | break; | |
4494 | case OPC2_32_RC_SHA: | |
4495 | const9 = sextract32(const9, 0, 6); | |
4496 | gen_shaci(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4497 | break; | |
4498 | case OPC2_32_RC_SHA_H: | |
4499 | const9 = sextract32(const9, 0, 5); | |
4500 | gen_sha_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4501 | break; | |
4502 | case OPC2_32_RC_SHAS: | |
4503 | gen_shasi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4504 | break; | |
4505 | case OPC2_32_RC_XNOR: | |
4506 | tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4507 | tcg_gen_not_tl(cpu_gpr_d[r2], cpu_gpr_d[r2]); | |
4508 | break; | |
4509 | case OPC2_32_RC_XOR: | |
4510 | tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4511 | break; | |
4512 | } | |
4513 | tcg_temp_free(temp); | |
4514 | } | |
4515 | ||
4516 | static void decode_rc_accumulator(CPUTriCoreState *env, DisasContext *ctx) | |
4517 | { | |
4518 | uint32_t op2; | |
4519 | int r1, r2; | |
4520 | int16_t const9; | |
4521 | ||
4522 | TCGv temp; | |
4523 | ||
4524 | r2 = MASK_OP_RC_D(ctx->opcode); | |
4525 | r1 = MASK_OP_RC_S1(ctx->opcode); | |
4526 | const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode); | |
4527 | ||
4528 | op2 = MASK_OP_RC_OP2(ctx->opcode); | |
4529 | ||
4530 | temp = tcg_temp_new(); | |
4531 | ||
4532 | switch (op2) { | |
4533 | case OPC2_32_RC_ABSDIF: | |
4534 | gen_absdifi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4535 | break; | |
4536 | case OPC2_32_RC_ABSDIFS: | |
4537 | gen_absdifsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4538 | break; | |
4539 | case OPC2_32_RC_ADD: | |
4540 | gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4541 | break; | |
4542 | case OPC2_32_RC_ADDC: | |
4543 | gen_addci_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4544 | break; | |
4545 | case OPC2_32_RC_ADDS: | |
4546 | gen_addsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4547 | break; | |
4548 | case OPC2_32_RC_ADDS_U: | |
4549 | gen_addsui(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4550 | break; | |
4551 | case OPC2_32_RC_ADDX: | |
4552 | gen_addi_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4553 | break; | |
4554 | case OPC2_32_RC_AND_EQ: | |
4555 | gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
4556 | const9, &tcg_gen_and_tl); | |
4557 | break; | |
4558 | case OPC2_32_RC_AND_GE: | |
4559 | gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
4560 | const9, &tcg_gen_and_tl); | |
4561 | break; | |
4562 | case OPC2_32_RC_AND_GE_U: | |
4563 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
4564 | gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
4565 | const9, &tcg_gen_and_tl); | |
4566 | break; | |
4567 | case OPC2_32_RC_AND_LT: | |
4568 | gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
4569 | const9, &tcg_gen_and_tl); | |
4570 | break; | |
4571 | case OPC2_32_RC_AND_LT_U: | |
4572 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
4573 | gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
4574 | const9, &tcg_gen_and_tl); | |
4575 | break; | |
4576 | case OPC2_32_RC_AND_NE: | |
4577 | gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
4578 | const9, &tcg_gen_and_tl); | |
4579 | break; | |
4580 | case OPC2_32_RC_EQ: | |
4581 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4582 | break; | |
4583 | case OPC2_32_RC_EQANY_B: | |
4584 | gen_eqany_bi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4585 | break; | |
4586 | case OPC2_32_RC_EQANY_H: | |
4587 | gen_eqany_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4588 | break; | |
4589 | case OPC2_32_RC_GE: | |
4590 | tcg_gen_setcondi_tl(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4591 | break; | |
4592 | case OPC2_32_RC_GE_U: | |
4593 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
4594 | tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4595 | break; | |
4596 | case OPC2_32_RC_LT: | |
4597 | tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4598 | break; | |
4599 | case OPC2_32_RC_LT_U: | |
4600 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
4601 | tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4602 | break; | |
4603 | case OPC2_32_RC_MAX: | |
4604 | tcg_gen_movi_tl(temp, const9); | |
4605 | tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, | |
4606 | cpu_gpr_d[r1], temp); | |
4607 | break; | |
4608 | case OPC2_32_RC_MAX_U: | |
4609 | tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode)); | |
4610 | tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, | |
4611 | cpu_gpr_d[r1], temp); | |
4612 | break; | |
4613 | case OPC2_32_RC_MIN: | |
4614 | tcg_gen_movi_tl(temp, const9); | |
4615 | tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, | |
4616 | cpu_gpr_d[r1], temp); | |
4617 | break; | |
4618 | case OPC2_32_RC_MIN_U: | |
4619 | tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode)); | |
4620 | tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, | |
4621 | cpu_gpr_d[r1], temp); | |
4622 | break; | |
4623 | case OPC2_32_RC_NE: | |
4624 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4625 | break; | |
4626 | case OPC2_32_RC_OR_EQ: | |
4627 | gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
4628 | const9, &tcg_gen_or_tl); | |
4629 | break; | |
4630 | case OPC2_32_RC_OR_GE: | |
4631 | gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
4632 | const9, &tcg_gen_or_tl); | |
4633 | break; | |
4634 | case OPC2_32_RC_OR_GE_U: | |
4635 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
4636 | gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
4637 | const9, &tcg_gen_or_tl); | |
4638 | break; | |
4639 | case OPC2_32_RC_OR_LT: | |
4640 | gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
4641 | const9, &tcg_gen_or_tl); | |
4642 | break; | |
4643 | case OPC2_32_RC_OR_LT_U: | |
4644 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
4645 | gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
4646 | const9, &tcg_gen_or_tl); | |
4647 | break; | |
4648 | case OPC2_32_RC_OR_NE: | |
4649 | gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
4650 | const9, &tcg_gen_or_tl); | |
4651 | break; | |
4652 | case OPC2_32_RC_RSUB: | |
4653 | tcg_gen_movi_tl(temp, const9); | |
4654 | gen_sub_d(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); | |
4655 | break; | |
4656 | case OPC2_32_RC_RSUBS: | |
4657 | tcg_gen_movi_tl(temp, const9); | |
4658 | gen_subs(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); | |
4659 | break; | |
4660 | case OPC2_32_RC_RSUBS_U: | |
4661 | tcg_gen_movi_tl(temp, const9); | |
4662 | gen_subsu(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); | |
4663 | break; | |
4664 | case OPC2_32_RC_SH_EQ: | |
4665 | gen_sh_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4666 | break; | |
4667 | case OPC2_32_RC_SH_GE: | |
4668 | gen_sh_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4669 | break; | |
4670 | case OPC2_32_RC_SH_GE_U: | |
4671 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
4672 | gen_sh_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4673 | break; | |
4674 | case OPC2_32_RC_SH_LT: | |
4675 | gen_sh_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4676 | break; | |
4677 | case OPC2_32_RC_SH_LT_U: | |
4678 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
4679 | gen_sh_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4680 | break; | |
4681 | case OPC2_32_RC_SH_NE: | |
4682 | gen_sh_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4683 | break; | |
4684 | case OPC2_32_RC_XOR_EQ: | |
4685 | gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
4686 | const9, &tcg_gen_xor_tl); | |
4687 | break; | |
4688 | case OPC2_32_RC_XOR_GE: | |
4689 | gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
4690 | const9, &tcg_gen_xor_tl); | |
4691 | break; | |
4692 | case OPC2_32_RC_XOR_GE_U: | |
4693 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
4694 | gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
4695 | const9, &tcg_gen_xor_tl); | |
4696 | break; | |
4697 | case OPC2_32_RC_XOR_LT: | |
4698 | gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
4699 | const9, &tcg_gen_xor_tl); | |
4700 | break; | |
4701 | case OPC2_32_RC_XOR_LT_U: | |
4702 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
4703 | gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
4704 | const9, &tcg_gen_xor_tl); | |
4705 | break; | |
4706 | case OPC2_32_RC_XOR_NE: | |
4707 | gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
4708 | const9, &tcg_gen_xor_tl); | |
4709 | break; | |
4710 | } | |
4711 | tcg_temp_free(temp); | |
4712 | } | |
4713 | ||
4714 | static void decode_rc_serviceroutine(CPUTriCoreState *env, DisasContext *ctx) | |
4715 | { | |
4716 | uint32_t op2; | |
4717 | uint32_t const9; | |
4718 | ||
4719 | op2 = MASK_OP_RC_OP2(ctx->opcode); | |
4720 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
4721 | ||
4722 | switch (op2) { | |
4723 | case OPC2_32_RC_BISR: | |
4724 | gen_helper_1arg(bisr, const9); | |
4725 | break; | |
4726 | case OPC2_32_RC_SYSCALL: | |
4727 | /* TODO: Add exception generation */ | |
4728 | break; | |
4729 | } | |
4730 | } | |
4731 | ||
4732 | static void decode_rc_mul(CPUTriCoreState *env, DisasContext *ctx) | |
4733 | { | |
4734 | uint32_t op2; | |
4735 | int r1, r2; | |
4736 | int16_t const9; | |
4737 | ||
4738 | r2 = MASK_OP_RC_D(ctx->opcode); | |
4739 | r1 = MASK_OP_RC_S1(ctx->opcode); | |
4740 | const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode); | |
4741 | ||
4742 | op2 = MASK_OP_RC_OP2(ctx->opcode); | |
4743 | ||
4744 | switch (op2) { | |
4745 | case OPC2_32_RC_MUL_32: | |
4746 | gen_muli_i32s(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4747 | break; | |
4748 | case OPC2_32_RC_MUL_64: | |
4749 | gen_muli_i64s(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9); | |
4750 | break; | |
4751 | case OPC2_32_RC_MULS_32: | |
4752 | gen_mulsi_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4753 | break; | |
4754 | case OPC2_32_RC_MUL_U_64: | |
4755 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
4756 | gen_muli_i64u(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9); | |
4757 | break; | |
4758 | case OPC2_32_RC_MULS_U_32: | |
4759 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
4760 | gen_mulsui_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4761 | break; | |
4762 | } | |
4763 | } | |
4764 | ||
ed516260 BK |
4765 | /* RCPW format */ |
4766 | static void decode_rcpw_insert(CPUTriCoreState *env, DisasContext *ctx) | |
4767 | { | |
4768 | uint32_t op2; | |
4769 | int r1, r2; | |
4770 | int32_t pos, width, const4; | |
4771 | ||
4772 | TCGv temp; | |
4773 | ||
4774 | op2 = MASK_OP_RCPW_OP2(ctx->opcode); | |
4775 | r1 = MASK_OP_RCPW_S1(ctx->opcode); | |
4776 | r2 = MASK_OP_RCPW_D(ctx->opcode); | |
4777 | const4 = MASK_OP_RCPW_CONST4(ctx->opcode); | |
4778 | width = MASK_OP_RCPW_WIDTH(ctx->opcode); | |
4779 | pos = MASK_OP_RCPW_POS(ctx->opcode); | |
4780 | ||
4781 | switch (op2) { | |
4782 | case OPC2_32_RCPW_IMASK: | |
4783 | /* if pos + width > 31 undefined result */ | |
4784 | if (pos + width <= 31) { | |
4785 | tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos); | |
4786 | tcg_gen_movi_tl(cpu_gpr_d[r2], (const4 << pos)); | |
4787 | } | |
4788 | break; | |
4789 | case OPC2_32_RCPW_INSERT: | |
4790 | /* if pos + width > 32 undefined result */ | |
4791 | if (pos + width <= 32) { | |
4792 | temp = tcg_const_i32(const4); | |
4793 | tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width); | |
4794 | tcg_temp_free(temp); | |
4795 | } | |
4796 | break; | |
4797 | } | |
4798 | } | |
4799 | ||
4800 | /* RCRW format */ | |
4801 | ||
4802 | static void decode_rcrw_insert(CPUTriCoreState *env, DisasContext *ctx) | |
4803 | { | |
4804 | uint32_t op2; | |
4805 | int r1, r3, r4; | |
4806 | int32_t width, const4; | |
4807 | ||
4808 | TCGv temp, temp2, temp3; | |
4809 | ||
4810 | op2 = MASK_OP_RCRW_OP2(ctx->opcode); | |
4811 | r1 = MASK_OP_RCRW_S1(ctx->opcode); | |
4812 | r3 = MASK_OP_RCRW_S3(ctx->opcode); | |
4813 | r4 = MASK_OP_RCRW_D(ctx->opcode); | |
4814 | width = MASK_OP_RCRW_WIDTH(ctx->opcode); | |
4815 | const4 = MASK_OP_RCRW_CONST4(ctx->opcode); | |
4816 | ||
4817 | temp = tcg_temp_new(); | |
4818 | temp2 = tcg_temp_new(); | |
4819 | ||
4820 | switch (op2) { | |
4821 | case OPC2_32_RCRW_IMASK: | |
4822 | tcg_gen_andi_tl(temp, cpu_gpr_d[r4], 0x1f); | |
4823 | tcg_gen_movi_tl(temp2, (1 << width) - 1); | |
4824 | tcg_gen_shl_tl(cpu_gpr_d[r3 + 1], temp2, temp); | |
4825 | tcg_gen_movi_tl(temp2, const4); | |
4826 | tcg_gen_shl_tl(cpu_gpr_d[r3], temp2, temp); | |
4827 | break; | |
4828 | case OPC2_32_RCRW_INSERT: | |
4829 | temp3 = tcg_temp_new(); | |
4830 | ||
4831 | tcg_gen_movi_tl(temp, width); | |
4832 | tcg_gen_movi_tl(temp2, const4); | |
4833 | tcg_gen_andi_tl(temp3, cpu_gpr_d[r4], 0x1f); | |
4834 | gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp2, temp, temp3); | |
4835 | ||
4836 | tcg_temp_free(temp3); | |
4837 | break; | |
4838 | } | |
4839 | tcg_temp_free(temp); | |
4840 | tcg_temp_free(temp2); | |
4841 | } | |
4842 | ||
328f1f0f BK |
4843 | /* RCR format */ |
4844 | ||
4845 | static void decode_rcr_cond_select(CPUTriCoreState *env, DisasContext *ctx) | |
4846 | { | |
4847 | uint32_t op2; | |
4848 | int r1, r3, r4; | |
4849 | int32_t const9; | |
4850 | ||
4851 | TCGv temp, temp2; | |
4852 | ||
4853 | op2 = MASK_OP_RCR_OP2(ctx->opcode); | |
4854 | r1 = MASK_OP_RCR_S1(ctx->opcode); | |
4855 | const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); | |
4856 | r3 = MASK_OP_RCR_S3(ctx->opcode); | |
4857 | r4 = MASK_OP_RCR_D(ctx->opcode); | |
4858 | ||
4859 | switch (op2) { | |
4860 | case OPC2_32_RCR_CADD: | |
4861 | gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const9, cpu_gpr_d[r3], | |
4862 | cpu_gpr_d[r4]); | |
4863 | break; | |
4864 | case OPC2_32_RCR_CADDN: | |
4865 | gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const9, cpu_gpr_d[r3], | |
4866 | cpu_gpr_d[r4]); | |
4867 | break; | |
4868 | case OPC2_32_RCR_SEL: | |
4869 | temp = tcg_const_i32(0); | |
4870 | temp2 = tcg_const_i32(const9); | |
5f30046f | 4871 | tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, |
328f1f0f BK |
4872 | cpu_gpr_d[r1], temp2); |
4873 | tcg_temp_free(temp); | |
4874 | tcg_temp_free(temp2); | |
4875 | break; | |
4876 | case OPC2_32_RCR_SELN: | |
4877 | temp = tcg_const_i32(0); | |
4878 | temp2 = tcg_const_i32(const9); | |
5f30046f | 4879 | tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, |
328f1f0f BK |
4880 | cpu_gpr_d[r1], temp2); |
4881 | tcg_temp_free(temp); | |
4882 | tcg_temp_free(temp2); | |
4883 | break; | |
4884 | } | |
4885 | } | |
4886 | ||
4887 | static void decode_rcr_madd(CPUTriCoreState *env, DisasContext *ctx) | |
4888 | { | |
4889 | uint32_t op2; | |
4890 | int r1, r3, r4; | |
4891 | int32_t const9; | |
4892 | ||
4893 | ||
4894 | op2 = MASK_OP_RCR_OP2(ctx->opcode); | |
4895 | r1 = MASK_OP_RCR_S1(ctx->opcode); | |
4896 | const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); | |
4897 | r3 = MASK_OP_RCR_S3(ctx->opcode); | |
4898 | r4 = MASK_OP_RCR_D(ctx->opcode); | |
4899 | ||
4900 | switch (op2) { | |
4901 | case OPC2_32_RCR_MADD_32: | |
4902 | gen_maddi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); | |
4903 | break; | |
4904 | case OPC2_32_RCR_MADD_64: | |
4905 | gen_maddi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], | |
4906 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); | |
4907 | break; | |
4908 | case OPC2_32_RCR_MADDS_32: | |
4909 | gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); | |
4910 | break; | |
4911 | case OPC2_32_RCR_MADDS_64: | |
4912 | gen_maddsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], | |
4913 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); | |
4914 | break; | |
4915 | case OPC2_32_RCR_MADD_U_64: | |
4916 | const9 = MASK_OP_RCR_CONST9(ctx->opcode); | |
4917 | gen_maddui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], | |
4918 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); | |
4919 | break; | |
4920 | case OPC2_32_RCR_MADDS_U_32: | |
4921 | const9 = MASK_OP_RCR_CONST9(ctx->opcode); | |
4922 | gen_maddsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); | |
4923 | break; | |
4924 | case OPC2_32_RCR_MADDS_U_64: | |
4925 | const9 = MASK_OP_RCR_CONST9(ctx->opcode); | |
4926 | gen_maddsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], | |
4927 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); | |
4928 | break; | |
4929 | } | |
4930 | } | |
4931 | ||
4932 | static void decode_rcr_msub(CPUTriCoreState *env, DisasContext *ctx) | |
4933 | { | |
4934 | uint32_t op2; | |
4935 | int r1, r3, r4; | |
4936 | int32_t const9; | |
4937 | ||
4938 | ||
4939 | op2 = MASK_OP_RCR_OP2(ctx->opcode); | |
4940 | r1 = MASK_OP_RCR_S1(ctx->opcode); | |
4941 | const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); | |
4942 | r3 = MASK_OP_RCR_S3(ctx->opcode); | |
4943 | r4 = MASK_OP_RCR_D(ctx->opcode); | |
4944 | ||
4945 | switch (op2) { | |
4946 | case OPC2_32_RCR_MSUB_32: | |
4947 | gen_msubi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); | |
4948 | break; | |
4949 | case OPC2_32_RCR_MSUB_64: | |
4950 | gen_msubi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], | |
4951 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); | |
4952 | break; | |
4953 | case OPC2_32_RCR_MSUBS_32: | |
4954 | gen_msubsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); | |
4955 | break; | |
4956 | case OPC2_32_RCR_MSUBS_64: | |
4957 | gen_msubsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], | |
4958 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); | |
4959 | break; | |
4960 | case OPC2_32_RCR_MSUB_U_64: | |
4961 | const9 = MASK_OP_RCR_CONST9(ctx->opcode); | |
4962 | gen_msubui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], | |
4963 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); | |
4964 | break; | |
4965 | case OPC2_32_RCR_MSUBS_U_32: | |
4966 | const9 = MASK_OP_RCR_CONST9(ctx->opcode); | |
4967 | gen_msubsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); | |
4968 | break; | |
4969 | case OPC2_32_RCR_MSUBS_U_64: | |
4970 | const9 = MASK_OP_RCR_CONST9(ctx->opcode); | |
4971 | gen_msubsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], | |
4972 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); | |
4973 | break; | |
4974 | } | |
4975 | } | |
4976 | ||
2b2f7d97 BK |
4977 | /* RLC format */ |
4978 | ||
4979 | static void decode_rlc_opc(CPUTriCoreState *env, DisasContext *ctx, | |
4980 | uint32_t op1) | |
4981 | { | |
4982 | int32_t const16; | |
4983 | int r1, r2; | |
4984 | ||
4985 | const16 = MASK_OP_RLC_CONST16_SEXT(ctx->opcode); | |
4986 | r1 = MASK_OP_RLC_S1(ctx->opcode); | |
4987 | r2 = MASK_OP_RLC_D(ctx->opcode); | |
4988 | ||
4989 | switch (op1) { | |
4990 | case OPC1_32_RLC_ADDI: | |
f0cab01b | 4991 | gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16); |
2b2f7d97 BK |
4992 | break; |
4993 | case OPC1_32_RLC_ADDIH: | |
f0cab01b | 4994 | gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16 << 16); |
2b2f7d97 BK |
4995 | break; |
4996 | case OPC1_32_RLC_ADDIH_A: | |
4997 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r1], const16 << 16); | |
4998 | break; | |
4999 | case OPC1_32_RLC_MFCR: | |
436d63ff | 5000 | const16 = MASK_OP_RLC_CONST16(ctx->opcode); |
2b2f7d97 BK |
5001 | gen_mfcr(env, cpu_gpr_d[r2], const16); |
5002 | break; | |
5003 | case OPC1_32_RLC_MOV: | |
5004 | tcg_gen_movi_tl(cpu_gpr_d[r2], const16); | |
5005 | break; | |
4b5b4435 AZ |
5006 | case OPC1_32_RLC_MOV_64: |
5007 | if (tricore_feature(env, TRICORE_FEATURE_16)) { | |
5008 | if ((r2 & 0x1) != 0) { | |
5009 | /* TODO: raise OPD trap */ | |
5010 | } | |
5011 | tcg_gen_movi_tl(cpu_gpr_d[r2], const16); | |
5012 | tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15); | |
5013 | } else { | |
5014 | /* TODO: raise illegal opcode trap */ | |
5015 | } | |
5016 | break; | |
2b2f7d97 BK |
5017 | case OPC1_32_RLC_MOV_U: |
5018 | const16 = MASK_OP_RLC_CONST16(ctx->opcode); | |
5019 | tcg_gen_movi_tl(cpu_gpr_d[r2], const16); | |
5020 | break; | |
5021 | case OPC1_32_RLC_MOV_H: | |
5022 | tcg_gen_movi_tl(cpu_gpr_d[r2], const16 << 16); | |
5023 | break; | |
5024 | case OPC1_32_RLC_MOVH_A: | |
5025 | tcg_gen_movi_tl(cpu_gpr_a[r2], const16 << 16); | |
5026 | break; | |
5027 | case OPC1_32_RLC_MTCR: | |
436d63ff BK |
5028 | const16 = MASK_OP_RLC_CONST16(ctx->opcode); |
5029 | gen_mtcr(env, ctx, cpu_gpr_d[r1], const16); | |
2b2f7d97 BK |
5030 | break; |
5031 | } | |
5032 | } | |
5033 | ||
d5de7839 BK |
5034 | /* RR format */ |
5035 | static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx) | |
5036 | { | |
5037 | uint32_t op2; | |
5038 | int r3, r2, r1; | |
5039 | ||
5040 | r3 = MASK_OP_RR_D(ctx->opcode); | |
5041 | r2 = MASK_OP_RR_S2(ctx->opcode); | |
5042 | r1 = MASK_OP_RR_S1(ctx->opcode); | |
5043 | op2 = MASK_OP_RR_OP2(ctx->opcode); | |
5044 | ||
5045 | switch (op2) { | |
5046 | case OPC2_32_RR_ABS: | |
5047 | gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]); | |
5048 | break; | |
5049 | case OPC2_32_RR_ABS_B: | |
5050 | gen_helper_abs_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); | |
5051 | break; | |
5052 | case OPC2_32_RR_ABS_H: | |
5053 | gen_helper_abs_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); | |
5054 | break; | |
5055 | case OPC2_32_RR_ABSDIF: | |
5056 | gen_absdif(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5057 | break; | |
5058 | case OPC2_32_RR_ABSDIF_B: | |
5059 | gen_helper_absdif_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], | |
5060 | cpu_gpr_d[r2]); | |
5061 | break; | |
5062 | case OPC2_32_RR_ABSDIF_H: | |
5063 | gen_helper_absdif_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], | |
5064 | cpu_gpr_d[r2]); | |
5065 | break; | |
5066 | case OPC2_32_RR_ABSDIFS: | |
5067 | gen_helper_absdif_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], | |
5068 | cpu_gpr_d[r2]); | |
5069 | break; | |
5070 | case OPC2_32_RR_ABSDIFS_H: | |
5071 | gen_helper_absdif_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], | |
5072 | cpu_gpr_d[r2]); | |
5073 | break; | |
5074 | case OPC2_32_RR_ABSS: | |
5075 | gen_helper_abs_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); | |
5076 | break; | |
5077 | case OPC2_32_RR_ABSS_H: | |
5078 | gen_helper_abs_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); | |
5079 | break; | |
5080 | case OPC2_32_RR_ADD: | |
5081 | gen_add_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5082 | break; | |
5083 | case OPC2_32_RR_ADD_B: | |
5084 | gen_helper_add_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5085 | break; | |
5086 | case OPC2_32_RR_ADD_H: | |
5087 | gen_helper_add_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5088 | break; | |
5089 | case OPC2_32_RR_ADDC: | |
5090 | gen_addc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5091 | break; | |
5092 | case OPC2_32_RR_ADDS: | |
5093 | gen_adds(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5094 | break; | |
5095 | case OPC2_32_RR_ADDS_H: | |
5096 | gen_helper_add_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], | |
5097 | cpu_gpr_d[r2]); | |
5098 | break; | |
5099 | case OPC2_32_RR_ADDS_HU: | |
5100 | gen_helper_add_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], | |
5101 | cpu_gpr_d[r2]); | |
5102 | break; | |
5103 | case OPC2_32_RR_ADDS_U: | |
5104 | gen_helper_add_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], | |
5105 | cpu_gpr_d[r2]); | |
5106 | break; | |
5107 | case OPC2_32_RR_ADDX: | |
5108 | gen_add_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5109 | break; | |
5110 | case OPC2_32_RR_AND_EQ: | |
5111 | gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5112 | cpu_gpr_d[r2], &tcg_gen_and_tl); | |
5113 | break; | |
5114 | case OPC2_32_RR_AND_GE: | |
5115 | gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5116 | cpu_gpr_d[r2], &tcg_gen_and_tl); | |
5117 | break; | |
5118 | case OPC2_32_RR_AND_GE_U: | |
5119 | gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5120 | cpu_gpr_d[r2], &tcg_gen_and_tl); | |
5121 | break; | |
5122 | case OPC2_32_RR_AND_LT: | |
5123 | gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5124 | cpu_gpr_d[r2], &tcg_gen_and_tl); | |
5125 | break; | |
5126 | case OPC2_32_RR_AND_LT_U: | |
5127 | gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5128 | cpu_gpr_d[r2], &tcg_gen_and_tl); | |
5129 | break; | |
5130 | case OPC2_32_RR_AND_NE: | |
5131 | gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5132 | cpu_gpr_d[r2], &tcg_gen_and_tl); | |
5133 | break; | |
5134 | case OPC2_32_RR_EQ: | |
5135 | tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5136 | cpu_gpr_d[r2]); | |
5137 | break; | |
5138 | case OPC2_32_RR_EQ_B: | |
5139 | gen_helper_eq_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5140 | break; | |
5141 | case OPC2_32_RR_EQ_H: | |
5142 | gen_helper_eq_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5143 | break; | |
5144 | case OPC2_32_RR_EQ_W: | |
5145 | gen_cond_w(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5146 | break; | |
5147 | case OPC2_32_RR_EQANY_B: | |
5148 | gen_helper_eqany_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5149 | break; | |
5150 | case OPC2_32_RR_EQANY_H: | |
5151 | gen_helper_eqany_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5152 | break; | |
5153 | case OPC2_32_RR_GE: | |
5154 | tcg_gen_setcond_tl(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5155 | cpu_gpr_d[r2]); | |
5156 | break; | |
5157 | case OPC2_32_RR_GE_U: | |
5158 | tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5159 | cpu_gpr_d[r2]); | |
5160 | break; | |
5161 | case OPC2_32_RR_LT: | |
5162 | tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5163 | cpu_gpr_d[r2]); | |
5164 | break; | |
5165 | case OPC2_32_RR_LT_U: | |
5166 | tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5167 | cpu_gpr_d[r2]); | |
5168 | break; | |
5169 | case OPC2_32_RR_LT_B: | |
5170 | gen_helper_lt_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5171 | break; | |
5172 | case OPC2_32_RR_LT_BU: | |
5173 | gen_helper_lt_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5174 | break; | |
5175 | case OPC2_32_RR_LT_H: | |
5176 | gen_helper_lt_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5177 | break; | |
5178 | case OPC2_32_RR_LT_HU: | |
5179 | gen_helper_lt_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5180 | break; | |
5181 | case OPC2_32_RR_LT_W: | |
5182 | gen_cond_w(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5183 | break; | |
5184 | case OPC2_32_RR_LT_WU: | |
5185 | gen_cond_w(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5186 | break; | |
5187 | case OPC2_32_RR_MAX: | |
5188 | tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5189 | cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5190 | break; | |
5191 | case OPC2_32_RR_MAX_U: | |
5192 | tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5193 | cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5194 | break; | |
5195 | case OPC2_32_RR_MAX_B: | |
5196 | gen_helper_max_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5197 | break; | |
5198 | case OPC2_32_RR_MAX_BU: | |
5199 | gen_helper_max_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5200 | break; | |
5201 | case OPC2_32_RR_MAX_H: | |
5202 | gen_helper_max_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5203 | break; | |
5204 | case OPC2_32_RR_MAX_HU: | |
5205 | gen_helper_max_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5206 | break; | |
5207 | case OPC2_32_RR_MIN: | |
5208 | tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5209 | cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5210 | break; | |
5211 | case OPC2_32_RR_MIN_U: | |
5212 | tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5213 | cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5214 | break; | |
5215 | case OPC2_32_RR_MIN_B: | |
5216 | gen_helper_min_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5217 | break; | |
5218 | case OPC2_32_RR_MIN_BU: | |
5219 | gen_helper_min_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5220 | break; | |
5221 | case OPC2_32_RR_MIN_H: | |
5222 | gen_helper_min_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5223 | break; | |
5224 | case OPC2_32_RR_MIN_HU: | |
5225 | gen_helper_min_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5226 | break; | |
5227 | case OPC2_32_RR_MOV: | |
5228 | tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); | |
5229 | break; | |
5230 | case OPC2_32_RR_NE: | |
5231 | tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5232 | cpu_gpr_d[r2]); | |
5233 | break; | |
5234 | case OPC2_32_RR_OR_EQ: | |
5235 | gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5236 | cpu_gpr_d[r2], &tcg_gen_or_tl); | |
5237 | break; | |
5238 | case OPC2_32_RR_OR_GE: | |
5239 | gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5240 | cpu_gpr_d[r2], &tcg_gen_or_tl); | |
5241 | break; | |
5242 | case OPC2_32_RR_OR_GE_U: | |
5243 | gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5244 | cpu_gpr_d[r2], &tcg_gen_or_tl); | |
5245 | break; | |
5246 | case OPC2_32_RR_OR_LT: | |
5247 | gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5248 | cpu_gpr_d[r2], &tcg_gen_or_tl); | |
5249 | break; | |
5250 | case OPC2_32_RR_OR_LT_U: | |
5251 | gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5252 | cpu_gpr_d[r2], &tcg_gen_or_tl); | |
5253 | break; | |
5254 | case OPC2_32_RR_OR_NE: | |
5255 | gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5256 | cpu_gpr_d[r2], &tcg_gen_or_tl); | |
5257 | break; | |
5258 | case OPC2_32_RR_SAT_B: | |
5259 | gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7f, -0x80); | |
5260 | break; | |
5261 | case OPC2_32_RR_SAT_BU: | |
5262 | gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xff); | |
5263 | break; | |
5264 | case OPC2_32_RR_SAT_H: | |
5265 | gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7fff, -0x8000); | |
5266 | break; | |
5267 | case OPC2_32_RR_SAT_HU: | |
5268 | gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xffff); | |
5269 | break; | |
5270 | case OPC2_32_RR_SH_EQ: | |
5271 | gen_sh_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5272 | cpu_gpr_d[r2]); | |
5273 | break; | |
5274 | case OPC2_32_RR_SH_GE: | |
5275 | gen_sh_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5276 | cpu_gpr_d[r2]); | |
5277 | break; | |
5278 | case OPC2_32_RR_SH_GE_U: | |
5279 | gen_sh_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5280 | cpu_gpr_d[r2]); | |
5281 | break; | |
5282 | case OPC2_32_RR_SH_LT: | |
5283 | gen_sh_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5284 | cpu_gpr_d[r2]); | |
5285 | break; | |
5286 | case OPC2_32_RR_SH_LT_U: | |
5287 | gen_sh_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5288 | cpu_gpr_d[r2]); | |
5289 | break; | |
5290 | case OPC2_32_RR_SH_NE: | |
5291 | gen_sh_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5292 | cpu_gpr_d[r2]); | |
5293 | break; | |
5294 | case OPC2_32_RR_SUB: | |
5295 | gen_sub_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5296 | break; | |
5297 | case OPC2_32_RR_SUB_B: | |
5298 | gen_helper_sub_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5299 | break; | |
5300 | case OPC2_32_RR_SUB_H: | |
5301 | gen_helper_sub_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5302 | break; | |
5303 | case OPC2_32_RR_SUBC: | |
5304 | gen_subc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5305 | break; | |
5306 | case OPC2_32_RR_SUBS: | |
5307 | gen_subs(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5308 | break; | |
5309 | case OPC2_32_RR_SUBS_U: | |
5310 | gen_subsu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5311 | break; | |
5312 | case OPC2_32_RR_SUBS_H: | |
5313 | gen_helper_sub_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], | |
5314 | cpu_gpr_d[r2]); | |
5315 | break; | |
5316 | case OPC2_32_RR_SUBS_HU: | |
5317 | gen_helper_sub_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], | |
5318 | cpu_gpr_d[r2]); | |
5319 | break; | |
5320 | case OPC2_32_RR_SUBX: | |
5321 | gen_sub_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5322 | break; | |
5323 | case OPC2_32_RR_XOR_EQ: | |
5324 | gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5325 | cpu_gpr_d[r2], &tcg_gen_xor_tl); | |
5326 | break; | |
5327 | case OPC2_32_RR_XOR_GE: | |
5328 | gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5329 | cpu_gpr_d[r2], &tcg_gen_xor_tl); | |
5330 | break; | |
5331 | case OPC2_32_RR_XOR_GE_U: | |
5332 | gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5333 | cpu_gpr_d[r2], &tcg_gen_xor_tl); | |
5334 | break; | |
5335 | case OPC2_32_RR_XOR_LT: | |
5336 | gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5337 | cpu_gpr_d[r2], &tcg_gen_xor_tl); | |
5338 | break; | |
5339 | case OPC2_32_RR_XOR_LT_U: | |
5340 | gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5341 | cpu_gpr_d[r2], &tcg_gen_xor_tl); | |
5342 | break; | |
5343 | case OPC2_32_RR_XOR_NE: | |
5344 | gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5345 | cpu_gpr_d[r2], &tcg_gen_xor_tl); | |
5346 | break; | |
5347 | } | |
5348 | } | |
5349 | ||
0b79a781 BK |
5350 | static void decode_rr_logical_shift(CPUTriCoreState *env, DisasContext *ctx) |
5351 | { | |
5352 | uint32_t op2; | |
5353 | int r3, r2, r1; | |
5354 | TCGv temp; | |
5355 | ||
5356 | r3 = MASK_OP_RR_D(ctx->opcode); | |
5357 | r2 = MASK_OP_RR_S2(ctx->opcode); | |
5358 | r1 = MASK_OP_RR_S1(ctx->opcode); | |
5359 | ||
5360 | temp = tcg_temp_new(); | |
5361 | op2 = MASK_OP_RR_OP2(ctx->opcode); | |
5362 | ||
5363 | switch (op2) { | |
5364 | case OPC2_32_RR_AND: | |
5365 | tcg_gen_and_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5366 | break; | |
5367 | case OPC2_32_RR_ANDN: | |
5368 | tcg_gen_andc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5369 | break; | |
5370 | case OPC2_32_RR_CLO: | |
5371 | gen_helper_clo(cpu_gpr_d[r3], cpu_gpr_d[r1]); | |
5372 | break; | |
5373 | case OPC2_32_RR_CLO_H: | |
5374 | gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); | |
5375 | break; | |
5376 | case OPC2_32_RR_CLS: | |
5377 | gen_helper_cls(cpu_gpr_d[r3], cpu_gpr_d[r1]); | |
5378 | break; | |
5379 | case OPC2_32_RR_CLS_H: | |
5380 | gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); | |
5381 | break; | |
5382 | case OPC2_32_RR_CLZ: | |
5383 | gen_helper_clz(cpu_gpr_d[r3], cpu_gpr_d[r1]); | |
5384 | break; | |
5385 | case OPC2_32_RR_CLZ_H: | |
5386 | gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); | |
5387 | break; | |
5388 | case OPC2_32_RR_NAND: | |
5389 | tcg_gen_nand_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5390 | break; | |
5391 | case OPC2_32_RR_NOR: | |
5392 | tcg_gen_nor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5393 | break; | |
5394 | case OPC2_32_RR_OR: | |
5395 | tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5396 | break; | |
5397 | case OPC2_32_RR_ORN: | |
5398 | tcg_gen_orc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5399 | break; | |
5400 | case OPC2_32_RR_SH: | |
5401 | gen_helper_sh(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5402 | break; | |
5403 | case OPC2_32_RR_SH_H: | |
5404 | gen_helper_sh_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5405 | break; | |
5406 | case OPC2_32_RR_SHA: | |
5407 | gen_helper_sha(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5408 | break; | |
5409 | case OPC2_32_RR_SHA_H: | |
5410 | gen_helper_sha_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5411 | break; | |
5412 | case OPC2_32_RR_SHAS: | |
5413 | gen_shas(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5414 | break; | |
5415 | case OPC2_32_RR_XNOR: | |
5416 | tcg_gen_eqv_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5417 | break; | |
5418 | case OPC2_32_RR_XOR: | |
5419 | tcg_gen_xor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5420 | break; | |
5421 | } | |
5422 | tcg_temp_free(temp); | |
5423 | } | |
5424 | ||
f2f1585f BK |
5425 | static void decode_rr_address(CPUTriCoreState *env, DisasContext *ctx) |
5426 | { | |
5427 | uint32_t op2, n; | |
5428 | int r1, r2, r3; | |
5429 | TCGv temp; | |
5430 | ||
5431 | op2 = MASK_OP_RR_OP2(ctx->opcode); | |
5432 | r3 = MASK_OP_RR_D(ctx->opcode); | |
5433 | r2 = MASK_OP_RR_S2(ctx->opcode); | |
5434 | r1 = MASK_OP_RR_S1(ctx->opcode); | |
5435 | n = MASK_OP_RR_N(ctx->opcode); | |
5436 | ||
5437 | switch (op2) { | |
5438 | case OPC2_32_RR_ADD_A: | |
5439 | tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]); | |
5440 | break; | |
5441 | case OPC2_32_RR_ADDSC_A: | |
5442 | temp = tcg_temp_new(); | |
5443 | tcg_gen_shli_tl(temp, cpu_gpr_d[r1], n); | |
5444 | tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r2], temp); | |
5445 | tcg_temp_free(temp); | |
5446 | break; | |
5447 | case OPC2_32_RR_ADDSC_AT: | |
5448 | temp = tcg_temp_new(); | |
5449 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 3); | |
5450 | tcg_gen_add_tl(temp, cpu_gpr_a[r2], temp); | |
5451 | tcg_gen_andi_tl(cpu_gpr_a[r3], temp, 0xFFFFFFFC); | |
5452 | tcg_temp_free(temp); | |
5453 | break; | |
5454 | case OPC2_32_RR_EQ_A: | |
5455 | tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], | |
5456 | cpu_gpr_a[r2]); | |
5457 | break; | |
5458 | case OPC2_32_RR_EQZ: | |
5459 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 0); | |
5460 | break; | |
5461 | case OPC2_32_RR_GE_A: | |
5462 | tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_a[r1], | |
5463 | cpu_gpr_a[r2]); | |
5464 | break; | |
5465 | case OPC2_32_RR_LT_A: | |
5466 | tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_a[r1], | |
5467 | cpu_gpr_a[r2]); | |
5468 | break; | |
5469 | case OPC2_32_RR_MOV_A: | |
5470 | tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_d[r2]); | |
5471 | break; | |
5472 | case OPC2_32_RR_MOV_AA: | |
5473 | tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_a[r2]); | |
5474 | break; | |
5475 | case OPC2_32_RR_MOV_D: | |
5476 | tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_a[r2]); | |
5477 | break; | |
5478 | case OPC2_32_RR_NE_A: | |
5479 | tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], | |
5480 | cpu_gpr_a[r2]); | |
5481 | break; | |
5482 | case OPC2_32_RR_NEZ_A: | |
5483 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 0); | |
5484 | break; | |
5485 | case OPC2_32_RR_SUB_A: | |
5486 | tcg_gen_sub_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]); | |
5487 | break; | |
5488 | } | |
5489 | } | |
5490 | ||
5491 | static void decode_rr_idirect(CPUTriCoreState *env, DisasContext *ctx) | |
5492 | { | |
5493 | uint32_t op2; | |
5494 | int r1; | |
5495 | ||
5496 | op2 = MASK_OP_RR_OP2(ctx->opcode); | |
5497 | r1 = MASK_OP_RR_S1(ctx->opcode); | |
5498 | ||
5499 | switch (op2) { | |
5500 | case OPC2_32_RR_JI: | |
5501 | tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); | |
5502 | break; | |
5503 | case OPC2_32_RR_JLI: | |
5504 | tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); | |
5505 | tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); | |
5506 | break; | |
5507 | case OPC2_32_RR_CALLI: | |
5508 | gen_helper_1arg(call, ctx->next_pc); | |
5509 | tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); | |
5510 | break; | |
5511 | } | |
5512 | tcg_gen_exit_tb(0); | |
5513 | ctx->bstate = BS_BRANCH; | |
5514 | } | |
5515 | ||
e2bed107 BK |
5516 | static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) |
5517 | { | |
5518 | uint32_t op2; | |
5519 | int r1, r2, r3; | |
5520 | ||
5521 | TCGv temp, temp2; | |
5522 | ||
5523 | op2 = MASK_OP_RR_OP2(ctx->opcode); | |
5524 | r3 = MASK_OP_RR_D(ctx->opcode); | |
5525 | r2 = MASK_OP_RR_S2(ctx->opcode); | |
5526 | r1 = MASK_OP_RR_S1(ctx->opcode); | |
5527 | ||
5528 | switch (op2) { | |
5529 | case OPC2_32_RR_BMERGE: | |
5530 | gen_helper_bmerge(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5531 | break; | |
5532 | case OPC2_32_RR_BSPLIT: | |
5533 | gen_bsplit(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]); | |
5534 | break; | |
5535 | case OPC2_32_RR_DVINIT_B: | |
5536 | gen_dvinit_b(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], | |
5537 | cpu_gpr_d[r2]); | |
5538 | break; | |
5539 | case OPC2_32_RR_DVINIT_BU: | |
5540 | temp = tcg_temp_new(); | |
5541 | temp2 = tcg_temp_new(); | |
5542 | /* reset av */ | |
5543 | tcg_gen_movi_tl(cpu_PSW_AV, 0); | |
5544 | if (!tricore_feature(env, TRICORE_FEATURE_131)) { | |
5545 | /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */ | |
5546 | tcg_gen_neg_tl(temp, cpu_gpr_d[r3+1]); | |
5547 | /* use cpu_PSW_AV to compare against 0 */ | |
5548 | tcg_gen_movcond_tl(TCG_COND_LT, temp, cpu_gpr_d[r3+1], cpu_PSW_AV, | |
5549 | temp, cpu_gpr_d[r3+1]); | |
5550 | tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]); | |
5551 | tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV, | |
5552 | temp2, cpu_gpr_d[r2]); | |
5553 | tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2); | |
5554 | } else { | |
5555 | /* overflow = (D[b] == 0) */ | |
5556 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); | |
5557 | } | |
5558 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); | |
5559 | /* sv */ | |
5560 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
5561 | /* write result */ | |
5562 | tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 8); | |
5563 | tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 24); | |
5564 | tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp); | |
5565 | ||
5566 | tcg_temp_free(temp); | |
5567 | tcg_temp_free(temp2); | |
5568 | break; | |
5569 | case OPC2_32_RR_DVINIT_H: | |
5570 | gen_dvinit_h(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], | |
5571 | cpu_gpr_d[r2]); | |
5572 | break; | |
5573 | case OPC2_32_RR_DVINIT_HU: | |
5574 | temp = tcg_temp_new(); | |
5575 | temp2 = tcg_temp_new(); | |
5576 | /* reset av */ | |
5577 | tcg_gen_movi_tl(cpu_PSW_AV, 0); | |
5578 | if (!tricore_feature(env, TRICORE_FEATURE_131)) { | |
5579 | /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */ | |
5580 | tcg_gen_neg_tl(temp, cpu_gpr_d[r3+1]); | |
5581 | /* use cpu_PSW_AV to compare against 0 */ | |
5582 | tcg_gen_movcond_tl(TCG_COND_LT, temp, cpu_gpr_d[r3+1], cpu_PSW_AV, | |
5583 | temp, cpu_gpr_d[r3+1]); | |
5584 | tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]); | |
5585 | tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV, | |
5586 | temp2, cpu_gpr_d[r2]); | |
5587 | tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2); | |
5588 | } else { | |
5589 | /* overflow = (D[b] == 0) */ | |
5590 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); | |
5591 | } | |
5592 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); | |
5593 | /* sv */ | |
5594 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
5595 | /* write result */ | |
5596 | tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); | |
5597 | tcg_gen_shri_tl(cpu_gpr_d[r3+1], temp, 16); | |
5598 | tcg_gen_shli_tl(cpu_gpr_d[r3], temp, 16); | |
5599 | tcg_temp_free(temp); | |
5600 | tcg_temp_free(temp2); | |
5601 | break; | |
5602 | case OPC2_32_RR_DVINIT: | |
5603 | temp = tcg_temp_new(); | |
5604 | temp2 = tcg_temp_new(); | |
5605 | /* overflow = ((D[b] == 0) || | |
5606 | ((D[b] == 0xFFFFFFFF) && (D[a] == 0x80000000))) */ | |
5607 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp, cpu_gpr_d[r2], 0xffffffff); | |
5608 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r1], 0x80000000); | |
5609 | tcg_gen_and_tl(temp, temp, temp2); | |
5610 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r2], 0); | |
5611 | tcg_gen_or_tl(cpu_PSW_V, temp, temp2); | |
5612 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); | |
5613 | /* sv */ | |
5614 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
5615 | /* reset av */ | |
5616 | tcg_gen_movi_tl(cpu_PSW_AV, 0); | |
5617 | /* write result */ | |
5618 | tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); | |
5619 | /* sign extend to high reg */ | |
5620 | tcg_gen_sari_tl(cpu_gpr_d[r3+1], cpu_gpr_d[r1], 31); | |
5621 | tcg_temp_free(temp); | |
5622 | tcg_temp_free(temp2); | |
5623 | break; | |
5624 | case OPC2_32_RR_DVINIT_U: | |
5625 | /* overflow = (D[b] == 0) */ | |
5626 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); | |
5627 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); | |
5628 | /* sv */ | |
5629 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
5630 | /* reset av */ | |
5631 | tcg_gen_movi_tl(cpu_PSW_AV, 0); | |
5632 | /* write result */ | |
5633 | tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); | |
5634 | /* zero extend to high reg*/ | |
5635 | tcg_gen_movi_tl(cpu_gpr_d[r3+1], 0); | |
5636 | break; | |
5637 | case OPC2_32_RR_PARITY: | |
5638 | gen_helper_parity(cpu_gpr_d[r3], cpu_gpr_d[r1]); | |
5639 | break; | |
5640 | case OPC2_32_RR_UNPACK: | |
5641 | gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]); | |
5642 | break; | |
5643 | } | |
5644 | } | |
5645 | ||
9655b932 BK |
5646 | /* RR1 Format */ |
5647 | static void decode_rr1_mul(CPUTriCoreState *env, DisasContext *ctx) | |
5648 | { | |
5649 | uint32_t op2; | |
5650 | ||
5651 | int r1, r2, r3; | |
5652 | TCGv n; | |
5653 | TCGv_i64 temp64; | |
5654 | ||
5655 | r1 = MASK_OP_RR1_S1(ctx->opcode); | |
5656 | r2 = MASK_OP_RR1_S2(ctx->opcode); | |
5657 | r3 = MASK_OP_RR1_D(ctx->opcode); | |
5658 | n = tcg_const_i32(MASK_OP_RR1_N(ctx->opcode)); | |
5659 | op2 = MASK_OP_RR1_OP2(ctx->opcode); | |
5660 | ||
5661 | switch (op2) { | |
5662 | case OPC2_32_RR1_MUL_H_32_LL: | |
5663 | temp64 = tcg_temp_new_i64(); | |
5664 | GEN_HELPER_LL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); | |
5665 | tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); | |
5666 | gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); | |
5667 | tcg_temp_free_i64(temp64); | |
5668 | break; | |
5669 | case OPC2_32_RR1_MUL_H_32_LU: | |
5670 | temp64 = tcg_temp_new_i64(); | |
5671 | GEN_HELPER_LU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); | |
5672 | tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); | |
5673 | gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); | |
5674 | tcg_temp_free_i64(temp64); | |
5675 | break; | |
5676 | case OPC2_32_RR1_MUL_H_32_UL: | |
5677 | temp64 = tcg_temp_new_i64(); | |
5678 | GEN_HELPER_UL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); | |
5679 | tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); | |
5680 | gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); | |
5681 | tcg_temp_free_i64(temp64); | |
5682 | break; | |
5683 | case OPC2_32_RR1_MUL_H_32_UU: | |
5684 | temp64 = tcg_temp_new_i64(); | |
5685 | GEN_HELPER_UU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); | |
5686 | tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); | |
5687 | gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); | |
5688 | tcg_temp_free_i64(temp64); | |
5689 | break; | |
5690 | case OPC2_32_RR1_MULM_H_64_LL: | |
5691 | temp64 = tcg_temp_new_i64(); | |
5692 | GEN_HELPER_LL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); | |
5693 | tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); | |
5694 | /* reset V bit */ | |
5695 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
5696 | /* reset AV bit */ | |
5697 | tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); | |
5698 | tcg_temp_free_i64(temp64); | |
5699 | break; | |
5700 | case OPC2_32_RR1_MULM_H_64_LU: | |
5701 | temp64 = tcg_temp_new_i64(); | |
5702 | GEN_HELPER_LU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); | |
5703 | tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); | |
5704 | /* reset V bit */ | |
5705 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
5706 | /* reset AV bit */ | |
5707 | tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); | |
5708 | tcg_temp_free_i64(temp64); | |
5709 | break; | |
5710 | case OPC2_32_RR1_MULM_H_64_UL: | |
5711 | temp64 = tcg_temp_new_i64(); | |
5712 | GEN_HELPER_UL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); | |
5713 | tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); | |
5714 | /* reset V bit */ | |
5715 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
5716 | /* reset AV bit */ | |
5717 | tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); | |
5718 | tcg_temp_free_i64(temp64); | |
5719 | break; | |
5720 | case OPC2_32_RR1_MULM_H_64_UU: | |
5721 | temp64 = tcg_temp_new_i64(); | |
5722 | GEN_HELPER_UU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); | |
5723 | tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); | |
5724 | /* reset V bit */ | |
5725 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
5726 | /* reset AV bit */ | |
5727 | tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); | |
5728 | tcg_temp_free_i64(temp64); | |
5729 | ||
5730 | break; | |
5731 | case OPC2_32_RR1_MULR_H_16_LL: | |
5732 | GEN_HELPER_LL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); | |
5733 | gen_calc_usb_mulr_h(cpu_gpr_d[r3]); | |
5734 | break; | |
5735 | case OPC2_32_RR1_MULR_H_16_LU: | |
5736 | GEN_HELPER_LU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); | |
5737 | gen_calc_usb_mulr_h(cpu_gpr_d[r3]); | |
5738 | break; | |
5739 | case OPC2_32_RR1_MULR_H_16_UL: | |
5740 | GEN_HELPER_UL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); | |
5741 | gen_calc_usb_mulr_h(cpu_gpr_d[r3]); | |
5742 | break; | |
5743 | case OPC2_32_RR1_MULR_H_16_UU: | |
5744 | GEN_HELPER_UU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); | |
5745 | gen_calc_usb_mulr_h(cpu_gpr_d[r3]); | |
5746 | break; | |
5747 | } | |
5748 | tcg_temp_free(n); | |
5749 | } | |
5750 | ||
f1cc6eaf BK |
5751 | static void decode_rr1_mulq(CPUTriCoreState *env, DisasContext *ctx) |
5752 | { | |
5753 | uint32_t op2; | |
5754 | int r1, r2, r3; | |
5755 | uint32_t n; | |
5756 | ||
5757 | TCGv temp, temp2; | |
5758 | ||
5759 | r1 = MASK_OP_RR1_S1(ctx->opcode); | |
5760 | r2 = MASK_OP_RR1_S2(ctx->opcode); | |
5761 | r3 = MASK_OP_RR1_D(ctx->opcode); | |
5762 | n = MASK_OP_RR1_N(ctx->opcode); | |
5763 | op2 = MASK_OP_RR1_OP2(ctx->opcode); | |
5764 | ||
5765 | temp = tcg_temp_new(); | |
5766 | temp2 = tcg_temp_new(); | |
5767 | ||
5768 | switch (op2) { | |
5769 | case OPC2_32_RR1_MUL_Q_32: | |
5770 | gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2], n, 32); | |
5771 | break; | |
5772 | case OPC2_32_RR1_MUL_Q_64: | |
5773 | gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
5774 | n, 0); | |
5775 | break; | |
5776 | case OPC2_32_RR1_MUL_Q_32_L: | |
5777 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); | |
5778 | gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16); | |
5779 | break; | |
5780 | case OPC2_32_RR1_MUL_Q_64_L: | |
5781 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); | |
5782 | gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0); | |
5783 | break; | |
5784 | case OPC2_32_RR1_MUL_Q_32_U: | |
5785 | tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); | |
5786 | gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16); | |
5787 | break; | |
5788 | case OPC2_32_RR1_MUL_Q_64_U: | |
5789 | tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); | |
5790 | gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0); | |
5791 | break; | |
5792 | case OPC2_32_RR1_MUL_Q_32_LL: | |
5793 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); | |
5794 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
5795 | gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n); | |
5796 | break; | |
5797 | case OPC2_32_RR1_MUL_Q_32_UU: | |
5798 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); | |
5799 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
5800 | gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n); | |
5801 | break; | |
5802 | case OPC2_32_RR1_MULR_Q_32_L: | |
5803 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); | |
5804 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
5805 | gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n); | |
5806 | break; | |
5807 | case OPC2_32_RR1_MULR_Q_32_U: | |
5808 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); | |
5809 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
5810 | gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n); | |
5811 | break; | |
5812 | } | |
5813 | tcg_temp_free(temp); | |
5814 | tcg_temp_free(temp2); | |
5815 | } | |
5816 | ||
12f323e6 BK |
5817 | /* RR2 format */ |
5818 | static void decode_rr2_mul(CPUTriCoreState *env, DisasContext *ctx) | |
5819 | { | |
5820 | uint32_t op2; | |
5821 | int r1, r2, r3; | |
5822 | ||
5823 | op2 = MASK_OP_RR2_OP2(ctx->opcode); | |
5824 | r1 = MASK_OP_RR2_S1(ctx->opcode); | |
5825 | r2 = MASK_OP_RR2_S2(ctx->opcode); | |
5826 | r3 = MASK_OP_RR2_D(ctx->opcode); | |
5827 | switch (op2) { | |
5828 | case OPC2_32_RR2_MUL_32: | |
5829 | gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5830 | break; | |
5831 | case OPC2_32_RR2_MUL_64: | |
5832 | gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], | |
5833 | cpu_gpr_d[r2]); | |
5834 | break; | |
5835 | case OPC2_32_RR2_MULS_32: | |
5836 | gen_helper_mul_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], | |
5837 | cpu_gpr_d[r2]); | |
5838 | break; | |
5839 | case OPC2_32_RR2_MUL_U_64: | |
5840 | gen_mul_i64u(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], | |
5841 | cpu_gpr_d[r2]); | |
5842 | break; | |
5843 | case OPC2_32_RR2_MULS_U_32: | |
5844 | gen_helper_mul_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], | |
5845 | cpu_gpr_d[r2]); | |
5846 | break; | |
5847 | } | |
5848 | } | |
5849 | ||
8fb9d0eb BK |
5850 | /* RRPW format */ |
5851 | static void decode_rrpw_extract_insert(CPUTriCoreState *env, DisasContext *ctx) | |
5852 | { | |
5853 | uint32_t op2; | |
5854 | int r1, r2, r3; | |
5855 | int32_t pos, width; | |
5856 | ||
5857 | op2 = MASK_OP_RRPW_OP2(ctx->opcode); | |
5858 | r1 = MASK_OP_RRPW_S1(ctx->opcode); | |
5859 | r2 = MASK_OP_RRPW_S2(ctx->opcode); | |
5860 | r3 = MASK_OP_RRPW_D(ctx->opcode); | |
5861 | pos = MASK_OP_RRPW_POS(ctx->opcode); | |
5862 | width = MASK_OP_RRPW_WIDTH(ctx->opcode); | |
5863 | ||
5864 | switch (op2) { | |
5865 | case OPC2_32_RRPW_EXTR: | |
5866 | if (pos + width <= 31) { | |
5867 | /* optimize special cases */ | |
5868 | if ((pos == 0) && (width == 8)) { | |
5869 | tcg_gen_ext8s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); | |
5870 | } else if ((pos == 0) && (width == 16)) { | |
5871 | tcg_gen_ext16s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); | |
5872 | } else { | |
5873 | tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 32 - pos - width); | |
5874 | tcg_gen_sari_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 32 - width); | |
5875 | } | |
5876 | } | |
5877 | break; | |
5878 | case OPC2_32_RRPW_EXTR_U: | |
5879 | if (width == 0) { | |
5880 | tcg_gen_movi_tl(cpu_gpr_d[r3], 0); | |
5881 | } else { | |
5882 | tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos); | |
5883 | tcg_gen_andi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], ~0u >> (32-width)); | |
5884 | } | |
5885 | break; | |
5886 | case OPC2_32_RRPW_IMASK: | |
5887 | if (pos + width <= 31) { | |
5888 | tcg_gen_movi_tl(cpu_gpr_d[r3+1], ((1u << width) - 1) << pos); | |
5889 | tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos); | |
5890 | } | |
5891 | break; | |
5892 | case OPC2_32_RRPW_INSERT: | |
5893 | if (pos + width <= 31) { | |
5894 | tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
5895 | width, pos); | |
5896 | } | |
5897 | break; | |
5898 | } | |
5899 | } | |
5900 | ||
09532255 BK |
5901 | /* RRR format */ |
5902 | static void decode_rrr_cond_select(CPUTriCoreState *env, DisasContext *ctx) | |
5903 | { | |
5904 | uint32_t op2; | |
5905 | int r1, r2, r3, r4; | |
5906 | TCGv temp; | |
5907 | ||
5908 | op2 = MASK_OP_RRR_OP2(ctx->opcode); | |
5909 | r1 = MASK_OP_RRR_S1(ctx->opcode); | |
5910 | r2 = MASK_OP_RRR_S2(ctx->opcode); | |
5911 | r3 = MASK_OP_RRR_S3(ctx->opcode); | |
5912 | r4 = MASK_OP_RRR_D(ctx->opcode); | |
5913 | ||
5914 | switch (op2) { | |
5915 | case OPC2_32_RRR_CADD: | |
5916 | gen_cond_add(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
5917 | cpu_gpr_d[r4], cpu_gpr_d[r3]); | |
5918 | break; | |
5919 | case OPC2_32_RRR_CADDN: | |
5920 | gen_cond_add(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], | |
5921 | cpu_gpr_d[r3]); | |
5922 | break; | |
5923 | case OPC2_32_RRR_CSUB: | |
5924 | gen_cond_sub(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], | |
5925 | cpu_gpr_d[r3]); | |
5926 | break; | |
5927 | case OPC2_32_RRR_CSUBN: | |
5928 | gen_cond_sub(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], | |
5929 | cpu_gpr_d[r3]); | |
5930 | break; | |
5931 | case OPC2_32_RRR_SEL: | |
5932 | temp = tcg_const_i32(0); | |
5933 | tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, | |
5934 | cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5935 | tcg_temp_free(temp); | |
5936 | break; | |
5937 | case OPC2_32_RRR_SELN: | |
5938 | temp = tcg_const_i32(0); | |
5939 | tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, | |
5940 | cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5941 | tcg_temp_free(temp); | |
5942 | break; | |
5943 | } | |
5944 | } | |
5945 | ||
5946 | static void decode_rrr_divide(CPUTriCoreState *env, DisasContext *ctx) | |
5947 | { | |
5948 | uint32_t op2; | |
5949 | ||
5950 | int r1, r2, r3, r4; | |
5951 | ||
5952 | op2 = MASK_OP_RRR_OP2(ctx->opcode); | |
5953 | r1 = MASK_OP_RRR_S1(ctx->opcode); | |
5954 | r2 = MASK_OP_RRR_S2(ctx->opcode); | |
5955 | r3 = MASK_OP_RRR_S3(ctx->opcode); | |
5956 | r4 = MASK_OP_RRR_D(ctx->opcode); | |
5957 | ||
5958 | switch (op2) { | |
5959 | case OPC2_32_RRR_DVADJ: | |
5960 | GEN_HELPER_RRR(dvadj, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
5961 | cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
5962 | break; | |
5963 | case OPC2_32_RRR_DVSTEP: | |
5964 | GEN_HELPER_RRR(dvstep, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
5965 | cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
5966 | break; | |
5967 | case OPC2_32_RRR_DVSTEP_U: | |
5968 | GEN_HELPER_RRR(dvstep_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
5969 | cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
5970 | break; | |
5971 | case OPC2_32_RRR_IXMAX: | |
5972 | GEN_HELPER_RRR(ixmax, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
5973 | cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
5974 | break; | |
5975 | case OPC2_32_RRR_IXMAX_U: | |
5976 | GEN_HELPER_RRR(ixmax_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
5977 | cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
5978 | break; | |
5979 | case OPC2_32_RRR_IXMIN: | |
5980 | GEN_HELPER_RRR(ixmin, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
5981 | cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
5982 | break; | |
5983 | case OPC2_32_RRR_IXMIN_U: | |
5984 | GEN_HELPER_RRR(ixmin_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
5985 | cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
5986 | break; | |
5987 | case OPC2_32_RRR_PACK: | |
5988 | gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3], | |
5989 | cpu_gpr_d[r3+1], cpu_gpr_d[r1]); | |
5990 | break; | |
5991 | } | |
5992 | } | |
5993 | ||
2984cfbd BK |
5994 | /* RRR2 format */ |
5995 | static void decode_rrr2_madd(CPUTriCoreState *env, DisasContext *ctx) | |
5996 | { | |
5997 | uint32_t op2; | |
5998 | uint32_t r1, r2, r3, r4; | |
5999 | ||
6000 | op2 = MASK_OP_RRR2_OP2(ctx->opcode); | |
6001 | r1 = MASK_OP_RRR2_S1(ctx->opcode); | |
6002 | r2 = MASK_OP_RRR2_S2(ctx->opcode); | |
6003 | r3 = MASK_OP_RRR2_S3(ctx->opcode); | |
6004 | r4 = MASK_OP_RRR2_D(ctx->opcode); | |
6005 | switch (op2) { | |
6006 | case OPC2_32_RRR2_MADD_32: | |
6007 | gen_madd32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], | |
6008 | cpu_gpr_d[r2]); | |
6009 | break; | |
6010 | case OPC2_32_RRR2_MADD_64: | |
6011 | gen_madd64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], | |
6012 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
6013 | break; | |
6014 | case OPC2_32_RRR2_MADDS_32: | |
6015 | gen_helper_madd32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], | |
6016 | cpu_gpr_d[r3], cpu_gpr_d[r2]); | |
6017 | break; | |
6018 | case OPC2_32_RRR2_MADDS_64: | |
6019 | gen_madds_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], | |
6020 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
6021 | break; | |
6022 | case OPC2_32_RRR2_MADD_U_64: | |
6023 | gen_maddu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], | |
6024 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
6025 | break; | |
6026 | case OPC2_32_RRR2_MADDS_U_32: | |
6027 | gen_helper_madd32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], | |
6028 | cpu_gpr_d[r3], cpu_gpr_d[r2]); | |
6029 | break; | |
6030 | case OPC2_32_RRR2_MADDS_U_64: | |
6031 | gen_maddsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], | |
6032 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
6033 | break; | |
6034 | } | |
6035 | } | |
6036 | ||
6037 | static void decode_rrr2_msub(CPUTriCoreState *env, DisasContext *ctx) | |
6038 | { | |
6039 | uint32_t op2; | |
6040 | uint32_t r1, r2, r3, r4; | |
6041 | ||
6042 | op2 = MASK_OP_RRR2_OP2(ctx->opcode); | |
6043 | r1 = MASK_OP_RRR2_S1(ctx->opcode); | |
6044 | r2 = MASK_OP_RRR2_S2(ctx->opcode); | |
6045 | r3 = MASK_OP_RRR2_S3(ctx->opcode); | |
6046 | r4 = MASK_OP_RRR2_D(ctx->opcode); | |
6047 | ||
6048 | switch (op2) { | |
6049 | case OPC2_32_RRR2_MSUB_32: | |
6050 | gen_msub32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], | |
6051 | cpu_gpr_d[r2]); | |
6052 | break; | |
6053 | case OPC2_32_RRR2_MSUB_64: | |
6054 | gen_msub64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], | |
6055 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
6056 | break; | |
6057 | case OPC2_32_RRR2_MSUBS_32: | |
6058 | gen_helper_msub32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], | |
6059 | cpu_gpr_d[r3], cpu_gpr_d[r2]); | |
6060 | break; | |
6061 | case OPC2_32_RRR2_MSUBS_64: | |
6062 | gen_msubs_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], | |
6063 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
6064 | break; | |
6065 | case OPC2_32_RRR2_MSUB_U_64: | |
6066 | gen_msubu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], | |
6067 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
6068 | break; | |
6069 | case OPC2_32_RRR2_MSUBS_U_32: | |
6070 | gen_helper_msub32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], | |
6071 | cpu_gpr_d[r3], cpu_gpr_d[r2]); | |
6072 | break; | |
6073 | case OPC2_32_RRR2_MSUBS_U_64: | |
6074 | gen_msubsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], | |
6075 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
6076 | break; | |
6077 | } | |
6078 | } | |
6079 | ||
2e430e1c BK |
6080 | /* RRR1 format */ |
6081 | static void decode_rrr1_madd(CPUTriCoreState *env, DisasContext *ctx) | |
6082 | { | |
6083 | uint32_t op2; | |
6084 | uint32_t r1, r2, r3, r4, n; | |
6085 | ||
6086 | op2 = MASK_OP_RRR1_OP2(ctx->opcode); | |
6087 | r1 = MASK_OP_RRR1_S1(ctx->opcode); | |
6088 | r2 = MASK_OP_RRR1_S2(ctx->opcode); | |
6089 | r3 = MASK_OP_RRR1_S3(ctx->opcode); | |
6090 | r4 = MASK_OP_RRR1_D(ctx->opcode); | |
6091 | n = MASK_OP_RRR1_N(ctx->opcode); | |
6092 | ||
6093 | switch (op2) { | |
6094 | case OPC2_32_RRR1_MADD_H_LL: | |
6095 | gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6096 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); | |
6097 | break; | |
6098 | case OPC2_32_RRR1_MADD_H_LU: | |
6099 | gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6100 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); | |
6101 | break; | |
6102 | case OPC2_32_RRR1_MADD_H_UL: | |
6103 | gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6104 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); | |
6105 | break; | |
6106 | case OPC2_32_RRR1_MADD_H_UU: | |
6107 | gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6108 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); | |
6109 | break; | |
6110 | case OPC2_32_RRR1_MADDS_H_LL: | |
6111 | gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6112 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); | |
6113 | break; | |
6114 | case OPC2_32_RRR1_MADDS_H_LU: | |
6115 | gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6116 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); | |
6117 | break; | |
6118 | case OPC2_32_RRR1_MADDS_H_UL: | |
6119 | gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6120 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); | |
6121 | break; | |
6122 | case OPC2_32_RRR1_MADDS_H_UU: | |
6123 | gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6124 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); | |
6125 | break; | |
6126 | case OPC2_32_RRR1_MADDM_H_LL: | |
6127 | gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6128 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); | |
6129 | break; | |
6130 | case OPC2_32_RRR1_MADDM_H_LU: | |
6131 | gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6132 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); | |
6133 | break; | |
6134 | case OPC2_32_RRR1_MADDM_H_UL: | |
6135 | gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6136 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); | |
6137 | break; | |
6138 | case OPC2_32_RRR1_MADDM_H_UU: | |
6139 | gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6140 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); | |
6141 | break; | |
6142 | case OPC2_32_RRR1_MADDMS_H_LL: | |
6143 | gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6144 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); | |
6145 | break; | |
6146 | case OPC2_32_RRR1_MADDMS_H_LU: | |
6147 | gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6148 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); | |
6149 | break; | |
6150 | case OPC2_32_RRR1_MADDMS_H_UL: | |
6151 | gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6152 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); | |
6153 | break; | |
6154 | case OPC2_32_RRR1_MADDMS_H_UU: | |
6155 | gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6156 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); | |
6157 | break; | |
6158 | case OPC2_32_RRR1_MADDR_H_LL: | |
6159 | gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6160 | cpu_gpr_d[r2], n, MODE_LL); | |
6161 | break; | |
6162 | case OPC2_32_RRR1_MADDR_H_LU: | |
6163 | gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6164 | cpu_gpr_d[r2], n, MODE_LU); | |
6165 | break; | |
6166 | case OPC2_32_RRR1_MADDR_H_UL: | |
6167 | gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6168 | cpu_gpr_d[r2], n, MODE_UL); | |
6169 | break; | |
6170 | case OPC2_32_RRR1_MADDR_H_UU: | |
6171 | gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6172 | cpu_gpr_d[r2], n, MODE_UU); | |
6173 | break; | |
6174 | case OPC2_32_RRR1_MADDRS_H_LL: | |
6175 | gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6176 | cpu_gpr_d[r2], n, MODE_LL); | |
6177 | break; | |
6178 | case OPC2_32_RRR1_MADDRS_H_LU: | |
6179 | gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6180 | cpu_gpr_d[r2], n, MODE_LU); | |
6181 | break; | |
6182 | case OPC2_32_RRR1_MADDRS_H_UL: | |
6183 | gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6184 | cpu_gpr_d[r2], n, MODE_UL); | |
6185 | break; | |
6186 | case OPC2_32_RRR1_MADDRS_H_UU: | |
6187 | gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6188 | cpu_gpr_d[r2], n, MODE_UU); | |
6189 | break; | |
6190 | } | |
6191 | } | |
6192 | ||
b00aa8ec BK |
6193 | static void decode_rrr1_maddq_h(CPUTriCoreState *env, DisasContext *ctx) |
6194 | { | |
6195 | uint32_t op2; | |
6196 | uint32_t r1, r2, r3, r4, n; | |
6197 | TCGv temp, temp2; | |
6198 | ||
6199 | op2 = MASK_OP_RRR1_OP2(ctx->opcode); | |
6200 | r1 = MASK_OP_RRR1_S1(ctx->opcode); | |
6201 | r2 = MASK_OP_RRR1_S2(ctx->opcode); | |
6202 | r3 = MASK_OP_RRR1_S3(ctx->opcode); | |
6203 | r4 = MASK_OP_RRR1_D(ctx->opcode); | |
6204 | n = MASK_OP_RRR1_N(ctx->opcode); | |
6205 | ||
6206 | temp = tcg_const_i32(n); | |
6207 | temp2 = tcg_temp_new(); | |
6208 | ||
6209 | switch (op2) { | |
6210 | case OPC2_32_RRR1_MADD_Q_32: | |
6211 | gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6212 | cpu_gpr_d[r2], n, 32, env); | |
6213 | break; | |
6214 | case OPC2_32_RRR1_MADD_Q_64: | |
6215 | gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6216 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
6217 | n, env); | |
6218 | break; | |
6219 | case OPC2_32_RRR1_MADD_Q_32_L: | |
6220 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); | |
6221 | gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6222 | temp, n, 16, env); | |
6223 | break; | |
6224 | case OPC2_32_RRR1_MADD_Q_64_L: | |
6225 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); | |
6226 | gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6227 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, | |
6228 | n, env); | |
6229 | break; | |
6230 | case OPC2_32_RRR1_MADD_Q_32_U: | |
6231 | tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); | |
6232 | gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6233 | temp, n, 16, env); | |
6234 | break; | |
6235 | case OPC2_32_RRR1_MADD_Q_64_U: | |
6236 | tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); | |
6237 | gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6238 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, | |
6239 | n, env); | |
6240 | break; | |
6241 | case OPC2_32_RRR1_MADD_Q_32_LL: | |
6242 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); | |
6243 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
6244 | gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
6245 | break; | |
6246 | case OPC2_32_RRR1_MADD_Q_64_LL: | |
6247 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); | |
6248 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
6249 | gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6250 | cpu_gpr_d[r3+1], temp, temp2, n); | |
6251 | break; | |
6252 | case OPC2_32_RRR1_MADD_Q_32_UU: | |
6253 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); | |
6254 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
6255 | gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
6256 | break; | |
6257 | case OPC2_32_RRR1_MADD_Q_64_UU: | |
6258 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); | |
6259 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
6260 | gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6261 | cpu_gpr_d[r3+1], temp, temp2, n); | |
6262 | break; | |
6263 | case OPC2_32_RRR1_MADDS_Q_32: | |
6264 | gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6265 | cpu_gpr_d[r2], n, 32); | |
6266 | break; | |
6267 | case OPC2_32_RRR1_MADDS_Q_64: | |
6268 | gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6269 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
6270 | n); | |
6271 | break; | |
6272 | case OPC2_32_RRR1_MADDS_Q_32_L: | |
6273 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); | |
6274 | gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6275 | temp, n, 16); | |
6276 | break; | |
6277 | case OPC2_32_RRR1_MADDS_Q_64_L: | |
6278 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); | |
6279 | gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6280 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, | |
6281 | n); | |
6282 | break; | |
6283 | case OPC2_32_RRR1_MADDS_Q_32_U: | |
6284 | tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); | |
6285 | gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6286 | temp, n, 16); | |
6287 | break; | |
6288 | case OPC2_32_RRR1_MADDS_Q_64_U: | |
6289 | tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); | |
6290 | gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6291 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, | |
6292 | n); | |
6293 | break; | |
6294 | case OPC2_32_RRR1_MADDS_Q_32_LL: | |
6295 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); | |
6296 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
6297 | gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
6298 | break; | |
6299 | case OPC2_32_RRR1_MADDS_Q_64_LL: | |
6300 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); | |
6301 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
6302 | gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6303 | cpu_gpr_d[r3+1], temp, temp2, n); | |
6304 | break; | |
6305 | case OPC2_32_RRR1_MADDS_Q_32_UU: | |
6306 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); | |
6307 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
6308 | gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
6309 | break; | |
6310 | case OPC2_32_RRR1_MADDS_Q_64_UU: | |
6311 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); | |
6312 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
6313 | gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6314 | cpu_gpr_d[r3+1], temp, temp2, n); | |
6315 | break; | |
6316 | case OPC2_32_RRR1_MADDR_H_64_UL: | |
6317 | gen_maddr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], | |
6318 | cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); | |
6319 | break; | |
6320 | case OPC2_32_RRR1_MADDRS_H_64_UL: | |
6321 | gen_maddr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], | |
6322 | cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); | |
6323 | break; | |
6324 | case OPC2_32_RRR1_MADDR_Q_32_LL: | |
6325 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); | |
6326 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
6327 | gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
6328 | break; | |
6329 | case OPC2_32_RRR1_MADDR_Q_32_UU: | |
6330 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); | |
6331 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
6332 | gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
6333 | break; | |
6334 | case OPC2_32_RRR1_MADDRS_Q_32_LL: | |
6335 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); | |
6336 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
6337 | gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
6338 | break; | |
6339 | case OPC2_32_RRR1_MADDRS_Q_32_UU: | |
6340 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); | |
6341 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
6342 | gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
6343 | break; | |
6344 | } | |
6345 | tcg_temp_free(temp); | |
6346 | tcg_temp_free(temp2); | |
6347 | } | |
6348 | ||
bebe80fc BK |
6349 | static void decode_rrr1_maddsu_h(CPUTriCoreState *env, DisasContext *ctx) |
6350 | { | |
6351 | uint32_t op2; | |
6352 | uint32_t r1, r2, r3, r4, n; | |
6353 | ||
6354 | op2 = MASK_OP_RRR1_OP2(ctx->opcode); | |
6355 | r1 = MASK_OP_RRR1_S1(ctx->opcode); | |
6356 | r2 = MASK_OP_RRR1_S2(ctx->opcode); | |
6357 | r3 = MASK_OP_RRR1_S3(ctx->opcode); | |
6358 | r4 = MASK_OP_RRR1_D(ctx->opcode); | |
6359 | n = MASK_OP_RRR1_N(ctx->opcode); | |
6360 | ||
6361 | switch (op2) { | |
6362 | case OPC2_32_RRR1_MADDSU_H_32_LL: | |
6363 | gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6364 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); | |
6365 | break; | |
6366 | case OPC2_32_RRR1_MADDSU_H_32_LU: | |
6367 | gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6368 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); | |
6369 | break; | |
6370 | case OPC2_32_RRR1_MADDSU_H_32_UL: | |
6371 | gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6372 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); | |
6373 | break; | |
6374 | case OPC2_32_RRR1_MADDSU_H_32_UU: | |
6375 | gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6376 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); | |
6377 | break; | |
6378 | case OPC2_32_RRR1_MADDSUS_H_32_LL: | |
6379 | gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6380 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
6381 | n, MODE_LL); | |
6382 | break; | |
6383 | case OPC2_32_RRR1_MADDSUS_H_32_LU: | |
6384 | gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6385 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
6386 | n, MODE_LU); | |
6387 | break; | |
6388 | case OPC2_32_RRR1_MADDSUS_H_32_UL: | |
6389 | gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6390 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
6391 | n, MODE_UL); | |
6392 | break; | |
6393 | case OPC2_32_RRR1_MADDSUS_H_32_UU: | |
6394 | gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6395 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
6396 | n, MODE_UU); | |
6397 | break; | |
6398 | case OPC2_32_RRR1_MADDSUM_H_64_LL: | |
6399 | gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6400 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
6401 | n, MODE_LL); | |
6402 | break; | |
6403 | case OPC2_32_RRR1_MADDSUM_H_64_LU: | |
6404 | gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6405 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
6406 | n, MODE_LU); | |
6407 | break; | |
6408 | case OPC2_32_RRR1_MADDSUM_H_64_UL: | |
6409 | gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6410 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
6411 | n, MODE_UL); | |
6412 | break; | |
6413 | case OPC2_32_RRR1_MADDSUM_H_64_UU: | |
6414 | gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6415 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
6416 | n, MODE_UU); | |
6417 | break; | |
6418 | case OPC2_32_RRR1_MADDSUMS_H_64_LL: | |
6419 | gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6420 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
6421 | n, MODE_LL); | |
6422 | break; | |
6423 | case OPC2_32_RRR1_MADDSUMS_H_64_LU: | |
6424 | gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6425 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
6426 | n, MODE_LU); | |
6427 | break; | |
6428 | case OPC2_32_RRR1_MADDSUMS_H_64_UL: | |
6429 | gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6430 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
6431 | n, MODE_UL); | |
6432 | break; | |
6433 | case OPC2_32_RRR1_MADDSUMS_H_64_UU: | |
6434 | gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
6435 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
6436 | n, MODE_UU); | |
6437 | break; | |
6438 | case OPC2_32_RRR1_MADDSUR_H_16_LL: | |
6439 | gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6440 | cpu_gpr_d[r2], n, MODE_LL); | |
6441 | break; | |
6442 | case OPC2_32_RRR1_MADDSUR_H_16_LU: | |
6443 | gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6444 | cpu_gpr_d[r2], n, MODE_LU); | |
6445 | break; | |
6446 | case OPC2_32_RRR1_MADDSUR_H_16_UL: | |
6447 | gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6448 | cpu_gpr_d[r2], n, MODE_UL); | |
6449 | break; | |
6450 | case OPC2_32_RRR1_MADDSUR_H_16_UU: | |
6451 | gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6452 | cpu_gpr_d[r2], n, MODE_UU); | |
6453 | break; | |
6454 | case OPC2_32_RRR1_MADDSURS_H_16_LL: | |
6455 | gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6456 | cpu_gpr_d[r2], n, MODE_LL); | |
6457 | break; | |
6458 | case OPC2_32_RRR1_MADDSURS_H_16_LU: | |
6459 | gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6460 | cpu_gpr_d[r2], n, MODE_LU); | |
6461 | break; | |
6462 | case OPC2_32_RRR1_MADDSURS_H_16_UL: | |
6463 | gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6464 | cpu_gpr_d[r2], n, MODE_UL); | |
6465 | break; | |
6466 | case OPC2_32_RRR1_MADDSURS_H_16_UU: | |
6467 | gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6468 | cpu_gpr_d[r2], n, MODE_UU); | |
6469 | break; | |
6470 | } | |
6471 | } | |
6472 | ||
0aaeb118 BK |
6473 | static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) |
6474 | { | |
59543d4e | 6475 | int op1; |
ed516260 BK |
6476 | int32_t r1, r2, r3; |
6477 | int32_t address, const16; | |
fc2ef4a3 | 6478 | int8_t b, const4; |
59543d4e | 6479 | int32_t bpos; |
ed516260 | 6480 | TCGv temp, temp2, temp3; |
59543d4e BK |
6481 | |
6482 | op1 = MASK_OP_MAJOR(ctx->opcode); | |
6483 | ||
7f13420e BK |
6484 | /* handle JNZ.T opcode only being 7 bit long */ |
6485 | if (unlikely((op1 & 0x7f) == OPCM_32_BRN_JTT)) { | |
83c1bb18 BK |
6486 | op1 = OPCM_32_BRN_JTT; |
6487 | } | |
6488 | ||
59543d4e BK |
6489 | switch (op1) { |
6490 | /* ABS-format */ | |
6491 | case OPCM_32_ABS_LDW: | |
6492 | decode_abs_ldw(env, ctx); | |
6493 | break; | |
6494 | case OPCM_32_ABS_LDB: | |
6495 | decode_abs_ldb(env, ctx); | |
6496 | break; | |
6497 | case OPCM_32_ABS_LDMST_SWAP: | |
6498 | decode_abs_ldst_swap(env, ctx); | |
6499 | break; | |
6500 | case OPCM_32_ABS_LDST_CONTEXT: | |
6501 | decode_abs_ldst_context(env, ctx); | |
6502 | break; | |
6503 | case OPCM_32_ABS_STORE: | |
6504 | decode_abs_store(env, ctx); | |
6505 | break; | |
6506 | case OPCM_32_ABS_STOREB_H: | |
6507 | decode_abs_storeb_h(env, ctx); | |
6508 | break; | |
6509 | case OPC1_32_ABS_STOREQ: | |
6510 | address = MASK_OP_ABS_OFF18(ctx->opcode); | |
6511 | r1 = MASK_OP_ABS_S1D(ctx->opcode); | |
6512 | temp = tcg_const_i32(EA_ABS_FORMAT(address)); | |
6513 | temp2 = tcg_temp_new(); | |
6514 | ||
6515 | tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16); | |
6516 | tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW); | |
6517 | ||
6518 | tcg_temp_free(temp2); | |
6519 | tcg_temp_free(temp); | |
6520 | break; | |
6521 | case OPC1_32_ABS_LD_Q: | |
6522 | address = MASK_OP_ABS_OFF18(ctx->opcode); | |
6523 | r1 = MASK_OP_ABS_S1D(ctx->opcode); | |
6524 | temp = tcg_const_i32(EA_ABS_FORMAT(address)); | |
6525 | ||
6526 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); | |
6527 | tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); | |
6528 | ||
6529 | tcg_temp_free(temp); | |
6530 | break; | |
6531 | case OPC1_32_ABS_LEA: | |
6532 | address = MASK_OP_ABS_OFF18(ctx->opcode); | |
6533 | r1 = MASK_OP_ABS_S1D(ctx->opcode); | |
6534 | tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address)); | |
6535 | break; | |
6536 | /* ABSB-format */ | |
6537 | case OPC1_32_ABSB_ST_T: | |
6538 | address = MASK_OP_ABS_OFF18(ctx->opcode); | |
6539 | b = MASK_OP_ABSB_B(ctx->opcode); | |
6540 | bpos = MASK_OP_ABSB_BPOS(ctx->opcode); | |
6541 | ||
6542 | temp = tcg_const_i32(EA_ABS_FORMAT(address)); | |
6543 | temp2 = tcg_temp_new(); | |
6544 | ||
6545 | tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB); | |
6546 | tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos)); | |
6547 | tcg_gen_ori_tl(temp2, temp2, (b << bpos)); | |
6548 | tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB); | |
6549 | ||
6550 | tcg_temp_free(temp); | |
6551 | tcg_temp_free(temp2); | |
6552 | break; | |
f718b0bb BK |
6553 | /* B-format */ |
6554 | case OPC1_32_B_CALL: | |
6555 | case OPC1_32_B_CALLA: | |
6556 | case OPC1_32_B_J: | |
6557 | case OPC1_32_B_JA: | |
6558 | case OPC1_32_B_JL: | |
6559 | case OPC1_32_B_JLA: | |
436d63ff | 6560 | address = MASK_OP_B_DISP24_SEXT(ctx->opcode); |
f718b0bb BK |
6561 | gen_compute_branch(ctx, op1, 0, 0, 0, address); |
6562 | break; | |
b74f2b5b BK |
6563 | /* Bit-format */ |
6564 | case OPCM_32_BIT_ANDACC: | |
6565 | decode_bit_andacc(env, ctx); | |
6566 | break; | |
6567 | case OPCM_32_BIT_LOGICAL_T1: | |
6568 | decode_bit_logical_t(env, ctx); | |
6569 | break; | |
6570 | case OPCM_32_BIT_INSERT: | |
6571 | decode_bit_insert(env, ctx); | |
6572 | break; | |
6573 | case OPCM_32_BIT_LOGICAL_T2: | |
6574 | decode_bit_logical_t2(env, ctx); | |
6575 | break; | |
6576 | case OPCM_32_BIT_ORAND: | |
6577 | decode_bit_orand(env, ctx); | |
6578 | break; | |
6579 | case OPCM_32_BIT_SH_LOGIC1: | |
6580 | decode_bit_sh_logic1(env, ctx); | |
6581 | break; | |
6582 | case OPCM_32_BIT_SH_LOGIC2: | |
6583 | decode_bit_sh_logic2(env, ctx); | |
6584 | break; | |
3a16ecb0 BK |
6585 | /* BO Format */ |
6586 | case OPCM_32_BO_ADDRMODE_POST_PRE_BASE: | |
6587 | decode_bo_addrmode_post_pre_base(env, ctx); | |
6588 | break; | |
6589 | case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR: | |
6590 | decode_bo_addrmode_bitreverse_circular(env, ctx); | |
6591 | break; | |
6592 | case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE: | |
6593 | decode_bo_addrmode_ld_post_pre_base(env, ctx); | |
6594 | break; | |
6595 | case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR: | |
6596 | decode_bo_addrmode_ld_bitreverse_circular(env, ctx); | |
6597 | break; | |
6598 | case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE: | |
6599 | decode_bo_addrmode_stctx_post_pre_base(env, ctx); | |
6600 | break; | |
6601 | case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR: | |
6602 | decode_bo_addrmode_ldmst_bitreverse_circular(env, ctx); | |
6603 | break; | |
3fb763cb BK |
6604 | /* BOL-format */ |
6605 | case OPC1_32_BOL_LD_A_LONGOFF: | |
af715d98 | 6606 | case OPC1_32_BOL_LD_W_LONGOFF: |
3fb763cb BK |
6607 | case OPC1_32_BOL_LEA_LONGOFF: |
6608 | case OPC1_32_BOL_ST_W_LONGOFF: | |
6609 | case OPC1_32_BOL_ST_A_LONGOFF: | |
b5fd8fa3 BK |
6610 | case OPC1_32_BOL_LD_B_LONGOFF: |
6611 | case OPC1_32_BOL_LD_BU_LONGOFF: | |
6612 | case OPC1_32_BOL_LD_H_LONGOFF: | |
6613 | case OPC1_32_BOL_LD_HU_LONGOFF: | |
6614 | case OPC1_32_BOL_ST_B_LONGOFF: | |
6615 | case OPC1_32_BOL_ST_H_LONGOFF: | |
3fb763cb BK |
6616 | decode_bol_opc(env, ctx, op1); |
6617 | break; | |
fc2ef4a3 BK |
6618 | /* BRC Format */ |
6619 | case OPCM_32_BRC_EQ_NEQ: | |
6620 | case OPCM_32_BRC_GE: | |
6621 | case OPCM_32_BRC_JLT: | |
6622 | case OPCM_32_BRC_JNE: | |
6623 | const4 = MASK_OP_BRC_CONST4_SEXT(ctx->opcode); | |
6624 | address = MASK_OP_BRC_DISP15_SEXT(ctx->opcode); | |
6625 | r1 = MASK_OP_BRC_S1(ctx->opcode); | |
6626 | gen_compute_branch(ctx, op1, r1, 0, const4, address); | |
6627 | break; | |
83c1bb18 BK |
6628 | /* BRN Format */ |
6629 | case OPCM_32_BRN_JTT: | |
6630 | address = MASK_OP_BRN_DISP15_SEXT(ctx->opcode); | |
6631 | r1 = MASK_OP_BRN_S1(ctx->opcode); | |
6632 | gen_compute_branch(ctx, op1, r1, 0, 0, address); | |
6633 | break; | |
a68e0d54 BK |
6634 | /* BRR Format */ |
6635 | case OPCM_32_BRR_EQ_NEQ: | |
6636 | case OPCM_32_BRR_ADDR_EQ_NEQ: | |
6637 | case OPCM_32_BRR_GE: | |
6638 | case OPCM_32_BRR_JLT: | |
6639 | case OPCM_32_BRR_JNE: | |
6640 | case OPCM_32_BRR_JNZ: | |
6641 | case OPCM_32_BRR_LOOP: | |
6642 | address = MASK_OP_BRR_DISP15_SEXT(ctx->opcode); | |
6643 | r2 = MASK_OP_BRR_S2(ctx->opcode); | |
6644 | r1 = MASK_OP_BRR_S1(ctx->opcode); | |
6645 | gen_compute_branch(ctx, op1, r1, r2, 0, address); | |
6646 | break; | |
0974257e BK |
6647 | /* RC Format */ |
6648 | case OPCM_32_RC_LOGICAL_SHIFT: | |
6649 | decode_rc_logical_shift(env, ctx); | |
6650 | break; | |
6651 | case OPCM_32_RC_ACCUMULATOR: | |
6652 | decode_rc_accumulator(env, ctx); | |
6653 | break; | |
6654 | case OPCM_32_RC_SERVICEROUTINE: | |
6655 | decode_rc_serviceroutine(env, ctx); | |
6656 | break; | |
6657 | case OPCM_32_RC_MUL: | |
6658 | decode_rc_mul(env, ctx); | |
6659 | break; | |
ed516260 BK |
6660 | /* RCPW Format */ |
6661 | case OPCM_32_RCPW_MASK_INSERT: | |
6662 | decode_rcpw_insert(env, ctx); | |
6663 | break; | |
6664 | /* RCRR Format */ | |
6665 | case OPC1_32_RCRR_INSERT: | |
6666 | r1 = MASK_OP_RCRR_S1(ctx->opcode); | |
6667 | r2 = MASK_OP_RCRR_S3(ctx->opcode); | |
6668 | r3 = MASK_OP_RCRR_D(ctx->opcode); | |
6669 | const16 = MASK_OP_RCRR_CONST4(ctx->opcode); | |
6670 | temp = tcg_const_i32(const16); | |
6671 | temp2 = tcg_temp_new(); /* width*/ | |
6672 | temp3 = tcg_temp_new(); /* pos */ | |
6673 | ||
6674 | tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f); | |
6675 | tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f); | |
6676 | ||
6677 | gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3); | |
6678 | ||
6679 | tcg_temp_free(temp); | |
6680 | tcg_temp_free(temp2); | |
6681 | tcg_temp_free(temp3); | |
6682 | break; | |
6683 | /* RCRW Format */ | |
6684 | case OPCM_32_RCRW_MASK_INSERT: | |
6685 | decode_rcrw_insert(env, ctx); | |
6686 | break; | |
328f1f0f BK |
6687 | /* RCR Format */ |
6688 | case OPCM_32_RCR_COND_SELECT: | |
6689 | decode_rcr_cond_select(env, ctx); | |
6690 | break; | |
6691 | case OPCM_32_RCR_MADD: | |
6692 | decode_rcr_madd(env, ctx); | |
6693 | break; | |
6694 | case OPCM_32_RCR_MSUB: | |
6695 | decode_rcr_msub(env, ctx); | |
6696 | break; | |
2b2f7d97 BK |
6697 | /* RLC Format */ |
6698 | case OPC1_32_RLC_ADDI: | |
6699 | case OPC1_32_RLC_ADDIH: | |
6700 | case OPC1_32_RLC_ADDIH_A: | |
6701 | case OPC1_32_RLC_MFCR: | |
6702 | case OPC1_32_RLC_MOV: | |
4b5b4435 | 6703 | case OPC1_32_RLC_MOV_64: |
2b2f7d97 BK |
6704 | case OPC1_32_RLC_MOV_U: |
6705 | case OPC1_32_RLC_MOV_H: | |
6706 | case OPC1_32_RLC_MOVH_A: | |
6707 | case OPC1_32_RLC_MTCR: | |
6708 | decode_rlc_opc(env, ctx, op1); | |
6709 | break; | |
d5de7839 BK |
6710 | /* RR Format */ |
6711 | case OPCM_32_RR_ACCUMULATOR: | |
6712 | decode_rr_accumulator(env, ctx); | |
6713 | break; | |
0b79a781 BK |
6714 | case OPCM_32_RR_LOGICAL_SHIFT: |
6715 | decode_rr_logical_shift(env, ctx); | |
6716 | break; | |
37097418 | 6717 | case OPCM_32_RR_ADDRESS: |
f2f1585f BK |
6718 | decode_rr_address(env, ctx); |
6719 | break; | |
6720 | case OPCM_32_RR_IDIRECT: | |
6721 | decode_rr_idirect(env, ctx); | |
6722 | break; | |
e2bed107 BK |
6723 | case OPCM_32_RR_DIVIDE: |
6724 | decode_rr_divide(env, ctx); | |
6725 | break; | |
9655b932 BK |
6726 | /* RR1 Format */ |
6727 | case OPCM_32_RR1_MUL: | |
6728 | decode_rr1_mul(env, ctx); | |
6729 | break; | |
f1cc6eaf BK |
6730 | case OPCM_32_RR1_MULQ: |
6731 | decode_rr1_mulq(env, ctx); | |
6732 | break; | |
12f323e6 BK |
6733 | /* RR2 format */ |
6734 | case OPCM_32_RR2_MUL: | |
6735 | decode_rr2_mul(env, ctx); | |
6736 | break; | |
8fb9d0eb BK |
6737 | /* RRPW format */ |
6738 | case OPCM_32_RRPW_EXTRACT_INSERT: | |
6739 | decode_rrpw_extract_insert(env, ctx); | |
6740 | break; | |
6741 | case OPC1_32_RRPW_DEXTR: | |
6742 | r1 = MASK_OP_RRPW_S1(ctx->opcode); | |
6743 | r2 = MASK_OP_RRPW_S2(ctx->opcode); | |
6744 | r3 = MASK_OP_RRPW_D(ctx->opcode); | |
6745 | const16 = MASK_OP_RRPW_POS(ctx->opcode); | |
6746 | if (r1 == r2) { | |
6747 | tcg_gen_rotli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], const16); | |
6748 | } else { | |
6749 | temp = tcg_temp_new(); | |
6750 | tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], const16); | |
6751 | tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 32 - const16); | |
6752 | tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); | |
6753 | tcg_temp_free(temp); | |
6754 | } | |
6755 | break; | |
09532255 BK |
6756 | /* RRR Format */ |
6757 | case OPCM_32_RRR_COND_SELECT: | |
6758 | decode_rrr_cond_select(env, ctx); | |
6759 | break; | |
6760 | case OPCM_32_RRR_DIVIDE: | |
6761 | decode_rrr_divide(env, ctx); | |
2984cfbd BK |
6762 | /* RRR2 Format */ |
6763 | case OPCM_32_RRR2_MADD: | |
6764 | decode_rrr2_madd(env, ctx); | |
6765 | break; | |
6766 | case OPCM_32_RRR2_MSUB: | |
6767 | decode_rrr2_msub(env, ctx); | |
6768 | break; | |
2e430e1c BK |
6769 | /* RRR1 format */ |
6770 | case OPCM_32_RRR1_MADD: | |
6771 | decode_rrr1_madd(env, ctx); | |
6772 | break; | |
b00aa8ec BK |
6773 | case OPCM_32_RRR1_MADDQ_H: |
6774 | decode_rrr1_maddq_h(env, ctx); | |
6775 | break; | |
bebe80fc BK |
6776 | case OPCM_32_RRR1_MADDSU_H: |
6777 | decode_rrr1_maddsu_h(env, ctx); | |
6778 | break; | |
59543d4e | 6779 | } |
0aaeb118 BK |
6780 | } |
6781 | ||
6782 | static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch) | |
6783 | { | |
6784 | /* 16-Bit Instruction */ | |
6785 | if ((ctx->opcode & 0x1) == 0) { | |
6786 | ctx->next_pc = ctx->pc + 2; | |
6787 | decode_16Bit_opc(env, ctx); | |
6788 | /* 32-Bit Instruction */ | |
6789 | } else { | |
6790 | ctx->next_pc = ctx->pc + 4; | |
6791 | decode_32Bit_opc(env, ctx); | |
6792 | } | |
6793 | } | |
6794 | ||
48e06fe0 BK |
6795 | static inline void |
6796 | gen_intermediate_code_internal(TriCoreCPU *cpu, struct TranslationBlock *tb, | |
6797 | int search_pc) | |
6798 | { | |
0aaeb118 BK |
6799 | CPUState *cs = CPU(cpu); |
6800 | CPUTriCoreState *env = &cpu->env; | |
6801 | DisasContext ctx; | |
6802 | target_ulong pc_start; | |
6803 | int num_insns; | |
0aaeb118 BK |
6804 | |
6805 | if (search_pc) { | |
6806 | qemu_log("search pc %d\n", search_pc); | |
6807 | } | |
6808 | ||
6809 | num_insns = 0; | |
6810 | pc_start = tb->pc; | |
0aaeb118 BK |
6811 | ctx.pc = pc_start; |
6812 | ctx.saved_pc = -1; | |
6813 | ctx.tb = tb; | |
6814 | ctx.singlestep_enabled = cs->singlestep_enabled; | |
6815 | ctx.bstate = BS_NONE; | |
6816 | ctx.mem_idx = cpu_mmu_index(env); | |
6817 | ||
6818 | tcg_clear_temp_count(); | |
cd42d5b2 | 6819 | gen_tb_start(tb); |
0aaeb118 BK |
6820 | while (ctx.bstate == BS_NONE) { |
6821 | ctx.opcode = cpu_ldl_code(env, ctx.pc); | |
6822 | decode_opc(env, &ctx, 0); | |
6823 | ||
6824 | num_insns++; | |
6825 | ||
fe700adb | 6826 | if (tcg_op_buf_full()) { |
9a31922b BK |
6827 | gen_save_pc(ctx.next_pc); |
6828 | tcg_gen_exit_tb(0); | |
0aaeb118 BK |
6829 | break; |
6830 | } | |
6831 | if (singlestep) { | |
9a31922b BK |
6832 | gen_save_pc(ctx.next_pc); |
6833 | tcg_gen_exit_tb(0); | |
0aaeb118 BK |
6834 | break; |
6835 | } | |
6836 | ctx.pc = ctx.next_pc; | |
6837 | } | |
6838 | ||
6839 | gen_tb_end(tb, num_insns); | |
0aaeb118 BK |
6840 | if (search_pc) { |
6841 | printf("done_generating search pc\n"); | |
6842 | } else { | |
6843 | tb->size = ctx.pc - pc_start; | |
6844 | tb->icount = num_insns; | |
6845 | } | |
6846 | if (tcg_check_temp_count()) { | |
6847 | printf("LEAK at %08x\n", env->PC); | |
6848 | } | |
6849 | ||
6850 | #ifdef DEBUG_DISAS | |
6851 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { | |
6852 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
6853 | log_target_disas(env, pc_start, ctx.pc - pc_start, 0); | |
6854 | qemu_log("\n"); | |
6855 | } | |
6856 | #endif | |
48e06fe0 BK |
6857 | } |
6858 | ||
6859 | void | |
6860 | gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb) | |
6861 | { | |
6862 | gen_intermediate_code_internal(tricore_env_get_cpu(env), tb, false); | |
6863 | } | |
6864 | ||
6865 | void | |
6866 | gen_intermediate_code_pc(CPUTriCoreState *env, struct TranslationBlock *tb) | |
6867 | { | |
6868 | gen_intermediate_code_internal(tricore_env_get_cpu(env), tb, true); | |
6869 | } | |
6870 | ||
6871 | void | |
6872 | restore_state_to_opc(CPUTriCoreState *env, TranslationBlock *tb, int pc_pos) | |
6873 | { | |
6874 | env->PC = tcg_ctx.gen_opc_pc[pc_pos]; | |
6875 | } | |
6876 | /* | |
6877 | * | |
6878 | * Initialization | |
6879 | * | |
6880 | */ | |
6881 | ||
6882 | void cpu_state_reset(CPUTriCoreState *env) | |
6883 | { | |
0aaeb118 BK |
6884 | /* Reset Regs to Default Value */ |
6885 | env->PSW = 0xb80; | |
6886 | } | |
6887 | ||
6888 | static void tricore_tcg_init_csfr(void) | |
6889 | { | |
6890 | cpu_PCXI = tcg_global_mem_new(TCG_AREG0, | |
6891 | offsetof(CPUTriCoreState, PCXI), "PCXI"); | |
6892 | cpu_PSW = tcg_global_mem_new(TCG_AREG0, | |
6893 | offsetof(CPUTriCoreState, PSW), "PSW"); | |
6894 | cpu_PC = tcg_global_mem_new(TCG_AREG0, | |
6895 | offsetof(CPUTriCoreState, PC), "PC"); | |
6896 | cpu_ICR = tcg_global_mem_new(TCG_AREG0, | |
6897 | offsetof(CPUTriCoreState, ICR), "ICR"); | |
48e06fe0 BK |
6898 | } |
6899 | ||
6900 | void tricore_tcg_init(void) | |
6901 | { | |
0aaeb118 BK |
6902 | int i; |
6903 | static int inited; | |
6904 | if (inited) { | |
6905 | return; | |
6906 | } | |
6907 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); | |
6908 | /* reg init */ | |
6909 | for (i = 0 ; i < 16 ; i++) { | |
6910 | cpu_gpr_a[i] = tcg_global_mem_new(TCG_AREG0, | |
6911 | offsetof(CPUTriCoreState, gpr_a[i]), | |
6912 | regnames_a[i]); | |
6913 | } | |
6914 | for (i = 0 ; i < 16 ; i++) { | |
6915 | cpu_gpr_d[i] = tcg_global_mem_new(TCG_AREG0, | |
6916 | offsetof(CPUTriCoreState, gpr_d[i]), | |
6917 | regnames_d[i]); | |
6918 | } | |
6919 | tricore_tcg_init_csfr(); | |
6920 | /* init PSW flag cache */ | |
6921 | cpu_PSW_C = tcg_global_mem_new(TCG_AREG0, | |
6922 | offsetof(CPUTriCoreState, PSW_USB_C), | |
6923 | "PSW_C"); | |
6924 | cpu_PSW_V = tcg_global_mem_new(TCG_AREG0, | |
6925 | offsetof(CPUTriCoreState, PSW_USB_V), | |
6926 | "PSW_V"); | |
6927 | cpu_PSW_SV = tcg_global_mem_new(TCG_AREG0, | |
6928 | offsetof(CPUTriCoreState, PSW_USB_SV), | |
6929 | "PSW_SV"); | |
6930 | cpu_PSW_AV = tcg_global_mem_new(TCG_AREG0, | |
6931 | offsetof(CPUTriCoreState, PSW_USB_AV), | |
6932 | "PSW_AV"); | |
6933 | cpu_PSW_SAV = tcg_global_mem_new(TCG_AREG0, | |
6934 | offsetof(CPUTriCoreState, PSW_USB_SAV), | |
6935 | "PSW_SAV"); | |
48e06fe0 | 6936 | } |