[mirror_qemu.git] / target-xtensa / cpu.h

/*
 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of the Open Source and Linux Lab nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef CPU_XTENSA_H
#define CPU_XTENSA_H

#define TARGET_LONG_BITS 32
#define ELF_MACHINE EM_XTENSA

#define CPUArchState struct CPUXtensaState

#include "config.h"
#include "qemu-common.h"
#include "exec/cpu-defs.h"
#include "fpu/softfloat.h"

#define TARGET_HAS_ICE 1

#define NB_MMU_MODES 4

#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#define TARGET_PAGE_BITS 12

enum {
    /* Additional instructions */
    XTENSA_OPTION_CODE_DENSITY,
    XTENSA_OPTION_LOOP,
    XTENSA_OPTION_EXTENDED_L32R,
    XTENSA_OPTION_16_BIT_IMUL,
    XTENSA_OPTION_32_BIT_IMUL,
    XTENSA_OPTION_32_BIT_IMUL_HIGH,
    XTENSA_OPTION_32_BIT_IDIV,
    XTENSA_OPTION_MAC16,
    XTENSA_OPTION_MISC_OP_NSA,
    XTENSA_OPTION_MISC_OP_MINMAX,
    XTENSA_OPTION_MISC_OP_SEXT,
    XTENSA_OPTION_MISC_OP_CLAMPS,
    XTENSA_OPTION_COPROCESSOR,
    XTENSA_OPTION_BOOLEAN,
    XTENSA_OPTION_FP_COPROCESSOR,
    XTENSA_OPTION_MP_SYNCHRO,
    XTENSA_OPTION_CONDITIONAL_STORE,
    XTENSA_OPTION_ATOMCTL,

    /* Interrupts and exceptions */
    XTENSA_OPTION_EXCEPTION,
    XTENSA_OPTION_RELOCATABLE_VECTOR,
    XTENSA_OPTION_UNALIGNED_EXCEPTION,
    XTENSA_OPTION_INTERRUPT,
    XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
    XTENSA_OPTION_TIMER_INTERRUPT,

    /* Local memory */
    XTENSA_OPTION_ICACHE,
    XTENSA_OPTION_ICACHE_TEST,
    XTENSA_OPTION_ICACHE_INDEX_LOCK,
    XTENSA_OPTION_DCACHE,
    XTENSA_OPTION_DCACHE_TEST,
    XTENSA_OPTION_DCACHE_INDEX_LOCK,
    XTENSA_OPTION_IRAM,
    XTENSA_OPTION_IROM,
    XTENSA_OPTION_DRAM,
    XTENSA_OPTION_DROM,
    XTENSA_OPTION_XLMI,
    XTENSA_OPTION_HW_ALIGNMENT,
    XTENSA_OPTION_MEMORY_ECC_PARITY,

    /* Memory protection and translation */
    XTENSA_OPTION_REGION_PROTECTION,
    XTENSA_OPTION_REGION_TRANSLATION,
    XTENSA_OPTION_MMU,
    XTENSA_OPTION_CACHEATTR,

    /* Other */
    XTENSA_OPTION_WINDOWED_REGISTER,
    XTENSA_OPTION_PROCESSOR_INTERFACE,
    XTENSA_OPTION_MISC_SR,
    XTENSA_OPTION_THREAD_POINTER,
    XTENSA_OPTION_PROCESSOR_ID,
    XTENSA_OPTION_DEBUG,
    XTENSA_OPTION_TRACE_PORT,
};

enum {
    THREADPTR = 231,
    FCR = 232,
    FSR = 233,
};

enum {
    LBEG = 0,
    LEND = 1,
    LCOUNT = 2,
    SAR = 3,
    BR = 4,
    LITBASE = 5,
    SCOMPARE1 = 12,
    ACCLO = 16,
    ACCHI = 17,
    MR = 32,
    WINDOW_BASE = 72,
    WINDOW_START = 73,
    PTEVADDR = 83,
    RASID = 90,
    ITLBCFG = 91,
    DTLBCFG = 92,
    IBREAKENABLE = 96,
    CACHEATTR = 98,
    ATOMCTL = 99,
    IBREAKA = 128,
    DBREAKA = 144,
    DBREAKC = 160,
    CONFIGID0 = 176,
    EPC1 = 177,
    DEPC = 192,
    EPS2 = 194,
    CONFIGID1 = 208,
    EXCSAVE1 = 209,
    CPENABLE = 224,
    INTSET = 226,
    INTCLEAR = 227,
    INTENABLE = 228,
    PS = 230,
    VECBASE = 231,
    EXCCAUSE = 232,
    DEBUGCAUSE = 233,
    CCOUNT = 234,
    PRID = 235,
    ICOUNT = 236,
    ICOUNTLEVEL = 237,
    EXCVADDR = 238,
    CCOMPARE = 240,
    MISC = 244,
};

#define PS_INTLEVEL 0xf
#define PS_INTLEVEL_SHIFT 0

#define PS_EXCM 0x10
#define PS_UM 0x20

#define PS_RING 0xc0
#define PS_RING_SHIFT 6

#define PS_OWB 0xf00
#define PS_OWB_SHIFT 8

#define PS_CALLINC 0x30000
#define PS_CALLINC_SHIFT 16
#define PS_CALLINC_LEN 2

#define PS_WOE 0x40000

#define DEBUGCAUSE_IC 0x1
#define DEBUGCAUSE_IB 0x2
#define DEBUGCAUSE_DB 0x4
#define DEBUGCAUSE_BI 0x8
#define DEBUGCAUSE_BN 0x10
#define DEBUGCAUSE_DI 0x20
#define DEBUGCAUSE_DBNUM 0xf00
#define DEBUGCAUSE_DBNUM_SHIFT 8

#define DBREAKC_SB 0x80000000
#define DBREAKC_LB 0x40000000
#define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB)
#define DBREAKC_MASK 0x3f

#define MAX_NAREG 64
#define MAX_NINTERRUPT 32
#define MAX_NLEVEL 6
#define MAX_NNMI 1
#define MAX_NCCOMPARE 3
#define MAX_TLB_WAY_SIZE 8
#define MAX_NDBREAK 2

#define REGION_PAGE_MASK 0xe0000000

#define PAGE_CACHE_MASK    0x700
#define PAGE_CACHE_SHIFT   8
#define PAGE_CACHE_INVALID 0x000
#define PAGE_CACHE_BYPASS  0x100
#define PAGE_CACHE_WT      0x200
#define PAGE_CACHE_WB      0x400
#define PAGE_CACHE_ISOLATE 0x600

enum {
    /* Static vectors */
    EXC_RESET,
    EXC_MEMORY_ERROR,

    /* Dynamic vectors */
    EXC_WINDOW_OVERFLOW4,
    EXC_WINDOW_UNDERFLOW4,
    EXC_WINDOW_OVERFLOW8,
    EXC_WINDOW_UNDERFLOW8,
    EXC_WINDOW_OVERFLOW12,
    EXC_WINDOW_UNDERFLOW12,
    EXC_IRQ,
    EXC_KERNEL,
    EXC_USER,
    EXC_DOUBLE,
    EXC_DEBUG,
    EXC_MAX
};

enum {
    ILLEGAL_INSTRUCTION_CAUSE = 0,
    SYSCALL_CAUSE,
    INSTRUCTION_FETCH_ERROR_CAUSE,
    LOAD_STORE_ERROR_CAUSE,
    LEVEL1_INTERRUPT_CAUSE,
    ALLOCA_CAUSE,
    INTEGER_DIVIDE_BY_ZERO_CAUSE,
    PRIVILEGED_CAUSE = 8,
    LOAD_STORE_ALIGNMENT_CAUSE,

    INSTR_PIF_DATA_ERROR_CAUSE = 12,
    LOAD_STORE_PIF_DATA_ERROR_CAUSE,
    INSTR_PIF_ADDR_ERROR_CAUSE,
    LOAD_STORE_PIF_ADDR_ERROR_CAUSE,

    INST_TLB_MISS_CAUSE,
    INST_TLB_MULTI_HIT_CAUSE,
    INST_FETCH_PRIVILEGE_CAUSE,
    INST_FETCH_PROHIBITED_CAUSE = 20,
    LOAD_STORE_TLB_MISS_CAUSE = 24,
    LOAD_STORE_TLB_MULTI_HIT_CAUSE,
    LOAD_STORE_PRIVILEGE_CAUSE,
    LOAD_PROHIBITED_CAUSE = 28,
    STORE_PROHIBITED_CAUSE,

    COPROCESSOR0_DISABLED = 32,
};

typedef enum {
    INTTYPE_LEVEL,
    INTTYPE_EDGE,
    INTTYPE_NMI,
    INTTYPE_SOFTWARE,
    INTTYPE_TIMER,
    INTTYPE_DEBUG,
    INTTYPE_WRITE_ERR,
    INTTYPE_MAX
} interrupt_type;

typedef struct xtensa_tlb_entry {
    uint32_t vaddr;
    uint32_t paddr;
    uint8_t asid;
    uint8_t attr;
    bool variable;
} xtensa_tlb_entry;

typedef struct xtensa_tlb {
    unsigned nways;
    const unsigned way_size[10];
    bool varway56;
    unsigned nrefillentries;
} xtensa_tlb;

typedef struct XtensaGdbReg {
    int targno;
    int type;
    int group;
} XtensaGdbReg;

typedef struct XtensaGdbRegmap {
    int num_regs;
    int num_core_regs;
    /* PC + a + ar + sr + ur */
    XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
} XtensaGdbRegmap;

typedef struct XtensaConfig {
    const char *name;
    uint64_t options;
    XtensaGdbRegmap gdb_regmap;
    unsigned nareg;
    int excm_level;
    int ndepc;
    uint32_t vecbase;
    uint32_t exception_vector[EXC_MAX];
    unsigned ninterrupt;
    unsigned nlevel;
    uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
    uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
    uint32_t inttype_mask[INTTYPE_MAX];
    struct {
        uint32_t level;
        interrupt_type inttype;
    } interrupt[MAX_NINTERRUPT];
    unsigned nccompare;
    uint32_t timerint[MAX_NCCOMPARE];
    unsigned nextint;
    unsigned extint[MAX_NINTERRUPT];

    unsigned debug_level;
    unsigned nibreak;
    unsigned ndbreak;

    uint32_t configid[2];

    uint32_t clock_freq_khz;

    xtensa_tlb itlb;
    xtensa_tlb dtlb;
} XtensaConfig;

typedef struct XtensaConfigList {
    const XtensaConfig *config;
    struct XtensaConfigList *next;
} XtensaConfigList;

typedef struct CPUXtensaState {
    const XtensaConfig *config;
    uint32_t regs[16];
    uint32_t pc;
    uint32_t sregs[256];
    uint32_t uregs[256];
    uint32_t phys_regs[MAX_NAREG];
    float32 fregs[16];
    float_status fp_status;

    xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
    xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
    unsigned autorefill_idx;

    int pending_irq_level; /* level of last raised IRQ */
    void **irq_inputs;
    QEMUTimer *ccompare_timer;
    uint32_t wake_ccount;
    int64_t halt_clock;

    int exception_taken;

    /* Watchpoints for DBREAK registers */
    CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];

    CPU_COMMON
} CPUXtensaState;

#include "cpu-qom.h"

#define cpu_exec cpu_xtensa_exec
#define cpu_gen_code cpu_xtensa_gen_code
#define cpu_signal_handler cpu_xtensa_signal_handler
#define cpu_list xtensa_cpu_list

#ifdef TARGET_WORDS_BIGENDIAN
#define XTENSA_DEFAULT_CPU_MODEL "fsf"
#else
#define XTENSA_DEFAULT_CPU_MODEL "dc232b"
#endif

XtensaCPU *cpu_xtensa_init(const char *cpu_model);

static inline CPUXtensaState *cpu_init(const char *cpu_model)
{
    XtensaCPU *cpu = cpu_xtensa_init(cpu_model);
    if (cpu == NULL) {
        return NULL;
    }
    return &cpu->env;
}

void xtensa_translate_init(void);
void xtensa_breakpoint_handler(CPUXtensaState *env);
int cpu_xtensa_exec(CPUXtensaState *s);
void xtensa_register_core(XtensaConfigList *node);
void check_interrupts(CPUXtensaState *s);
void xtensa_irq_init(CPUXtensaState *env);
void *xtensa_get_extint(CPUXtensaState *env, unsigned extint);
void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d);
void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active);
void xtensa_rearm_ccompare_timer(CPUXtensaState *env);
int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);
void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
void xtensa_sync_window_from_phys(CPUXtensaState *env);
void xtensa_sync_phys_from_window(CPUXtensaState *env);
uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way);
void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
        uint32_t *vpn, uint32_t wi, uint32_t *ei);
int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
        uint32_t *pwi, uint32_t *pei, uint8_t *pring);
void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
        xtensa_tlb_entry *entry, bool dtlb,
        unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
        unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
        uint32_t vaddr, int is_write, int mmu_idx,
        uint32_t *paddr, uint32_t *page_size, unsigned *access);
void reset_mmu(CPUXtensaState *env);
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env);
void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);


#define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
#define XTENSA_OPTION_ALL (~(uint64_t)0)

static inline bool xtensa_option_bits_enabled(const XtensaConfig *config,
        uint64_t opt)
{
    return (config->options & opt) != 0;
}

static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
{
    return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
}

static inline int xtensa_get_cintlevel(const CPUXtensaState *env)
{
    int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
    if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
        level = env->config->excm_level;
    }
    return level;
}

static inline int xtensa_get_ring(const CPUXtensaState *env)
{
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
        return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
    } else {
        return 0;
    }
}

static inline int xtensa_get_cring(const CPUXtensaState *env)
{
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
            (env->sregs[PS] & PS_EXCM) == 0) {
        return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
    } else {
        return 0;
    }
}

static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env,
        bool dtlb, unsigned wi, unsigned ei)
{
    return dtlb ?
        env->dtlb[wi] + ei :
        env->itlb[wi] + ei;
}

/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _ring0
#define MMU_MODE1_SUFFIX _ring1
#define MMU_MODE2_SUFFIX _ring2
#define MMU_MODE3_SUFFIX _ring3

static inline int cpu_mmu_index(CPUXtensaState *env)
{
    return xtensa_get_cring(env);
}

#define XTENSA_TBFLAG_RING_MASK 0x3
#define XTENSA_TBFLAG_EXCM 0x4
#define XTENSA_TBFLAG_LITBASE 0x8
#define XTENSA_TBFLAG_DEBUG 0x10
#define XTENSA_TBFLAG_ICOUNT 0x20
#define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
#define XTENSA_TBFLAG_CPENABLE_SHIFT 6
#define XTENSA_TBFLAG_EXCEPTION 0x4000

static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
        target_ulong *cs_base, int *flags)
{
    CPUState *cs = CPU(xtensa_env_get_cpu(env));

    *pc = env->pc;
    *cs_base = 0;
    *flags = 0;
    *flags |= xtensa_get_ring(env);
    if (env->sregs[PS] & PS_EXCM) {
        *flags |= XTENSA_TBFLAG_EXCM;
    }
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
            (env->sregs[LITBASE] & 1)) {
        *flags |= XTENSA_TBFLAG_LITBASE;
    }
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
        if (xtensa_get_cintlevel(env) < env->config->debug_level) {
            *flags |= XTENSA_TBFLAG_DEBUG;
        }
        if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
            *flags |= XTENSA_TBFLAG_ICOUNT;
        }
    }
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
        *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
    }
    if (cs->singlestep_enabled && env->exception_taken) {
        *flags |= XTENSA_TBFLAG_EXCEPTION;
    }
}

#include "exec/cpu-all.h"
#include "exec/exec-all.h"

static inline int cpu_has_work(CPUState *cpu)
{
    CPUXtensaState *env = &XTENSA_CPU(cpu)->env;

    return env->pending_irq_level;
}

#endif
Commit	Line	Data
2328826b MF	1	/*
	2	* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
	3	* All rights reserved.
	4	*
	5	* Redistribution and use in source and binary forms, with or without
	6	* modification, are permitted provided that the following conditions are met:
	7	* * Redistributions of source code must retain the above copyright
	8	* notice, this list of conditions and the following disclaimer.
	9	* * Redistributions in binary form must reproduce the above copyright
	10	* notice, this list of conditions and the following disclaimer in the
	11	* documentation and/or other materials provided with the distribution.
	12	* * Neither the name of the Open Source and Linux Lab nor the
	13	* names of its contributors may be used to endorse or promote products
	14	* derived from this software without specific prior written permission.
	15	*
	16	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	17	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	18	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	19	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
	20	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	21	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	22	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	23	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	24	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	25	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	26	*/
	27
	28	#ifndef CPU_XTENSA_H
	29	#define CPU_XTENSA_H
	30
	31	#define TARGET_LONG_BITS 32
	32	#define ELF_MACHINE EM_XTENSA
	33
9349b4f9	34	#define CPUArchState struct CPUXtensaState
2328826b MF	35
	36	#include "config.h"
	37	#include "qemu-common.h"
022c62cb	38	#include "exec/cpu-defs.h"
dd519cbe	39	#include "fpu/softfloat.h"
2328826b MF	40
	41	#define TARGET_HAS_ICE 1
	42
	43	#define NB_MMU_MODES 4
	44
	45	#define TARGET_PHYS_ADDR_SPACE_BITS 32
	46	#define TARGET_VIRT_ADDR_SPACE_BITS 32
	47	#define TARGET_PAGE_BITS 12
	48
dedc5eae MF	49	enum {
	50	/* Additional instructions */
	51	XTENSA_OPTION_CODE_DENSITY,
	52	XTENSA_OPTION_LOOP,
	53	XTENSA_OPTION_EXTENDED_L32R,
	54	XTENSA_OPTION_16_BIT_IMUL,
	55	XTENSA_OPTION_32_BIT_IMUL,
7f65f4b0	56	XTENSA_OPTION_32_BIT_IMUL_HIGH,
dedc5eae MF	57	XTENSA_OPTION_32_BIT_IDIV,
dedc5eae MF	58	XTENSA_OPTION_MAC16,
7f65f4b0 MF	59	XTENSA_OPTION_MISC_OP_NSA,
	60	XTENSA_OPTION_MISC_OP_MINMAX,
	61	XTENSA_OPTION_MISC_OP_SEXT,
	62	XTENSA_OPTION_MISC_OP_CLAMPS,
dedc5eae MF	63	XTENSA_OPTION_COPROCESSOR,
	64	XTENSA_OPTION_BOOLEAN,
	65	XTENSA_OPTION_FP_COPROCESSOR,
	66	XTENSA_OPTION_MP_SYNCHRO,
	67	XTENSA_OPTION_CONDITIONAL_STORE,
fcc803d1	68	XTENSA_OPTION_ATOMCTL,
dedc5eae MF	69
	70	/* Interrupts and exceptions */
	71	XTENSA_OPTION_EXCEPTION,
	72	XTENSA_OPTION_RELOCATABLE_VECTOR,
	73	XTENSA_OPTION_UNALIGNED_EXCEPTION,
	74	XTENSA_OPTION_INTERRUPT,
	75	XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
	76	XTENSA_OPTION_TIMER_INTERRUPT,
	77
	78	/* Local memory */
	79	XTENSA_OPTION_ICACHE,
	80	XTENSA_OPTION_ICACHE_TEST,
	81	XTENSA_OPTION_ICACHE_INDEX_LOCK,
	82	XTENSA_OPTION_DCACHE,
	83	XTENSA_OPTION_DCACHE_TEST,
	84	XTENSA_OPTION_DCACHE_INDEX_LOCK,
	85	XTENSA_OPTION_IRAM,
	86	XTENSA_OPTION_IROM,
	87	XTENSA_OPTION_DRAM,
	88	XTENSA_OPTION_DROM,
	89	XTENSA_OPTION_XLMI,
	90	XTENSA_OPTION_HW_ALIGNMENT,
	91	XTENSA_OPTION_MEMORY_ECC_PARITY,
	92
	93	/* Memory protection and translation */
	94	XTENSA_OPTION_REGION_PROTECTION,
	95	XTENSA_OPTION_REGION_TRANSLATION,
	96	XTENSA_OPTION_MMU,
4e41d2f5	97	XTENSA_OPTION_CACHEATTR,
dedc5eae MF	98
	99	/* Other */
	100	XTENSA_OPTION_WINDOWED_REGISTER,
	101	XTENSA_OPTION_PROCESSOR_INTERFACE,
	102	XTENSA_OPTION_MISC_SR,
	103	XTENSA_OPTION_THREAD_POINTER,
	104	XTENSA_OPTION_PROCESSOR_ID,
	105	XTENSA_OPTION_DEBUG,
	106	XTENSA_OPTION_TRACE_PORT,
	107	};
	108
2af3da91 MF	109	enum {
	110	THREADPTR = 231,
	111	FCR = 232,
	112	FSR = 233,
	113	};
	114
3580ecad	115	enum {
797d780b MF	116	LBEG = 0,
	117	LEND = 1,
	118	LCOUNT = 2,
3580ecad	119	SAR = 3,
4dd85b6b	120	BR = 4,
6ad6dbf7	121	LITBASE = 5,
809377aa	122	SCOMPARE1 = 12,
6825b6c3 MF	123	ACCLO = 16,
	124	ACCHI = 17,
	125	MR = 32,
553e44f9 MF	126	WINDOW_BASE = 72,
553e44f9 MF	127	WINDOW_START = 73,
b67ea0cd MF	128	PTEVADDR = 83,
	129	RASID = 90,
	130	ITLBCFG = 91,
	131	DTLBCFG = 92,
e61dc8f7	132	IBREAKENABLE = 96,
4e41d2f5	133	CACHEATTR = 98,
fcc803d1	134	ATOMCTL = 99,
e61dc8f7	135	IBREAKA = 128,
f14c4b5f MF	136	DBREAKA = 144,
f14c4b5f MF	137	DBREAKC = 160,
604e1f9c	138	CONFIGID0 = 176,
40643d7c MF	139	EPC1 = 177,
40643d7c MF	140	DEPC = 192,
b994e91b	141	EPS2 = 194,
604e1f9c	142	CONFIGID1 = 208,
40643d7c	143	EXCSAVE1 = 209,
f3df4c04	144	CPENABLE = 224,
b994e91b MF	145	INTSET = 226,
	146	INTCLEAR = 227,
	147	INTENABLE = 228,
f0a548b9	148	PS = 230,
97836cee	149	VECBASE = 231,
40643d7c	150	EXCCAUSE = 232,
ab58c5b4	151	DEBUGCAUSE = 233,
b994e91b	152	CCOUNT = 234,
f3df4c04	153	PRID = 235,
35b5c044 MF	154	ICOUNT = 236,
35b5c044 MF	155	ICOUNTLEVEL = 237,
40643d7c	156	EXCVADDR = 238,
b994e91b	157	CCOMPARE = 240,
b7909d81	158	MISC = 244,
3580ecad MF	159	};
3580ecad MF	160
f0a548b9 MF	161	#define PS_INTLEVEL 0xf
	162	#define PS_INTLEVEL_SHIFT 0
	163
	164	#define PS_EXCM 0x10
	165	#define PS_UM 0x20
	166
	167	#define PS_RING 0xc0
	168	#define PS_RING_SHIFT 6
	169
	170	#define PS_OWB 0xf00
	171	#define PS_OWB_SHIFT 8
	172
	173	#define PS_CALLINC 0x30000
	174	#define PS_CALLINC_SHIFT 16
	175	#define PS_CALLINC_LEN 2
	176
	177	#define PS_WOE 0x40000
	178
ab58c5b4 MF	179	#define DEBUGCAUSE_IC 0x1
	180	#define DEBUGCAUSE_IB 0x2
	181	#define DEBUGCAUSE_DB 0x4
	182	#define DEBUGCAUSE_BI 0x8
	183	#define DEBUGCAUSE_BN 0x10
	184	#define DEBUGCAUSE_DI 0x20
	185	#define DEBUGCAUSE_DBNUM 0xf00
	186	#define DEBUGCAUSE_DBNUM_SHIFT 8
	187
f14c4b5f MF	188	#define DBREAKC_SB 0x80000000
	189	#define DBREAKC_LB 0x40000000
	190	#define DBREAKC_SB_LB (DBREAKC_SB \| DBREAKC_LB)
	191	#define DBREAKC_MASK 0x3f
	192
553e44f9	193	#define MAX_NAREG 64
b994e91b MF	194	#define MAX_NINTERRUPT 32
	195	#define MAX_NLEVEL 6
	196	#define MAX_NNMI 1
	197	#define MAX_NCCOMPARE 3
b67ea0cd	198	#define MAX_TLB_WAY_SIZE 8
f14c4b5f	199	#define MAX_NDBREAK 2
b67ea0cd MF	200
b67ea0cd MF	201	#define REGION_PAGE_MASK 0xe0000000
553e44f9	202
fcc803d1 MF	203	#define PAGE_CACHE_MASK 0x700
	204	#define PAGE_CACHE_SHIFT 8
	205	#define PAGE_CACHE_INVALID 0x000
	206	#define PAGE_CACHE_BYPASS 0x100
	207	#define PAGE_CACHE_WT 0x200
	208	#define PAGE_CACHE_WB 0x400
	209	#define PAGE_CACHE_ISOLATE 0x600
	210
40643d7c MF	211	enum {
	212	/* Static vectors */
	213	EXC_RESET,
	214	EXC_MEMORY_ERROR,
	215
	216	/* Dynamic vectors */
	217	EXC_WINDOW_OVERFLOW4,
	218	EXC_WINDOW_UNDERFLOW4,
	219	EXC_WINDOW_OVERFLOW8,
	220	EXC_WINDOW_UNDERFLOW8,
	221	EXC_WINDOW_OVERFLOW12,
	222	EXC_WINDOW_UNDERFLOW12,
	223	EXC_IRQ,
	224	EXC_KERNEL,
	225	EXC_USER,
	226	EXC_DOUBLE,
e61dc8f7	227	EXC_DEBUG,
40643d7c MF	228	EXC_MAX
	229	};
	230
	231	enum {
	232	ILLEGAL_INSTRUCTION_CAUSE = 0,
	233	SYSCALL_CAUSE,
	234	INSTRUCTION_FETCH_ERROR_CAUSE,
	235	LOAD_STORE_ERROR_CAUSE,
	236	LEVEL1_INTERRUPT_CAUSE,
	237	ALLOCA_CAUSE,
	238	INTEGER_DIVIDE_BY_ZERO_CAUSE,
	239	PRIVILEGED_CAUSE = 8,
	240	LOAD_STORE_ALIGNMENT_CAUSE,
	241
	242	INSTR_PIF_DATA_ERROR_CAUSE = 12,
	243	LOAD_STORE_PIF_DATA_ERROR_CAUSE,
	244	INSTR_PIF_ADDR_ERROR_CAUSE,
	245	LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
	246
	247	INST_TLB_MISS_CAUSE,
	248	INST_TLB_MULTI_HIT_CAUSE,
	249	INST_FETCH_PRIVILEGE_CAUSE,
	250	INST_FETCH_PROHIBITED_CAUSE = 20,
	251	LOAD_STORE_TLB_MISS_CAUSE = 24,
	252	LOAD_STORE_TLB_MULTI_HIT_CAUSE,
	253	LOAD_STORE_PRIVILEGE_CAUSE,
	254	LOAD_PROHIBITED_CAUSE = 28,
	255	STORE_PROHIBITED_CAUSE,
	256
	257	COPROCESSOR0_DISABLED = 32,
	258	};
	259
b994e91b MF	260	typedef enum {
	261	INTTYPE_LEVEL,
	262	INTTYPE_EDGE,
	263	INTTYPE_NMI,
	264	INTTYPE_SOFTWARE,
	265	INTTYPE_TIMER,
	266	INTTYPE_DEBUG,
	267	INTTYPE_WRITE_ERR,
	268	INTTYPE_MAX
	269	} interrupt_type;
	270
b67ea0cd MF	271	typedef struct xtensa_tlb_entry {
	272	uint32_t vaddr;
	273	uint32_t paddr;
	274	uint8_t asid;
	275	uint8_t attr;
	276	bool variable;
	277	} xtensa_tlb_entry;
	278
	279	typedef struct xtensa_tlb {
	280	unsigned nways;
	281	const unsigned way_size[10];
	282	bool varway56;
	283	unsigned nrefillentries;
	284	} xtensa_tlb;
	285
ccfcaba6 MF	286	typedef struct XtensaGdbReg {
	287	int targno;
	288	int type;
	289	int group;
	290	} XtensaGdbReg;
	291
	292	typedef struct XtensaGdbRegmap {
	293	int num_regs;
	294	int num_core_regs;
	295	/* PC + a + ar + sr + ur */
	296	XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
	297	} XtensaGdbRegmap;
	298
dedc5eae MF	299	typedef struct XtensaConfig {
	300	const char *name;
	301	uint64_t options;
ccfcaba6	302	XtensaGdbRegmap gdb_regmap;
553e44f9	303	unsigned nareg;
40643d7c MF	304	int excm_level;
40643d7c MF	305	int ndepc;
97836cee	306	uint32_t vecbase;
40643d7c	307	uint32_t exception_vector[EXC_MAX];
b994e91b MF	308	unsigned ninterrupt;
	309	unsigned nlevel;
	310	uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
	311	uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
	312	uint32_t inttype_mask[INTTYPE_MAX];
	313	struct {
	314	uint32_t level;
	315	interrupt_type inttype;
	316	} interrupt[MAX_NINTERRUPT];
	317	unsigned nccompare;
	318	uint32_t timerint[MAX_NCCOMPARE];
b8929a54 MF	319	unsigned nextint;
b8929a54 MF	320	unsigned extint[MAX_NINTERRUPT];
ab58c5b4 MF	321
	322	unsigned debug_level;
	323	unsigned nibreak;
	324	unsigned ndbreak;
	325
604e1f9c MF	326	uint32_t configid[2];
604e1f9c MF	327
b994e91b	328	uint32_t clock_freq_khz;
b67ea0cd MF	329
	330	xtensa_tlb itlb;
	331	xtensa_tlb dtlb;
dedc5eae MF	332	} XtensaConfig;
dedc5eae MF	333
ac8b7db4 MF	334	typedef struct XtensaConfigList {
	335	const XtensaConfig *config;
	336	struct XtensaConfigList *next;
	337	} XtensaConfigList;
	338
2328826b	339	typedef struct CPUXtensaState {
dedc5eae	340	const XtensaConfig *config;
2328826b MF	341	uint32_t regs[16];
	342	uint32_t pc;
	343	uint32_t sregs[256];
2af3da91	344	uint32_t uregs[256];
553e44f9	345	uint32_t phys_regs[MAX_NAREG];
dd519cbe MF	346	float32 fregs[16];
dd519cbe MF	347	float_status fp_status;
2328826b	348
b67ea0cd MF	349	xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
	350	xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
	351	unsigned autorefill_idx;
	352
b994e91b MF	353	int pending_irq_level; /* level of last raised IRQ */
	354	void **irq_inputs;
	355	QEMUTimer *ccompare_timer;
	356	uint32_t wake_ccount;
	357	int64_t halt_clock;
	358
40643d7c MF	359	int exception_taken;
40643d7c MF	360
f14c4b5f MF	361	/* Watchpoints for DBREAK registers */
	362	CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
	363
2328826b MF	364	CPU_COMMON
	365	} CPUXtensaState;
	366
15be3171 AF	367	#include "cpu-qom.h"
15be3171 AF	368
2328826b MF	369	#define cpu_exec cpu_xtensa_exec
	370	#define cpu_gen_code cpu_xtensa_gen_code
	371	#define cpu_signal_handler cpu_xtensa_signal_handler
	372	#define cpu_list xtensa_cpu_list
	373
e38077ff MF	374	#ifdef TARGET_WORDS_BIGENDIAN
	375	#define XTENSA_DEFAULT_CPU_MODEL "fsf"
	376	#else
	377	#define XTENSA_DEFAULT_CPU_MODEL "dc232b"
	378	#endif
	379
15be3171 AF	380	XtensaCPU cpu_xtensa_init(const char cpu_model);
	381
	382	static inline CPUXtensaState cpu_init(const char cpu_model)
	383	{
	384	XtensaCPU *cpu = cpu_xtensa_init(cpu_model);
	385	if (cpu == NULL) {
	386	return NULL;
	387	}
	388	return &cpu->env;
	389	}
	390
2328826b	391	void xtensa_translate_init(void);
25733ead	392	void xtensa_breakpoint_handler(CPUXtensaState *env);
2328826b	393	int cpu_xtensa_exec(CPUXtensaState *s);
ac8b7db4	394	void xtensa_register_core(XtensaConfigList *node);
b994e91b	395	void check_interrupts(CPUXtensaState *s);
97129ac8 AF	396	void xtensa_irq_init(CPUXtensaState *env);
	397	void xtensa_get_extint(CPUXtensaState env, unsigned extint);
	398	void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d);
	399	void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active);
	400	void xtensa_rearm_ccompare_timer(CPUXtensaState *env);
2328826b MF	401	int cpu_xtensa_signal_handler(int host_signum, void pinfo, void puc);
2328826b MF	402	void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
97129ac8 AF	403	void xtensa_sync_window_from_phys(CPUXtensaState *env);
	404	void xtensa_sync_phys_from_window(CPUXtensaState *env);
	405	uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way);
	406	void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
b67ea0cd	407	uint32_t vpn, uint32_t wi, uint32_t ei);
97129ac8	408	int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
b67ea0cd	409	uint32_t pwi, uint32_t pei, uint8_t *pring);
16bde77a MF	410	void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
	411	xtensa_tlb_entry *entry, bool dtlb,
	412	unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
97129ac8	413	void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
b67ea0cd	414	unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
ae4e7982	415	int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
b67ea0cd MF	416	uint32_t vaddr, int is_write, int mmu_idx,
b67ea0cd MF	417	uint32_t paddr, uint32_t page_size, unsigned *access);
5087a72c	418	void reset_mmu(CPUXtensaState *env);
97129ac8 AF	419	void dump_mmu(FILE f, fprintf_function cpu_fprintf, CPUXtensaState env);
97129ac8 AF	420	void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);
b67ea0cd	421
2328826b	422
dedc5eae	423	#define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
fe0bd475	424	#define XTENSA_OPTION_ALL (~(uint64_t)0)
dedc5eae	425
b67ea0cd MF	426	static inline bool xtensa_option_bits_enabled(const XtensaConfig *config,
	427	uint64_t opt)
	428	{
	429	return (config->options & opt) != 0;
	430	}
	431
dedc5eae MF	432	static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
dedc5eae MF	433	{
b67ea0cd	434	return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
dedc5eae MF	435	}
dedc5eae MF	436
97129ac8	437	static inline int xtensa_get_cintlevel(const CPUXtensaState *env)
40643d7c MF	438	{
	439	int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
	440	if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
	441	level = env->config->excm_level;
	442	}
	443	return level;
	444	}
	445
97129ac8	446	static inline int xtensa_get_ring(const CPUXtensaState *env)
f0a548b9 MF	447	{
	448	if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
	449	return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
	450	} else {
	451	return 0;
	452	}
	453	}
	454
97129ac8	455	static inline int xtensa_get_cring(const CPUXtensaState *env)
f0a548b9 MF	456	{
	457	if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
	458	(env->sregs[PS] & PS_EXCM) == 0) {
	459	return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
	460	} else {
	461	return 0;
	462	}
	463	}
	464
97129ac8	465	static inline xtensa_tlb_entry xtensa_tlb_get_entry(CPUXtensaState env,
b67ea0cd MF	466	bool dtlb, unsigned wi, unsigned ei)
	467	{
	468	return dtlb ?
	469	env->dtlb[wi] + ei :
	470	env->itlb[wi] + ei;
	471	}
	472
f0a548b9 MF	473	/* MMU modes definitions */
	474	#define MMU_MODE0_SUFFIX _ring0
	475	#define MMU_MODE1_SUFFIX _ring1
	476	#define MMU_MODE2_SUFFIX _ring2
	477	#define MMU_MODE3_SUFFIX _ring3
	478
97129ac8	479	static inline int cpu_mmu_index(CPUXtensaState *env)
2328826b	480	{
f0a548b9	481	return xtensa_get_cring(env);
2328826b MF	482	}
2328826b MF	483
f0a548b9 MF	484	#define XTENSA_TBFLAG_RING_MASK 0x3
f0a548b9 MF	485	#define XTENSA_TBFLAG_EXCM 0x4
6ad6dbf7	486	#define XTENSA_TBFLAG_LITBASE 0x8
e61dc8f7	487	#define XTENSA_TBFLAG_DEBUG 0x10
35b5c044	488	#define XTENSA_TBFLAG_ICOUNT 0x20
ef04a846 MF	489	#define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
ef04a846 MF	490	#define XTENSA_TBFLAG_CPENABLE_SHIFT 6
a00817cc	491	#define XTENSA_TBFLAG_EXCEPTION 0x4000
f0a548b9	492
97129ac8	493	static inline void cpu_get_tb_cpu_state(CPUXtensaState env, target_ulong pc,
2328826b MF	494	target_ulong cs_base, int flags)
2328826b MF	495	{
1cf5ccbc AF	496	CPUState *cs = CPU(xtensa_env_get_cpu(env));
1cf5ccbc AF	497
2328826b MF	498	*pc = env->pc;
	499	*cs_base = 0;
	500	*flags = 0;
f0a548b9 MF	501	*flags \|= xtensa_get_ring(env);
	502	if (env->sregs[PS] & PS_EXCM) {
	503	*flags \|= XTENSA_TBFLAG_EXCM;
	504	}
6ad6dbf7 MF	505	if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
	506	(env->sregs[LITBASE] & 1)) {
	507	*flags \|= XTENSA_TBFLAG_LITBASE;
	508	}
e61dc8f7 MF	509	if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
	510	if (xtensa_get_cintlevel(env) < env->config->debug_level) {
	511	*flags \|= XTENSA_TBFLAG_DEBUG;
	512	}
35b5c044 MF	513	if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
	514	*flags \|= XTENSA_TBFLAG_ICOUNT;
	515	}
e61dc8f7	516	}
ef04a846 MF	517	if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
	518	*flags \|= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
	519	}
1cf5ccbc	520	if (cs->singlestep_enabled && env->exception_taken) {
a00817cc MF	521	*flags \|= XTENSA_TBFLAG_EXCEPTION;
a00817cc MF	522	}
2328826b MF	523	}
2328826b MF	524
022c62cb PB	525	#include "exec/cpu-all.h"
022c62cb PB	526	#include "exec/exec-all.h"
2328826b	527
3993c6bd	528	static inline int cpu_has_work(CPUState *cpu)
2328826b	529	{
3993c6bd AF	530	CPUXtensaState *env = &XTENSA_CPU(cpu)->env;
3993c6bd AF	531
b994e91b	532	return env->pending_irq_level;
2328826b MF	533	}
2328826b MF	534
2328826b	535	#endif