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2328826b MF |
1 | /* |
2 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. | |
3 | * All rights reserved. | |
4 | * | |
5 | * Redistribution and use in source and binary forms, with or without | |
6 | * modification, are permitted provided that the following conditions are met: | |
7 | * * Redistributions of source code must retain the above copyright | |
8 | * notice, this list of conditions and the following disclaimer. | |
9 | * * Redistributions in binary form must reproduce the above copyright | |
10 | * notice, this list of conditions and the following disclaimer in the | |
11 | * documentation and/or other materials provided with the distribution. | |
12 | * * Neither the name of the Open Source and Linux Lab nor the | |
13 | * names of its contributors may be used to endorse or promote products | |
14 | * derived from this software without specific prior written permission. | |
15 | * | |
16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
20 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
21 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
22 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
23 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
25 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
26 | */ | |
27 | ||
28 | #ifndef CPU_XTENSA_H | |
29 | #define CPU_XTENSA_H | |
30 | ||
31 | #define TARGET_LONG_BITS 32 | |
32 | #define ELF_MACHINE EM_XTENSA | |
33 | ||
34 | #define CPUState struct CPUXtensaState | |
35 | ||
36 | #include "config.h" | |
37 | #include "qemu-common.h" | |
38 | #include "cpu-defs.h" | |
39 | ||
40 | #define TARGET_HAS_ICE 1 | |
41 | ||
42 | #define NB_MMU_MODES 4 | |
43 | ||
44 | #define TARGET_PHYS_ADDR_SPACE_BITS 32 | |
45 | #define TARGET_VIRT_ADDR_SPACE_BITS 32 | |
46 | #define TARGET_PAGE_BITS 12 | |
47 | ||
dedc5eae MF |
48 | enum { |
49 | /* Additional instructions */ | |
50 | XTENSA_OPTION_CODE_DENSITY, | |
51 | XTENSA_OPTION_LOOP, | |
52 | XTENSA_OPTION_EXTENDED_L32R, | |
53 | XTENSA_OPTION_16_BIT_IMUL, | |
54 | XTENSA_OPTION_32_BIT_IMUL, | |
55 | XTENSA_OPTION_32_BIT_IDIV, | |
56 | XTENSA_OPTION_MAC16, | |
57 | XTENSA_OPTION_MISC_OP, | |
58 | XTENSA_OPTION_COPROCESSOR, | |
59 | XTENSA_OPTION_BOOLEAN, | |
60 | XTENSA_OPTION_FP_COPROCESSOR, | |
61 | XTENSA_OPTION_MP_SYNCHRO, | |
62 | XTENSA_OPTION_CONDITIONAL_STORE, | |
63 | ||
64 | /* Interrupts and exceptions */ | |
65 | XTENSA_OPTION_EXCEPTION, | |
66 | XTENSA_OPTION_RELOCATABLE_VECTOR, | |
67 | XTENSA_OPTION_UNALIGNED_EXCEPTION, | |
68 | XTENSA_OPTION_INTERRUPT, | |
69 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, | |
70 | XTENSA_OPTION_TIMER_INTERRUPT, | |
71 | ||
72 | /* Local memory */ | |
73 | XTENSA_OPTION_ICACHE, | |
74 | XTENSA_OPTION_ICACHE_TEST, | |
75 | XTENSA_OPTION_ICACHE_INDEX_LOCK, | |
76 | XTENSA_OPTION_DCACHE, | |
77 | XTENSA_OPTION_DCACHE_TEST, | |
78 | XTENSA_OPTION_DCACHE_INDEX_LOCK, | |
79 | XTENSA_OPTION_IRAM, | |
80 | XTENSA_OPTION_IROM, | |
81 | XTENSA_OPTION_DRAM, | |
82 | XTENSA_OPTION_DROM, | |
83 | XTENSA_OPTION_XLMI, | |
84 | XTENSA_OPTION_HW_ALIGNMENT, | |
85 | XTENSA_OPTION_MEMORY_ECC_PARITY, | |
86 | ||
87 | /* Memory protection and translation */ | |
88 | XTENSA_OPTION_REGION_PROTECTION, | |
89 | XTENSA_OPTION_REGION_TRANSLATION, | |
90 | XTENSA_OPTION_MMU, | |
91 | ||
92 | /* Other */ | |
93 | XTENSA_OPTION_WINDOWED_REGISTER, | |
94 | XTENSA_OPTION_PROCESSOR_INTERFACE, | |
95 | XTENSA_OPTION_MISC_SR, | |
96 | XTENSA_OPTION_THREAD_POINTER, | |
97 | XTENSA_OPTION_PROCESSOR_ID, | |
98 | XTENSA_OPTION_DEBUG, | |
99 | XTENSA_OPTION_TRACE_PORT, | |
100 | }; | |
101 | ||
2af3da91 MF |
102 | enum { |
103 | THREADPTR = 231, | |
104 | FCR = 232, | |
105 | FSR = 233, | |
106 | }; | |
107 | ||
3580ecad | 108 | enum { |
797d780b MF |
109 | LBEG = 0, |
110 | LEND = 1, | |
111 | LCOUNT = 2, | |
3580ecad | 112 | SAR = 3, |
4dd85b6b | 113 | BR = 4, |
6ad6dbf7 | 114 | LITBASE = 5, |
809377aa | 115 | SCOMPARE1 = 12, |
6825b6c3 MF |
116 | ACCLO = 16, |
117 | ACCHI = 17, | |
118 | MR = 32, | |
553e44f9 MF |
119 | WINDOW_BASE = 72, |
120 | WINDOW_START = 73, | |
b67ea0cd MF |
121 | PTEVADDR = 83, |
122 | RASID = 90, | |
123 | ITLBCFG = 91, | |
124 | DTLBCFG = 92, | |
40643d7c MF |
125 | EPC1 = 177, |
126 | DEPC = 192, | |
b994e91b | 127 | EPS2 = 194, |
40643d7c | 128 | EXCSAVE1 = 209, |
f3df4c04 | 129 | CPENABLE = 224, |
b994e91b MF |
130 | INTSET = 226, |
131 | INTCLEAR = 227, | |
132 | INTENABLE = 228, | |
f0a548b9 | 133 | PS = 230, |
97836cee | 134 | VECBASE = 231, |
40643d7c | 135 | EXCCAUSE = 232, |
b994e91b | 136 | CCOUNT = 234, |
f3df4c04 | 137 | PRID = 235, |
40643d7c | 138 | EXCVADDR = 238, |
b994e91b | 139 | CCOMPARE = 240, |
3580ecad MF |
140 | }; |
141 | ||
f0a548b9 MF |
142 | #define PS_INTLEVEL 0xf |
143 | #define PS_INTLEVEL_SHIFT 0 | |
144 | ||
145 | #define PS_EXCM 0x10 | |
146 | #define PS_UM 0x20 | |
147 | ||
148 | #define PS_RING 0xc0 | |
149 | #define PS_RING_SHIFT 6 | |
150 | ||
151 | #define PS_OWB 0xf00 | |
152 | #define PS_OWB_SHIFT 8 | |
153 | ||
154 | #define PS_CALLINC 0x30000 | |
155 | #define PS_CALLINC_SHIFT 16 | |
156 | #define PS_CALLINC_LEN 2 | |
157 | ||
158 | #define PS_WOE 0x40000 | |
159 | ||
553e44f9 | 160 | #define MAX_NAREG 64 |
b994e91b MF |
161 | #define MAX_NINTERRUPT 32 |
162 | #define MAX_NLEVEL 6 | |
163 | #define MAX_NNMI 1 | |
164 | #define MAX_NCCOMPARE 3 | |
b67ea0cd MF |
165 | #define MAX_TLB_WAY_SIZE 8 |
166 | ||
167 | #define REGION_PAGE_MASK 0xe0000000 | |
553e44f9 | 168 | |
40643d7c MF |
169 | enum { |
170 | /* Static vectors */ | |
171 | EXC_RESET, | |
172 | EXC_MEMORY_ERROR, | |
173 | ||
174 | /* Dynamic vectors */ | |
175 | EXC_WINDOW_OVERFLOW4, | |
176 | EXC_WINDOW_UNDERFLOW4, | |
177 | EXC_WINDOW_OVERFLOW8, | |
178 | EXC_WINDOW_UNDERFLOW8, | |
179 | EXC_WINDOW_OVERFLOW12, | |
180 | EXC_WINDOW_UNDERFLOW12, | |
181 | EXC_IRQ, | |
182 | EXC_KERNEL, | |
183 | EXC_USER, | |
184 | EXC_DOUBLE, | |
185 | EXC_MAX | |
186 | }; | |
187 | ||
188 | enum { | |
189 | ILLEGAL_INSTRUCTION_CAUSE = 0, | |
190 | SYSCALL_CAUSE, | |
191 | INSTRUCTION_FETCH_ERROR_CAUSE, | |
192 | LOAD_STORE_ERROR_CAUSE, | |
193 | LEVEL1_INTERRUPT_CAUSE, | |
194 | ALLOCA_CAUSE, | |
195 | INTEGER_DIVIDE_BY_ZERO_CAUSE, | |
196 | PRIVILEGED_CAUSE = 8, | |
197 | LOAD_STORE_ALIGNMENT_CAUSE, | |
198 | ||
199 | INSTR_PIF_DATA_ERROR_CAUSE = 12, | |
200 | LOAD_STORE_PIF_DATA_ERROR_CAUSE, | |
201 | INSTR_PIF_ADDR_ERROR_CAUSE, | |
202 | LOAD_STORE_PIF_ADDR_ERROR_CAUSE, | |
203 | ||
204 | INST_TLB_MISS_CAUSE, | |
205 | INST_TLB_MULTI_HIT_CAUSE, | |
206 | INST_FETCH_PRIVILEGE_CAUSE, | |
207 | INST_FETCH_PROHIBITED_CAUSE = 20, | |
208 | LOAD_STORE_TLB_MISS_CAUSE = 24, | |
209 | LOAD_STORE_TLB_MULTI_HIT_CAUSE, | |
210 | LOAD_STORE_PRIVILEGE_CAUSE, | |
211 | LOAD_PROHIBITED_CAUSE = 28, | |
212 | STORE_PROHIBITED_CAUSE, | |
213 | ||
214 | COPROCESSOR0_DISABLED = 32, | |
215 | }; | |
216 | ||
b994e91b MF |
217 | typedef enum { |
218 | INTTYPE_LEVEL, | |
219 | INTTYPE_EDGE, | |
220 | INTTYPE_NMI, | |
221 | INTTYPE_SOFTWARE, | |
222 | INTTYPE_TIMER, | |
223 | INTTYPE_DEBUG, | |
224 | INTTYPE_WRITE_ERR, | |
225 | INTTYPE_MAX | |
226 | } interrupt_type; | |
227 | ||
b67ea0cd MF |
228 | typedef struct xtensa_tlb_entry { |
229 | uint32_t vaddr; | |
230 | uint32_t paddr; | |
231 | uint8_t asid; | |
232 | uint8_t attr; | |
233 | bool variable; | |
234 | } xtensa_tlb_entry; | |
235 | ||
236 | typedef struct xtensa_tlb { | |
237 | unsigned nways; | |
238 | const unsigned way_size[10]; | |
239 | bool varway56; | |
240 | unsigned nrefillentries; | |
241 | } xtensa_tlb; | |
242 | ||
ccfcaba6 MF |
243 | typedef struct XtensaGdbReg { |
244 | int targno; | |
245 | int type; | |
246 | int group; | |
247 | } XtensaGdbReg; | |
248 | ||
249 | typedef struct XtensaGdbRegmap { | |
250 | int num_regs; | |
251 | int num_core_regs; | |
252 | /* PC + a + ar + sr + ur */ | |
253 | XtensaGdbReg reg[1 + 16 + 64 + 256 + 256]; | |
254 | } XtensaGdbRegmap; | |
255 | ||
dedc5eae MF |
256 | typedef struct XtensaConfig { |
257 | const char *name; | |
258 | uint64_t options; | |
ccfcaba6 | 259 | XtensaGdbRegmap gdb_regmap; |
553e44f9 | 260 | unsigned nareg; |
40643d7c MF |
261 | int excm_level; |
262 | int ndepc; | |
97836cee | 263 | uint32_t vecbase; |
40643d7c | 264 | uint32_t exception_vector[EXC_MAX]; |
b994e91b MF |
265 | unsigned ninterrupt; |
266 | unsigned nlevel; | |
267 | uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1]; | |
268 | uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1]; | |
269 | uint32_t inttype_mask[INTTYPE_MAX]; | |
270 | struct { | |
271 | uint32_t level; | |
272 | interrupt_type inttype; | |
273 | } interrupt[MAX_NINTERRUPT]; | |
274 | unsigned nccompare; | |
275 | uint32_t timerint[MAX_NCCOMPARE]; | |
276 | uint32_t clock_freq_khz; | |
b67ea0cd MF |
277 | |
278 | xtensa_tlb itlb; | |
279 | xtensa_tlb dtlb; | |
dedc5eae MF |
280 | } XtensaConfig; |
281 | ||
2328826b | 282 | typedef struct CPUXtensaState { |
dedc5eae | 283 | const XtensaConfig *config; |
2328826b MF |
284 | uint32_t regs[16]; |
285 | uint32_t pc; | |
286 | uint32_t sregs[256]; | |
2af3da91 | 287 | uint32_t uregs[256]; |
553e44f9 | 288 | uint32_t phys_regs[MAX_NAREG]; |
2328826b | 289 | |
b67ea0cd MF |
290 | xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE]; |
291 | xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE]; | |
292 | unsigned autorefill_idx; | |
293 | ||
b994e91b MF |
294 | int pending_irq_level; /* level of last raised IRQ */ |
295 | void **irq_inputs; | |
296 | QEMUTimer *ccompare_timer; | |
297 | uint32_t wake_ccount; | |
298 | int64_t halt_clock; | |
299 | ||
40643d7c MF |
300 | int exception_taken; |
301 | ||
2328826b MF |
302 | CPU_COMMON |
303 | } CPUXtensaState; | |
304 | ||
305 | #define cpu_init cpu_xtensa_init | |
306 | #define cpu_exec cpu_xtensa_exec | |
307 | #define cpu_gen_code cpu_xtensa_gen_code | |
308 | #define cpu_signal_handler cpu_xtensa_signal_handler | |
309 | #define cpu_list xtensa_cpu_list | |
310 | ||
311 | CPUXtensaState *cpu_xtensa_init(const char *cpu_model); | |
312 | void xtensa_translate_init(void); | |
313 | int cpu_xtensa_exec(CPUXtensaState *s); | |
314 | void do_interrupt(CPUXtensaState *s); | |
b994e91b MF |
315 | void check_interrupts(CPUXtensaState *s); |
316 | void xtensa_irq_init(CPUState *env); | |
317 | void xtensa_advance_ccount(CPUState *env, uint32_t d); | |
318 | void xtensa_timer_irq(CPUState *env, uint32_t id, uint32_t active); | |
890c6333 | 319 | void xtensa_rearm_ccompare_timer(CPUState *env); |
2328826b MF |
320 | int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc); |
321 | void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf); | |
553e44f9 MF |
322 | void xtensa_sync_window_from_phys(CPUState *env); |
323 | void xtensa_sync_phys_from_window(CPUState *env); | |
b67ea0cd MF |
324 | uint32_t xtensa_tlb_get_addr_mask(const CPUState *env, bool dtlb, uint32_t way); |
325 | void split_tlb_entry_spec_way(const CPUState *env, uint32_t v, bool dtlb, | |
326 | uint32_t *vpn, uint32_t wi, uint32_t *ei); | |
327 | int xtensa_tlb_lookup(const CPUState *env, uint32_t addr, bool dtlb, | |
328 | uint32_t *pwi, uint32_t *pei, uint8_t *pring); | |
329 | void xtensa_tlb_set_entry(CPUState *env, bool dtlb, | |
330 | unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte); | |
331 | int xtensa_get_physical_addr(CPUState *env, | |
332 | uint32_t vaddr, int is_write, int mmu_idx, | |
333 | uint32_t *paddr, uint32_t *page_size, unsigned *access); | |
334 | ||
2328826b | 335 | |
dedc5eae MF |
336 | #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt)) |
337 | ||
b67ea0cd MF |
338 | static inline bool xtensa_option_bits_enabled(const XtensaConfig *config, |
339 | uint64_t opt) | |
340 | { | |
341 | return (config->options & opt) != 0; | |
342 | } | |
343 | ||
dedc5eae MF |
344 | static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt) |
345 | { | |
b67ea0cd | 346 | return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt)); |
dedc5eae MF |
347 | } |
348 | ||
40643d7c MF |
349 | static inline int xtensa_get_cintlevel(const CPUState *env) |
350 | { | |
351 | int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT; | |
352 | if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) { | |
353 | level = env->config->excm_level; | |
354 | } | |
355 | return level; | |
356 | } | |
357 | ||
f0a548b9 MF |
358 | static inline int xtensa_get_ring(const CPUState *env) |
359 | { | |
360 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { | |
361 | return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT; | |
362 | } else { | |
363 | return 0; | |
364 | } | |
365 | } | |
366 | ||
367 | static inline int xtensa_get_cring(const CPUState *env) | |
368 | { | |
369 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) && | |
370 | (env->sregs[PS] & PS_EXCM) == 0) { | |
371 | return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT; | |
372 | } else { | |
373 | return 0; | |
374 | } | |
375 | } | |
376 | ||
b67ea0cd MF |
377 | static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUState *env, |
378 | bool dtlb, unsigned wi, unsigned ei) | |
379 | { | |
380 | return dtlb ? | |
381 | env->dtlb[wi] + ei : | |
382 | env->itlb[wi] + ei; | |
383 | } | |
384 | ||
f0a548b9 MF |
385 | /* MMU modes definitions */ |
386 | #define MMU_MODE0_SUFFIX _ring0 | |
387 | #define MMU_MODE1_SUFFIX _ring1 | |
388 | #define MMU_MODE2_SUFFIX _ring2 | |
389 | #define MMU_MODE3_SUFFIX _ring3 | |
390 | ||
2328826b MF |
391 | static inline int cpu_mmu_index(CPUState *env) |
392 | { | |
f0a548b9 | 393 | return xtensa_get_cring(env); |
2328826b MF |
394 | } |
395 | ||
f0a548b9 MF |
396 | #define XTENSA_TBFLAG_RING_MASK 0x3 |
397 | #define XTENSA_TBFLAG_EXCM 0x4 | |
6ad6dbf7 | 398 | #define XTENSA_TBFLAG_LITBASE 0x8 |
f0a548b9 | 399 | |
2328826b MF |
400 | static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
401 | target_ulong *cs_base, int *flags) | |
402 | { | |
403 | *pc = env->pc; | |
404 | *cs_base = 0; | |
405 | *flags = 0; | |
f0a548b9 MF |
406 | *flags |= xtensa_get_ring(env); |
407 | if (env->sregs[PS] & PS_EXCM) { | |
408 | *flags |= XTENSA_TBFLAG_EXCM; | |
409 | } | |
6ad6dbf7 MF |
410 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && |
411 | (env->sregs[LITBASE] & 1)) { | |
412 | *flags |= XTENSA_TBFLAG_LITBASE; | |
413 | } | |
2328826b MF |
414 | } |
415 | ||
416 | #include "cpu-all.h" | |
417 | #include "exec-all.h" | |
418 | ||
419 | static inline int cpu_has_work(CPUState *env) | |
420 | { | |
b994e91b | 421 | return env->pending_irq_level; |
2328826b MF |
422 | } |
423 | ||
424 | static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) | |
425 | { | |
426 | env->pc = tb->pc; | |
427 | } | |
428 | ||
429 | #endif |