]>
Commit | Line | Data |
---|---|---|
2328826b MF |
1 | /* |
2 | * Xtensa ISA: | |
3 | * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm | |
4 | * | |
5 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. | |
6 | * All rights reserved. | |
7 | * | |
8 | * Redistribution and use in source and binary forms, with or without | |
9 | * modification, are permitted provided that the following conditions are met: | |
10 | * * Redistributions of source code must retain the above copyright | |
11 | * notice, this list of conditions and the following disclaimer. | |
12 | * * Redistributions in binary form must reproduce the above copyright | |
13 | * notice, this list of conditions and the following disclaimer in the | |
14 | * documentation and/or other materials provided with the distribution. | |
15 | * * Neither the name of the Open Source and Linux Lab nor the | |
16 | * names of its contributors may be used to endorse or promote products | |
17 | * derived from this software without specific prior written permission. | |
18 | * | |
19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
23 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
26 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
29 | */ | |
30 | ||
09aae23d | 31 | #include "qemu/osdep.h" |
2328826b MF |
32 | |
33 | #include "cpu.h" | |
022c62cb | 34 | #include "exec/exec-all.h" |
76cad711 | 35 | #include "disas/disas.h" |
2328826b | 36 | #include "tcg-op.h" |
1de7afc9 | 37 | #include "qemu/log.h" |
9c17d615 | 38 | #include "sysemu/sysemu.h" |
f08b6170 | 39 | #include "exec/cpu_ldst.h" |
cfe67cef | 40 | #include "exec/semihost.h" |
2328826b | 41 | |
2ef6175a RH |
42 | #include "exec/helper-proto.h" |
43 | #include "exec/helper-gen.h" | |
dedc5eae | 44 | |
a7e30d84 | 45 | #include "trace-tcg.h" |
508127e2 | 46 | #include "exec/log.h" |
a7e30d84 LV |
47 | |
48 | ||
dedc5eae MF |
49 | typedef struct DisasContext { |
50 | const XtensaConfig *config; | |
51 | TranslationBlock *tb; | |
52 | uint32_t pc; | |
53 | uint32_t next_pc; | |
f0a548b9 MF |
54 | int cring; |
55 | int ring; | |
797d780b MF |
56 | uint32_t lbeg; |
57 | uint32_t lend; | |
6ad6dbf7 | 58 | TCGv_i32 litbase; |
dedc5eae MF |
59 | int is_jmp; |
60 | int singlestep_enabled; | |
3580ecad MF |
61 | |
62 | bool sar_5bit; | |
63 | bool sar_m32_5bit; | |
64 | bool sar_m32_allocated; | |
65 | TCGv_i32 sar_m32; | |
b994e91b MF |
66 | |
67 | uint32_t ccount_delta; | |
2db59a76 | 68 | unsigned window; |
e61dc8f7 MF |
69 | |
70 | bool debug; | |
35b5c044 MF |
71 | bool icount; |
72 | TCGv_i32 next_icount; | |
ef04a846 MF |
73 | |
74 | unsigned cpenable; | |
dedc5eae MF |
75 | } DisasContext; |
76 | ||
1bcea73e | 77 | static TCGv_env cpu_env; |
dedc5eae MF |
78 | static TCGv_i32 cpu_pc; |
79 | static TCGv_i32 cpu_R[16]; | |
dd519cbe | 80 | static TCGv_i32 cpu_FR[16]; |
2af3da91 MF |
81 | static TCGv_i32 cpu_SR[256]; |
82 | static TCGv_i32 cpu_UR[256]; | |
dedc5eae | 83 | |
022c62cb | 84 | #include "exec/gen-icount.h" |
2328826b | 85 | |
fe0bd475 MF |
86 | typedef struct XtensaReg { |
87 | const char *name; | |
88 | uint64_t opt_bits; | |
53593e90 MF |
89 | enum { |
90 | SR_R = 1, | |
91 | SR_W = 2, | |
92 | SR_X = 4, | |
93 | SR_RW = 3, | |
94 | SR_RWX = 7, | |
95 | } access; | |
fe0bd475 MF |
96 | } XtensaReg; |
97 | ||
53593e90 | 98 | #define XTENSA_REG_ACCESS(regname, opt, acc) { \ |
fe0bd475 MF |
99 | .name = (regname), \ |
100 | .opt_bits = XTENSA_OPTION_BIT(opt), \ | |
53593e90 | 101 | .access = (acc), \ |
fe0bd475 MF |
102 | } |
103 | ||
53593e90 MF |
104 | #define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX) |
105 | ||
604e1f9c | 106 | #define XTENSA_REG_BITS_ACCESS(regname, opt, acc) { \ |
fe0bd475 MF |
107 | .name = (regname), \ |
108 | .opt_bits = (opt), \ | |
604e1f9c | 109 | .access = (acc), \ |
fe0bd475 MF |
110 | } |
111 | ||
604e1f9c MF |
112 | #define XTENSA_REG_BITS(regname, opt) \ |
113 | XTENSA_REG_BITS_ACCESS(regname, opt, SR_RWX) | |
114 | ||
fe0bd475 MF |
115 | static const XtensaReg sregnames[256] = { |
116 | [LBEG] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP), | |
117 | [LEND] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP), | |
118 | [LCOUNT] = XTENSA_REG("LCOUNT", XTENSA_OPTION_LOOP), | |
119 | [SAR] = XTENSA_REG_BITS("SAR", XTENSA_OPTION_ALL), | |
120 | [BR] = XTENSA_REG("BR", XTENSA_OPTION_BOOLEAN), | |
121 | [LITBASE] = XTENSA_REG("LITBASE", XTENSA_OPTION_EXTENDED_L32R), | |
122 | [SCOMPARE1] = XTENSA_REG("SCOMPARE1", XTENSA_OPTION_CONDITIONAL_STORE), | |
123 | [ACCLO] = XTENSA_REG("ACCLO", XTENSA_OPTION_MAC16), | |
124 | [ACCHI] = XTENSA_REG("ACCHI", XTENSA_OPTION_MAC16), | |
125 | [MR] = XTENSA_REG("MR0", XTENSA_OPTION_MAC16), | |
126 | [MR + 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16), | |
127 | [MR + 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16), | |
128 | [MR + 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16), | |
129 | [WINDOW_BASE] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER), | |
130 | [WINDOW_START] = XTENSA_REG("WINDOW_START", | |
131 | XTENSA_OPTION_WINDOWED_REGISTER), | |
132 | [PTEVADDR] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU), | |
133 | [RASID] = XTENSA_REG("RASID", XTENSA_OPTION_MMU), | |
134 | [ITLBCFG] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU), | |
135 | [DTLBCFG] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU), | |
136 | [IBREAKENABLE] = XTENSA_REG("IBREAKENABLE", XTENSA_OPTION_DEBUG), | |
137 | [CACHEATTR] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR), | |
138 | [ATOMCTL] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL), | |
139 | [IBREAKA] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG), | |
140 | [IBREAKA + 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG), | |
141 | [DBREAKA] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG), | |
142 | [DBREAKA + 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG), | |
143 | [DBREAKC] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG), | |
144 | [DBREAKC + 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG), | |
604e1f9c | 145 | [CONFIGID0] = XTENSA_REG_BITS_ACCESS("CONFIGID0", XTENSA_OPTION_ALL, SR_R), |
fe0bd475 MF |
146 | [EPC1] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION), |
147 | [EPC1 + 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
148 | [EPC1 + 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
149 | [EPC1 + 3] = XTENSA_REG("EPC4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
150 | [EPC1 + 4] = XTENSA_REG("EPC5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
151 | [EPC1 + 5] = XTENSA_REG("EPC6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
152 | [EPC1 + 6] = XTENSA_REG("EPC7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
153 | [DEPC] = XTENSA_REG("DEPC", XTENSA_OPTION_EXCEPTION), | |
154 | [EPS2] = XTENSA_REG("EPS2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
155 | [EPS2 + 1] = XTENSA_REG("EPS3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
156 | [EPS2 + 2] = XTENSA_REG("EPS4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
157 | [EPS2 + 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
158 | [EPS2 + 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
159 | [EPS2 + 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
604e1f9c | 160 | [CONFIGID1] = XTENSA_REG_BITS_ACCESS("CONFIGID1", XTENSA_OPTION_ALL, SR_R), |
fe0bd475 MF |
161 | [EXCSAVE1] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION), |
162 | [EXCSAVE1 + 1] = XTENSA_REG("EXCSAVE2", | |
163 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
164 | [EXCSAVE1 + 2] = XTENSA_REG("EXCSAVE3", | |
165 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
166 | [EXCSAVE1 + 3] = XTENSA_REG("EXCSAVE4", | |
167 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
168 | [EXCSAVE1 + 4] = XTENSA_REG("EXCSAVE5", | |
169 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
170 | [EXCSAVE1 + 5] = XTENSA_REG("EXCSAVE6", | |
171 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
172 | [EXCSAVE1 + 6] = XTENSA_REG("EXCSAVE7", | |
173 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
174 | [CPENABLE] = XTENSA_REG("CPENABLE", XTENSA_OPTION_COPROCESSOR), | |
53593e90 MF |
175 | [INTSET] = XTENSA_REG_ACCESS("INTSET", XTENSA_OPTION_INTERRUPT, SR_RW), |
176 | [INTCLEAR] = XTENSA_REG_ACCESS("INTCLEAR", XTENSA_OPTION_INTERRUPT, SR_W), | |
fe0bd475 MF |
177 | [INTENABLE] = XTENSA_REG("INTENABLE", XTENSA_OPTION_INTERRUPT), |
178 | [PS] = XTENSA_REG_BITS("PS", XTENSA_OPTION_ALL), | |
179 | [VECBASE] = XTENSA_REG("VECBASE", XTENSA_OPTION_RELOCATABLE_VECTOR), | |
180 | [EXCCAUSE] = XTENSA_REG("EXCCAUSE", XTENSA_OPTION_EXCEPTION), | |
53593e90 | 181 | [DEBUGCAUSE] = XTENSA_REG_ACCESS("DEBUGCAUSE", XTENSA_OPTION_DEBUG, SR_R), |
fe0bd475 | 182 | [CCOUNT] = XTENSA_REG("CCOUNT", XTENSA_OPTION_TIMER_INTERRUPT), |
53593e90 | 183 | [PRID] = XTENSA_REG_ACCESS("PRID", XTENSA_OPTION_PROCESSOR_ID, SR_R), |
fe0bd475 MF |
184 | [ICOUNT] = XTENSA_REG("ICOUNT", XTENSA_OPTION_DEBUG), |
185 | [ICOUNTLEVEL] = XTENSA_REG("ICOUNTLEVEL", XTENSA_OPTION_DEBUG), | |
186 | [EXCVADDR] = XTENSA_REG("EXCVADDR", XTENSA_OPTION_EXCEPTION), | |
187 | [CCOMPARE] = XTENSA_REG("CCOMPARE0", XTENSA_OPTION_TIMER_INTERRUPT), | |
188 | [CCOMPARE + 1] = XTENSA_REG("CCOMPARE1", | |
189 | XTENSA_OPTION_TIMER_INTERRUPT), | |
190 | [CCOMPARE + 2] = XTENSA_REG("CCOMPARE2", | |
191 | XTENSA_OPTION_TIMER_INTERRUPT), | |
b7909d81 MF |
192 | [MISC] = XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR), |
193 | [MISC + 1] = XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR), | |
194 | [MISC + 2] = XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR), | |
195 | [MISC + 3] = XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR), | |
2af3da91 MF |
196 | }; |
197 | ||
fe0bd475 MF |
198 | static const XtensaReg uregnames[256] = { |
199 | [THREADPTR] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER), | |
200 | [FCR] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR), | |
201 | [FSR] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR), | |
2af3da91 MF |
202 | }; |
203 | ||
2328826b MF |
204 | void xtensa_translate_init(void) |
205 | { | |
dedc5eae MF |
206 | static const char * const regnames[] = { |
207 | "ar0", "ar1", "ar2", "ar3", | |
208 | "ar4", "ar5", "ar6", "ar7", | |
209 | "ar8", "ar9", "ar10", "ar11", | |
210 | "ar12", "ar13", "ar14", "ar15", | |
211 | }; | |
dd519cbe MF |
212 | static const char * const fregnames[] = { |
213 | "f0", "f1", "f2", "f3", | |
214 | "f4", "f5", "f6", "f7", | |
215 | "f8", "f9", "f10", "f11", | |
216 | "f12", "f13", "f14", "f15", | |
217 | }; | |
dedc5eae MF |
218 | int i; |
219 | ||
220 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); | |
e1ccc054 | 221 | cpu_pc = tcg_global_mem_new_i32(cpu_env, |
97129ac8 | 222 | offsetof(CPUXtensaState, pc), "pc"); |
dedc5eae MF |
223 | |
224 | for (i = 0; i < 16; i++) { | |
e1ccc054 | 225 | cpu_R[i] = tcg_global_mem_new_i32(cpu_env, |
97129ac8 | 226 | offsetof(CPUXtensaState, regs[i]), |
dedc5eae MF |
227 | regnames[i]); |
228 | } | |
2af3da91 | 229 | |
dd519cbe | 230 | for (i = 0; i < 16; i++) { |
e1ccc054 | 231 | cpu_FR[i] = tcg_global_mem_new_i32(cpu_env, |
ddd44279 | 232 | offsetof(CPUXtensaState, fregs[i].f32[FP_F32_LOW]), |
dd519cbe MF |
233 | fregnames[i]); |
234 | } | |
235 | ||
2af3da91 | 236 | for (i = 0; i < 256; ++i) { |
fe0bd475 | 237 | if (sregnames[i].name) { |
e1ccc054 | 238 | cpu_SR[i] = tcg_global_mem_new_i32(cpu_env, |
97129ac8 | 239 | offsetof(CPUXtensaState, sregs[i]), |
fe0bd475 | 240 | sregnames[i].name); |
2af3da91 MF |
241 | } |
242 | } | |
243 | ||
244 | for (i = 0; i < 256; ++i) { | |
fe0bd475 | 245 | if (uregnames[i].name) { |
e1ccc054 | 246 | cpu_UR[i] = tcg_global_mem_new_i32(cpu_env, |
97129ac8 | 247 | offsetof(CPUXtensaState, uregs[i]), |
fe0bd475 | 248 | uregnames[i].name); |
2af3da91 MF |
249 | } |
250 | } | |
dedc5eae MF |
251 | } |
252 | ||
b67ea0cd MF |
253 | static inline bool option_bits_enabled(DisasContext *dc, uint64_t opt) |
254 | { | |
255 | return xtensa_option_bits_enabled(dc->config, opt); | |
256 | } | |
257 | ||
dedc5eae MF |
258 | static inline bool option_enabled(DisasContext *dc, int opt) |
259 | { | |
260 | return xtensa_option_enabled(dc->config, opt); | |
261 | } | |
262 | ||
6ad6dbf7 MF |
263 | static void init_litbase(DisasContext *dc) |
264 | { | |
265 | if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { | |
266 | dc->litbase = tcg_temp_local_new_i32(); | |
267 | tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000); | |
268 | } | |
269 | } | |
270 | ||
271 | static void reset_litbase(DisasContext *dc) | |
272 | { | |
273 | if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { | |
274 | tcg_temp_free(dc->litbase); | |
275 | } | |
276 | } | |
277 | ||
3580ecad MF |
278 | static void init_sar_tracker(DisasContext *dc) |
279 | { | |
280 | dc->sar_5bit = false; | |
281 | dc->sar_m32_5bit = false; | |
282 | dc->sar_m32_allocated = false; | |
283 | } | |
284 | ||
285 | static void reset_sar_tracker(DisasContext *dc) | |
286 | { | |
287 | if (dc->sar_m32_allocated) { | |
288 | tcg_temp_free(dc->sar_m32); | |
289 | } | |
290 | } | |
291 | ||
292 | static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa) | |
293 | { | |
294 | tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f); | |
295 | if (dc->sar_m32_5bit) { | |
296 | tcg_gen_discard_i32(dc->sar_m32); | |
297 | } | |
298 | dc->sar_5bit = true; | |
299 | dc->sar_m32_5bit = false; | |
300 | } | |
301 | ||
302 | static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa) | |
303 | { | |
304 | TCGv_i32 tmp = tcg_const_i32(32); | |
305 | if (!dc->sar_m32_allocated) { | |
306 | dc->sar_m32 = tcg_temp_local_new_i32(); | |
307 | dc->sar_m32_allocated = true; | |
308 | } | |
309 | tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f); | |
310 | tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32); | |
311 | dc->sar_5bit = false; | |
312 | dc->sar_m32_5bit = true; | |
313 | tcg_temp_free(tmp); | |
314 | } | |
315 | ||
2db59a76 | 316 | static void gen_advance_ccount(DisasContext *dc) |
b994e91b MF |
317 | { |
318 | if (dc->ccount_delta > 0) { | |
319 | TCGv_i32 tmp = tcg_const_i32(dc->ccount_delta); | |
f492b82d | 320 | gen_helper_advance_ccount(cpu_env, tmp); |
b994e91b MF |
321 | tcg_temp_free(tmp); |
322 | } | |
908c67fc MF |
323 | dc->ccount_delta = 0; |
324 | } | |
325 | ||
b994e91b | 326 | static void gen_exception(DisasContext *dc, int excp) |
dedc5eae MF |
327 | { |
328 | TCGv_i32 tmp = tcg_const_i32(excp); | |
b994e91b | 329 | gen_advance_ccount(dc); |
f492b82d | 330 | gen_helper_exception(cpu_env, tmp); |
dedc5eae MF |
331 | tcg_temp_free(tmp); |
332 | } | |
333 | ||
40643d7c MF |
334 | static void gen_exception_cause(DisasContext *dc, uint32_t cause) |
335 | { | |
336 | TCGv_i32 tpc = tcg_const_i32(dc->pc); | |
337 | TCGv_i32 tcause = tcg_const_i32(cause); | |
b994e91b | 338 | gen_advance_ccount(dc); |
f492b82d | 339 | gen_helper_exception_cause(cpu_env, tpc, tcause); |
40643d7c MF |
340 | tcg_temp_free(tpc); |
341 | tcg_temp_free(tcause); | |
6b814719 MF |
342 | if (cause == ILLEGAL_INSTRUCTION_CAUSE || |
343 | cause == SYSCALL_CAUSE) { | |
344 | dc->is_jmp = DISAS_UPDATE; | |
345 | } | |
40643d7c MF |
346 | } |
347 | ||
5b4e481b MF |
348 | static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause, |
349 | TCGv_i32 vaddr) | |
350 | { | |
351 | TCGv_i32 tpc = tcg_const_i32(dc->pc); | |
352 | TCGv_i32 tcause = tcg_const_i32(cause); | |
b994e91b | 353 | gen_advance_ccount(dc); |
f492b82d | 354 | gen_helper_exception_cause_vaddr(cpu_env, tpc, tcause, vaddr); |
5b4e481b MF |
355 | tcg_temp_free(tpc); |
356 | tcg_temp_free(tcause); | |
357 | } | |
358 | ||
e61dc8f7 MF |
359 | static void gen_debug_exception(DisasContext *dc, uint32_t cause) |
360 | { | |
361 | TCGv_i32 tpc = tcg_const_i32(dc->pc); | |
362 | TCGv_i32 tcause = tcg_const_i32(cause); | |
363 | gen_advance_ccount(dc); | |
f492b82d | 364 | gen_helper_debug_exception(cpu_env, tpc, tcause); |
e61dc8f7 MF |
365 | tcg_temp_free(tpc); |
366 | tcg_temp_free(tcause); | |
367 | if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) { | |
368 | dc->is_jmp = DISAS_UPDATE; | |
369 | } | |
370 | } | |
371 | ||
97e89ee9 | 372 | static bool gen_check_privilege(DisasContext *dc) |
40643d7c MF |
373 | { |
374 | if (dc->cring) { | |
375 | gen_exception_cause(dc, PRIVILEGED_CAUSE); | |
6b814719 | 376 | dc->is_jmp = DISAS_UPDATE; |
97e89ee9 | 377 | return false; |
40643d7c | 378 | } |
97e89ee9 | 379 | return true; |
40643d7c MF |
380 | } |
381 | ||
97e89ee9 | 382 | static bool gen_check_cpenable(DisasContext *dc, unsigned cp) |
ef04a846 MF |
383 | { |
384 | if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) && | |
385 | !(dc->cpenable & (1 << cp))) { | |
386 | gen_exception_cause(dc, COPROCESSOR0_DISABLED + cp); | |
387 | dc->is_jmp = DISAS_UPDATE; | |
97e89ee9 | 388 | return false; |
ef04a846 | 389 | } |
97e89ee9 | 390 | return true; |
ef04a846 MF |
391 | } |
392 | ||
dedc5eae MF |
393 | static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot) |
394 | { | |
395 | tcg_gen_mov_i32(cpu_pc, dest); | |
35b5c044 MF |
396 | gen_advance_ccount(dc); |
397 | if (dc->icount) { | |
398 | tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount); | |
399 | } | |
dedc5eae | 400 | if (dc->singlestep_enabled) { |
b994e91b | 401 | gen_exception(dc, EXCP_DEBUG); |
dedc5eae MF |
402 | } else { |
403 | if (slot >= 0) { | |
404 | tcg_gen_goto_tb(slot); | |
8cfd0495 | 405 | tcg_gen_exit_tb((uintptr_t)dc->tb + slot); |
dedc5eae MF |
406 | } else { |
407 | tcg_gen_exit_tb(0); | |
408 | } | |
409 | } | |
410 | dc->is_jmp = DISAS_UPDATE; | |
411 | } | |
412 | ||
67882fd1 MF |
413 | static void gen_jump(DisasContext *dc, TCGv dest) |
414 | { | |
415 | gen_jump_slot(dc, dest, -1); | |
416 | } | |
417 | ||
dedc5eae MF |
418 | static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot) |
419 | { | |
420 | TCGv_i32 tmp = tcg_const_i32(dest); | |
433d33c5 | 421 | if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) { |
dedc5eae MF |
422 | slot = -1; |
423 | } | |
424 | gen_jump_slot(dc, tmp, slot); | |
425 | tcg_temp_free(tmp); | |
426 | } | |
427 | ||
553e44f9 MF |
428 | static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest, |
429 | int slot) | |
430 | { | |
431 | TCGv_i32 tcallinc = tcg_const_i32(callinc); | |
432 | ||
433 | tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS], | |
434 | tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN); | |
435 | tcg_temp_free(tcallinc); | |
436 | tcg_gen_movi_i32(cpu_R[callinc << 2], | |
437 | (callinc << 30) | (dc->next_pc & 0x3fffffff)); | |
438 | gen_jump_slot(dc, dest, slot); | |
439 | } | |
440 | ||
441 | static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest) | |
442 | { | |
443 | gen_callw_slot(dc, callinc, dest, -1); | |
444 | } | |
445 | ||
446 | static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot) | |
447 | { | |
448 | TCGv_i32 tmp = tcg_const_i32(dest); | |
433d33c5 | 449 | if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) { |
553e44f9 MF |
450 | slot = -1; |
451 | } | |
452 | gen_callw_slot(dc, callinc, tmp, slot); | |
453 | tcg_temp_free(tmp); | |
454 | } | |
455 | ||
797d780b MF |
456 | static bool gen_check_loop_end(DisasContext *dc, int slot) |
457 | { | |
458 | if (option_enabled(dc, XTENSA_OPTION_LOOP) && | |
459 | !(dc->tb->flags & XTENSA_TBFLAG_EXCM) && | |
460 | dc->next_pc == dc->lend) { | |
42a268c2 | 461 | TCGLabel *label = gen_new_label(); |
797d780b | 462 | |
d865f307 | 463 | gen_advance_ccount(dc); |
797d780b MF |
464 | tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label); |
465 | tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1); | |
466 | gen_jumpi(dc, dc->lbeg, slot); | |
467 | gen_set_label(label); | |
468 | gen_jumpi(dc, dc->next_pc, -1); | |
469 | return true; | |
470 | } | |
471 | return false; | |
472 | } | |
473 | ||
474 | static void gen_jumpi_check_loop_end(DisasContext *dc, int slot) | |
475 | { | |
476 | if (!gen_check_loop_end(dc, slot)) { | |
477 | gen_jumpi(dc, dc->next_pc, slot); | |
478 | } | |
479 | } | |
480 | ||
bd57fb91 MF |
481 | static void gen_brcond(DisasContext *dc, TCGCond cond, |
482 | TCGv_i32 t0, TCGv_i32 t1, uint32_t offset) | |
483 | { | |
42a268c2 | 484 | TCGLabel *label = gen_new_label(); |
bd57fb91 | 485 | |
d865f307 | 486 | gen_advance_ccount(dc); |
bd57fb91 | 487 | tcg_gen_brcond_i32(cond, t0, t1, label); |
797d780b | 488 | gen_jumpi_check_loop_end(dc, 0); |
bd57fb91 MF |
489 | gen_set_label(label); |
490 | gen_jumpi(dc, dc->pc + offset, 1); | |
491 | } | |
492 | ||
493 | static void gen_brcondi(DisasContext *dc, TCGCond cond, | |
494 | TCGv_i32 t0, uint32_t t1, uint32_t offset) | |
495 | { | |
496 | TCGv_i32 tmp = tcg_const_i32(t1); | |
497 | gen_brcond(dc, cond, t0, tmp, offset); | |
498 | tcg_temp_free(tmp); | |
499 | } | |
500 | ||
0857a06e | 501 | static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access) |
fe0bd475 MF |
502 | { |
503 | if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) { | |
504 | if (sregnames[sr].name) { | |
c30f0d18 | 505 | qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not configured\n", sregnames[sr].name); |
fe0bd475 | 506 | } else { |
c30f0d18 | 507 | qemu_log_mask(LOG_UNIMP, "SR %d is not implemented\n", sr); |
fe0bd475 MF |
508 | } |
509 | gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); | |
0857a06e | 510 | return false; |
53593e90 MF |
511 | } else if (!(sregnames[sr].access & access)) { |
512 | static const char * const access_text[] = { | |
513 | [SR_R] = "rsr", | |
514 | [SR_W] = "wsr", | |
515 | [SR_X] = "xsr", | |
516 | }; | |
517 | assert(access < ARRAY_SIZE(access_text) && access_text[access]); | |
c30f0d18 PB |
518 | qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not available for %s\n", sregnames[sr].name, |
519 | access_text[access]); | |
53593e90 | 520 | gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); |
0857a06e | 521 | return false; |
fe0bd475 | 522 | } |
0857a06e | 523 | return true; |
fe0bd475 MF |
524 | } |
525 | ||
b994e91b MF |
526 | static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr) |
527 | { | |
528 | gen_advance_ccount(dc); | |
529 | tcg_gen_mov_i32(d, cpu_SR[sr]); | |
530 | } | |
531 | ||
b67ea0cd MF |
532 | static void gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr) |
533 | { | |
534 | tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10); | |
535 | tcg_gen_or_i32(d, d, cpu_SR[sr]); | |
536 | tcg_gen_andi_i32(d, d, 0xfffffffc); | |
537 | } | |
538 | ||
b8132eff MF |
539 | static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr) |
540 | { | |
541 | static void (* const rsr_handler[256])(DisasContext *dc, | |
542 | TCGv_i32 d, uint32_t sr) = { | |
b994e91b | 543 | [CCOUNT] = gen_rsr_ccount, |
b67ea0cd | 544 | [PTEVADDR] = gen_rsr_ptevaddr, |
b8132eff MF |
545 | }; |
546 | ||
fe0bd475 MF |
547 | if (rsr_handler[sr]) { |
548 | rsr_handler[sr](dc, d, sr); | |
b8132eff | 549 | } else { |
fe0bd475 | 550 | tcg_gen_mov_i32(d, cpu_SR[sr]); |
b8132eff MF |
551 | } |
552 | } | |
553 | ||
797d780b MF |
554 | static void gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s) |
555 | { | |
f492b82d | 556 | gen_helper_wsr_lbeg(cpu_env, s); |
3d0be8a5 | 557 | gen_jumpi_check_loop_end(dc, 0); |
797d780b MF |
558 | } |
559 | ||
560 | static void gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s) | |
561 | { | |
f492b82d | 562 | gen_helper_wsr_lend(cpu_env, s); |
3d0be8a5 | 563 | gen_jumpi_check_loop_end(dc, 0); |
797d780b MF |
564 | } |
565 | ||
3580ecad MF |
566 | static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s) |
567 | { | |
568 | tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f); | |
569 | if (dc->sar_m32_5bit) { | |
570 | tcg_gen_discard_i32(dc->sar_m32); | |
571 | } | |
572 | dc->sar_5bit = false; | |
573 | dc->sar_m32_5bit = false; | |
574 | } | |
575 | ||
4dd85b6b MF |
576 | static void gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s) |
577 | { | |
578 | tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff); | |
579 | } | |
580 | ||
6ad6dbf7 MF |
581 | static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s) |
582 | { | |
583 | tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001); | |
584 | /* This can change tb->flags, so exit tb */ | |
585 | gen_jumpi_check_loop_end(dc, -1); | |
586 | } | |
587 | ||
6825b6c3 MF |
588 | static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s) |
589 | { | |
590 | tcg_gen_ext8s_i32(cpu_SR[sr], s); | |
591 | } | |
592 | ||
553e44f9 MF |
593 | static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
594 | { | |
f492b82d | 595 | gen_helper_wsr_windowbase(cpu_env, v); |
2db59a76 MF |
596 | /* This can change tb->flags, so exit tb */ |
597 | gen_jumpi_check_loop_end(dc, -1); | |
772177c1 MF |
598 | } |
599 | ||
600 | static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v) | |
601 | { | |
53a72dfd | 602 | tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1); |
2db59a76 MF |
603 | /* This can change tb->flags, so exit tb */ |
604 | gen_jumpi_check_loop_end(dc, -1); | |
553e44f9 MF |
605 | } |
606 | ||
b67ea0cd MF |
607 | static void gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
608 | { | |
609 | tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000); | |
610 | } | |
611 | ||
612 | static void gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v) | |
613 | { | |
f492b82d | 614 | gen_helper_wsr_rasid(cpu_env, v); |
b67ea0cd MF |
615 | /* This can change tb->flags, so exit tb */ |
616 | gen_jumpi_check_loop_end(dc, -1); | |
617 | } | |
618 | ||
619 | static void gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v) | |
620 | { | |
621 | tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000); | |
622 | } | |
623 | ||
e61dc8f7 MF |
624 | static void gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
625 | { | |
f492b82d | 626 | gen_helper_wsr_ibreakenable(cpu_env, v); |
e61dc8f7 MF |
627 | gen_jumpi_check_loop_end(dc, 0); |
628 | } | |
629 | ||
fcc803d1 MF |
630 | static void gen_wsr_atomctl(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
631 | { | |
632 | tcg_gen_andi_i32(cpu_SR[sr], v, 0x3f); | |
633 | } | |
634 | ||
e61dc8f7 MF |
635 | static void gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
636 | { | |
637 | unsigned id = sr - IBREAKA; | |
638 | ||
639 | if (id < dc->config->nibreak) { | |
640 | TCGv_i32 tmp = tcg_const_i32(id); | |
f492b82d | 641 | gen_helper_wsr_ibreaka(cpu_env, tmp, v); |
e61dc8f7 MF |
642 | tcg_temp_free(tmp); |
643 | gen_jumpi_check_loop_end(dc, 0); | |
644 | } | |
645 | } | |
646 | ||
f14c4b5f MF |
647 | static void gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
648 | { | |
649 | unsigned id = sr - DBREAKA; | |
650 | ||
651 | if (id < dc->config->ndbreak) { | |
652 | TCGv_i32 tmp = tcg_const_i32(id); | |
f492b82d | 653 | gen_helper_wsr_dbreaka(cpu_env, tmp, v); |
f14c4b5f MF |
654 | tcg_temp_free(tmp); |
655 | } | |
656 | } | |
657 | ||
658 | static void gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v) | |
659 | { | |
660 | unsigned id = sr - DBREAKC; | |
661 | ||
662 | if (id < dc->config->ndbreak) { | |
663 | TCGv_i32 tmp = tcg_const_i32(id); | |
f492b82d | 664 | gen_helper_wsr_dbreakc(cpu_env, tmp, v); |
f14c4b5f MF |
665 | tcg_temp_free(tmp); |
666 | } | |
667 | } | |
668 | ||
ef04a846 MF |
669 | static void gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
670 | { | |
671 | tcg_gen_andi_i32(cpu_SR[sr], v, 0xff); | |
672 | /* This can change tb->flags, so exit tb */ | |
673 | gen_jumpi_check_loop_end(dc, -1); | |
674 | } | |
675 | ||
b994e91b MF |
676 | static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
677 | { | |
678 | tcg_gen_andi_i32(cpu_SR[sr], v, | |
679 | dc->config->inttype_mask[INTTYPE_SOFTWARE]); | |
680 | gen_helper_check_interrupts(cpu_env); | |
681 | gen_jumpi_check_loop_end(dc, 0); | |
682 | } | |
683 | ||
684 | static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v) | |
685 | { | |
686 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
687 | ||
688 | tcg_gen_andi_i32(tmp, v, | |
689 | dc->config->inttype_mask[INTTYPE_EDGE] | | |
690 | dc->config->inttype_mask[INTTYPE_NMI] | | |
691 | dc->config->inttype_mask[INTTYPE_SOFTWARE]); | |
692 | tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp); | |
693 | tcg_temp_free(tmp); | |
694 | gen_helper_check_interrupts(cpu_env); | |
695 | } | |
696 | ||
697 | static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) | |
698 | { | |
699 | tcg_gen_mov_i32(cpu_SR[sr], v); | |
700 | gen_helper_check_interrupts(cpu_env); | |
701 | gen_jumpi_check_loop_end(dc, 0); | |
702 | } | |
703 | ||
f0a548b9 MF |
704 | static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
705 | { | |
706 | uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB | | |
707 | PS_UM | PS_EXCM | PS_INTLEVEL; | |
708 | ||
709 | if (option_enabled(dc, XTENSA_OPTION_MMU)) { | |
710 | mask |= PS_RING; | |
711 | } | |
712 | tcg_gen_andi_i32(cpu_SR[sr], v, mask); | |
b994e91b MF |
713 | gen_helper_check_interrupts(cpu_env); |
714 | /* This can change mmu index and tb->flags, so exit tb */ | |
797d780b | 715 | gen_jumpi_check_loop_end(dc, -1); |
f0a548b9 MF |
716 | } |
717 | ||
35b5c044 MF |
718 | static void gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
719 | { | |
720 | if (dc->icount) { | |
721 | tcg_gen_mov_i32(dc->next_icount, v); | |
722 | } else { | |
723 | tcg_gen_mov_i32(cpu_SR[sr], v); | |
724 | } | |
725 | } | |
726 | ||
727 | static void gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v) | |
728 | { | |
729 | tcg_gen_andi_i32(cpu_SR[sr], v, 0xf); | |
730 | /* This can change tb->flags, so exit tb */ | |
731 | gen_jumpi_check_loop_end(dc, -1); | |
732 | } | |
733 | ||
b994e91b MF |
734 | static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
735 | { | |
736 | uint32_t id = sr - CCOMPARE; | |
737 | if (id < dc->config->nccompare) { | |
738 | uint32_t int_bit = 1 << dc->config->timerint[id]; | |
739 | gen_advance_ccount(dc); | |
740 | tcg_gen_mov_i32(cpu_SR[sr], v); | |
741 | tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit); | |
742 | gen_helper_check_interrupts(cpu_env); | |
743 | } | |
744 | } | |
745 | ||
b8132eff MF |
746 | static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s) |
747 | { | |
748 | static void (* const wsr_handler[256])(DisasContext *dc, | |
749 | uint32_t sr, TCGv_i32 v) = { | |
797d780b MF |
750 | [LBEG] = gen_wsr_lbeg, |
751 | [LEND] = gen_wsr_lend, | |
3580ecad | 752 | [SAR] = gen_wsr_sar, |
4dd85b6b | 753 | [BR] = gen_wsr_br, |
6ad6dbf7 | 754 | [LITBASE] = gen_wsr_litbase, |
6825b6c3 | 755 | [ACCHI] = gen_wsr_acchi, |
553e44f9 | 756 | [WINDOW_BASE] = gen_wsr_windowbase, |
772177c1 | 757 | [WINDOW_START] = gen_wsr_windowstart, |
b67ea0cd MF |
758 | [PTEVADDR] = gen_wsr_ptevaddr, |
759 | [RASID] = gen_wsr_rasid, | |
760 | [ITLBCFG] = gen_wsr_tlbcfg, | |
761 | [DTLBCFG] = gen_wsr_tlbcfg, | |
e61dc8f7 | 762 | [IBREAKENABLE] = gen_wsr_ibreakenable, |
fcc803d1 | 763 | [ATOMCTL] = gen_wsr_atomctl, |
e61dc8f7 MF |
764 | [IBREAKA] = gen_wsr_ibreaka, |
765 | [IBREAKA + 1] = gen_wsr_ibreaka, | |
f14c4b5f MF |
766 | [DBREAKA] = gen_wsr_dbreaka, |
767 | [DBREAKA + 1] = gen_wsr_dbreaka, | |
768 | [DBREAKC] = gen_wsr_dbreakc, | |
769 | [DBREAKC + 1] = gen_wsr_dbreakc, | |
ef04a846 | 770 | [CPENABLE] = gen_wsr_cpenable, |
b994e91b MF |
771 | [INTSET] = gen_wsr_intset, |
772 | [INTCLEAR] = gen_wsr_intclear, | |
773 | [INTENABLE] = gen_wsr_intenable, | |
f0a548b9 | 774 | [PS] = gen_wsr_ps, |
35b5c044 MF |
775 | [ICOUNT] = gen_wsr_icount, |
776 | [ICOUNTLEVEL] = gen_wsr_icountlevel, | |
b994e91b MF |
777 | [CCOMPARE] = gen_wsr_ccompare, |
778 | [CCOMPARE + 1] = gen_wsr_ccompare, | |
779 | [CCOMPARE + 2] = gen_wsr_ccompare, | |
b8132eff MF |
780 | }; |
781 | ||
fe0bd475 MF |
782 | if (wsr_handler[sr]) { |
783 | wsr_handler[sr](dc, sr, s); | |
b8132eff | 784 | } else { |
fe0bd475 | 785 | tcg_gen_mov_i32(cpu_SR[sr], s); |
b8132eff MF |
786 | } |
787 | } | |
788 | ||
dd519cbe MF |
789 | static void gen_wur(uint32_t ur, TCGv_i32 s) |
790 | { | |
791 | switch (ur) { | |
792 | case FCR: | |
793 | gen_helper_wur_fcr(cpu_env, s); | |
794 | break; | |
795 | ||
796 | case FSR: | |
797 | tcg_gen_andi_i32(cpu_UR[ur], s, 0xffffff80); | |
798 | break; | |
799 | ||
800 | default: | |
801 | tcg_gen_mov_i32(cpu_UR[ur], s); | |
802 | break; | |
803 | } | |
804 | } | |
805 | ||
5b4e481b MF |
806 | static void gen_load_store_alignment(DisasContext *dc, int shift, |
807 | TCGv_i32 addr, bool no_hw_alignment) | |
808 | { | |
809 | if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) { | |
810 | tcg_gen_andi_i32(addr, addr, ~0 << shift); | |
811 | } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) && | |
812 | no_hw_alignment) { | |
42a268c2 | 813 | TCGLabel *label = gen_new_label(); |
5b4e481b MF |
814 | TCGv_i32 tmp = tcg_temp_new_i32(); |
815 | tcg_gen_andi_i32(tmp, addr, ~(~0 << shift)); | |
816 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label); | |
817 | gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr); | |
818 | gen_set_label(label); | |
819 | tcg_temp_free(tmp); | |
820 | } | |
821 | } | |
822 | ||
b994e91b MF |
823 | static void gen_waiti(DisasContext *dc, uint32_t imm4) |
824 | { | |
825 | TCGv_i32 pc = tcg_const_i32(dc->next_pc); | |
826 | TCGv_i32 intlevel = tcg_const_i32(imm4); | |
827 | gen_advance_ccount(dc); | |
f492b82d | 828 | gen_helper_waiti(cpu_env, pc, intlevel); |
b994e91b MF |
829 | tcg_temp_free(pc); |
830 | tcg_temp_free(intlevel); | |
831 | } | |
832 | ||
97e89ee9 | 833 | static bool gen_window_check1(DisasContext *dc, unsigned r1) |
772177c1 | 834 | { |
2db59a76 MF |
835 | if (r1 / 4 > dc->window) { |
836 | TCGv_i32 pc = tcg_const_i32(dc->pc); | |
837 | TCGv_i32 w = tcg_const_i32(r1 / 4); | |
908c67fc | 838 | |
2db59a76 MF |
839 | gen_advance_ccount(dc); |
840 | gen_helper_window_check(cpu_env, pc, w); | |
841 | dc->is_jmp = DISAS_UPDATE; | |
97e89ee9 | 842 | return false; |
772177c1 | 843 | } |
97e89ee9 | 844 | return true; |
772177c1 MF |
845 | } |
846 | ||
97e89ee9 | 847 | static bool gen_window_check2(DisasContext *dc, unsigned r1, unsigned r2) |
772177c1 | 848 | { |
97e89ee9 | 849 | return gen_window_check1(dc, r1 > r2 ? r1 : r2); |
772177c1 MF |
850 | } |
851 | ||
97e89ee9 | 852 | static bool gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2, |
772177c1 MF |
853 | unsigned r3) |
854 | { | |
97e89ee9 | 855 | return gen_window_check2(dc, r1, r2 > r3 ? r2 : r3); |
772177c1 MF |
856 | } |
857 | ||
6825b6c3 MF |
858 | static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned) |
859 | { | |
860 | TCGv_i32 m = tcg_temp_new_i32(); | |
861 | ||
862 | if (hi) { | |
863 | (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16); | |
864 | } else { | |
865 | (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v); | |
866 | } | |
867 | return m; | |
868 | } | |
869 | ||
01673a34 MF |
870 | static inline unsigned xtensa_op0_insn_len(unsigned op0) |
871 | { | |
872 | return op0 >= 8 ? 2 : 3; | |
873 | } | |
874 | ||
0c4fabea | 875 | static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) |
dedc5eae | 876 | { |
b67ea0cd MF |
877 | #define HAS_OPTION_BITS(opt) do { \ |
878 | if (!option_bits_enabled(dc, opt)) { \ | |
c30f0d18 PB |
879 | qemu_log_mask(LOG_GUEST_ERROR, "Option is not enabled %s:%d\n", \ |
880 | __FILE__, __LINE__); \ | |
dedc5eae MF |
881 | goto invalid_opcode; \ |
882 | } \ | |
883 | } while (0) | |
884 | ||
b67ea0cd MF |
885 | #define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt)) |
886 | ||
c30f0d18 | 887 | #define TBD() qemu_log_mask(LOG_UNIMP, "TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__) |
91a5bb76 | 888 | #define RESERVED() do { \ |
c30f0d18 PB |
889 | qemu_log_mask(LOG_GUEST_ERROR, "RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \ |
890 | dc->pc, b0, b1, b2, __FILE__, __LINE__); \ | |
91a5bb76 MF |
891 | goto invalid_opcode; \ |
892 | } while (0) | |
893 | ||
894 | ||
dedc5eae MF |
895 | #ifdef TARGET_WORDS_BIGENDIAN |
896 | #define OP0 (((b0) & 0xf0) >> 4) | |
897 | #define OP1 (((b2) & 0xf0) >> 4) | |
898 | #define OP2 ((b2) & 0xf) | |
899 | #define RRR_R ((b1) & 0xf) | |
900 | #define RRR_S (((b1) & 0xf0) >> 4) | |
901 | #define RRR_T ((b0) & 0xf) | |
902 | #else | |
903 | #define OP0 (((b0) & 0xf)) | |
904 | #define OP1 (((b2) & 0xf)) | |
905 | #define OP2 (((b2) & 0xf0) >> 4) | |
906 | #define RRR_R (((b1) & 0xf0) >> 4) | |
907 | #define RRR_S (((b1) & 0xf)) | |
908 | #define RRR_T (((b0) & 0xf0) >> 4) | |
909 | #endif | |
6825b6c3 MF |
910 | #define RRR_X ((RRR_R & 0x4) >> 2) |
911 | #define RRR_Y ((RRR_T & 0x4) >> 2) | |
912 | #define RRR_W (RRR_R & 0x3) | |
dedc5eae MF |
913 | |
914 | #define RRRN_R RRR_R | |
915 | #define RRRN_S RRR_S | |
916 | #define RRRN_T RRR_T | |
917 | ||
65026682 MF |
918 | #define RRI4_R RRR_R |
919 | #define RRI4_S RRR_S | |
920 | #define RRI4_T RRR_T | |
921 | #ifdef TARGET_WORDS_BIGENDIAN | |
922 | #define RRI4_IMM4 ((b2) & 0xf) | |
923 | #else | |
924 | #define RRI4_IMM4 (((b2) & 0xf0) >> 4) | |
925 | #endif | |
926 | ||
dedc5eae MF |
927 | #define RRI8_R RRR_R |
928 | #define RRI8_S RRR_S | |
929 | #define RRI8_T RRR_T | |
930 | #define RRI8_IMM8 (b2) | |
931 | #define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8) | |
932 | ||
933 | #ifdef TARGET_WORDS_BIGENDIAN | |
934 | #define RI16_IMM16 (((b1) << 8) | (b2)) | |
935 | #else | |
936 | #define RI16_IMM16 (((b2) << 8) | (b1)) | |
937 | #endif | |
938 | ||
939 | #ifdef TARGET_WORDS_BIGENDIAN | |
940 | #define CALL_N (((b0) & 0xc) >> 2) | |
941 | #define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2)) | |
942 | #else | |
943 | #define CALL_N (((b0) & 0x30) >> 4) | |
944 | #define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10)) | |
945 | #endif | |
946 | #define CALL_OFFSET_SE \ | |
947 | (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET) | |
948 | ||
949 | #define CALLX_N CALL_N | |
950 | #ifdef TARGET_WORDS_BIGENDIAN | |
951 | #define CALLX_M ((b0) & 0x3) | |
952 | #else | |
953 | #define CALLX_M (((b0) & 0xc0) >> 6) | |
954 | #endif | |
955 | #define CALLX_S RRR_S | |
956 | ||
957 | #define BRI12_M CALLX_M | |
958 | #define BRI12_S RRR_S | |
959 | #ifdef TARGET_WORDS_BIGENDIAN | |
960 | #define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2)) | |
961 | #else | |
962 | #define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4)) | |
963 | #endif | |
964 | #define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12) | |
965 | ||
966 | #define BRI8_M BRI12_M | |
967 | #define BRI8_R RRI8_R | |
968 | #define BRI8_S RRI8_S | |
969 | #define BRI8_IMM8 RRI8_IMM8 | |
970 | #define BRI8_IMM8_SE RRI8_IMM8_SE | |
971 | ||
972 | #define RSR_SR (b1) | |
973 | ||
0c4fabea BS |
974 | uint8_t b0 = cpu_ldub_code(env, dc->pc); |
975 | uint8_t b1 = cpu_ldub_code(env, dc->pc + 1); | |
a044ec2a | 976 | uint8_t b2 = 0; |
01673a34 | 977 | unsigned len = xtensa_op0_insn_len(OP0); |
dedc5eae | 978 | |
bd57fb91 MF |
979 | static const uint32_t B4CONST[] = { |
980 | 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256 | |
981 | }; | |
982 | ||
983 | static const uint32_t B4CONSTU[] = { | |
984 | 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256 | |
985 | }; | |
986 | ||
01673a34 MF |
987 | switch (len) { |
988 | case 2: | |
dedc5eae | 989 | HAS_OPTION(XTENSA_OPTION_CODE_DENSITY); |
01673a34 MF |
990 | break; |
991 | ||
992 | case 3: | |
0c4fabea | 993 | b2 = cpu_ldub_code(env, dc->pc + 2); |
01673a34 MF |
994 | break; |
995 | ||
996 | default: | |
997 | RESERVED(); | |
dedc5eae | 998 | } |
01673a34 | 999 | dc->next_pc = dc->pc + len; |
dedc5eae MF |
1000 | |
1001 | switch (OP0) { | |
1002 | case 0: /*QRST*/ | |
1003 | switch (OP1) { | |
1004 | case 0: /*RST0*/ | |
1005 | switch (OP2) { | |
1006 | case 0: /*ST0*/ | |
1007 | if ((RRR_R & 0xc) == 0x8) { | |
1008 | HAS_OPTION(XTENSA_OPTION_BOOLEAN); | |
1009 | } | |
1010 | ||
1011 | switch (RRR_R) { | |
1012 | case 0: /*SNM0*/ | |
5da4a6a8 MF |
1013 | switch (CALLX_M) { |
1014 | case 0: /*ILL*/ | |
40643d7c | 1015 | gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); |
5da4a6a8 MF |
1016 | break; |
1017 | ||
1018 | case 1: /*reserved*/ | |
91a5bb76 | 1019 | RESERVED(); |
5da4a6a8 MF |
1020 | break; |
1021 | ||
1022 | case 2: /*JR*/ | |
1023 | switch (CALLX_N) { | |
1024 | case 0: /*RET*/ | |
1025 | case 2: /*JX*/ | |
97e89ee9 MF |
1026 | if (gen_window_check1(dc, CALLX_S)) { |
1027 | gen_jump(dc, cpu_R[CALLX_S]); | |
1028 | } | |
5da4a6a8 MF |
1029 | break; |
1030 | ||
1031 | case 1: /*RETWw*/ | |
1032 | HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); | |
553e44f9 MF |
1033 | { |
1034 | TCGv_i32 tmp = tcg_const_i32(dc->pc); | |
b994e91b | 1035 | gen_advance_ccount(dc); |
f492b82d | 1036 | gen_helper_retw(tmp, cpu_env, tmp); |
553e44f9 MF |
1037 | gen_jump(dc, tmp); |
1038 | tcg_temp_free(tmp); | |
1039 | } | |
5da4a6a8 MF |
1040 | break; |
1041 | ||
1042 | case 3: /*reserved*/ | |
91a5bb76 | 1043 | RESERVED(); |
5da4a6a8 MF |
1044 | break; |
1045 | } | |
1046 | break; | |
1047 | ||
1048 | case 3: /*CALLX*/ | |
97e89ee9 MF |
1049 | if (!gen_window_check2(dc, CALLX_S, CALLX_N << 2)) { |
1050 | break; | |
1051 | } | |
5da4a6a8 MF |
1052 | switch (CALLX_N) { |
1053 | case 0: /*CALLX0*/ | |
1054 | { | |
1055 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
1056 | tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]); | |
1057 | tcg_gen_movi_i32(cpu_R[0], dc->next_pc); | |
1058 | gen_jump(dc, tmp); | |
1059 | tcg_temp_free(tmp); | |
1060 | } | |
1061 | break; | |
1062 | ||
1063 | case 1: /*CALLX4w*/ | |
1064 | case 2: /*CALLX8w*/ | |
1065 | case 3: /*CALLX12w*/ | |
1066 | HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); | |
553e44f9 MF |
1067 | { |
1068 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
1069 | ||
1070 | tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]); | |
1071 | gen_callw(dc, CALLX_N, tmp); | |
1072 | tcg_temp_free(tmp); | |
1073 | } | |
5da4a6a8 MF |
1074 | break; |
1075 | } | |
1076 | break; | |
1077 | } | |
dedc5eae MF |
1078 | break; |
1079 | ||
1080 | case 1: /*MOVSPw*/ | |
1081 | HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); | |
97e89ee9 | 1082 | if (gen_window_check2(dc, RRR_T, RRR_S)) { |
553e44f9 | 1083 | TCGv_i32 pc = tcg_const_i32(dc->pc); |
b994e91b | 1084 | gen_advance_ccount(dc); |
f492b82d | 1085 | gen_helper_movsp(cpu_env, pc); |
553e44f9 MF |
1086 | tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]); |
1087 | tcg_temp_free(pc); | |
1088 | } | |
dedc5eae MF |
1089 | break; |
1090 | ||
1091 | case 2: /*SYNC*/ | |
28067b22 MF |
1092 | switch (RRR_T) { |
1093 | case 0: /*ISYNC*/ | |
1094 | break; | |
1095 | ||
1096 | case 1: /*RSYNC*/ | |
1097 | break; | |
1098 | ||
1099 | case 2: /*ESYNC*/ | |
1100 | break; | |
1101 | ||
1102 | case 3: /*DSYNC*/ | |
1103 | break; | |
1104 | ||
1105 | case 8: /*EXCW*/ | |
1106 | HAS_OPTION(XTENSA_OPTION_EXCEPTION); | |
1107 | break; | |
1108 | ||
1109 | case 12: /*MEMW*/ | |
1110 | break; | |
1111 | ||
1112 | case 13: /*EXTW*/ | |
1113 | break; | |
1114 | ||
1115 | case 15: /*NOP*/ | |
1116 | break; | |
1117 | ||
1118 | default: /*reserved*/ | |
1119 | RESERVED(); | |
1120 | break; | |
1121 | } | |
91a5bb76 MF |
1122 | break; |
1123 | ||
1124 | case 3: /*RFEIx*/ | |
40643d7c MF |
1125 | switch (RRR_T) { |
1126 | case 0: /*RFETx*/ | |
1127 | HAS_OPTION(XTENSA_OPTION_EXCEPTION); | |
1128 | switch (RRR_S) { | |
1129 | case 0: /*RFEx*/ | |
97e89ee9 MF |
1130 | if (gen_check_privilege(dc)) { |
1131 | tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); | |
1132 | gen_helper_check_interrupts(cpu_env); | |
1133 | gen_jump(dc, cpu_SR[EPC1]); | |
1134 | } | |
40643d7c MF |
1135 | break; |
1136 | ||
1137 | case 1: /*RFUEx*/ | |
1138 | RESERVED(); | |
1139 | break; | |
1140 | ||
1141 | case 2: /*RFDEx*/ | |
97e89ee9 MF |
1142 | if (gen_check_privilege(dc)) { |
1143 | gen_jump(dc, cpu_SR[ | |
1144 | dc->config->ndepc ? DEPC : EPC1]); | |
1145 | } | |
40643d7c MF |
1146 | break; |
1147 | ||
1148 | case 4: /*RFWOw*/ | |
1149 | case 5: /*RFWUw*/ | |
1150 | HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); | |
97e89ee9 | 1151 | if (gen_check_privilege(dc)) { |
553e44f9 MF |
1152 | TCGv_i32 tmp = tcg_const_i32(1); |
1153 | ||
1154 | tcg_gen_andi_i32( | |
1155 | cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); | |
1156 | tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]); | |
1157 | ||
1158 | if (RRR_S == 4) { | |
1159 | tcg_gen_andc_i32(cpu_SR[WINDOW_START], | |
1160 | cpu_SR[WINDOW_START], tmp); | |
1161 | } else { | |
1162 | tcg_gen_or_i32(cpu_SR[WINDOW_START], | |
1163 | cpu_SR[WINDOW_START], tmp); | |
1164 | } | |
1165 | ||
f492b82d | 1166 | gen_helper_restore_owb(cpu_env); |
b994e91b | 1167 | gen_helper_check_interrupts(cpu_env); |
553e44f9 MF |
1168 | gen_jump(dc, cpu_SR[EPC1]); |
1169 | ||
1170 | tcg_temp_free(tmp); | |
1171 | } | |
40643d7c MF |
1172 | break; |
1173 | ||
1174 | default: /*reserved*/ | |
1175 | RESERVED(); | |
1176 | break; | |
1177 | } | |
1178 | break; | |
1179 | ||
1180 | case 1: /*RFIx*/ | |
1181 | HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT); | |
b994e91b | 1182 | if (RRR_S >= 2 && RRR_S <= dc->config->nlevel) { |
97e89ee9 MF |
1183 | if (gen_check_privilege(dc)) { |
1184 | tcg_gen_mov_i32(cpu_SR[PS], | |
1185 | cpu_SR[EPS2 + RRR_S - 2]); | |
1186 | gen_helper_check_interrupts(cpu_env); | |
1187 | gen_jump(dc, cpu_SR[EPC1 + RRR_S - 1]); | |
1188 | } | |
b994e91b | 1189 | } else { |
c30f0d18 | 1190 | qemu_log_mask(LOG_GUEST_ERROR, "RFI %d is illegal\n", RRR_S); |
b994e91b MF |
1191 | gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); |
1192 | } | |
40643d7c MF |
1193 | break; |
1194 | ||
1195 | case 2: /*RFME*/ | |
1196 | TBD(); | |
1197 | break; | |
1198 | ||
1199 | default: /*reserved*/ | |
1200 | RESERVED(); | |
1201 | break; | |
1202 | ||
1203 | } | |
91a5bb76 MF |
1204 | break; |
1205 | ||
1206 | case 4: /*BREAKx*/ | |
e61dc8f7 MF |
1207 | HAS_OPTION(XTENSA_OPTION_DEBUG); |
1208 | if (dc->debug) { | |
1209 | gen_debug_exception(dc, DEBUGCAUSE_BI); | |
1210 | } | |
91a5bb76 MF |
1211 | break; |
1212 | ||
1213 | case 5: /*SYSCALLx*/ | |
1214 | HAS_OPTION(XTENSA_OPTION_EXCEPTION); | |
40643d7c MF |
1215 | switch (RRR_S) { |
1216 | case 0: /*SYSCALLx*/ | |
1217 | gen_exception_cause(dc, SYSCALL_CAUSE); | |
1218 | break; | |
1219 | ||
1220 | case 1: /*SIMCALL*/ | |
cfe67cef | 1221 | if (semihosting_enabled()) { |
97e89ee9 MF |
1222 | if (gen_check_privilege(dc)) { |
1223 | gen_helper_simcall(cpu_env); | |
1224 | } | |
1ddeaa5d | 1225 | } else { |
c30f0d18 | 1226 | qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n"); |
1ddeaa5d MF |
1227 | gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); |
1228 | } | |
40643d7c MF |
1229 | break; |
1230 | ||
1231 | default: | |
1232 | RESERVED(); | |
1233 | break; | |
1234 | } | |
91a5bb76 MF |
1235 | break; |
1236 | ||
1237 | case 6: /*RSILx*/ | |
1238 | HAS_OPTION(XTENSA_OPTION_INTERRUPT); | |
97e89ee9 MF |
1239 | if (gen_check_privilege(dc) && |
1240 | gen_window_check1(dc, RRR_T)) { | |
1241 | tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]); | |
1242 | tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL); | |
1243 | tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S); | |
1244 | gen_helper_check_interrupts(cpu_env); | |
1245 | gen_jumpi_check_loop_end(dc, 0); | |
1246 | } | |
91a5bb76 MF |
1247 | break; |
1248 | ||
1249 | case 7: /*WAITIx*/ | |
1250 | HAS_OPTION(XTENSA_OPTION_INTERRUPT); | |
97e89ee9 MF |
1251 | if (gen_check_privilege(dc)) { |
1252 | gen_waiti(dc, RRR_S); | |
1253 | } | |
91a5bb76 MF |
1254 | break; |
1255 | ||
1256 | case 8: /*ANY4p*/ | |
91a5bb76 | 1257 | case 9: /*ALL4p*/ |
91a5bb76 | 1258 | case 10: /*ANY8p*/ |
91a5bb76 MF |
1259 | case 11: /*ALL8p*/ |
1260 | HAS_OPTION(XTENSA_OPTION_BOOLEAN); | |
4dd85b6b MF |
1261 | { |
1262 | const unsigned shift = (RRR_R & 2) ? 8 : 4; | |
1263 | TCGv_i32 mask = tcg_const_i32( | |
1264 | ((1 << shift) - 1) << RRR_S); | |
1265 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
1266 | ||
1267 | tcg_gen_and_i32(tmp, cpu_SR[BR], mask); | |
1268 | if (RRR_R & 1) { /*ALL*/ | |
1269 | tcg_gen_addi_i32(tmp, tmp, 1 << RRR_S); | |
1270 | } else { /*ANY*/ | |
1271 | tcg_gen_add_i32(tmp, tmp, mask); | |
1272 | } | |
1273 | tcg_gen_shri_i32(tmp, tmp, RRR_S + shift); | |
1274 | tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], | |
1275 | tmp, RRR_T, 1); | |
1276 | tcg_temp_free(mask); | |
1277 | tcg_temp_free(tmp); | |
1278 | } | |
91a5bb76 MF |
1279 | break; |
1280 | ||
1281 | default: /*reserved*/ | |
1282 | RESERVED(); | |
dedc5eae MF |
1283 | break; |
1284 | ||
1285 | } | |
1286 | break; | |
1287 | ||
1288 | case 1: /*AND*/ | |
97e89ee9 MF |
1289 | if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { |
1290 | tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); | |
1291 | } | |
dedc5eae MF |
1292 | break; |
1293 | ||
1294 | case 2: /*OR*/ | |
97e89ee9 MF |
1295 | if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { |
1296 | tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); | |
1297 | } | |
dedc5eae MF |
1298 | break; |
1299 | ||
1300 | case 3: /*XOR*/ | |
97e89ee9 MF |
1301 | if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { |
1302 | tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); | |
1303 | } | |
dedc5eae MF |
1304 | break; |
1305 | ||
1306 | case 4: /*ST1*/ | |
3580ecad MF |
1307 | switch (RRR_R) { |
1308 | case 0: /*SSR*/ | |
97e89ee9 MF |
1309 | if (gen_window_check1(dc, RRR_S)) { |
1310 | gen_right_shift_sar(dc, cpu_R[RRR_S]); | |
1311 | } | |
3580ecad MF |
1312 | break; |
1313 | ||
1314 | case 1: /*SSL*/ | |
97e89ee9 MF |
1315 | if (gen_window_check1(dc, RRR_S)) { |
1316 | gen_left_shift_sar(dc, cpu_R[RRR_S]); | |
1317 | } | |
3580ecad MF |
1318 | break; |
1319 | ||
1320 | case 2: /*SSA8L*/ | |
97e89ee9 | 1321 | if (gen_window_check1(dc, RRR_S)) { |
3580ecad MF |
1322 | TCGv_i32 tmp = tcg_temp_new_i32(); |
1323 | tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3); | |
1324 | gen_right_shift_sar(dc, tmp); | |
1325 | tcg_temp_free(tmp); | |
1326 | } | |
1327 | break; | |
1328 | ||
1329 | case 3: /*SSA8B*/ | |
97e89ee9 | 1330 | if (gen_window_check1(dc, RRR_S)) { |
3580ecad MF |
1331 | TCGv_i32 tmp = tcg_temp_new_i32(); |
1332 | tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3); | |
1333 | gen_left_shift_sar(dc, tmp); | |
1334 | tcg_temp_free(tmp); | |
1335 | } | |
1336 | break; | |
1337 | ||
1338 | case 4: /*SSAI*/ | |
1339 | { | |
1340 | TCGv_i32 tmp = tcg_const_i32( | |
1341 | RRR_S | ((RRR_T & 1) << 4)); | |
1342 | gen_right_shift_sar(dc, tmp); | |
1343 | tcg_temp_free(tmp); | |
1344 | } | |
1345 | break; | |
1346 | ||
1347 | case 6: /*RER*/ | |
91a5bb76 | 1348 | TBD(); |
3580ecad MF |
1349 | break; |
1350 | ||
1351 | case 7: /*WER*/ | |
91a5bb76 | 1352 | TBD(); |
3580ecad MF |
1353 | break; |
1354 | ||
1355 | case 8: /*ROTWw*/ | |
1356 | HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); | |
97e89ee9 | 1357 | if (gen_check_privilege(dc)) { |
553e44f9 MF |
1358 | TCGv_i32 tmp = tcg_const_i32( |
1359 | RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0)); | |
f492b82d | 1360 | gen_helper_rotw(cpu_env, tmp); |
553e44f9 | 1361 | tcg_temp_free(tmp); |
2db59a76 MF |
1362 | /* This can change tb->flags, so exit tb */ |
1363 | gen_jumpi_check_loop_end(dc, -1); | |
553e44f9 | 1364 | } |
3580ecad MF |
1365 | break; |
1366 | ||
1367 | case 14: /*NSAu*/ | |
7f65f4b0 | 1368 | HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA); |
97e89ee9 MF |
1369 | if (gen_window_check2(dc, RRR_S, RRR_T)) { |
1370 | gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]); | |
1371 | } | |
3580ecad MF |
1372 | break; |
1373 | ||
1374 | case 15: /*NSAUu*/ | |
7f65f4b0 | 1375 | HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA); |
97e89ee9 MF |
1376 | if (gen_window_check2(dc, RRR_S, RRR_T)) { |
1377 | gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]); | |
1378 | } | |
3580ecad MF |
1379 | break; |
1380 | ||
1381 | default: /*reserved*/ | |
91a5bb76 | 1382 | RESERVED(); |
3580ecad MF |
1383 | break; |
1384 | } | |
dedc5eae MF |
1385 | break; |
1386 | ||
1387 | case 5: /*TLB*/ | |
b67ea0cd MF |
1388 | HAS_OPTION_BITS( |
1389 | XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) | | |
1390 | XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | | |
1391 | XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION)); | |
97e89ee9 MF |
1392 | if (gen_check_privilege(dc) && |
1393 | gen_window_check2(dc, RRR_S, RRR_T)) { | |
b67ea0cd MF |
1394 | TCGv_i32 dtlb = tcg_const_i32((RRR_R & 8) != 0); |
1395 | ||
1396 | switch (RRR_R & 7) { | |
1397 | case 3: /*RITLB0*/ /*RDTLB0*/ | |
f492b82d MF |
1398 | gen_helper_rtlb0(cpu_R[RRR_T], |
1399 | cpu_env, cpu_R[RRR_S], dtlb); | |
b67ea0cd MF |
1400 | break; |
1401 | ||
1402 | case 4: /*IITLB*/ /*IDTLB*/ | |
f492b82d | 1403 | gen_helper_itlb(cpu_env, cpu_R[RRR_S], dtlb); |
b67ea0cd MF |
1404 | /* This could change memory mapping, so exit tb */ |
1405 | gen_jumpi_check_loop_end(dc, -1); | |
1406 | break; | |
1407 | ||
1408 | case 5: /*PITLB*/ /*PDTLB*/ | |
1409 | tcg_gen_movi_i32(cpu_pc, dc->pc); | |
f492b82d MF |
1410 | gen_helper_ptlb(cpu_R[RRR_T], |
1411 | cpu_env, cpu_R[RRR_S], dtlb); | |
b67ea0cd MF |
1412 | break; |
1413 | ||
1414 | case 6: /*WITLB*/ /*WDTLB*/ | |
f492b82d MF |
1415 | gen_helper_wtlb( |
1416 | cpu_env, cpu_R[RRR_T], cpu_R[RRR_S], dtlb); | |
b67ea0cd MF |
1417 | /* This could change memory mapping, so exit tb */ |
1418 | gen_jumpi_check_loop_end(dc, -1); | |
1419 | break; | |
1420 | ||
1421 | case 7: /*RITLB1*/ /*RDTLB1*/ | |
f492b82d MF |
1422 | gen_helper_rtlb1(cpu_R[RRR_T], |
1423 | cpu_env, cpu_R[RRR_S], dtlb); | |
b67ea0cd MF |
1424 | break; |
1425 | ||
1426 | default: | |
1427 | tcg_temp_free(dtlb); | |
1428 | RESERVED(); | |
1429 | break; | |
1430 | } | |
1431 | tcg_temp_free(dtlb); | |
1432 | } | |
dedc5eae MF |
1433 | break; |
1434 | ||
1435 | case 6: /*RT0*/ | |
97e89ee9 MF |
1436 | if (!gen_window_check2(dc, RRR_R, RRR_T)) { |
1437 | break; | |
1438 | } | |
f331fe5e MF |
1439 | switch (RRR_S) { |
1440 | case 0: /*NEG*/ | |
1441 | tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]); | |
1442 | break; | |
1443 | ||
1444 | case 1: /*ABS*/ | |
1445 | { | |
f877d09e MF |
1446 | TCGv_i32 zero = tcg_const_i32(0); |
1447 | TCGv_i32 neg = tcg_temp_new_i32(); | |
1448 | ||
1449 | tcg_gen_neg_i32(neg, cpu_R[RRR_T]); | |
1450 | tcg_gen_movcond_i32(TCG_COND_GE, cpu_R[RRR_R], | |
1451 | cpu_R[RRR_T], zero, cpu_R[RRR_T], neg); | |
1452 | tcg_temp_free(neg); | |
1453 | tcg_temp_free(zero); | |
f331fe5e MF |
1454 | } |
1455 | break; | |
1456 | ||
1457 | default: /*reserved*/ | |
91a5bb76 | 1458 | RESERVED(); |
f331fe5e MF |
1459 | break; |
1460 | } | |
dedc5eae MF |
1461 | break; |
1462 | ||
1463 | case 7: /*reserved*/ | |
91a5bb76 | 1464 | RESERVED(); |
dedc5eae MF |
1465 | break; |
1466 | ||
1467 | case 8: /*ADD*/ | |
97e89ee9 MF |
1468 | if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { |
1469 | tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); | |
1470 | } | |
dedc5eae MF |
1471 | break; |
1472 | ||
1473 | case 9: /*ADD**/ | |
1474 | case 10: | |
1475 | case 11: | |
97e89ee9 | 1476 | if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { |
dedc5eae MF |
1477 | TCGv_i32 tmp = tcg_temp_new_i32(); |
1478 | tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8); | |
1479 | tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]); | |
1480 | tcg_temp_free(tmp); | |
1481 | } | |
1482 | break; | |
1483 | ||
1484 | case 12: /*SUB*/ | |
97e89ee9 MF |
1485 | if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { |
1486 | tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); | |
1487 | } | |
dedc5eae MF |
1488 | break; |
1489 | ||
1490 | case 13: /*SUB**/ | |
1491 | case 14: | |
1492 | case 15: | |
97e89ee9 | 1493 | if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { |
dedc5eae MF |
1494 | TCGv_i32 tmp = tcg_temp_new_i32(); |
1495 | tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12); | |
1496 | tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]); | |
1497 | tcg_temp_free(tmp); | |
1498 | } | |
1499 | break; | |
1500 | } | |
1501 | break; | |
1502 | ||
1503 | case 1: /*RST1*/ | |
3580ecad MF |
1504 | switch (OP2) { |
1505 | case 0: /*SLLI*/ | |
1506 | case 1: | |
97e89ee9 MF |
1507 | if (gen_window_check2(dc, RRR_R, RRR_S)) { |
1508 | tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S], | |
1509 | 32 - (RRR_T | ((OP2 & 1) << 4))); | |
1510 | } | |
3580ecad MF |
1511 | break; |
1512 | ||
1513 | case 2: /*SRAI*/ | |
1514 | case 3: | |
97e89ee9 MF |
1515 | if (gen_window_check2(dc, RRR_R, RRR_T)) { |
1516 | tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T], | |
1517 | RRR_S | ((OP2 & 1) << 4)); | |
1518 | } | |
3580ecad MF |
1519 | break; |
1520 | ||
1521 | case 4: /*SRLI*/ | |
97e89ee9 MF |
1522 | if (gen_window_check2(dc, RRR_R, RRR_T)) { |
1523 | tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S); | |
1524 | } | |
3580ecad MF |
1525 | break; |
1526 | ||
1527 | case 6: /*XSR*/ | |
97e89ee9 MF |
1528 | if (gen_check_sr(dc, RSR_SR, SR_X) && |
1529 | (RSR_SR < 64 || gen_check_privilege(dc)) && | |
1530 | gen_window_check1(dc, RRR_T)) { | |
3580ecad | 1531 | TCGv_i32 tmp = tcg_temp_new_i32(); |
0857a06e | 1532 | |
3580ecad MF |
1533 | tcg_gen_mov_i32(tmp, cpu_R[RRR_T]); |
1534 | gen_rsr(dc, cpu_R[RRR_T], RSR_SR); | |
1535 | gen_wsr(dc, RSR_SR, tmp); | |
1536 | tcg_temp_free(tmp); | |
1537 | } | |
1538 | break; | |
1539 | ||
1540 | /* | |
1541 | * Note: 64 bit ops are used here solely because SAR values | |
1542 | * have range 0..63 | |
1543 | */ | |
1544 | #define gen_shift_reg(cmd, reg) do { \ | |
1545 | TCGv_i64 tmp = tcg_temp_new_i64(); \ | |
1546 | tcg_gen_extu_i32_i64(tmp, reg); \ | |
1547 | tcg_gen_##cmd##_i64(v, v, tmp); \ | |
ecc7b3aa | 1548 | tcg_gen_extrl_i64_i32(cpu_R[RRR_R], v); \ |
3580ecad MF |
1549 | tcg_temp_free_i64(v); \ |
1550 | tcg_temp_free_i64(tmp); \ | |
1551 | } while (0) | |
1552 | ||
1553 | #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR]) | |
1554 | ||
1555 | case 8: /*SRC*/ | |
97e89ee9 | 1556 | if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { |
3580ecad MF |
1557 | TCGv_i64 v = tcg_temp_new_i64(); |
1558 | tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]); | |
1559 | gen_shift(shr); | |
1560 | } | |
1561 | break; | |
1562 | ||
1563 | case 9: /*SRL*/ | |
97e89ee9 MF |
1564 | if (!gen_window_check2(dc, RRR_R, RRR_T)) { |
1565 | break; | |
1566 | } | |
3580ecad MF |
1567 | if (dc->sar_5bit) { |
1568 | tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]); | |
1569 | } else { | |
1570 | TCGv_i64 v = tcg_temp_new_i64(); | |
1571 | tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]); | |
1572 | gen_shift(shr); | |
1573 | } | |
1574 | break; | |
1575 | ||
1576 | case 10: /*SLL*/ | |
97e89ee9 MF |
1577 | if (!gen_window_check2(dc, RRR_R, RRR_S)) { |
1578 | break; | |
1579 | } | |
3580ecad MF |
1580 | if (dc->sar_m32_5bit) { |
1581 | tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32); | |
1582 | } else { | |
1583 | TCGv_i64 v = tcg_temp_new_i64(); | |
1584 | TCGv_i32 s = tcg_const_i32(32); | |
1585 | tcg_gen_sub_i32(s, s, cpu_SR[SAR]); | |
1586 | tcg_gen_andi_i32(s, s, 0x3f); | |
1587 | tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]); | |
1588 | gen_shift_reg(shl, s); | |
1589 | tcg_temp_free(s); | |
1590 | } | |
1591 | break; | |
1592 | ||
1593 | case 11: /*SRA*/ | |
97e89ee9 MF |
1594 | if (!gen_window_check2(dc, RRR_R, RRR_T)) { |
1595 | break; | |
1596 | } | |
3580ecad MF |
1597 | if (dc->sar_5bit) { |
1598 | tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]); | |
1599 | } else { | |
1600 | TCGv_i64 v = tcg_temp_new_i64(); | |
1601 | tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]); | |
1602 | gen_shift(sar); | |
1603 | } | |
1604 | break; | |
1605 | #undef gen_shift | |
1606 | #undef gen_shift_reg | |
1607 | ||
1608 | case 12: /*MUL16U*/ | |
1609 | HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL); | |
97e89ee9 | 1610 | if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { |
3580ecad MF |
1611 | TCGv_i32 v1 = tcg_temp_new_i32(); |
1612 | TCGv_i32 v2 = tcg_temp_new_i32(); | |
1613 | tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]); | |
1614 | tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]); | |
1615 | tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2); | |
1616 | tcg_temp_free(v2); | |
1617 | tcg_temp_free(v1); | |
1618 | } | |
1619 | break; | |
1620 | ||
1621 | case 13: /*MUL16S*/ | |
1622 | HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL); | |
97e89ee9 | 1623 | if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { |
3580ecad MF |
1624 | TCGv_i32 v1 = tcg_temp_new_i32(); |
1625 | TCGv_i32 v2 = tcg_temp_new_i32(); | |
1626 | tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]); | |
1627 | tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]); | |
1628 | tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2); | |
1629 | tcg_temp_free(v2); | |
1630 | tcg_temp_free(v1); | |
1631 | } | |
1632 | break; | |
1633 | ||
1634 | default: /*reserved*/ | |
91a5bb76 | 1635 | RESERVED(); |
3580ecad MF |
1636 | break; |
1637 | } | |
dedc5eae MF |
1638 | break; |
1639 | ||
1640 | case 2: /*RST2*/ | |
97e89ee9 MF |
1641 | if (OP2 >= 8 && !gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { |
1642 | break; | |
4dd85b6b | 1643 | } |
772177c1 | 1644 | |
f76ebf55 MF |
1645 | if (OP2 >= 12) { |
1646 | HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV); | |
42a268c2 | 1647 | TCGLabel *label = gen_new_label(); |
f76ebf55 MF |
1648 | tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label); |
1649 | gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE); | |
1650 | gen_set_label(label); | |
1651 | } | |
1652 | ||
1653 | switch (OP2) { | |
4dd85b6b MF |
1654 | #define BOOLEAN_LOGIC(fn, r, s, t) \ |
1655 | do { \ | |
1656 | HAS_OPTION(XTENSA_OPTION_BOOLEAN); \ | |
1657 | TCGv_i32 tmp1 = tcg_temp_new_i32(); \ | |
1658 | TCGv_i32 tmp2 = tcg_temp_new_i32(); \ | |
1659 | \ | |
1660 | tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \ | |
1661 | tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \ | |
1662 | tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \ | |
1663 | tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \ | |
1664 | tcg_temp_free(tmp1); \ | |
1665 | tcg_temp_free(tmp2); \ | |
1666 | } while (0) | |
1667 | ||
1668 | case 0: /*ANDBp*/ | |
1669 | BOOLEAN_LOGIC(and, RRR_R, RRR_S, RRR_T); | |
1670 | break; | |
1671 | ||
1672 | case 1: /*ANDBCp*/ | |
1673 | BOOLEAN_LOGIC(andc, RRR_R, RRR_S, RRR_T); | |
1674 | break; | |
1675 | ||
1676 | case 2: /*ORBp*/ | |
1677 | BOOLEAN_LOGIC(or, RRR_R, RRR_S, RRR_T); | |
1678 | break; | |
1679 | ||
1680 | case 3: /*ORBCp*/ | |
1681 | BOOLEAN_LOGIC(orc, RRR_R, RRR_S, RRR_T); | |
1682 | break; | |
1683 | ||
1684 | case 4: /*XORBp*/ | |
1685 | BOOLEAN_LOGIC(xor, RRR_R, RRR_S, RRR_T); | |
1686 | break; | |
1687 | ||
1688 | #undef BOOLEAN_LOGIC | |
1689 | ||
f76ebf55 MF |
1690 | case 8: /*MULLi*/ |
1691 | HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL); | |
1692 | tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); | |
1693 | break; | |
1694 | ||
1695 | case 10: /*MULUHi*/ | |
1696 | case 11: /*MULSHi*/ | |
7f65f4b0 | 1697 | HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH); |
f76ebf55 | 1698 | { |
c9cda20b | 1699 | TCGv lo = tcg_temp_new(); |
f76ebf55 MF |
1700 | |
1701 | if (OP2 == 10) { | |
c9cda20b RH |
1702 | tcg_gen_mulu2_i32(lo, cpu_R[RRR_R], |
1703 | cpu_R[RRR_S], cpu_R[RRR_T]); | |
f76ebf55 | 1704 | } else { |
c9cda20b RH |
1705 | tcg_gen_muls2_i32(lo, cpu_R[RRR_R], |
1706 | cpu_R[RRR_S], cpu_R[RRR_T]); | |
f76ebf55 | 1707 | } |
c9cda20b | 1708 | tcg_temp_free(lo); |
f76ebf55 MF |
1709 | } |
1710 | break; | |
1711 | ||
1712 | case 12: /*QUOUi*/ | |
1713 | tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); | |
1714 | break; | |
1715 | ||
1716 | case 13: /*QUOSi*/ | |
1717 | case 15: /*REMSi*/ | |
1718 | { | |
42a268c2 RH |
1719 | TCGLabel *label1 = gen_new_label(); |
1720 | TCGLabel *label2 = gen_new_label(); | |
f76ebf55 MF |
1721 | |
1722 | tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000, | |
1723 | label1); | |
1724 | tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff, | |
1725 | label1); | |
1726 | tcg_gen_movi_i32(cpu_R[RRR_R], | |
1727 | OP2 == 13 ? 0x80000000 : 0); | |
1728 | tcg_gen_br(label2); | |
1729 | gen_set_label(label1); | |
1730 | if (OP2 == 13) { | |
1731 | tcg_gen_div_i32(cpu_R[RRR_R], | |
1732 | cpu_R[RRR_S], cpu_R[RRR_T]); | |
1733 | } else { | |
1734 | tcg_gen_rem_i32(cpu_R[RRR_R], | |
1735 | cpu_R[RRR_S], cpu_R[RRR_T]); | |
1736 | } | |
1737 | gen_set_label(label2); | |
1738 | } | |
1739 | break; | |
1740 | ||
1741 | case 14: /*REMUi*/ | |
1742 | tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); | |
1743 | break; | |
1744 | ||
1745 | default: /*reserved*/ | |
1746 | RESERVED(); | |
1747 | break; | |
1748 | } | |
dedc5eae MF |
1749 | break; |
1750 | ||
1751 | case 3: /*RST3*/ | |
b8132eff MF |
1752 | switch (OP2) { |
1753 | case 0: /*RSR*/ | |
97e89ee9 MF |
1754 | if (gen_check_sr(dc, RSR_SR, SR_R) && |
1755 | (RSR_SR < 64 || gen_check_privilege(dc)) && | |
1756 | gen_window_check1(dc, RRR_T)) { | |
0857a06e | 1757 | gen_rsr(dc, cpu_R[RRR_T], RSR_SR); |
40643d7c | 1758 | } |
b8132eff MF |
1759 | break; |
1760 | ||
1761 | case 1: /*WSR*/ | |
97e89ee9 MF |
1762 | if (gen_check_sr(dc, RSR_SR, SR_W) && |
1763 | (RSR_SR < 64 || gen_check_privilege(dc)) && | |
1764 | gen_window_check1(dc, RRR_T)) { | |
0857a06e | 1765 | gen_wsr(dc, RSR_SR, cpu_R[RRR_T]); |
40643d7c | 1766 | } |
b8132eff MF |
1767 | break; |
1768 | ||
1769 | case 2: /*SEXTu*/ | |
7f65f4b0 | 1770 | HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT); |
97e89ee9 | 1771 | if (gen_window_check2(dc, RRR_R, RRR_S)) { |
b8132eff MF |
1772 | int shift = 24 - RRR_T; |
1773 | ||
1774 | if (shift == 24) { | |
1775 | tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]); | |
1776 | } else if (shift == 16) { | |
1777 | tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]); | |
1778 | } else { | |
1779 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
1780 | tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift); | |
1781 | tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift); | |
1782 | tcg_temp_free(tmp); | |
1783 | } | |
1784 | } | |
1785 | break; | |
1786 | ||
1787 | case 3: /*CLAMPSu*/ | |
7f65f4b0 | 1788 | HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS); |
97e89ee9 | 1789 | if (gen_window_check2(dc, RRR_R, RRR_S)) { |
b8132eff MF |
1790 | TCGv_i32 tmp1 = tcg_temp_new_i32(); |
1791 | TCGv_i32 tmp2 = tcg_temp_new_i32(); | |
f877d09e | 1792 | TCGv_i32 zero = tcg_const_i32(0); |
b8132eff MF |
1793 | |
1794 | tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T); | |
1795 | tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]); | |
1796 | tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7)); | |
b8132eff MF |
1797 | |
1798 | tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31); | |
f877d09e | 1799 | tcg_gen_xori_i32(tmp1, tmp1, 0xffffffff >> (25 - RRR_T)); |
b8132eff | 1800 | |
f877d09e MF |
1801 | tcg_gen_movcond_i32(TCG_COND_EQ, cpu_R[RRR_R], tmp2, zero, |
1802 | cpu_R[RRR_S], tmp1); | |
b8132eff MF |
1803 | tcg_temp_free(tmp1); |
1804 | tcg_temp_free(tmp2); | |
f877d09e | 1805 | tcg_temp_free(zero); |
b8132eff MF |
1806 | } |
1807 | break; | |
1808 | ||
1809 | case 4: /*MINu*/ | |
1810 | case 5: /*MAXu*/ | |
1811 | case 6: /*MINUu*/ | |
1812 | case 7: /*MAXUu*/ | |
7f65f4b0 | 1813 | HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX); |
97e89ee9 | 1814 | if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { |
b8132eff MF |
1815 | static const TCGCond cond[] = { |
1816 | TCG_COND_LE, | |
1817 | TCG_COND_GE, | |
1818 | TCG_COND_LEU, | |
1819 | TCG_COND_GEU | |
1820 | }; | |
f877d09e MF |
1821 | tcg_gen_movcond_i32(cond[OP2 - 4], cpu_R[RRR_R], |
1822 | cpu_R[RRR_S], cpu_R[RRR_T], | |
1823 | cpu_R[RRR_S], cpu_R[RRR_T]); | |
b8132eff MF |
1824 | } |
1825 | break; | |
1826 | ||
1827 | case 8: /*MOVEQZ*/ | |
1828 | case 9: /*MOVNEZ*/ | |
1829 | case 10: /*MOVLTZ*/ | |
1830 | case 11: /*MOVGEZ*/ | |
97e89ee9 | 1831 | if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { |
b8132eff | 1832 | static const TCGCond cond[] = { |
b8132eff | 1833 | TCG_COND_EQ, |
f877d09e MF |
1834 | TCG_COND_NE, |
1835 | TCG_COND_LT, | |
b8132eff | 1836 | TCG_COND_GE, |
b8132eff | 1837 | }; |
f877d09e MF |
1838 | TCGv_i32 zero = tcg_const_i32(0); |
1839 | ||
1840 | tcg_gen_movcond_i32(cond[OP2 - 8], cpu_R[RRR_R], | |
1841 | cpu_R[RRR_T], zero, cpu_R[RRR_S], cpu_R[RRR_R]); | |
1842 | tcg_temp_free(zero); | |
b8132eff MF |
1843 | } |
1844 | break; | |
1845 | ||
1846 | case 12: /*MOVFp*/ | |
b8132eff MF |
1847 | case 13: /*MOVTp*/ |
1848 | HAS_OPTION(XTENSA_OPTION_BOOLEAN); | |
97e89ee9 | 1849 | if (gen_window_check2(dc, RRR_R, RRR_S)) { |
f877d09e | 1850 | TCGv_i32 zero = tcg_const_i32(0); |
4dd85b6b MF |
1851 | TCGv_i32 tmp = tcg_temp_new_i32(); |
1852 | ||
1853 | tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T); | |
f877d09e MF |
1854 | tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ, |
1855 | cpu_R[RRR_R], tmp, zero, | |
1856 | cpu_R[RRR_S], cpu_R[RRR_R]); | |
1857 | ||
4dd85b6b | 1858 | tcg_temp_free(tmp); |
f877d09e | 1859 | tcg_temp_free(zero); |
4dd85b6b | 1860 | } |
b8132eff MF |
1861 | break; |
1862 | ||
1863 | case 14: /*RUR*/ | |
97e89ee9 | 1864 | if (gen_window_check1(dc, RRR_R)) { |
b8132eff | 1865 | int st = (RRR_S << 4) + RRR_T; |
fe0bd475 | 1866 | if (uregnames[st].name) { |
b8132eff MF |
1867 | tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]); |
1868 | } else { | |
c30f0d18 | 1869 | qemu_log_mask(LOG_UNIMP, "RUR %d not implemented, ", st); |
91a5bb76 | 1870 | TBD(); |
b8132eff MF |
1871 | } |
1872 | } | |
1873 | break; | |
1874 | ||
1875 | case 15: /*WUR*/ | |
97e89ee9 MF |
1876 | if (gen_window_check1(dc, RRR_T)) { |
1877 | if (uregnames[RSR_SR].name) { | |
1878 | gen_wur(RSR_SR, cpu_R[RRR_T]); | |
1879 | } else { | |
c30f0d18 | 1880 | qemu_log_mask(LOG_UNIMP, "WUR %d not implemented, ", RSR_SR); |
97e89ee9 MF |
1881 | TBD(); |
1882 | } | |
b8132eff MF |
1883 | } |
1884 | break; | |
1885 | ||
1886 | } | |
dedc5eae MF |
1887 | break; |
1888 | ||
1889 | case 4: /*EXTUI*/ | |
1890 | case 5: | |
97e89ee9 | 1891 | if (gen_window_check2(dc, RRR_R, RRR_T)) { |
f9cb5045 | 1892 | int shiftimm = RRR_S | ((OP1 & 1) << 4); |
3580ecad MF |
1893 | int maskimm = (1 << (OP2 + 1)) - 1; |
1894 | ||
1895 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
f783cb22 AJ |
1896 | tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm); |
1897 | tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm); | |
3580ecad MF |
1898 | tcg_temp_free(tmp); |
1899 | } | |
dedc5eae MF |
1900 | break; |
1901 | ||
1902 | case 6: /*CUST0*/ | |
91a5bb76 | 1903 | RESERVED(); |
dedc5eae MF |
1904 | break; |
1905 | ||
1906 | case 7: /*CUST1*/ | |
91a5bb76 | 1907 | RESERVED(); |
dedc5eae MF |
1908 | break; |
1909 | ||
1910 | case 8: /*LSCXp*/ | |
9ed7ae12 MF |
1911 | switch (OP2) { |
1912 | case 0: /*LSXf*/ | |
1913 | case 1: /*LSXUf*/ | |
1914 | case 4: /*SSXf*/ | |
1915 | case 5: /*SSXUf*/ | |
1916 | HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); | |
97e89ee9 MF |
1917 | if (gen_window_check2(dc, RRR_S, RRR_T) && |
1918 | gen_check_cpenable(dc, 0)) { | |
9ed7ae12 MF |
1919 | TCGv_i32 addr = tcg_temp_new_i32(); |
1920 | tcg_gen_add_i32(addr, cpu_R[RRR_S], cpu_R[RRR_T]); | |
1921 | gen_load_store_alignment(dc, 2, addr, false); | |
1922 | if (OP2 & 0x4) { | |
1923 | tcg_gen_qemu_st32(cpu_FR[RRR_R], addr, dc->cring); | |
1924 | } else { | |
1925 | tcg_gen_qemu_ld32u(cpu_FR[RRR_R], addr, dc->cring); | |
1926 | } | |
1927 | if (OP2 & 0x1) { | |
1928 | tcg_gen_mov_i32(cpu_R[RRR_S], addr); | |
1929 | } | |
1930 | tcg_temp_free(addr); | |
1931 | } | |
1932 | break; | |
1933 | ||
1934 | default: /*reserved*/ | |
1935 | RESERVED(); | |
1936 | break; | |
1937 | } | |
dedc5eae MF |
1938 | break; |
1939 | ||
1940 | case 9: /*LSC4*/ | |
97e89ee9 MF |
1941 | if (!gen_window_check2(dc, RRR_S, RRR_T)) { |
1942 | break; | |
1943 | } | |
553e44f9 MF |
1944 | switch (OP2) { |
1945 | case 0: /*L32E*/ | |
1946 | HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); | |
f822b7e4 MF |
1947 | if (gen_check_privilege(dc) && |
1948 | gen_window_check2(dc, RRR_S, RRR_T)) { | |
553e44f9 MF |
1949 | TCGv_i32 addr = tcg_temp_new_i32(); |
1950 | tcg_gen_addi_i32(addr, cpu_R[RRR_S], | |
1951 | (0xffffffc0 | (RRR_R << 2))); | |
1952 | tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring); | |
1953 | tcg_temp_free(addr); | |
1954 | } | |
1955 | break; | |
1956 | ||
1957 | case 4: /*S32E*/ | |
1958 | HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); | |
f822b7e4 MF |
1959 | if (gen_check_privilege(dc) && |
1960 | gen_window_check2(dc, RRR_S, RRR_T)) { | |
553e44f9 MF |
1961 | TCGv_i32 addr = tcg_temp_new_i32(); |
1962 | tcg_gen_addi_i32(addr, cpu_R[RRR_S], | |
1963 | (0xffffffc0 | (RRR_R << 2))); | |
1964 | tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring); | |
1965 | tcg_temp_free(addr); | |
1966 | } | |
1967 | break; | |
1968 | ||
19b7bec4 MF |
1969 | case 5: /*S32N*/ |
1970 | if (gen_window_check2(dc, RRI4_S, RRI4_T)) { | |
1971 | TCGv_i32 addr = tcg_temp_new_i32(); | |
1972 | ||
1973 | tcg_gen_addi_i32(addr, cpu_R[RRI4_S], RRI4_IMM4 << 2); | |
1974 | gen_load_store_alignment(dc, 2, addr, false); | |
1975 | tcg_gen_qemu_st32(cpu_R[RRI4_T], addr, dc->cring); | |
1976 | tcg_temp_free(addr); | |
1977 | } | |
1978 | break; | |
1979 | ||
553e44f9 MF |
1980 | default: |
1981 | RESERVED(); | |
1982 | break; | |
1983 | } | |
dedc5eae MF |
1984 | break; |
1985 | ||
1986 | case 10: /*FP0*/ | |
5eeb40c5 MF |
1987 | /*DEPBITS*/ |
1988 | if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) { | |
1989 | if (!gen_window_check2(dc, RRR_S, RRR_T)) { | |
1990 | break; | |
1991 | } | |
1992 | tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S], | |
1993 | OP2, RRR_R + 1); | |
1994 | break; | |
1995 | } | |
1996 | ||
dedc5eae | 1997 | HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); |
0b6df838 MF |
1998 | switch (OP2) { |
1999 | case 0: /*ADD.Sf*/ | |
97e89ee9 MF |
2000 | if (gen_check_cpenable(dc, 0)) { |
2001 | gen_helper_add_s(cpu_FR[RRR_R], cpu_env, | |
2002 | cpu_FR[RRR_S], cpu_FR[RRR_T]); | |
2003 | } | |
0b6df838 MF |
2004 | break; |
2005 | ||
2006 | case 1: /*SUB.Sf*/ | |
97e89ee9 MF |
2007 | if (gen_check_cpenable(dc, 0)) { |
2008 | gen_helper_sub_s(cpu_FR[RRR_R], cpu_env, | |
2009 | cpu_FR[RRR_S], cpu_FR[RRR_T]); | |
2010 | } | |
0b6df838 MF |
2011 | break; |
2012 | ||
2013 | case 2: /*MUL.Sf*/ | |
97e89ee9 MF |
2014 | if (gen_check_cpenable(dc, 0)) { |
2015 | gen_helper_mul_s(cpu_FR[RRR_R], cpu_env, | |
2016 | cpu_FR[RRR_S], cpu_FR[RRR_T]); | |
2017 | } | |
0b6df838 MF |
2018 | break; |
2019 | ||
2020 | case 4: /*MADD.Sf*/ | |
97e89ee9 MF |
2021 | if (gen_check_cpenable(dc, 0)) { |
2022 | gen_helper_madd_s(cpu_FR[RRR_R], cpu_env, | |
2023 | cpu_FR[RRR_R], cpu_FR[RRR_S], | |
2024 | cpu_FR[RRR_T]); | |
2025 | } | |
0b6df838 MF |
2026 | break; |
2027 | ||
2028 | case 5: /*MSUB.Sf*/ | |
97e89ee9 MF |
2029 | if (gen_check_cpenable(dc, 0)) { |
2030 | gen_helper_msub_s(cpu_FR[RRR_R], cpu_env, | |
2031 | cpu_FR[RRR_R], cpu_FR[RRR_S], | |
2032 | cpu_FR[RRR_T]); | |
2033 | } | |
0b6df838 MF |
2034 | break; |
2035 | ||
b7ee8c6a MF |
2036 | case 8: /*ROUND.Sf*/ |
2037 | case 9: /*TRUNC.Sf*/ | |
2038 | case 10: /*FLOOR.Sf*/ | |
2039 | case 11: /*CEIL.Sf*/ | |
2040 | case 14: /*UTRUNC.Sf*/ | |
97e89ee9 MF |
2041 | if (gen_window_check1(dc, RRR_R) && |
2042 | gen_check_cpenable(dc, 0)) { | |
b7ee8c6a MF |
2043 | static const unsigned rounding_mode_const[] = { |
2044 | float_round_nearest_even, | |
2045 | float_round_to_zero, | |
2046 | float_round_down, | |
2047 | float_round_up, | |
2048 | [6] = float_round_to_zero, | |
2049 | }; | |
2050 | TCGv_i32 rounding_mode = tcg_const_i32( | |
2051 | rounding_mode_const[OP2 & 7]); | |
2052 | TCGv_i32 scale = tcg_const_i32(RRR_T); | |
2053 | ||
2054 | if (OP2 == 14) { | |
2055 | gen_helper_ftoui(cpu_R[RRR_R], cpu_FR[RRR_S], | |
2056 | rounding_mode, scale); | |
2057 | } else { | |
2058 | gen_helper_ftoi(cpu_R[RRR_R], cpu_FR[RRR_S], | |
2059 | rounding_mode, scale); | |
2060 | } | |
2061 | ||
2062 | tcg_temp_free(rounding_mode); | |
2063 | tcg_temp_free(scale); | |
2064 | } | |
2065 | break; | |
2066 | ||
2067 | case 12: /*FLOAT.Sf*/ | |
2068 | case 13: /*UFLOAT.Sf*/ | |
97e89ee9 MF |
2069 | if (gen_window_check1(dc, RRR_S) && |
2070 | gen_check_cpenable(dc, 0)) { | |
b7ee8c6a MF |
2071 | TCGv_i32 scale = tcg_const_i32(-RRR_T); |
2072 | ||
2073 | if (OP2 == 13) { | |
2074 | gen_helper_uitof(cpu_FR[RRR_R], cpu_env, | |
2075 | cpu_R[RRR_S], scale); | |
2076 | } else { | |
2077 | gen_helper_itof(cpu_FR[RRR_R], cpu_env, | |
2078 | cpu_R[RRR_S], scale); | |
2079 | } | |
2080 | tcg_temp_free(scale); | |
2081 | } | |
2082 | break; | |
2083 | ||
0b6df838 MF |
2084 | case 15: /*FP1OP*/ |
2085 | switch (RRR_T) { | |
2086 | case 0: /*MOV.Sf*/ | |
97e89ee9 MF |
2087 | if (gen_check_cpenable(dc, 0)) { |
2088 | tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]); | |
2089 | } | |
0b6df838 MF |
2090 | break; |
2091 | ||
2092 | case 1: /*ABS.Sf*/ | |
97e89ee9 MF |
2093 | if (gen_check_cpenable(dc, 0)) { |
2094 | gen_helper_abs_s(cpu_FR[RRR_R], cpu_FR[RRR_S]); | |
2095 | } | |
0b6df838 MF |
2096 | break; |
2097 | ||
2098 | case 4: /*RFRf*/ | |
97e89ee9 MF |
2099 | if (gen_window_check1(dc, RRR_R) && |
2100 | gen_check_cpenable(dc, 0)) { | |
2101 | tcg_gen_mov_i32(cpu_R[RRR_R], cpu_FR[RRR_S]); | |
2102 | } | |
0b6df838 MF |
2103 | break; |
2104 | ||
2105 | case 5: /*WFRf*/ | |
97e89ee9 MF |
2106 | if (gen_window_check1(dc, RRR_S) && |
2107 | gen_check_cpenable(dc, 0)) { | |
2108 | tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_R[RRR_S]); | |
2109 | } | |
0b6df838 MF |
2110 | break; |
2111 | ||
2112 | case 6: /*NEG.Sf*/ | |
97e89ee9 MF |
2113 | if (gen_check_cpenable(dc, 0)) { |
2114 | gen_helper_neg_s(cpu_FR[RRR_R], cpu_FR[RRR_S]); | |
2115 | } | |
0b6df838 MF |
2116 | break; |
2117 | ||
2118 | default: /*reserved*/ | |
2119 | RESERVED(); | |
2120 | break; | |
2121 | } | |
2122 | break; | |
2123 | ||
2124 | default: /*reserved*/ | |
2125 | RESERVED(); | |
2126 | break; | |
2127 | } | |
dedc5eae MF |
2128 | break; |
2129 | ||
2130 | case 11: /*FP1*/ | |
5eeb40c5 MF |
2131 | /*DEPBITS*/ |
2132 | if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) { | |
2133 | if (!gen_window_check2(dc, RRR_S, RRR_T)) { | |
2134 | break; | |
2135 | } | |
2136 | tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S], | |
2137 | OP2 + 16, RRR_R + 1); | |
2138 | break; | |
2139 | } | |
2140 | ||
dedc5eae | 2141 | HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); |
4e273869 MF |
2142 | |
2143 | #define gen_compare(rel, br, a, b) \ | |
2144 | do { \ | |
97e89ee9 MF |
2145 | if (gen_check_cpenable(dc, 0)) { \ |
2146 | TCGv_i32 bit = tcg_const_i32(1 << br); \ | |
2147 | \ | |
2148 | gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \ | |
2149 | tcg_temp_free(bit); \ | |
2150 | } \ | |
4e273869 MF |
2151 | } while (0) |
2152 | ||
2153 | switch (OP2) { | |
2154 | case 1: /*UN.Sf*/ | |
2155 | gen_compare(un_s, RRR_R, RRR_S, RRR_T); | |
2156 | break; | |
2157 | ||
2158 | case 2: /*OEQ.Sf*/ | |
2159 | gen_compare(oeq_s, RRR_R, RRR_S, RRR_T); | |
2160 | break; | |
2161 | ||
2162 | case 3: /*UEQ.Sf*/ | |
2163 | gen_compare(ueq_s, RRR_R, RRR_S, RRR_T); | |
2164 | break; | |
2165 | ||
2166 | case 4: /*OLT.Sf*/ | |
2167 | gen_compare(olt_s, RRR_R, RRR_S, RRR_T); | |
2168 | break; | |
2169 | ||
2170 | case 5: /*ULT.Sf*/ | |
2171 | gen_compare(ult_s, RRR_R, RRR_S, RRR_T); | |
2172 | break; | |
2173 | ||
2174 | case 6: /*OLE.Sf*/ | |
2175 | gen_compare(ole_s, RRR_R, RRR_S, RRR_T); | |
2176 | break; | |
2177 | ||
2178 | case 7: /*ULE.Sf*/ | |
2179 | gen_compare(ule_s, RRR_R, RRR_S, RRR_T); | |
2180 | break; | |
2181 | ||
2182 | #undef gen_compare | |
2183 | ||
2184 | case 8: /*MOVEQZ.Sf*/ | |
2185 | case 9: /*MOVNEZ.Sf*/ | |
2186 | case 10: /*MOVLTZ.Sf*/ | |
2187 | case 11: /*MOVGEZ.Sf*/ | |
97e89ee9 MF |
2188 | if (gen_window_check1(dc, RRR_T) && |
2189 | gen_check_cpenable(dc, 0)) { | |
4e273869 | 2190 | static const TCGCond cond[] = { |
4e273869 | 2191 | TCG_COND_EQ, |
f877d09e MF |
2192 | TCG_COND_NE, |
2193 | TCG_COND_LT, | |
4e273869 | 2194 | TCG_COND_GE, |
4e273869 | 2195 | }; |
f877d09e MF |
2196 | TCGv_i32 zero = tcg_const_i32(0); |
2197 | ||
2198 | tcg_gen_movcond_i32(cond[OP2 - 8], cpu_FR[RRR_R], | |
2199 | cpu_R[RRR_T], zero, cpu_FR[RRR_S], cpu_FR[RRR_R]); | |
2200 | tcg_temp_free(zero); | |
4e273869 MF |
2201 | } |
2202 | break; | |
2203 | ||
2204 | case 12: /*MOVF.Sf*/ | |
2205 | case 13: /*MOVT.Sf*/ | |
2206 | HAS_OPTION(XTENSA_OPTION_BOOLEAN); | |
97e89ee9 | 2207 | if (gen_check_cpenable(dc, 0)) { |
f877d09e | 2208 | TCGv_i32 zero = tcg_const_i32(0); |
4e273869 MF |
2209 | TCGv_i32 tmp = tcg_temp_new_i32(); |
2210 | ||
2211 | tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T); | |
f877d09e MF |
2212 | tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ, |
2213 | cpu_FR[RRR_R], tmp, zero, | |
2214 | cpu_FR[RRR_S], cpu_FR[RRR_R]); | |
2215 | ||
4e273869 | 2216 | tcg_temp_free(tmp); |
f877d09e | 2217 | tcg_temp_free(zero); |
4e273869 MF |
2218 | } |
2219 | break; | |
2220 | ||
2221 | default: /*reserved*/ | |
2222 | RESERVED(); | |
2223 | break; | |
2224 | } | |
dedc5eae MF |
2225 | break; |
2226 | ||
2227 | default: /*reserved*/ | |
91a5bb76 | 2228 | RESERVED(); |
dedc5eae MF |
2229 | break; |
2230 | } | |
2231 | break; | |
2232 | ||
2233 | case 1: /*L32R*/ | |
97e89ee9 | 2234 | if (gen_window_check1(dc, RRR_T)) { |
dedc5eae | 2235 | TCGv_i32 tmp = tcg_const_i32( |
6ad6dbf7 MF |
2236 | ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ? |
2237 | 0 : ((dc->pc + 3) & ~3)) + | |
2238 | (0xfffc0000 | (RI16_IMM16 << 2))); | |
dedc5eae | 2239 | |
6ad6dbf7 MF |
2240 | if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { |
2241 | tcg_gen_add_i32(tmp, tmp, dc->litbase); | |
2242 | } | |
f0a548b9 | 2243 | tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring); |
dedc5eae MF |
2244 | tcg_temp_free(tmp); |
2245 | } | |
2246 | break; | |
2247 | ||
2248 | case 2: /*LSAI*/ | |
809377aa | 2249 | #define gen_load_store(type, shift) do { \ |
97e89ee9 MF |
2250 | if (gen_window_check2(dc, RRI8_S, RRI8_T)) { \ |
2251 | TCGv_i32 addr = tcg_temp_new_i32(); \ | |
2252 | \ | |
2253 | tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \ | |
2254 | if (shift) { \ | |
2255 | gen_load_store_alignment(dc, shift, addr, false); \ | |
2256 | } \ | |
2257 | tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \ | |
2258 | tcg_temp_free(addr); \ | |
5b4e481b | 2259 | } \ |
809377aa MF |
2260 | } while (0) |
2261 | ||
2262 | switch (RRI8_R) { | |
2263 | case 0: /*L8UI*/ | |
2264 | gen_load_store(ld8u, 0); | |
2265 | break; | |
2266 | ||
2267 | case 1: /*L16UI*/ | |
2268 | gen_load_store(ld16u, 1); | |
2269 | break; | |
2270 | ||
2271 | case 2: /*L32I*/ | |
2272 | gen_load_store(ld32u, 2); | |
2273 | break; | |
2274 | ||
2275 | case 4: /*S8I*/ | |
2276 | gen_load_store(st8, 0); | |
2277 | break; | |
2278 | ||
2279 | case 5: /*S16I*/ | |
2280 | gen_load_store(st16, 1); | |
2281 | break; | |
2282 | ||
2283 | case 6: /*S32I*/ | |
2284 | gen_load_store(st32, 2); | |
2285 | break; | |
2286 | ||
7c842590 | 2287 | #define gen_dcache_hit_test(w, shift) do { \ |
97e89ee9 MF |
2288 | if (gen_window_check1(dc, RRI##w##_S)) { \ |
2289 | TCGv_i32 addr = tcg_temp_new_i32(); \ | |
2290 | TCGv_i32 res = tcg_temp_new_i32(); \ | |
2291 | tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \ | |
2292 | RRI##w##_IMM##w << shift); \ | |
2293 | tcg_gen_qemu_ld8u(res, addr, dc->cring); \ | |
2294 | tcg_temp_free(addr); \ | |
2295 | tcg_temp_free(res); \ | |
2296 | } \ | |
7c842590 MF |
2297 | } while (0) |
2298 | ||
2299 | #define gen_dcache_hit_test4() gen_dcache_hit_test(4, 4) | |
2300 | #define gen_dcache_hit_test8() gen_dcache_hit_test(8, 2) | |
2301 | ||
809377aa | 2302 | case 7: /*CACHEc*/ |
8ffc2d0d MF |
2303 | if (RRI8_T < 8) { |
2304 | HAS_OPTION(XTENSA_OPTION_DCACHE); | |
2305 | } | |
2306 | ||
2307 | switch (RRI8_T) { | |
2308 | case 0: /*DPFRc*/ | |
7c842590 | 2309 | gen_window_check1(dc, RRI8_S); |
8ffc2d0d MF |
2310 | break; |
2311 | ||
2312 | case 1: /*DPFWc*/ | |
7c842590 | 2313 | gen_window_check1(dc, RRI8_S); |
8ffc2d0d MF |
2314 | break; |
2315 | ||
2316 | case 2: /*DPFROc*/ | |
7c842590 | 2317 | gen_window_check1(dc, RRI8_S); |
8ffc2d0d MF |
2318 | break; |
2319 | ||
2320 | case 3: /*DPFWOc*/ | |
7c842590 | 2321 | gen_window_check1(dc, RRI8_S); |
8ffc2d0d MF |
2322 | break; |
2323 | ||
2324 | case 4: /*DHWBc*/ | |
7c842590 | 2325 | gen_dcache_hit_test8(); |
8ffc2d0d MF |
2326 | break; |
2327 | ||
2328 | case 5: /*DHWBIc*/ | |
7c842590 | 2329 | gen_dcache_hit_test8(); |
8ffc2d0d MF |
2330 | break; |
2331 | ||
2332 | case 6: /*DHIc*/ | |
97e89ee9 MF |
2333 | if (gen_check_privilege(dc)) { |
2334 | gen_dcache_hit_test8(); | |
2335 | } | |
8ffc2d0d MF |
2336 | break; |
2337 | ||
2338 | case 7: /*DIIc*/ | |
97e89ee9 MF |
2339 | if (gen_check_privilege(dc)) { |
2340 | gen_window_check1(dc, RRI8_S); | |
2341 | } | |
8ffc2d0d MF |
2342 | break; |
2343 | ||
2344 | case 8: /*DCEc*/ | |
2345 | switch (OP1) { | |
2346 | case 0: /*DPFLl*/ | |
2347 | HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK); | |
97e89ee9 MF |
2348 | if (gen_check_privilege(dc)) { |
2349 | gen_dcache_hit_test4(); | |
2350 | } | |
8ffc2d0d MF |
2351 | break; |
2352 | ||
2353 | case 2: /*DHUl*/ | |
2354 | HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK); | |
97e89ee9 MF |
2355 | if (gen_check_privilege(dc)) { |
2356 | gen_dcache_hit_test4(); | |
2357 | } | |
8ffc2d0d MF |
2358 | break; |
2359 | ||
2360 | case 3: /*DIUl*/ | |
2361 | HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK); | |
97e89ee9 MF |
2362 | if (gen_check_privilege(dc)) { |
2363 | gen_window_check1(dc, RRI4_S); | |
2364 | } | |
8ffc2d0d MF |
2365 | break; |
2366 | ||
2367 | case 4: /*DIWBc*/ | |
2368 | HAS_OPTION(XTENSA_OPTION_DCACHE); | |
97e89ee9 MF |
2369 | if (gen_check_privilege(dc)) { |
2370 | gen_window_check1(dc, RRI4_S); | |
2371 | } | |
8ffc2d0d MF |
2372 | break; |
2373 | ||
2374 | case 5: /*DIWBIc*/ | |
2375 | HAS_OPTION(XTENSA_OPTION_DCACHE); | |
97e89ee9 MF |
2376 | if (gen_check_privilege(dc)) { |
2377 | gen_window_check1(dc, RRI4_S); | |
2378 | } | |
8ffc2d0d MF |
2379 | break; |
2380 | ||
2381 | default: /*reserved*/ | |
2382 | RESERVED(); | |
2383 | break; | |
2384 | ||
2385 | } | |
2386 | break; | |
2387 | ||
7c842590 MF |
2388 | #undef gen_dcache_hit_test |
2389 | #undef gen_dcache_hit_test4 | |
2390 | #undef gen_dcache_hit_test8 | |
2391 | ||
e848dd42 | 2392 | #define gen_icache_hit_test(w, shift) do { \ |
97e89ee9 MF |
2393 | if (gen_window_check1(dc, RRI##w##_S)) { \ |
2394 | TCGv_i32 addr = tcg_temp_new_i32(); \ | |
2395 | tcg_gen_movi_i32(cpu_pc, dc->pc); \ | |
2396 | tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \ | |
2397 | RRI##w##_IMM##w << shift); \ | |
2398 | gen_helper_itlb_hit_test(cpu_env, addr); \ | |
2399 | tcg_temp_free(addr); \ | |
2400 | }\ | |
e848dd42 MF |
2401 | } while (0) |
2402 | ||
2403 | #define gen_icache_hit_test4() gen_icache_hit_test(4, 4) | |
2404 | #define gen_icache_hit_test8() gen_icache_hit_test(8, 2) | |
2405 | ||
8ffc2d0d MF |
2406 | case 12: /*IPFc*/ |
2407 | HAS_OPTION(XTENSA_OPTION_ICACHE); | |
e848dd42 | 2408 | gen_window_check1(dc, RRI8_S); |
8ffc2d0d MF |
2409 | break; |
2410 | ||
2411 | case 13: /*ICEc*/ | |
2412 | switch (OP1) { | |
2413 | case 0: /*IPFLl*/ | |
2414 | HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK); | |
97e89ee9 MF |
2415 | if (gen_check_privilege(dc)) { |
2416 | gen_icache_hit_test4(); | |
2417 | } | |
8ffc2d0d MF |
2418 | break; |
2419 | ||
2420 | case 2: /*IHUl*/ | |
2421 | HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK); | |
97e89ee9 MF |
2422 | if (gen_check_privilege(dc)) { |
2423 | gen_icache_hit_test4(); | |
2424 | } | |
8ffc2d0d MF |
2425 | break; |
2426 | ||
2427 | case 3: /*IIUl*/ | |
2428 | HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK); | |
97e89ee9 MF |
2429 | if (gen_check_privilege(dc)) { |
2430 | gen_window_check1(dc, RRI4_S); | |
2431 | } | |
8ffc2d0d MF |
2432 | break; |
2433 | ||
2434 | default: /*reserved*/ | |
2435 | RESERVED(); | |
2436 | break; | |
2437 | } | |
2438 | break; | |
2439 | ||
2440 | case 14: /*IHIc*/ | |
2441 | HAS_OPTION(XTENSA_OPTION_ICACHE); | |
e848dd42 | 2442 | gen_icache_hit_test8(); |
8ffc2d0d MF |
2443 | break; |
2444 | ||
2445 | case 15: /*IIIc*/ | |
2446 | HAS_OPTION(XTENSA_OPTION_ICACHE); | |
97e89ee9 MF |
2447 | if (gen_check_privilege(dc)) { |
2448 | gen_window_check1(dc, RRI8_S); | |
2449 | } | |
8ffc2d0d MF |
2450 | break; |
2451 | ||
2452 | default: /*reserved*/ | |
2453 | RESERVED(); | |
2454 | break; | |
2455 | } | |
809377aa MF |
2456 | break; |
2457 | ||
e848dd42 MF |
2458 | #undef gen_icache_hit_test |
2459 | #undef gen_icache_hit_test4 | |
2460 | #undef gen_icache_hit_test8 | |
2461 | ||
809377aa MF |
2462 | case 9: /*L16SI*/ |
2463 | gen_load_store(ld16s, 1); | |
2464 | break; | |
5b4e481b | 2465 | #undef gen_load_store |
809377aa MF |
2466 | |
2467 | case 10: /*MOVI*/ | |
97e89ee9 MF |
2468 | if (gen_window_check1(dc, RRI8_T)) { |
2469 | tcg_gen_movi_i32(cpu_R[RRI8_T], | |
2470 | RRI8_IMM8 | (RRI8_S << 8) | | |
2471 | ((RRI8_S & 0x8) ? 0xfffff000 : 0)); | |
2472 | } | |
809377aa MF |
2473 | break; |
2474 | ||
5b4e481b | 2475 | #define gen_load_store_no_hw_align(type) do { \ |
97e89ee9 MF |
2476 | if (gen_window_check2(dc, RRI8_S, RRI8_T)) { \ |
2477 | TCGv_i32 addr = tcg_temp_local_new_i32(); \ | |
2478 | tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \ | |
2479 | gen_load_store_alignment(dc, 2, addr, true); \ | |
2480 | tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \ | |
2481 | tcg_temp_free(addr); \ | |
2482 | } \ | |
5b4e481b MF |
2483 | } while (0) |
2484 | ||
809377aa MF |
2485 | case 11: /*L32AIy*/ |
2486 | HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO); | |
5b4e481b | 2487 | gen_load_store_no_hw_align(ld32u); /*TODO acquire?*/ |
809377aa MF |
2488 | break; |
2489 | ||
2490 | case 12: /*ADDI*/ | |
97e89ee9 MF |
2491 | if (gen_window_check2(dc, RRI8_S, RRI8_T)) { |
2492 | tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE); | |
2493 | } | |
809377aa MF |
2494 | break; |
2495 | ||
2496 | case 13: /*ADDMI*/ | |
97e89ee9 MF |
2497 | if (gen_window_check2(dc, RRI8_S, RRI8_T)) { |
2498 | tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], | |
2499 | RRI8_IMM8_SE << 8); | |
2500 | } | |
809377aa MF |
2501 | break; |
2502 | ||
2503 | case 14: /*S32C1Iy*/ | |
7f65f4b0 | 2504 | HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE); |
97e89ee9 | 2505 | if (gen_window_check2(dc, RRI8_S, RRI8_T)) { |
42a268c2 | 2506 | TCGLabel *label = gen_new_label(); |
809377aa MF |
2507 | TCGv_i32 tmp = tcg_temp_local_new_i32(); |
2508 | TCGv_i32 addr = tcg_temp_local_new_i32(); | |
fcc803d1 | 2509 | TCGv_i32 tpc; |
809377aa MF |
2510 | |
2511 | tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]); | |
2512 | tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); | |
5b4e481b | 2513 | gen_load_store_alignment(dc, 2, addr, true); |
fcc803d1 MF |
2514 | |
2515 | gen_advance_ccount(dc); | |
2516 | tpc = tcg_const_i32(dc->pc); | |
2517 | gen_helper_check_atomctl(cpu_env, tpc, addr); | |
f0a548b9 | 2518 | tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring); |
809377aa MF |
2519 | tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T], |
2520 | cpu_SR[SCOMPARE1], label); | |
2521 | ||
f0a548b9 | 2522 | tcg_gen_qemu_st32(tmp, addr, dc->cring); |
809377aa MF |
2523 | |
2524 | gen_set_label(label); | |
fcc803d1 | 2525 | tcg_temp_free(tpc); |
809377aa MF |
2526 | tcg_temp_free(addr); |
2527 | tcg_temp_free(tmp); | |
2528 | } | |
2529 | break; | |
2530 | ||
2531 | case 15: /*S32RIy*/ | |
2532 | HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO); | |
5b4e481b | 2533 | gen_load_store_no_hw_align(st32); /*TODO release?*/ |
809377aa | 2534 | break; |
5b4e481b | 2535 | #undef gen_load_store_no_hw_align |
809377aa MF |
2536 | |
2537 | default: /*reserved*/ | |
91a5bb76 | 2538 | RESERVED(); |
809377aa MF |
2539 | break; |
2540 | } | |
dedc5eae MF |
2541 | break; |
2542 | ||
2543 | case 3: /*LSCIp*/ | |
9ed7ae12 MF |
2544 | switch (RRI8_R) { |
2545 | case 0: /*LSIf*/ | |
2546 | case 4: /*SSIf*/ | |
2547 | case 8: /*LSIUf*/ | |
2548 | case 12: /*SSIUf*/ | |
2549 | HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); | |
97e89ee9 MF |
2550 | if (gen_window_check1(dc, RRI8_S) && |
2551 | gen_check_cpenable(dc, 0)) { | |
9ed7ae12 MF |
2552 | TCGv_i32 addr = tcg_temp_new_i32(); |
2553 | tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); | |
2554 | gen_load_store_alignment(dc, 2, addr, false); | |
2555 | if (RRI8_R & 0x4) { | |
2556 | tcg_gen_qemu_st32(cpu_FR[RRI8_T], addr, dc->cring); | |
2557 | } else { | |
2558 | tcg_gen_qemu_ld32u(cpu_FR[RRI8_T], addr, dc->cring); | |
2559 | } | |
2560 | if (RRI8_R & 0x8) { | |
2561 | tcg_gen_mov_i32(cpu_R[RRI8_S], addr); | |
2562 | } | |
2563 | tcg_temp_free(addr); | |
2564 | } | |
2565 | break; | |
2566 | ||
2567 | default: /*reserved*/ | |
2568 | RESERVED(); | |
2569 | break; | |
2570 | } | |
dedc5eae MF |
2571 | break; |
2572 | ||
2573 | case 4: /*MAC16d*/ | |
2574 | HAS_OPTION(XTENSA_OPTION_MAC16); | |
6825b6c3 MF |
2575 | { |
2576 | enum { | |
2577 | MAC16_UMUL = 0x0, | |
2578 | MAC16_MUL = 0x4, | |
2579 | MAC16_MULA = 0x8, | |
2580 | MAC16_MULS = 0xc, | |
2581 | MAC16_NONE = 0xf, | |
2582 | } op = OP1 & 0xc; | |
2583 | bool is_m1_sr = (OP2 & 0x3) == 2; | |
2584 | bool is_m2_sr = (OP2 & 0xc) == 0; | |
2585 | uint32_t ld_offset = 0; | |
2586 | ||
2587 | if (OP2 > 9) { | |
2588 | RESERVED(); | |
2589 | } | |
2590 | ||
2591 | switch (OP2 & 2) { | |
2592 | case 0: /*MACI?/MACC?*/ | |
2593 | is_m1_sr = true; | |
2594 | ld_offset = (OP2 & 1) ? -4 : 4; | |
2595 | ||
2596 | if (OP2 >= 8) { /*MACI/MACC*/ | |
2597 | if (OP1 == 0) { /*LDINC/LDDEC*/ | |
2598 | op = MAC16_NONE; | |
2599 | } else { | |
2600 | RESERVED(); | |
2601 | } | |
2602 | } else if (op != MAC16_MULA) { /*MULA.*.*.LDINC/LDDEC*/ | |
2603 | RESERVED(); | |
2604 | } | |
2605 | break; | |
2606 | ||
2607 | case 2: /*MACD?/MACA?*/ | |
2608 | if (op == MAC16_UMUL && OP2 != 7) { /*UMUL only in MACAA*/ | |
2609 | RESERVED(); | |
2610 | } | |
2611 | break; | |
2612 | } | |
2613 | ||
2614 | if (op != MAC16_NONE) { | |
97e89ee9 MF |
2615 | if (!is_m1_sr && !gen_window_check1(dc, RRR_S)) { |
2616 | break; | |
6825b6c3 | 2617 | } |
97e89ee9 MF |
2618 | if (!is_m2_sr && !gen_window_check1(dc, RRR_T)) { |
2619 | break; | |
6825b6c3 MF |
2620 | } |
2621 | } | |
2622 | ||
97e89ee9 MF |
2623 | if (ld_offset && !gen_window_check1(dc, RRR_S)) { |
2624 | break; | |
2625 | } | |
2626 | ||
6825b6c3 MF |
2627 | { |
2628 | TCGv_i32 vaddr = tcg_temp_new_i32(); | |
2629 | TCGv_i32 mem32 = tcg_temp_new_i32(); | |
2630 | ||
2631 | if (ld_offset) { | |
6825b6c3 MF |
2632 | tcg_gen_addi_i32(vaddr, cpu_R[RRR_S], ld_offset); |
2633 | gen_load_store_alignment(dc, 2, vaddr, false); | |
2634 | tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring); | |
2635 | } | |
2636 | if (op != MAC16_NONE) { | |
2637 | TCGv_i32 m1 = gen_mac16_m( | |
2638 | is_m1_sr ? cpu_SR[MR + RRR_X] : cpu_R[RRR_S], | |
2639 | OP1 & 1, op == MAC16_UMUL); | |
2640 | TCGv_i32 m2 = gen_mac16_m( | |
2641 | is_m2_sr ? cpu_SR[MR + 2 + RRR_Y] : cpu_R[RRR_T], | |
2642 | OP1 & 2, op == MAC16_UMUL); | |
2643 | ||
2644 | if (op == MAC16_MUL || op == MAC16_UMUL) { | |
2645 | tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2); | |
2646 | if (op == MAC16_UMUL) { | |
2647 | tcg_gen_movi_i32(cpu_SR[ACCHI], 0); | |
2648 | } else { | |
2649 | tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31); | |
2650 | } | |
2651 | } else { | |
d2123a07 RH |
2652 | TCGv_i32 lo = tcg_temp_new_i32(); |
2653 | TCGv_i32 hi = tcg_temp_new_i32(); | |
2654 | ||
2655 | tcg_gen_mul_i32(lo, m1, m2); | |
2656 | tcg_gen_sari_i32(hi, lo, 31); | |
6825b6c3 | 2657 | if (op == MAC16_MULA) { |
d2123a07 RH |
2658 | tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], |
2659 | cpu_SR[ACCLO], cpu_SR[ACCHI], | |
2660 | lo, hi); | |
6825b6c3 | 2661 | } else { |
d2123a07 RH |
2662 | tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], |
2663 | cpu_SR[ACCLO], cpu_SR[ACCHI], | |
2664 | lo, hi); | |
6825b6c3 | 2665 | } |
6825b6c3 MF |
2666 | tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]); |
2667 | ||
d2123a07 RH |
2668 | tcg_temp_free_i32(lo); |
2669 | tcg_temp_free_i32(hi); | |
6825b6c3 MF |
2670 | } |
2671 | tcg_temp_free(m1); | |
2672 | tcg_temp_free(m2); | |
2673 | } | |
2674 | if (ld_offset) { | |
2675 | tcg_gen_mov_i32(cpu_R[RRR_S], vaddr); | |
2676 | tcg_gen_mov_i32(cpu_SR[MR + RRR_W], mem32); | |
2677 | } | |
2678 | tcg_temp_free(vaddr); | |
2679 | tcg_temp_free(mem32); | |
2680 | } | |
2681 | } | |
dedc5eae MF |
2682 | break; |
2683 | ||
2684 | case 5: /*CALLN*/ | |
2685 | switch (CALL_N) { | |
2686 | case 0: /*CALL0*/ | |
2687 | tcg_gen_movi_i32(cpu_R[0], dc->next_pc); | |
2688 | gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0); | |
2689 | break; | |
2690 | ||
2691 | case 1: /*CALL4w*/ | |
2692 | case 2: /*CALL8w*/ | |
2693 | case 3: /*CALL12w*/ | |
2694 | HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); | |
97e89ee9 MF |
2695 | if (gen_window_check1(dc, CALL_N << 2)) { |
2696 | gen_callwi(dc, CALL_N, | |
2697 | (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0); | |
2698 | } | |
dedc5eae MF |
2699 | break; |
2700 | } | |
2701 | break; | |
2702 | ||
2703 | case 6: /*SI*/ | |
2704 | switch (CALL_N) { | |
2705 | case 0: /*J*/ | |
2706 | gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0); | |
2707 | break; | |
2708 | ||
bd57fb91 | 2709 | case 1: /*BZ*/ |
97e89ee9 | 2710 | if (gen_window_check1(dc, BRI12_S)) { |
bd57fb91 MF |
2711 | static const TCGCond cond[] = { |
2712 | TCG_COND_EQ, /*BEQZ*/ | |
2713 | TCG_COND_NE, /*BNEZ*/ | |
2714 | TCG_COND_LT, /*BLTZ*/ | |
2715 | TCG_COND_GE, /*BGEZ*/ | |
2716 | }; | |
2717 | ||
2718 | gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0, | |
2719 | 4 + BRI12_IMM12_SE); | |
2720 | } | |
2721 | break; | |
2722 | ||
2723 | case 2: /*BI0*/ | |
97e89ee9 | 2724 | if (gen_window_check1(dc, BRI8_S)) { |
bd57fb91 MF |
2725 | static const TCGCond cond[] = { |
2726 | TCG_COND_EQ, /*BEQI*/ | |
2727 | TCG_COND_NE, /*BNEI*/ | |
2728 | TCG_COND_LT, /*BLTI*/ | |
2729 | TCG_COND_GE, /*BGEI*/ | |
2730 | }; | |
2731 | ||
2732 | gen_brcondi(dc, cond[BRI8_M & 3], | |
2733 | cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE); | |
2734 | } | |
2735 | break; | |
2736 | ||
2737 | case 3: /*BI1*/ | |
2738 | switch (BRI8_M) { | |
2739 | case 0: /*ENTRYw*/ | |
2740 | HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); | |
553e44f9 MF |
2741 | { |
2742 | TCGv_i32 pc = tcg_const_i32(dc->pc); | |
2743 | TCGv_i32 s = tcg_const_i32(BRI12_S); | |
2744 | TCGv_i32 imm = tcg_const_i32(BRI12_IMM12); | |
b994e91b | 2745 | gen_advance_ccount(dc); |
f492b82d | 2746 | gen_helper_entry(cpu_env, pc, s, imm); |
553e44f9 MF |
2747 | tcg_temp_free(imm); |
2748 | tcg_temp_free(s); | |
2749 | tcg_temp_free(pc); | |
2db59a76 MF |
2750 | /* This can change tb->flags, so exit tb */ |
2751 | gen_jumpi_check_loop_end(dc, -1); | |
553e44f9 | 2752 | } |
bd57fb91 MF |
2753 | break; |
2754 | ||
2755 | case 1: /*B1*/ | |
2756 | switch (BRI8_R) { | |
2757 | case 0: /*BFp*/ | |
bd57fb91 MF |
2758 | case 1: /*BTp*/ |
2759 | HAS_OPTION(XTENSA_OPTION_BOOLEAN); | |
4dd85b6b MF |
2760 | { |
2761 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
2762 | tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRI8_S); | |
2763 | gen_brcondi(dc, | |
2764 | BRI8_R == 1 ? TCG_COND_NE : TCG_COND_EQ, | |
2765 | tmp, 0, 4 + RRI8_IMM8_SE); | |
2766 | tcg_temp_free(tmp); | |
2767 | } | |
bd57fb91 MF |
2768 | break; |
2769 | ||
2770 | case 8: /*LOOP*/ | |
bd57fb91 | 2771 | case 9: /*LOOPNEZ*/ |
bd57fb91 | 2772 | case 10: /*LOOPGTZ*/ |
797d780b | 2773 | HAS_OPTION(XTENSA_OPTION_LOOP); |
97e89ee9 | 2774 | if (gen_window_check1(dc, RRI8_S)) { |
797d780b MF |
2775 | uint32_t lend = dc->pc + RRI8_IMM8 + 4; |
2776 | TCGv_i32 tmp = tcg_const_i32(lend); | |
2777 | ||
2778 | tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[RRI8_S], 1); | |
2779 | tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc); | |
f492b82d | 2780 | gen_helper_wsr_lend(cpu_env, tmp); |
797d780b MF |
2781 | tcg_temp_free(tmp); |
2782 | ||
2783 | if (BRI8_R > 8) { | |
42a268c2 | 2784 | TCGLabel *label = gen_new_label(); |
797d780b MF |
2785 | tcg_gen_brcondi_i32( |
2786 | BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT, | |
2787 | cpu_R[RRI8_S], 0, label); | |
2788 | gen_jumpi(dc, lend, 1); | |
2789 | gen_set_label(label); | |
2790 | } | |
2791 | ||
2792 | gen_jumpi(dc, dc->next_pc, 0); | |
2793 | } | |
bd57fb91 MF |
2794 | break; |
2795 | ||
2796 | default: /*reserved*/ | |
91a5bb76 | 2797 | RESERVED(); |
bd57fb91 MF |
2798 | break; |
2799 | ||
2800 | } | |
2801 | break; | |
2802 | ||
2803 | case 2: /*BLTUI*/ | |
2804 | case 3: /*BGEUI*/ | |
97e89ee9 MF |
2805 | if (gen_window_check1(dc, BRI8_S)) { |
2806 | gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU, | |
2807 | cpu_R[BRI8_S], B4CONSTU[BRI8_R], | |
2808 | 4 + BRI8_IMM8_SE); | |
2809 | } | |
bd57fb91 MF |
2810 | break; |
2811 | } | |
2812 | break; | |
2813 | ||
dedc5eae MF |
2814 | } |
2815 | break; | |
2816 | ||
2817 | case 7: /*B*/ | |
bd57fb91 MF |
2818 | { |
2819 | TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ; | |
2820 | ||
2821 | switch (RRI8_R & 7) { | |
2822 | case 0: /*BNONE*/ /*BANY*/ | |
97e89ee9 | 2823 | if (gen_window_check2(dc, RRI8_S, RRI8_T)) { |
bd57fb91 MF |
2824 | TCGv_i32 tmp = tcg_temp_new_i32(); |
2825 | tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]); | |
2826 | gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE); | |
2827 | tcg_temp_free(tmp); | |
2828 | } | |
2829 | break; | |
2830 | ||
2831 | case 1: /*BEQ*/ /*BNE*/ | |
2832 | case 2: /*BLT*/ /*BGE*/ | |
2833 | case 3: /*BLTU*/ /*BGEU*/ | |
97e89ee9 | 2834 | if (gen_window_check2(dc, RRI8_S, RRI8_T)) { |
bd57fb91 MF |
2835 | static const TCGCond cond[] = { |
2836 | [1] = TCG_COND_EQ, | |
2837 | [2] = TCG_COND_LT, | |
2838 | [3] = TCG_COND_LTU, | |
2839 | [9] = TCG_COND_NE, | |
2840 | [10] = TCG_COND_GE, | |
2841 | [11] = TCG_COND_GEU, | |
2842 | }; | |
2843 | gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T], | |
2844 | 4 + RRI8_IMM8_SE); | |
2845 | } | |
2846 | break; | |
2847 | ||
2848 | case 4: /*BALL*/ /*BNALL*/ | |
97e89ee9 | 2849 | if (gen_window_check2(dc, RRI8_S, RRI8_T)) { |
bd57fb91 MF |
2850 | TCGv_i32 tmp = tcg_temp_new_i32(); |
2851 | tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]); | |
2852 | gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T], | |
2853 | 4 + RRI8_IMM8_SE); | |
2854 | tcg_temp_free(tmp); | |
2855 | } | |
2856 | break; | |
2857 | ||
2858 | case 5: /*BBC*/ /*BBS*/ | |
97e89ee9 | 2859 | if (gen_window_check2(dc, RRI8_S, RRI8_T)) { |
7ff7563f MF |
2860 | #ifdef TARGET_WORDS_BIGENDIAN |
2861 | TCGv_i32 bit = tcg_const_i32(0x80000000); | |
2862 | #else | |
2863 | TCGv_i32 bit = tcg_const_i32(0x00000001); | |
2864 | #endif | |
bd57fb91 MF |
2865 | TCGv_i32 tmp = tcg_temp_new_i32(); |
2866 | tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f); | |
7ff7563f MF |
2867 | #ifdef TARGET_WORDS_BIGENDIAN |
2868 | tcg_gen_shr_i32(bit, bit, tmp); | |
2869 | #else | |
bd57fb91 | 2870 | tcg_gen_shl_i32(bit, bit, tmp); |
7ff7563f | 2871 | #endif |
bd57fb91 MF |
2872 | tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit); |
2873 | gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE); | |
2874 | tcg_temp_free(tmp); | |
2875 | tcg_temp_free(bit); | |
2876 | } | |
2877 | break; | |
2878 | ||
2879 | case 6: /*BBCI*/ /*BBSI*/ | |
2880 | case 7: | |
97e89ee9 | 2881 | if (gen_window_check1(dc, RRI8_S)) { |
bd57fb91 MF |
2882 | TCGv_i32 tmp = tcg_temp_new_i32(); |
2883 | tcg_gen_andi_i32(tmp, cpu_R[RRI8_S], | |
7ff7563f MF |
2884 | #ifdef TARGET_WORDS_BIGENDIAN |
2885 | 0x80000000 >> (((RRI8_R & 1) << 4) | RRI8_T)); | |
2886 | #else | |
2887 | 0x00000001 << (((RRI8_R & 1) << 4) | RRI8_T)); | |
2888 | #endif | |
bd57fb91 MF |
2889 | gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE); |
2890 | tcg_temp_free(tmp); | |
2891 | } | |
2892 | break; | |
2893 | ||
2894 | } | |
2895 | } | |
dedc5eae MF |
2896 | break; |
2897 | ||
67882fd1 | 2898 | #define gen_narrow_load_store(type) do { \ |
97e89ee9 MF |
2899 | if (gen_window_check2(dc, RRRN_S, RRRN_T)) { \ |
2900 | TCGv_i32 addr = tcg_temp_new_i32(); \ | |
2901 | tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \ | |
2902 | gen_load_store_alignment(dc, 2, addr, false); \ | |
2903 | tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \ | |
2904 | tcg_temp_free(addr); \ | |
2905 | } \ | |
67882fd1 MF |
2906 | } while (0) |
2907 | ||
dedc5eae | 2908 | case 8: /*L32I.Nn*/ |
67882fd1 | 2909 | gen_narrow_load_store(ld32u); |
dedc5eae MF |
2910 | break; |
2911 | ||
2912 | case 9: /*S32I.Nn*/ | |
67882fd1 | 2913 | gen_narrow_load_store(st32); |
dedc5eae | 2914 | break; |
67882fd1 | 2915 | #undef gen_narrow_load_store |
dedc5eae MF |
2916 | |
2917 | case 10: /*ADD.Nn*/ | |
97e89ee9 MF |
2918 | if (gen_window_check3(dc, RRRN_R, RRRN_S, RRRN_T)) { |
2919 | tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]); | |
2920 | } | |
dedc5eae MF |
2921 | break; |
2922 | ||
2923 | case 11: /*ADDI.Nn*/ | |
97e89ee9 MF |
2924 | if (gen_window_check2(dc, RRRN_R, RRRN_S)) { |
2925 | tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], | |
2926 | RRRN_T ? RRRN_T : -1); | |
2927 | } | |
dedc5eae MF |
2928 | break; |
2929 | ||
2930 | case 12: /*ST2n*/ | |
97e89ee9 MF |
2931 | if (!gen_window_check1(dc, RRRN_S)) { |
2932 | break; | |
2933 | } | |
67882fd1 MF |
2934 | if (RRRN_T < 8) { /*MOVI.Nn*/ |
2935 | tcg_gen_movi_i32(cpu_R[RRRN_S], | |
2936 | RRRN_R | (RRRN_T << 4) | | |
2937 | ((RRRN_T & 6) == 6 ? 0xffffff80 : 0)); | |
2938 | } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/ | |
bd57fb91 MF |
2939 | TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ; |
2940 | ||
2941 | gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0, | |
2942 | 4 + (RRRN_R | ((RRRN_T & 3) << 4))); | |
67882fd1 | 2943 | } |
dedc5eae MF |
2944 | break; |
2945 | ||
2946 | case 13: /*ST3n*/ | |
67882fd1 MF |
2947 | switch (RRRN_R) { |
2948 | case 0: /*MOV.Nn*/ | |
97e89ee9 MF |
2949 | if (gen_window_check2(dc, RRRN_S, RRRN_T)) { |
2950 | tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]); | |
2951 | } | |
67882fd1 MF |
2952 | break; |
2953 | ||
2954 | case 15: /*S3*/ | |
2955 | switch (RRRN_T) { | |
2956 | case 0: /*RET.Nn*/ | |
2957 | gen_jump(dc, cpu_R[0]); | |
2958 | break; | |
2959 | ||
2960 | case 1: /*RETW.Nn*/ | |
91a5bb76 | 2961 | HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); |
553e44f9 MF |
2962 | { |
2963 | TCGv_i32 tmp = tcg_const_i32(dc->pc); | |
b994e91b | 2964 | gen_advance_ccount(dc); |
f492b82d | 2965 | gen_helper_retw(tmp, cpu_env, tmp); |
553e44f9 MF |
2966 | gen_jump(dc, tmp); |
2967 | tcg_temp_free(tmp); | |
2968 | } | |
67882fd1 MF |
2969 | break; |
2970 | ||
2971 | case 2: /*BREAK.Nn*/ | |
e61dc8f7 MF |
2972 | HAS_OPTION(XTENSA_OPTION_DEBUG); |
2973 | if (dc->debug) { | |
2974 | gen_debug_exception(dc, DEBUGCAUSE_BN); | |
2975 | } | |
67882fd1 MF |
2976 | break; |
2977 | ||
2978 | case 3: /*NOP.Nn*/ | |
2979 | break; | |
2980 | ||
2981 | case 6: /*ILL.Nn*/ | |
40643d7c | 2982 | gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); |
67882fd1 MF |
2983 | break; |
2984 | ||
2985 | default: /*reserved*/ | |
91a5bb76 | 2986 | RESERVED(); |
67882fd1 MF |
2987 | break; |
2988 | } | |
2989 | break; | |
2990 | ||
2991 | default: /*reserved*/ | |
91a5bb76 | 2992 | RESERVED(); |
67882fd1 MF |
2993 | break; |
2994 | } | |
dedc5eae MF |
2995 | break; |
2996 | ||
2997 | default: /*reserved*/ | |
91a5bb76 | 2998 | RESERVED(); |
dedc5eae MF |
2999 | break; |
3000 | } | |
3001 | ||
c26032b2 MF |
3002 | if (dc->is_jmp == DISAS_NEXT) { |
3003 | gen_check_loop_end(dc, 0); | |
3004 | } | |
dedc5eae | 3005 | dc->pc = dc->next_pc; |
797d780b | 3006 | |
dedc5eae MF |
3007 | return; |
3008 | ||
3009 | invalid_opcode: | |
c30f0d18 | 3010 | qemu_log_mask(LOG_GUEST_ERROR, "INVALID(pc = %08x)\n", dc->pc); |
6b814719 | 3011 | gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); |
dedc5eae MF |
3012 | #undef HAS_OPTION |
3013 | } | |
3014 | ||
01673a34 MF |
3015 | static inline unsigned xtensa_insn_len(CPUXtensaState *env, DisasContext *dc) |
3016 | { | |
3017 | uint8_t b0 = cpu_ldub_code(env, dc->pc); | |
3018 | return xtensa_op0_insn_len(OP0); | |
3019 | } | |
3020 | ||
97129ac8 | 3021 | static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc) |
e61dc8f7 MF |
3022 | { |
3023 | unsigned i; | |
3024 | ||
3025 | for (i = 0; i < dc->config->nibreak; ++i) { | |
3026 | if ((env->sregs[IBREAKENABLE] & (1 << i)) && | |
3027 | env->sregs[IBREAKA + i] == dc->pc) { | |
3028 | gen_debug_exception(dc, DEBUGCAUSE_IB); | |
3029 | break; | |
3030 | } | |
3031 | } | |
3032 | } | |
3033 | ||
4e5e1215 | 3034 | void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb) |
dedc5eae | 3035 | { |
4e5e1215 | 3036 | XtensaCPU *cpu = xtensa_env_get_cpu(env); |
ed2803da | 3037 | CPUState *cs = CPU(cpu); |
dedc5eae MF |
3038 | DisasContext dc; |
3039 | int insn_count = 0; | |
dedc5eae MF |
3040 | int max_insns = tb->cflags & CF_COUNT_MASK; |
3041 | uint32_t pc_start = tb->pc; | |
3042 | uint32_t next_page_start = | |
3043 | (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; | |
3044 | ||
3045 | if (max_insns == 0) { | |
3046 | max_insns = CF_COUNT_MASK; | |
3047 | } | |
190ce7fb RH |
3048 | if (max_insns > TCG_MAX_INSNS) { |
3049 | max_insns = TCG_MAX_INSNS; | |
3050 | } | |
dedc5eae MF |
3051 | |
3052 | dc.config = env->config; | |
ed2803da | 3053 | dc.singlestep_enabled = cs->singlestep_enabled; |
dedc5eae MF |
3054 | dc.tb = tb; |
3055 | dc.pc = pc_start; | |
f0a548b9 MF |
3056 | dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK; |
3057 | dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring; | |
797d780b MF |
3058 | dc.lbeg = env->sregs[LBEG]; |
3059 | dc.lend = env->sregs[LEND]; | |
dedc5eae | 3060 | dc.is_jmp = DISAS_NEXT; |
b994e91b | 3061 | dc.ccount_delta = 0; |
e61dc8f7 | 3062 | dc.debug = tb->flags & XTENSA_TBFLAG_DEBUG; |
35b5c044 | 3063 | dc.icount = tb->flags & XTENSA_TBFLAG_ICOUNT; |
ef04a846 MF |
3064 | dc.cpenable = (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >> |
3065 | XTENSA_TBFLAG_CPENABLE_SHIFT; | |
2db59a76 MF |
3066 | dc.window = ((tb->flags & XTENSA_TBFLAG_WINDOW_MASK) >> |
3067 | XTENSA_TBFLAG_WINDOW_SHIFT); | |
dedc5eae | 3068 | |
6ad6dbf7 | 3069 | init_litbase(&dc); |
3580ecad | 3070 | init_sar_tracker(&dc); |
35b5c044 MF |
3071 | if (dc.icount) { |
3072 | dc.next_icount = tcg_temp_local_new_i32(); | |
3073 | } | |
3580ecad | 3074 | |
cd42d5b2 | 3075 | gen_tb_start(tb); |
dedc5eae | 3076 | |
a00817cc | 3077 | if (tb->flags & XTENSA_TBFLAG_EXCEPTION) { |
40643d7c | 3078 | tcg_gen_movi_i32(cpu_pc, dc.pc); |
b994e91b | 3079 | gen_exception(&dc, EXCP_DEBUG); |
40643d7c MF |
3080 | } |
3081 | ||
dedc5eae | 3082 | do { |
667b8e29 | 3083 | tcg_gen_insn_start(dc.pc); |
959082fc | 3084 | ++insn_count; |
dedc5eae | 3085 | |
b994e91b MF |
3086 | ++dc.ccount_delta; |
3087 | ||
b933066a RH |
3088 | if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) { |
3089 | tcg_gen_movi_i32(cpu_pc, dc.pc); | |
3090 | gen_exception(&dc, EXCP_DEBUG); | |
3091 | dc.is_jmp = DISAS_UPDATE; | |
522a0d4e RH |
3092 | /* The address covered by the breakpoint must be included in |
3093 | [tb->pc, tb->pc + tb->size) in order to for it to be | |
3094 | properly cleared -- thus we increment the PC here so that | |
3095 | the logic setting tb->size below does the right thing. */ | |
3096 | dc.pc += 2; | |
b933066a RH |
3097 | break; |
3098 | } | |
3099 | ||
959082fc | 3100 | if (insn_count == max_insns && (tb->cflags & CF_LAST_IO)) { |
b994e91b MF |
3101 | gen_io_start(); |
3102 | } | |
3103 | ||
35b5c044 | 3104 | if (dc.icount) { |
42a268c2 | 3105 | TCGLabel *label = gen_new_label(); |
35b5c044 MF |
3106 | |
3107 | tcg_gen_addi_i32(dc.next_icount, cpu_SR[ICOUNT], 1); | |
3108 | tcg_gen_brcondi_i32(TCG_COND_NE, dc.next_icount, 0, label); | |
3109 | tcg_gen_mov_i32(dc.next_icount, cpu_SR[ICOUNT]); | |
3110 | if (dc.debug) { | |
3111 | gen_debug_exception(&dc, DEBUGCAUSE_IC); | |
3112 | } | |
3113 | gen_set_label(label); | |
3114 | } | |
3115 | ||
e61dc8f7 MF |
3116 | if (dc.debug) { |
3117 | gen_ibreak_check(env, &dc); | |
3118 | } | |
3119 | ||
0c4fabea | 3120 | disas_xtensa_insn(env, &dc); |
35b5c044 MF |
3121 | if (dc.icount) { |
3122 | tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount); | |
3123 | } | |
ed2803da | 3124 | if (cs->singlestep_enabled) { |
dedc5eae | 3125 | tcg_gen_movi_i32(cpu_pc, dc.pc); |
b994e91b | 3126 | gen_exception(&dc, EXCP_DEBUG); |
dedc5eae MF |
3127 | break; |
3128 | } | |
3129 | } while (dc.is_jmp == DISAS_NEXT && | |
3130 | insn_count < max_insns && | |
3131 | dc.pc < next_page_start && | |
01673a34 | 3132 | dc.pc + xtensa_insn_len(env, &dc) <= next_page_start && |
fe700adb | 3133 | !tcg_op_buf_full()); |
dedc5eae | 3134 | |
6ad6dbf7 | 3135 | reset_litbase(&dc); |
3580ecad | 3136 | reset_sar_tracker(&dc); |
35b5c044 MF |
3137 | if (dc.icount) { |
3138 | tcg_temp_free(dc.next_icount); | |
3139 | } | |
3580ecad | 3140 | |
b994e91b MF |
3141 | if (tb->cflags & CF_LAST_IO) { |
3142 | gen_io_end(); | |
3143 | } | |
3144 | ||
dedc5eae MF |
3145 | if (dc.is_jmp == DISAS_NEXT) { |
3146 | gen_jumpi(&dc, dc.pc, 0); | |
3147 | } | |
806f352d | 3148 | gen_tb_end(tb, insn_count); |
dedc5eae | 3149 | |
ca529f8e MF |
3150 | #ifdef DEBUG_DISAS |
3151 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { | |
3152 | qemu_log("----------------\n"); | |
3153 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
d49190c4 | 3154 | log_target_disas(cs, pc_start, dc.pc - pc_start, 0); |
ca529f8e MF |
3155 | qemu_log("\n"); |
3156 | } | |
3157 | #endif | |
4e5e1215 RH |
3158 | tb->size = dc.pc - pc_start; |
3159 | tb->icount = insn_count; | |
2328826b MF |
3160 | } |
3161 | ||
878096ee AF |
3162 | void xtensa_cpu_dump_state(CPUState *cs, FILE *f, |
3163 | fprintf_function cpu_fprintf, int flags) | |
2328826b | 3164 | { |
878096ee AF |
3165 | XtensaCPU *cpu = XTENSA_CPU(cs); |
3166 | CPUXtensaState *env = &cpu->env; | |
2af3da91 MF |
3167 | int i, j; |
3168 | ||
3169 | cpu_fprintf(f, "PC=%08x\n\n", env->pc); | |
3170 | ||
3171 | for (i = j = 0; i < 256; ++i) { | |
fe0bd475 MF |
3172 | if (xtensa_option_bits_enabled(env->config, sregnames[i].opt_bits)) { |
3173 | cpu_fprintf(f, "%12s=%08x%c", sregnames[i].name, env->sregs[i], | |
2af3da91 MF |
3174 | (j++ % 4) == 3 ? '\n' : ' '); |
3175 | } | |
3176 | } | |
3177 | ||
3178 | cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n"); | |
3179 | ||
3180 | for (i = j = 0; i < 256; ++i) { | |
fe0bd475 MF |
3181 | if (xtensa_option_bits_enabled(env->config, uregnames[i].opt_bits)) { |
3182 | cpu_fprintf(f, "%s=%08x%c", uregnames[i].name, env->uregs[i], | |
2af3da91 MF |
3183 | (j++ % 4) == 3 ? '\n' : ' '); |
3184 | } | |
3185 | } | |
2328826b | 3186 | |
2af3da91 | 3187 | cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n"); |
2328826b MF |
3188 | |
3189 | for (i = 0; i < 16; ++i) { | |
fe0bd475 | 3190 | cpu_fprintf(f, " A%02d=%08x%c", i, env->regs[i], |
2328826b MF |
3191 | (i % 4) == 3 ? '\n' : ' '); |
3192 | } | |
553e44f9 MF |
3193 | |
3194 | cpu_fprintf(f, "\n"); | |
3195 | ||
3196 | for (i = 0; i < env->config->nareg; ++i) { | |
3197 | cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i], | |
3198 | (i % 4) == 3 ? '\n' : ' '); | |
3199 | } | |
dd519cbe MF |
3200 | |
3201 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) { | |
3202 | cpu_fprintf(f, "\n"); | |
3203 | ||
3204 | for (i = 0; i < 16; ++i) { | |
3205 | cpu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i, | |
ddd44279 MF |
3206 | float32_val(env->fregs[i].f32[FP_F32_LOW]), |
3207 | *(float *)(env->fregs[i].f32 + FP_F32_LOW), | |
3208 | (i % 2) == 1 ? '\n' : ' '); | |
dd519cbe MF |
3209 | } |
3210 | } | |
2328826b MF |
3211 | } |
3212 | ||
bad729e2 RH |
3213 | void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb, |
3214 | target_ulong *data) | |
2328826b | 3215 | { |
bad729e2 | 3216 | env->pc = data[0]; |
2328826b | 3217 | } |