]> git.proxmox.com Git - mirror_qemu.git/blame - target-xtensa/translate.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
target-xtensa: implement interrupt option
[mirror_qemu.git] / target-xtensa / translate.c
CommitLineData
2328826b
MF		 1/*
2 * Xtensa ISA:
3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
4 *
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <stdio.h>
32
33#include "cpu.h"
34#include "exec-all.h"
35#include "disas.h"
36#include "tcg-op.h"
37#include "qemu-log.h"
1ddeaa5d 38#include "sysemu.h"
2328826b 39
dedc5eae
MF		 40#include "helpers.h"
41#define GEN_HELPER 1
42#include "helpers.h"
43
44typedef struct DisasContext {
45 const XtensaConfig *config;
46 TranslationBlock *tb;
47 uint32_t pc;
48 uint32_t next_pc;
f0a548b9
MF		 49 int cring;
50 int ring;
797d780b
MF		 51 uint32_t lbeg;
52 uint32_t lend;
6ad6dbf7 53 TCGv_i32 litbase;
dedc5eae
MF		 54 int is_jmp;
55 int singlestep_enabled;
3580ecad
MF		 56
57 bool sar_5bit;
58 bool sar_m32_5bit;
59 bool sar_m32_allocated;
60 TCGv_i32 sar_m32;
b994e91b
MF		 61
62 uint32_t ccount_delta;
dedc5eae
MF		 63} DisasContext;
64
65static TCGv_ptr cpu_env;
66static TCGv_i32 cpu_pc;
67static TCGv_i32 cpu_R[16];
2af3da91
MF		 68static TCGv_i32 cpu_SR[256];
69static TCGv_i32 cpu_UR[256];
dedc5eae
MF		 70
71#include "gen-icount.h"
2328826b 72
2af3da91 73static const char * const sregnames[256] = {
797d780b
MF		 74 [LBEG] = "LBEG",
75 [LEND] = "LEND",
76 [LCOUNT] = "LCOUNT",
3580ecad 77 [SAR] = "SAR",
6ad6dbf7 78 [LITBASE] = "LITBASE",
809377aa 79 [SCOMPARE1] = "SCOMPARE1",
553e44f9
MF		 80 [WINDOW_BASE] = "WINDOW_BASE",
81 [WINDOW_START] = "WINDOW_START",
40643d7c 82 [EPC1] = "EPC1",
b994e91b
MF		 83 [EPC1 + 1] = "EPC2",
84 [EPC1 + 2] = "EPC3",
85 [EPC1 + 3] = "EPC4",
86 [EPC1 + 4] = "EPC5",
87 [EPC1 + 5] = "EPC6",
88 [EPC1 + 6] = "EPC7",
40643d7c 89 [DEPC] = "DEPC",
b994e91b
MF		 90 [EPS2] = "EPS2",
91 [EPS2 + 1] = "EPS3",
92 [EPS2 + 2] = "EPS4",
93 [EPS2 + 3] = "EPS5",
94 [EPS2 + 4] = "EPS6",
95 [EPS2 + 5] = "EPS7",
40643d7c 96 [EXCSAVE1] = "EXCSAVE1",
b994e91b
MF		 97 [EXCSAVE1 + 1] = "EXCSAVE2",
98 [EXCSAVE1 + 2] = "EXCSAVE3",
99 [EXCSAVE1 + 3] = "EXCSAVE4",
100 [EXCSAVE1 + 4] = "EXCSAVE5",
101 [EXCSAVE1 + 5] = "EXCSAVE6",
102 [EXCSAVE1 + 6] = "EXCSAVE7",
103 [INTSET] = "INTSET",
104 [INTCLEAR] = "INTCLEAR",
105 [INTENABLE] = "INTENABLE",
f0a548b9 106 [PS] = "PS",
40643d7c 107 [EXCCAUSE] = "EXCCAUSE",
b994e91b 108 [CCOUNT] = "CCOUNT",
40643d7c 109 [EXCVADDR] = "EXCVADDR",
b994e91b
MF		 110 [CCOMPARE] = "CCOMPARE0",
111 [CCOMPARE + 1] = "CCOMPARE1",
112 [CCOMPARE + 2] = "CCOMPARE2",
2af3da91
MF		 113};
114
115static const char * const uregnames[256] = {
116 [THREADPTR] = "THREADPTR",
117 [FCR] = "FCR",
118 [FSR] = "FSR",
119};
120
2328826b
MF		 121void xtensa_translate_init(void)
122{
dedc5eae
MF		 123 static const char * const regnames[] = {
124 "ar0", "ar1", "ar2", "ar3",
125 "ar4", "ar5", "ar6", "ar7",
126 "ar8", "ar9", "ar10", "ar11",
127 "ar12", "ar13", "ar14", "ar15",
128 };
129 int i;
130
131 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
132 cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
133 offsetof(CPUState, pc), "pc");
134
135 for (i = 0; i < 16; i++) {
136 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
137 offsetof(CPUState, regs[i]),
138 regnames[i]);
139 }
2af3da91
MF		 140
141 for (i = 0; i < 256; ++i) {
142 if (sregnames[i]) {
143 cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0,
144 offsetof(CPUState, sregs[i]),
145 sregnames[i]);
146 }
147 }
148
149 for (i = 0; i < 256; ++i) {
150 if (uregnames[i]) {
151 cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0,
152 offsetof(CPUState, uregs[i]),
153 uregnames[i]);
154 }
155 }
dedc5eae
MF		 156#define GEN_HELPER 2
157#include "helpers.h"
158}
159
160static inline bool option_enabled(DisasContext *dc, int opt)
161{
162 return xtensa_option_enabled(dc->config, opt);
163}
164
6ad6dbf7
MF		 165static void init_litbase(DisasContext *dc)
166{
167 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
168 dc->litbase = tcg_temp_local_new_i32();
169 tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000);
170 }
171}
172
173static void reset_litbase(DisasContext *dc)
174{
175 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
176 tcg_temp_free(dc->litbase);
177 }
178}
179
3580ecad
MF		 180static void init_sar_tracker(DisasContext *dc)
181{
182 dc->sar_5bit = false;
183 dc->sar_m32_5bit = false;
184 dc->sar_m32_allocated = false;
185}
186
187static void reset_sar_tracker(DisasContext *dc)
188{
189 if (dc->sar_m32_allocated) {
190 tcg_temp_free(dc->sar_m32);
191 }
192}
193
194static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
195{
196 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);
197 if (dc->sar_m32_5bit) {
198 tcg_gen_discard_i32(dc->sar_m32);
199 }
200 dc->sar_5bit = true;
201 dc->sar_m32_5bit = false;
202}
203
204static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
205{
206 TCGv_i32 tmp = tcg_const_i32(32);
207 if (!dc->sar_m32_allocated) {
208 dc->sar_m32 = tcg_temp_local_new_i32();
209 dc->sar_m32_allocated = true;
210 }
211 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
212 tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
213 dc->sar_5bit = false;
214 dc->sar_m32_5bit = true;
215 tcg_temp_free(tmp);
216}
217
b994e91b
MF		 218static void gen_advance_ccount(DisasContext *dc)
219{
220 if (dc->ccount_delta > 0) {
221 TCGv_i32 tmp = tcg_const_i32(dc->ccount_delta);
222 dc->ccount_delta = 0;
223 gen_helper_advance_ccount(tmp);
224 tcg_temp_free(tmp);
225 }
226}
227
228static void gen_exception(DisasContext *dc, int excp)
dedc5eae
MF		 229{
230 TCGv_i32 tmp = tcg_const_i32(excp);
b994e91b 231 gen_advance_ccount(dc);
dedc5eae
MF		 232 gen_helper_exception(tmp);
233 tcg_temp_free(tmp);
234}
235
40643d7c
MF		 236static void gen_exception_cause(DisasContext *dc, uint32_t cause)
237{
238 TCGv_i32 tpc = tcg_const_i32(dc->pc);
239 TCGv_i32 tcause = tcg_const_i32(cause);
b994e91b 240 gen_advance_ccount(dc);
40643d7c
MF		 241 gen_helper_exception_cause(tpc, tcause);
242 tcg_temp_free(tpc);
243 tcg_temp_free(tcause);
244}
245
5b4e481b
MF		 246static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause,
247 TCGv_i32 vaddr)
248{
249 TCGv_i32 tpc = tcg_const_i32(dc->pc);
250 TCGv_i32 tcause = tcg_const_i32(cause);
b994e91b 251 gen_advance_ccount(dc);
5b4e481b
MF		 252 gen_helper_exception_cause_vaddr(tpc, tcause, vaddr);
253 tcg_temp_free(tpc);
254 tcg_temp_free(tcause);
255}
256
40643d7c
MF		 257static void gen_check_privilege(DisasContext *dc)
258{
259 if (dc->cring) {
260 gen_exception_cause(dc, PRIVILEGED_CAUSE);
261 }
262}
263
dedc5eae
MF		 264static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
265{
266 tcg_gen_mov_i32(cpu_pc, dest);
267 if (dc->singlestep_enabled) {
b994e91b 268 gen_exception(dc, EXCP_DEBUG);
dedc5eae 269 } else {
b994e91b 270 gen_advance_ccount(dc);
dedc5eae
MF		 271 if (slot >= 0) {
272 tcg_gen_goto_tb(slot);
273 tcg_gen_exit_tb((tcg_target_long)dc->tb + slot);
274 } else {
275 tcg_gen_exit_tb(0);
276 }
277 }
278 dc->is_jmp = DISAS_UPDATE;
279}
280
67882fd1
MF		 281static void gen_jump(DisasContext *dc, TCGv dest)
282{
283 gen_jump_slot(dc, dest, -1);
284}
285
dedc5eae
MF		 286static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
287{
288 TCGv_i32 tmp = tcg_const_i32(dest);
289 if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
290 slot = -1;
291 }
292 gen_jump_slot(dc, tmp, slot);
293 tcg_temp_free(tmp);
294}
295
553e44f9
MF		 296static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
297 int slot)
298{
299 TCGv_i32 tcallinc = tcg_const_i32(callinc);
300
301 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
302 tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
303 tcg_temp_free(tcallinc);
304 tcg_gen_movi_i32(cpu_R[callinc << 2],
305 (callinc << 30) | (dc->next_pc & 0x3fffffff));
306 gen_jump_slot(dc, dest, slot);
307}
308
309static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest)
310{
311 gen_callw_slot(dc, callinc, dest, -1);
312}
313
314static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)
315{
316 TCGv_i32 tmp = tcg_const_i32(dest);
317 if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
318 slot = -1;
319 }
320 gen_callw_slot(dc, callinc, tmp, slot);
321 tcg_temp_free(tmp);
322}
323
797d780b
MF		 324static bool gen_check_loop_end(DisasContext *dc, int slot)
325{
326 if (option_enabled(dc, XTENSA_OPTION_LOOP) &&
327 !(dc->tb->flags & XTENSA_TBFLAG_EXCM) &&
328 dc->next_pc == dc->lend) {
329 int label = gen_new_label();
330
331 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
332 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
333 gen_jumpi(dc, dc->lbeg, slot);
334 gen_set_label(label);
335 gen_jumpi(dc, dc->next_pc, -1);
336 return true;
337 }
338 return false;
339}
340
341static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)
342{
343 if (!gen_check_loop_end(dc, slot)) {
344 gen_jumpi(dc, dc->next_pc, slot);
345 }
346}
347
bd57fb91
MF		 348static void gen_brcond(DisasContext *dc, TCGCond cond,
349 TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
350{
351 int label = gen_new_label();
352
353 tcg_gen_brcond_i32(cond, t0, t1, label);
797d780b 354 gen_jumpi_check_loop_end(dc, 0);
bd57fb91
MF		 355 gen_set_label(label);
356 gen_jumpi(dc, dc->pc + offset, 1);
357}
358
359static void gen_brcondi(DisasContext *dc, TCGCond cond,
360 TCGv_i32 t0, uint32_t t1, uint32_t offset)
361{
362 TCGv_i32 tmp = tcg_const_i32(t1);
363 gen_brcond(dc, cond, t0, tmp, offset);
364 tcg_temp_free(tmp);
365}
366
b994e91b
MF		 367static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
368{
369 gen_advance_ccount(dc);
370 tcg_gen_mov_i32(d, cpu_SR[sr]);
371}
372
b8132eff
MF		 373static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
374{
375 static void (* const rsr_handler[256])(DisasContext *dc,
376 TCGv_i32 d, uint32_t sr) = {
b994e91b 377 [CCOUNT] = gen_rsr_ccount,
b8132eff
MF		 378 };
379
380 if (sregnames[sr]) {
381 if (rsr_handler[sr]) {
382 rsr_handler[sr](dc, d, sr);
383 } else {
384 tcg_gen_mov_i32(d, cpu_SR[sr]);
385 }
386 } else {
387 qemu_log("RSR %d not implemented, ", sr);
388 }
389}
390
797d780b
MF		 391static void gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s)
392{
393 gen_helper_wsr_lbeg(s);
394}
395
396static void gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s)
397{
398 gen_helper_wsr_lend(s);
399}
400
3580ecad
MF		 401static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
402{
403 tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);
404 if (dc->sar_m32_5bit) {
405 tcg_gen_discard_i32(dc->sar_m32);
406 }
407 dc->sar_5bit = false;
408 dc->sar_m32_5bit = false;
409}
410
6ad6dbf7
MF		 411static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)
412{
413 tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001);
414 /* This can change tb->flags, so exit tb */
415 gen_jumpi_check_loop_end(dc, -1);
416}
417
553e44f9
MF		 418static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
419{
420 gen_helper_wsr_windowbase(v);
421}
422
b994e91b
MF		 423static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v)
424{
425 tcg_gen_andi_i32(cpu_SR[sr], v,
426 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
427 gen_helper_check_interrupts(cpu_env);
428 gen_jumpi_check_loop_end(dc, 0);
429}
430
431static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v)
432{
433 TCGv_i32 tmp = tcg_temp_new_i32();
434
435 tcg_gen_andi_i32(tmp, v,
436 dc->config->inttype_mask[INTTYPE_EDGE] |
437 dc->config->inttype_mask[INTTYPE_NMI] |
438 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
439 tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp);
440 tcg_temp_free(tmp);
441 gen_helper_check_interrupts(cpu_env);
442}
443
444static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
445{
446 tcg_gen_mov_i32(cpu_SR[sr], v);
447 gen_helper_check_interrupts(cpu_env);
448 gen_jumpi_check_loop_end(dc, 0);
449}
450
f0a548b9
MF		 451static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
452{
453 uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
454 PS_UM | PS_EXCM | PS_INTLEVEL;
455
456 if (option_enabled(dc, XTENSA_OPTION_MMU)) {
457 mask |= PS_RING;
458 }
459 tcg_gen_andi_i32(cpu_SR[sr], v, mask);
b994e91b
MF		 460 gen_helper_check_interrupts(cpu_env);
461 /* This can change mmu index and tb->flags, so exit tb */
797d780b 462 gen_jumpi_check_loop_end(dc, -1);
f0a548b9
MF		 463}
464
b994e91b
MF		 465static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
466{
467 uint32_t id = sr - CCOMPARE;
468 if (id < dc->config->nccompare) {
469 uint32_t int_bit = 1 << dc->config->timerint[id];
470 gen_advance_ccount(dc);
471 tcg_gen_mov_i32(cpu_SR[sr], v);
472 tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
473 gen_helper_check_interrupts(cpu_env);
474 }
475}
476
b8132eff
MF		 477static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
478{
479 static void (* const wsr_handler[256])(DisasContext *dc,
480 uint32_t sr, TCGv_i32 v) = {
797d780b
MF		 481 [LBEG] = gen_wsr_lbeg,
482 [LEND] = gen_wsr_lend,
3580ecad 483 [SAR] = gen_wsr_sar,
6ad6dbf7 484 [LITBASE] = gen_wsr_litbase,
553e44f9 485 [WINDOW_BASE] = gen_wsr_windowbase,
b994e91b
MF		 486 [INTSET] = gen_wsr_intset,
487 [INTCLEAR] = gen_wsr_intclear,
488 [INTENABLE] = gen_wsr_intenable,
f0a548b9 489 [PS] = gen_wsr_ps,
b994e91b
MF		 490 [CCOMPARE] = gen_wsr_ccompare,
491 [CCOMPARE + 1] = gen_wsr_ccompare,
492 [CCOMPARE + 2] = gen_wsr_ccompare,
b8132eff
MF		 493 };
494
495 if (sregnames[sr]) {
496 if (wsr_handler[sr]) {
497 wsr_handler[sr](dc, sr, s);
498 } else {
499 tcg_gen_mov_i32(cpu_SR[sr], s);
500 }
501 } else {
502 qemu_log("WSR %d not implemented, ", sr);
503 }
504}
505
5b4e481b
MF		 506static void gen_load_store_alignment(DisasContext *dc, int shift,
507 TCGv_i32 addr, bool no_hw_alignment)
508{
509 if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
510 tcg_gen_andi_i32(addr, addr, ~0 << shift);
511 } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) &&
512 no_hw_alignment) {
513 int label = gen_new_label();
514 TCGv_i32 tmp = tcg_temp_new_i32();
515 tcg_gen_andi_i32(tmp, addr, ~(~0 << shift));
516 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
517 gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
518 gen_set_label(label);
519 tcg_temp_free(tmp);
520 }
521}
522
b994e91b
MF		 523static void gen_waiti(DisasContext *dc, uint32_t imm4)
524{
525 TCGv_i32 pc = tcg_const_i32(dc->next_pc);
526 TCGv_i32 intlevel = tcg_const_i32(imm4);
527 gen_advance_ccount(dc);
528 gen_helper_waiti(pc, intlevel);
529 tcg_temp_free(pc);
530 tcg_temp_free(intlevel);
531}
532
dedc5eae
MF		 533static void disas_xtensa_insn(DisasContext *dc)
534{
535#define HAS_OPTION(opt) do { \
536 if (!option_enabled(dc, opt)) { \
537 qemu_log("Option %d is not enabled %s:%d\n", \
538 (opt), __FILE__, __LINE__); \
539 goto invalid_opcode; \
540 } \
541 } while (0)
542
91a5bb76
MF		 543#define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
544#define RESERVED() do { \
545 qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
546 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
547 goto invalid_opcode; \
548 } while (0)
549
550
dedc5eae
MF		 551#ifdef TARGET_WORDS_BIGENDIAN
552#define OP0 (((b0) & 0xf0) >> 4)
553#define OP1 (((b2) & 0xf0) >> 4)
554#define OP2 ((b2) & 0xf)
555#define RRR_R ((b1) & 0xf)
556#define RRR_S (((b1) & 0xf0) >> 4)
557#define RRR_T ((b0) & 0xf)
558#else
559#define OP0 (((b0) & 0xf))
560#define OP1 (((b2) & 0xf))
561#define OP2 (((b2) & 0xf0) >> 4)
562#define RRR_R (((b1) & 0xf0) >> 4)
563#define RRR_S (((b1) & 0xf))
564#define RRR_T (((b0) & 0xf0) >> 4)
565#endif
566
567#define RRRN_R RRR_R
568#define RRRN_S RRR_S
569#define RRRN_T RRR_T
570
571#define RRI8_R RRR_R
572#define RRI8_S RRR_S
573#define RRI8_T RRR_T
574#define RRI8_IMM8 (b2)
575#define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
576
577#ifdef TARGET_WORDS_BIGENDIAN
578#define RI16_IMM16 (((b1) << 8) | (b2))
579#else
580#define RI16_IMM16 (((b2) << 8) | (b1))
581#endif
582
583#ifdef TARGET_WORDS_BIGENDIAN
584#define CALL_N (((b0) & 0xc) >> 2)
585#define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
586#else
587#define CALL_N (((b0) & 0x30) >> 4)
588#define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
589#endif
590#define CALL_OFFSET_SE \
591 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
592
593#define CALLX_N CALL_N
594#ifdef TARGET_WORDS_BIGENDIAN
595#define CALLX_M ((b0) & 0x3)
596#else
597#define CALLX_M (((b0) & 0xc0) >> 6)
598#endif
599#define CALLX_S RRR_S
600
601#define BRI12_M CALLX_M
602#define BRI12_S RRR_S
603#ifdef TARGET_WORDS_BIGENDIAN
604#define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
605#else
606#define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
607#endif
608#define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
609
610#define BRI8_M BRI12_M
611#define BRI8_R RRI8_R
612#define BRI8_S RRI8_S
613#define BRI8_IMM8 RRI8_IMM8
614#define BRI8_IMM8_SE RRI8_IMM8_SE
615
616#define RSR_SR (b1)
617
618 uint8_t b0 = ldub_code(dc->pc);
619 uint8_t b1 = ldub_code(dc->pc + 1);
620 uint8_t b2 = ldub_code(dc->pc + 2);
621
bd57fb91
MF		 622 static const uint32_t B4CONST[] = {
623 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
624 };
625
626 static const uint32_t B4CONSTU[] = {
627 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
628 };
629
dedc5eae
MF		 630 if (OP0 >= 8) {
631 dc->next_pc = dc->pc + 2;
632 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
633 } else {
634 dc->next_pc = dc->pc + 3;
635 }
636
637 switch (OP0) {
638 case 0: /*QRST*/
639 switch (OP1) {
640 case 0: /*RST0*/
641 switch (OP2) {
642 case 0: /*ST0*/
643 if ((RRR_R & 0xc) == 0x8) {
644 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
645 }
646
647 switch (RRR_R) {
648 case 0: /*SNM0*/
5da4a6a8
MF		 649 switch (CALLX_M) {
650 case 0: /*ILL*/
40643d7c 651 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
5da4a6a8
MF		 652 break;
653
654 case 1: /*reserved*/
91a5bb76 655 RESERVED();
5da4a6a8
MF		 656 break;
657
658 case 2: /*JR*/
659 switch (CALLX_N) {
660 case 0: /*RET*/
661 case 2: /*JX*/
662 gen_jump(dc, cpu_R[CALLX_S]);
663 break;
664
665 case 1: /*RETWw*/
666 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 667 {
668 TCGv_i32 tmp = tcg_const_i32(dc->pc);
b994e91b 669 gen_advance_ccount(dc);
553e44f9
MF		 670 gen_helper_retw(tmp, tmp);
671 gen_jump(dc, tmp);
672 tcg_temp_free(tmp);
673 }
5da4a6a8
MF		 674 break;
675
676 case 3: /*reserved*/
91a5bb76 677 RESERVED();
5da4a6a8
MF		 678 break;
679 }
680 break;
681
682 case 3: /*CALLX*/
683 switch (CALLX_N) {
684 case 0: /*CALLX0*/
685 {
686 TCGv_i32 tmp = tcg_temp_new_i32();
687 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
688 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
689 gen_jump(dc, tmp);
690 tcg_temp_free(tmp);
691 }
692 break;
693
694 case 1: /*CALLX4w*/
695 case 2: /*CALLX8w*/
696 case 3: /*CALLX12w*/
697 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 698 {
699 TCGv_i32 tmp = tcg_temp_new_i32();
700
701 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
702 gen_callw(dc, CALLX_N, tmp);
703 tcg_temp_free(tmp);
704 }
5da4a6a8
MF		 705 break;
706 }
707 break;
708 }
dedc5eae
MF		 709 break;
710
711 case 1: /*MOVSPw*/
712 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 713 {
714 TCGv_i32 pc = tcg_const_i32(dc->pc);
b994e91b 715 gen_advance_ccount(dc);
553e44f9
MF		 716 gen_helper_movsp(pc);
717 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]);
718 tcg_temp_free(pc);
719 }
dedc5eae
MF		 720 break;
721
722 case 2: /*SYNC*/
28067b22
MF		 723 switch (RRR_T) {
724 case 0: /*ISYNC*/
725 break;
726
727 case 1: /*RSYNC*/
728 break;
729
730 case 2: /*ESYNC*/
731 break;
732
733 case 3: /*DSYNC*/
734 break;
735
736 case 8: /*EXCW*/
737 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
738 break;
739
740 case 12: /*MEMW*/
741 break;
742
743 case 13: /*EXTW*/
744 break;
745
746 case 15: /*NOP*/
747 break;
748
749 default: /*reserved*/
750 RESERVED();
751 break;
752 }
91a5bb76
MF		 753 break;
754
755 case 3: /*RFEIx*/
40643d7c
MF		 756 switch (RRR_T) {
757 case 0: /*RFETx*/
758 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
759 switch (RRR_S) {
760 case 0: /*RFEx*/
761 gen_check_privilege(dc);
762 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
b994e91b 763 gen_helper_check_interrupts(cpu_env);
40643d7c
MF		 764 gen_jump(dc, cpu_SR[EPC1]);
765 break;
766
767 case 1: /*RFUEx*/
768 RESERVED();
769 break;
770
771 case 2: /*RFDEx*/
772 gen_check_privilege(dc);
773 gen_jump(dc, cpu_SR[
774 dc->config->ndepc ? DEPC : EPC1]);
775 break;
776
777 case 4: /*RFWOw*/
778 case 5: /*RFWUw*/
779 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 780 gen_check_privilege(dc);
781 {
782 TCGv_i32 tmp = tcg_const_i32(1);
783
784 tcg_gen_andi_i32(
785 cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
786 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
787
788 if (RRR_S == 4) {
789 tcg_gen_andc_i32(cpu_SR[WINDOW_START],
790 cpu_SR[WINDOW_START], tmp);
791 } else {
792 tcg_gen_or_i32(cpu_SR[WINDOW_START],
793 cpu_SR[WINDOW_START], tmp);
794 }
795
796 gen_helper_restore_owb();
b994e91b 797 gen_helper_check_interrupts(cpu_env);
553e44f9
MF		 798 gen_jump(dc, cpu_SR[EPC1]);
799
800 tcg_temp_free(tmp);
801 }
40643d7c
MF		 802 break;
803
804 default: /*reserved*/
805 RESERVED();
806 break;
807 }
808 break;
809
810 case 1: /*RFIx*/
811 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT);
b994e91b
MF		 812 if (RRR_S >= 2 && RRR_S <= dc->config->nlevel) {
813 gen_check_privilege(dc);
814 tcg_gen_mov_i32(cpu_SR[PS],
815 cpu_SR[EPS2 + RRR_S - 2]);
816 gen_helper_check_interrupts(cpu_env);
817 gen_jump(dc, cpu_SR[EPC1 + RRR_S - 1]);
818 } else {
819 qemu_log("RFI %d is illegal\n", RRR_S);
820 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
821 }
40643d7c
MF		 822 break;
823
824 case 2: /*RFME*/
825 TBD();
826 break;
827
828 default: /*reserved*/
829 RESERVED();
830 break;
831
832 }
91a5bb76
MF		 833 break;
834
835 case 4: /*BREAKx*/
836 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
837 TBD();
838 break;
839
840 case 5: /*SYSCALLx*/
841 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
40643d7c
MF		 842 switch (RRR_S) {
843 case 0: /*SYSCALLx*/
844 gen_exception_cause(dc, SYSCALL_CAUSE);
845 break;
846
847 case 1: /*SIMCALL*/
1ddeaa5d
MF		 848 if (semihosting_enabled) {
849 gen_check_privilege(dc);
850 gen_helper_simcall(cpu_env);
851 } else {
852 qemu_log("SIMCALL but semihosting is disabled\n");
853 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
854 }
40643d7c
MF		 855 break;
856
857 default:
858 RESERVED();
859 break;
860 }
91a5bb76
MF		 861 break;
862
863 case 6: /*RSILx*/
864 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
40643d7c
MF		 865 gen_check_privilege(dc);
866 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]);
b994e91b 867 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
40643d7c 868 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S);
b994e91b
MF		 869 gen_helper_check_interrupts(cpu_env);
870 gen_jumpi_check_loop_end(dc, 0);
91a5bb76
MF		 871 break;
872
873 case 7: /*WAITIx*/
874 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
b994e91b
MF		 875 gen_check_privilege(dc);
876 gen_waiti(dc, RRR_S);
91a5bb76
MF		 877 break;
878
879 case 8: /*ANY4p*/
880 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
881 TBD();
882 break;
883
884 case 9: /*ALL4p*/
885 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
886 TBD();
dedc5eae
MF		 887 break;
888
91a5bb76
MF		 889 case 10: /*ANY8p*/
890 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
891 TBD();
892 break;
893
894 case 11: /*ALL8p*/
895 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
896 TBD();
897 break;
898
899 default: /*reserved*/
900 RESERVED();
dedc5eae
MF		 901 break;
902
903 }
904 break;
905
906 case 1: /*AND*/
907 tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
908 break;
909
910 case 2: /*OR*/
911 tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
912 break;
913
914 case 3: /*XOR*/
915 tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
916 break;
917
918 case 4: /*ST1*/
3580ecad
MF		 919 switch (RRR_R) {
920 case 0: /*SSR*/
921 gen_right_shift_sar(dc, cpu_R[RRR_S]);
922 break;
923
924 case 1: /*SSL*/
925 gen_left_shift_sar(dc, cpu_R[RRR_S]);
926 break;
927
928 case 2: /*SSA8L*/
929 {
930 TCGv_i32 tmp = tcg_temp_new_i32();
931 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
932 gen_right_shift_sar(dc, tmp);
933 tcg_temp_free(tmp);
934 }
935 break;
936
937 case 3: /*SSA8B*/
938 {
939 TCGv_i32 tmp = tcg_temp_new_i32();
940 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
941 gen_left_shift_sar(dc, tmp);
942 tcg_temp_free(tmp);
943 }
944 break;
945
946 case 4: /*SSAI*/
947 {
948 TCGv_i32 tmp = tcg_const_i32(
949 RRR_S | ((RRR_T & 1) << 4));
950 gen_right_shift_sar(dc, tmp);
951 tcg_temp_free(tmp);
952 }
953 break;
954
955 case 6: /*RER*/
91a5bb76 956 TBD();
3580ecad
MF		 957 break;
958
959 case 7: /*WER*/
91a5bb76 960 TBD();
3580ecad
MF		 961 break;
962
963 case 8: /*ROTWw*/
964 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 965 gen_check_privilege(dc);
966 {
967 TCGv_i32 tmp = tcg_const_i32(
968 RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0));
969 gen_helper_rotw(tmp);
970 tcg_temp_free(tmp);
971 }
3580ecad
MF		 972 break;
973
974 case 14: /*NSAu*/
975 HAS_OPTION(XTENSA_OPTION_MISC_OP);
976 gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]);
977 break;
978
979 case 15: /*NSAUu*/
980 HAS_OPTION(XTENSA_OPTION_MISC_OP);
981 gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]);
982 break;
983
984 default: /*reserved*/
91a5bb76 985 RESERVED();
3580ecad
MF		 986 break;
987 }
dedc5eae
MF		 988 break;
989
990 case 5: /*TLB*/
91a5bb76 991 TBD();
dedc5eae
MF		 992 break;
993
994 case 6: /*RT0*/
f331fe5e
MF		 995 switch (RRR_S) {
996 case 0: /*NEG*/
997 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
998 break;
999
1000 case 1: /*ABS*/
1001 {
1002 int label = gen_new_label();
1003 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1004 tcg_gen_brcondi_i32(
1005 TCG_COND_GE, cpu_R[RRR_R], 0, label);
1006 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1007 gen_set_label(label);
1008 }
1009 break;
1010
1011 default: /*reserved*/
91a5bb76 1012 RESERVED();
f331fe5e
MF		 1013 break;
1014 }
dedc5eae
MF		 1015 break;
1016
1017 case 7: /*reserved*/
91a5bb76 1018 RESERVED();
dedc5eae
MF		 1019 break;
1020
1021 case 8: /*ADD*/
1022 tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1023 break;
1024
1025 case 9: /*ADD**/
1026 case 10:
1027 case 11:
1028 {
1029 TCGv_i32 tmp = tcg_temp_new_i32();
1030 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
1031 tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1032 tcg_temp_free(tmp);
1033 }
1034 break;
1035
1036 case 12: /*SUB*/
1037 tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1038 break;
1039
1040 case 13: /*SUB**/
1041 case 14:
1042 case 15:
1043 {
1044 TCGv_i32 tmp = tcg_temp_new_i32();
1045 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
1046 tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1047 tcg_temp_free(tmp);
1048 }
1049 break;
1050 }
1051 break;
1052
1053 case 1: /*RST1*/
3580ecad
MF		 1054 switch (OP2) {
1055 case 0: /*SLLI*/
1056 case 1:
1057 tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S],
1058 32 - (RRR_T | ((OP2 & 1) << 4)));
1059 break;
1060
1061 case 2: /*SRAI*/
1062 case 3:
1063 tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T],
1064 RRR_S | ((OP2 & 1) << 4));
1065 break;
1066
1067 case 4: /*SRLI*/
1068 tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S);
1069 break;
1070
1071 case 6: /*XSR*/
1072 {
1073 TCGv_i32 tmp = tcg_temp_new_i32();
40643d7c
MF		 1074 if (RSR_SR >= 64) {
1075 gen_check_privilege(dc);
1076 }
3580ecad
MF		 1077 tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
1078 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1079 gen_wsr(dc, RSR_SR, tmp);
1080 tcg_temp_free(tmp);
91a5bb76
MF		 1081 if (!sregnames[RSR_SR]) {
1082 TBD();
1083 }
3580ecad
MF		 1084 }
1085 break;
1086
1087 /*
1088 * Note: 64 bit ops are used here solely because SAR values
1089 * have range 0..63
1090 */
1091#define gen_shift_reg(cmd, reg) do { \
1092 TCGv_i64 tmp = tcg_temp_new_i64(); \
1093 tcg_gen_extu_i32_i64(tmp, reg); \
1094 tcg_gen_##cmd##_i64(v, v, tmp); \
1095 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], v); \
1096 tcg_temp_free_i64(v); \
1097 tcg_temp_free_i64(tmp); \
1098 } while (0)
1099
1100#define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1101
1102 case 8: /*SRC*/
1103 {
1104 TCGv_i64 v = tcg_temp_new_i64();
1105 tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]);
1106 gen_shift(shr);
1107 }
1108 break;
1109
1110 case 9: /*SRL*/
1111 if (dc->sar_5bit) {
1112 tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1113 } else {
1114 TCGv_i64 v = tcg_temp_new_i64();
1115 tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]);
1116 gen_shift(shr);
1117 }
1118 break;
1119
1120 case 10: /*SLL*/
1121 if (dc->sar_m32_5bit) {
1122 tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32);
1123 } else {
1124 TCGv_i64 v = tcg_temp_new_i64();
1125 TCGv_i32 s = tcg_const_i32(32);
1126 tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
1127 tcg_gen_andi_i32(s, s, 0x3f);
1128 tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]);
1129 gen_shift_reg(shl, s);
1130 tcg_temp_free(s);
1131 }
1132 break;
1133
1134 case 11: /*SRA*/
1135 if (dc->sar_5bit) {
1136 tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1137 } else {
1138 TCGv_i64 v = tcg_temp_new_i64();
1139 tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]);
1140 gen_shift(sar);
1141 }
1142 break;
1143#undef gen_shift
1144#undef gen_shift_reg
1145
1146 case 12: /*MUL16U*/
1147 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
1148 {
1149 TCGv_i32 v1 = tcg_temp_new_i32();
1150 TCGv_i32 v2 = tcg_temp_new_i32();
1151 tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]);
1152 tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]);
1153 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1154 tcg_temp_free(v2);
1155 tcg_temp_free(v1);
1156 }
1157 break;
1158
1159 case 13: /*MUL16S*/
1160 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
1161 {
1162 TCGv_i32 v1 = tcg_temp_new_i32();
1163 TCGv_i32 v2 = tcg_temp_new_i32();
1164 tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]);
1165 tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]);
1166 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1167 tcg_temp_free(v2);
1168 tcg_temp_free(v1);
1169 }
1170 break;
1171
1172 default: /*reserved*/
91a5bb76 1173 RESERVED();
3580ecad
MF		 1174 break;
1175 }
dedc5eae
MF		 1176 break;
1177
1178 case 2: /*RST2*/
f76ebf55
MF		 1179 if (OP2 >= 12) {
1180 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV);
1181 int label = gen_new_label();
1182 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label);
1183 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
1184 gen_set_label(label);
1185 }
1186
1187 switch (OP2) {
1188 case 8: /*MULLi*/
1189 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
1190 tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1191 break;
1192
1193 case 10: /*MULUHi*/
1194 case 11: /*MULSHi*/
1195 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
1196 {
1197 TCGv_i64 r = tcg_temp_new_i64();
1198 TCGv_i64 s = tcg_temp_new_i64();
1199 TCGv_i64 t = tcg_temp_new_i64();
1200
1201 if (OP2 == 10) {
1202 tcg_gen_extu_i32_i64(s, cpu_R[RRR_S]);
1203 tcg_gen_extu_i32_i64(t, cpu_R[RRR_T]);
1204 } else {
1205 tcg_gen_ext_i32_i64(s, cpu_R[RRR_S]);
1206 tcg_gen_ext_i32_i64(t, cpu_R[RRR_T]);
1207 }
1208 tcg_gen_mul_i64(r, s, t);
1209 tcg_gen_shri_i64(r, r, 32);
1210 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], r);
1211
1212 tcg_temp_free_i64(r);
1213 tcg_temp_free_i64(s);
1214 tcg_temp_free_i64(t);
1215 }
1216 break;
1217
1218 case 12: /*QUOUi*/
1219 tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1220 break;
1221
1222 case 13: /*QUOSi*/
1223 case 15: /*REMSi*/
1224 {
1225 int label1 = gen_new_label();
1226 int label2 = gen_new_label();
1227
1228 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000,
1229 label1);
1230 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff,
1231 label1);
1232 tcg_gen_movi_i32(cpu_R[RRR_R],
1233 OP2 == 13 ? 0x80000000 : 0);
1234 tcg_gen_br(label2);
1235 gen_set_label(label1);
1236 if (OP2 == 13) {
1237 tcg_gen_div_i32(cpu_R[RRR_R],
1238 cpu_R[RRR_S], cpu_R[RRR_T]);
1239 } else {
1240 tcg_gen_rem_i32(cpu_R[RRR_R],
1241 cpu_R[RRR_S], cpu_R[RRR_T]);
1242 }
1243 gen_set_label(label2);
1244 }
1245 break;
1246
1247 case 14: /*REMUi*/
1248 tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1249 break;
1250
1251 default: /*reserved*/
1252 RESERVED();
1253 break;
1254 }
dedc5eae
MF		 1255 break;
1256
1257 case 3: /*RST3*/
b8132eff
MF		 1258 switch (OP2) {
1259 case 0: /*RSR*/
40643d7c
MF		 1260 if (RSR_SR >= 64) {
1261 gen_check_privilege(dc);
1262 }
b8132eff 1263 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
91a5bb76
MF		 1264 if (!sregnames[RSR_SR]) {
1265 TBD();
1266 }
b8132eff
MF		 1267 break;
1268
1269 case 1: /*WSR*/
40643d7c
MF		 1270 if (RSR_SR >= 64) {
1271 gen_check_privilege(dc);
1272 }
b8132eff 1273 gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
91a5bb76
MF		 1274 if (!sregnames[RSR_SR]) {
1275 TBD();
1276 }
b8132eff
MF		 1277 break;
1278
1279 case 2: /*SEXTu*/
1280 HAS_OPTION(XTENSA_OPTION_MISC_OP);
1281 {
1282 int shift = 24 - RRR_T;
1283
1284 if (shift == 24) {
1285 tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1286 } else if (shift == 16) {
1287 tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1288 } else {
1289 TCGv_i32 tmp = tcg_temp_new_i32();
1290 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift);
1291 tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift);
1292 tcg_temp_free(tmp);
1293 }
1294 }
1295 break;
1296
1297 case 3: /*CLAMPSu*/
1298 HAS_OPTION(XTENSA_OPTION_MISC_OP);
1299 {
1300 TCGv_i32 tmp1 = tcg_temp_new_i32();
1301 TCGv_i32 tmp2 = tcg_temp_new_i32();
1302 int label = gen_new_label();
1303
1304 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T);
1305 tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]);
1306 tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7));
1307 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1308 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp2, 0, label);
1309
1310 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31);
1311 tcg_gen_xori_i32(cpu_R[RRR_R], tmp1,
1312 0xffffffff >> (25 - RRR_T));
1313
1314 gen_set_label(label);
1315
1316 tcg_temp_free(tmp1);
1317 tcg_temp_free(tmp2);
1318 }
1319 break;
1320
1321 case 4: /*MINu*/
1322 case 5: /*MAXu*/
1323 case 6: /*MINUu*/
1324 case 7: /*MAXUu*/
1325 HAS_OPTION(XTENSA_OPTION_MISC_OP);
1326 {
1327 static const TCGCond cond[] = {
1328 TCG_COND_LE,
1329 TCG_COND_GE,
1330 TCG_COND_LEU,
1331 TCG_COND_GEU
1332 };
1333 int label = gen_new_label();
1334
1335 if (RRR_R != RRR_T) {
1336 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1337 tcg_gen_brcond_i32(cond[OP2 - 4],
1338 cpu_R[RRR_S], cpu_R[RRR_T], label);
1339 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1340 } else {
1341 tcg_gen_brcond_i32(cond[OP2 - 4],
1342 cpu_R[RRR_T], cpu_R[RRR_S], label);
1343 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1344 }
1345 gen_set_label(label);
1346 }
1347 break;
1348
1349 case 8: /*MOVEQZ*/
1350 case 9: /*MOVNEZ*/
1351 case 10: /*MOVLTZ*/
1352 case 11: /*MOVGEZ*/
1353 {
1354 static const TCGCond cond[] = {
1355 TCG_COND_NE,
1356 TCG_COND_EQ,
1357 TCG_COND_GE,
1358 TCG_COND_LT
1359 };
1360 int label = gen_new_label();
1361 tcg_gen_brcondi_i32(cond[OP2 - 8], cpu_R[RRR_T], 0, label);
1362 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1363 gen_set_label(label);
1364 }
1365 break;
1366
1367 case 12: /*MOVFp*/
1368 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
91a5bb76 1369 TBD();
b8132eff
MF		 1370 break;
1371
1372 case 13: /*MOVTp*/
1373 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
91a5bb76 1374 TBD();
b8132eff
MF		 1375 break;
1376
1377 case 14: /*RUR*/
1378 {
1379 int st = (RRR_S << 4) + RRR_T;
1380 if (uregnames[st]) {
1381 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]);
1382 } else {
1383 qemu_log("RUR %d not implemented, ", st);
91a5bb76 1384 TBD();
b8132eff
MF		 1385 }
1386 }
1387 break;
1388
1389 case 15: /*WUR*/
1390 {
1391 if (uregnames[RSR_SR]) {
1392 tcg_gen_mov_i32(cpu_UR[RSR_SR], cpu_R[RRR_T]);
1393 } else {
1394 qemu_log("WUR %d not implemented, ", RSR_SR);
91a5bb76 1395 TBD();
b8132eff
MF		 1396 }
1397 }
1398 break;
1399
1400 }
dedc5eae
MF		 1401 break;
1402
1403 case 4: /*EXTUI*/
1404 case 5:
3580ecad
MF		 1405 {
1406 int shiftimm = RRR_S | (OP1 << 4);
1407 int maskimm = (1 << (OP2 + 1)) - 1;
1408
1409 TCGv_i32 tmp = tcg_temp_new_i32();
1410 tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
1411 tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
1412 tcg_temp_free(tmp);
1413 }
dedc5eae
MF		 1414 break;
1415
1416 case 6: /*CUST0*/
91a5bb76 1417 RESERVED();
dedc5eae
MF		 1418 break;
1419
1420 case 7: /*CUST1*/
91a5bb76 1421 RESERVED();
dedc5eae
MF		 1422 break;
1423
1424 case 8: /*LSCXp*/
1425 HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
91a5bb76 1426 TBD();
dedc5eae
MF		 1427 break;
1428
1429 case 9: /*LSC4*/
553e44f9
MF		 1430 switch (OP2) {
1431 case 0: /*L32E*/
1432 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1433 gen_check_privilege(dc);
1434 {
1435 TCGv_i32 addr = tcg_temp_new_i32();
1436 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1437 (0xffffffc0 | (RRR_R << 2)));
1438 tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring);
1439 tcg_temp_free(addr);
1440 }
1441 break;
1442
1443 case 4: /*S32E*/
1444 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1445 gen_check_privilege(dc);
1446 {
1447 TCGv_i32 addr = tcg_temp_new_i32();
1448 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1449 (0xffffffc0 | (RRR_R << 2)));
1450 tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring);
1451 tcg_temp_free(addr);
1452 }
1453 break;
1454
1455 default:
1456 RESERVED();
1457 break;
1458 }
dedc5eae
MF		 1459 break;
1460
1461 case 10: /*FP0*/
1462 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
91a5bb76 1463 TBD();
dedc5eae
MF		 1464 break;
1465
1466 case 11: /*FP1*/
1467 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
91a5bb76 1468 TBD();
dedc5eae
MF		 1469 break;
1470
1471 default: /*reserved*/
91a5bb76 1472 RESERVED();
dedc5eae
MF		 1473 break;
1474 }
1475 break;
1476
1477 case 1: /*L32R*/
1478 {
1479 TCGv_i32 tmp = tcg_const_i32(
6ad6dbf7
MF		 1480 ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ?
1481 0 : ((dc->pc + 3) & ~3)) +
1482 (0xfffc0000 | (RI16_IMM16 << 2)));
dedc5eae 1483
6ad6dbf7
MF		 1484 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
1485 tcg_gen_add_i32(tmp, tmp, dc->litbase);
1486 }
f0a548b9 1487 tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring);
dedc5eae
MF		 1488 tcg_temp_free(tmp);
1489 }
1490 break;
1491
1492 case 2: /*LSAI*/
809377aa
MF		 1493#define gen_load_store(type, shift) do { \
1494 TCGv_i32 addr = tcg_temp_new_i32(); \
1495 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
5b4e481b
MF		 1496 if (shift) { \
1497 gen_load_store_alignment(dc, shift, addr, false); \
1498 } \
f0a548b9 1499 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
809377aa
MF		 1500 tcg_temp_free(addr); \
1501 } while (0)
1502
1503 switch (RRI8_R) {
1504 case 0: /*L8UI*/
1505 gen_load_store(ld8u, 0);
1506 break;
1507
1508 case 1: /*L16UI*/
1509 gen_load_store(ld16u, 1);
1510 break;
1511
1512 case 2: /*L32I*/
1513 gen_load_store(ld32u, 2);
1514 break;
1515
1516 case 4: /*S8I*/
1517 gen_load_store(st8, 0);
1518 break;
1519
1520 case 5: /*S16I*/
1521 gen_load_store(st16, 1);
1522 break;
1523
1524 case 6: /*S32I*/
1525 gen_load_store(st32, 2);
1526 break;
1527
1528 case 7: /*CACHEc*/
8ffc2d0d
MF		 1529 if (RRI8_T < 8) {
1530 HAS_OPTION(XTENSA_OPTION_DCACHE);
1531 }
1532
1533 switch (RRI8_T) {
1534 case 0: /*DPFRc*/
1535 break;
1536
1537 case 1: /*DPFWc*/
1538 break;
1539
1540 case 2: /*DPFROc*/
1541 break;
1542
1543 case 3: /*DPFWOc*/
1544 break;
1545
1546 case 4: /*DHWBc*/
1547 break;
1548
1549 case 5: /*DHWBIc*/
1550 break;
1551
1552 case 6: /*DHIc*/
1553 break;
1554
1555 case 7: /*DIIc*/
1556 break;
1557
1558 case 8: /*DCEc*/
1559 switch (OP1) {
1560 case 0: /*DPFLl*/
1561 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
1562 break;
1563
1564 case 2: /*DHUl*/
1565 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
1566 break;
1567
1568 case 3: /*DIUl*/
1569 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
1570 break;
1571
1572 case 4: /*DIWBc*/
1573 HAS_OPTION(XTENSA_OPTION_DCACHE);
1574 break;
1575
1576 case 5: /*DIWBIc*/
1577 HAS_OPTION(XTENSA_OPTION_DCACHE);
1578 break;
1579
1580 default: /*reserved*/
1581 RESERVED();
1582 break;
1583
1584 }
1585 break;
1586
1587 case 12: /*IPFc*/
1588 HAS_OPTION(XTENSA_OPTION_ICACHE);
1589 break;
1590
1591 case 13: /*ICEc*/
1592 switch (OP1) {
1593 case 0: /*IPFLl*/
1594 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
1595 break;
1596
1597 case 2: /*IHUl*/
1598 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
1599 break;
1600
1601 case 3: /*IIUl*/
1602 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
1603 break;
1604
1605 default: /*reserved*/
1606 RESERVED();
1607 break;
1608 }
1609 break;
1610
1611 case 14: /*IHIc*/
1612 HAS_OPTION(XTENSA_OPTION_ICACHE);
1613 break;
1614
1615 case 15: /*IIIc*/
1616 HAS_OPTION(XTENSA_OPTION_ICACHE);
1617 break;
1618
1619 default: /*reserved*/
1620 RESERVED();
1621 break;
1622 }
809377aa
MF		 1623 break;
1624
1625 case 9: /*L16SI*/
1626 gen_load_store(ld16s, 1);
1627 break;
5b4e481b 1628#undef gen_load_store
809377aa
MF		 1629
1630 case 10: /*MOVI*/
1631 tcg_gen_movi_i32(cpu_R[RRI8_T],
1632 RRI8_IMM8 | (RRI8_S << 8) |
1633 ((RRI8_S & 0x8) ? 0xfffff000 : 0));
1634 break;
1635
5b4e481b
MF		 1636#define gen_load_store_no_hw_align(type) do { \
1637 TCGv_i32 addr = tcg_temp_local_new_i32(); \
1638 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
1639 gen_load_store_alignment(dc, 2, addr, true); \
1640 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
1641 tcg_temp_free(addr); \
1642 } while (0)
1643
809377aa
MF		 1644 case 11: /*L32AIy*/
1645 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
5b4e481b 1646 gen_load_store_no_hw_align(ld32u); /*TODO acquire?*/
809377aa
MF		 1647 break;
1648
1649 case 12: /*ADDI*/
1650 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE);
1651 break;
1652
1653 case 13: /*ADDMI*/
1654 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE << 8);
1655 break;
1656
1657 case 14: /*S32C1Iy*/
1658 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
1659 {
1660 int label = gen_new_label();
1661 TCGv_i32 tmp = tcg_temp_local_new_i32();
1662 TCGv_i32 addr = tcg_temp_local_new_i32();
1663
1664 tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]);
1665 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
5b4e481b 1666 gen_load_store_alignment(dc, 2, addr, true);
f0a548b9 1667 tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring);
809377aa
MF		 1668 tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T],
1669 cpu_SR[SCOMPARE1], label);
1670
f0a548b9 1671 tcg_gen_qemu_st32(tmp, addr, dc->cring);
809377aa
MF		 1672
1673 gen_set_label(label);
1674 tcg_temp_free(addr);
1675 tcg_temp_free(tmp);
1676 }
1677 break;
1678
1679 case 15: /*S32RIy*/
1680 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
5b4e481b 1681 gen_load_store_no_hw_align(st32); /*TODO release?*/
809377aa 1682 break;
5b4e481b 1683#undef gen_load_store_no_hw_align
809377aa
MF		 1684
1685 default: /*reserved*/
91a5bb76 1686 RESERVED();
809377aa
MF		 1687 break;
1688 }
dedc5eae
MF		 1689 break;
1690
1691 case 3: /*LSCIp*/
1692 HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
91a5bb76 1693 TBD();
dedc5eae
MF		 1694 break;
1695
1696 case 4: /*MAC16d*/
1697 HAS_OPTION(XTENSA_OPTION_MAC16);
91a5bb76 1698 TBD();
dedc5eae
MF		 1699 break;
1700
1701 case 5: /*CALLN*/
1702 switch (CALL_N) {
1703 case 0: /*CALL0*/
1704 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
1705 gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
1706 break;
1707
1708 case 1: /*CALL4w*/
1709 case 2: /*CALL8w*/
1710 case 3: /*CALL12w*/
1711 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 1712 gen_callwi(dc, CALL_N,
1713 (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
dedc5eae
MF		 1714 break;
1715 }
1716 break;
1717
1718 case 6: /*SI*/
1719 switch (CALL_N) {
1720 case 0: /*J*/
1721 gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
1722 break;
1723
bd57fb91
MF		 1724 case 1: /*BZ*/
1725 {
1726 static const TCGCond cond[] = {
1727 TCG_COND_EQ, /*BEQZ*/
1728 TCG_COND_NE, /*BNEZ*/
1729 TCG_COND_LT, /*BLTZ*/
1730 TCG_COND_GE, /*BGEZ*/
1731 };
1732
1733 gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0,
1734 4 + BRI12_IMM12_SE);
1735 }
1736 break;
1737
1738 case 2: /*BI0*/
1739 {
1740 static const TCGCond cond[] = {
1741 TCG_COND_EQ, /*BEQI*/
1742 TCG_COND_NE, /*BNEI*/
1743 TCG_COND_LT, /*BLTI*/
1744 TCG_COND_GE, /*BGEI*/
1745 };
1746
1747 gen_brcondi(dc, cond[BRI8_M & 3],
1748 cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE);
1749 }
1750 break;
1751
1752 case 3: /*BI1*/
1753 switch (BRI8_M) {
1754 case 0: /*ENTRYw*/
1755 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 1756 {
1757 TCGv_i32 pc = tcg_const_i32(dc->pc);
1758 TCGv_i32 s = tcg_const_i32(BRI12_S);
1759 TCGv_i32 imm = tcg_const_i32(BRI12_IMM12);
b994e91b 1760 gen_advance_ccount(dc);
553e44f9
MF		 1761 gen_helper_entry(pc, s, imm);
1762 tcg_temp_free(imm);
1763 tcg_temp_free(s);
1764 tcg_temp_free(pc);
1765 }
bd57fb91
MF		 1766 break;
1767
1768 case 1: /*B1*/
1769 switch (BRI8_R) {
1770 case 0: /*BFp*/
1771 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
91a5bb76 1772 TBD();
bd57fb91
MF		 1773 break;
1774
1775 case 1: /*BTp*/
1776 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
91a5bb76 1777 TBD();
bd57fb91
MF		 1778 break;
1779
1780 case 8: /*LOOP*/
bd57fb91 1781 case 9: /*LOOPNEZ*/
bd57fb91 1782 case 10: /*LOOPGTZ*/
797d780b
MF		 1783 HAS_OPTION(XTENSA_OPTION_LOOP);
1784 {
1785 uint32_t lend = dc->pc + RRI8_IMM8 + 4;
1786 TCGv_i32 tmp = tcg_const_i32(lend);
1787
1788 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[RRI8_S], 1);
1789 tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc);
1790 gen_wsr_lend(dc, LEND, tmp);
1791 tcg_temp_free(tmp);
1792
1793 if (BRI8_R > 8) {
1794 int label = gen_new_label();
1795 tcg_gen_brcondi_i32(
1796 BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT,
1797 cpu_R[RRI8_S], 0, label);
1798 gen_jumpi(dc, lend, 1);
1799 gen_set_label(label);
1800 }
1801
1802 gen_jumpi(dc, dc->next_pc, 0);
1803 }
bd57fb91
MF		 1804 break;
1805
1806 default: /*reserved*/
91a5bb76 1807 RESERVED();
bd57fb91
MF		 1808 break;
1809
1810 }
1811 break;
1812
1813 case 2: /*BLTUI*/
1814 case 3: /*BGEUI*/
1815 gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU,
1816 cpu_R[BRI8_S], B4CONSTU[BRI8_R], 4 + BRI8_IMM8_SE);
1817 break;
1818 }
1819 break;
1820
dedc5eae
MF		 1821 }
1822 break;
1823
1824 case 7: /*B*/
bd57fb91
MF		 1825 {
1826 TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ;
1827
1828 switch (RRI8_R & 7) {
1829 case 0: /*BNONE*/ /*BANY*/
1830 {
1831 TCGv_i32 tmp = tcg_temp_new_i32();
1832 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
1833 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
1834 tcg_temp_free(tmp);
1835 }
1836 break;
1837
1838 case 1: /*BEQ*/ /*BNE*/
1839 case 2: /*BLT*/ /*BGE*/
1840 case 3: /*BLTU*/ /*BGEU*/
1841 {
1842 static const TCGCond cond[] = {
1843 [1] = TCG_COND_EQ,
1844 [2] = TCG_COND_LT,
1845 [3] = TCG_COND_LTU,
1846 [9] = TCG_COND_NE,
1847 [10] = TCG_COND_GE,
1848 [11] = TCG_COND_GEU,
1849 };
1850 gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T],
1851 4 + RRI8_IMM8_SE);
1852 }
1853 break;
1854
1855 case 4: /*BALL*/ /*BNALL*/
1856 {
1857 TCGv_i32 tmp = tcg_temp_new_i32();
1858 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
1859 gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T],
1860 4 + RRI8_IMM8_SE);
1861 tcg_temp_free(tmp);
1862 }
1863 break;
1864
1865 case 5: /*BBC*/ /*BBS*/
1866 {
1867 TCGv_i32 bit = tcg_const_i32(1);
1868 TCGv_i32 tmp = tcg_temp_new_i32();
1869 tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
1870 tcg_gen_shl_i32(bit, bit, tmp);
1871 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
1872 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
1873 tcg_temp_free(tmp);
1874 tcg_temp_free(bit);
1875 }
1876 break;
1877
1878 case 6: /*BBCI*/ /*BBSI*/
1879 case 7:
1880 {
1881 TCGv_i32 tmp = tcg_temp_new_i32();
1882 tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
1883 1 << (((RRI8_R & 1) << 4) | RRI8_T));
1884 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
1885 tcg_temp_free(tmp);
1886 }
1887 break;
1888
1889 }
1890 }
dedc5eae
MF		 1891 break;
1892
67882fd1
MF		 1893#define gen_narrow_load_store(type) do { \
1894 TCGv_i32 addr = tcg_temp_new_i32(); \
1895 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
5b4e481b 1896 gen_load_store_alignment(dc, 2, addr, false); \
f0a548b9 1897 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
67882fd1
MF		 1898 tcg_temp_free(addr); \
1899 } while (0)
1900
dedc5eae 1901 case 8: /*L32I.Nn*/
67882fd1 1902 gen_narrow_load_store(ld32u);
dedc5eae
MF		 1903 break;
1904
1905 case 9: /*S32I.Nn*/
67882fd1 1906 gen_narrow_load_store(st32);
dedc5eae 1907 break;
67882fd1 1908#undef gen_narrow_load_store
dedc5eae
MF		 1909
1910 case 10: /*ADD.Nn*/
67882fd1 1911 tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
dedc5eae
MF		 1912 break;
1913
1914 case 11: /*ADDI.Nn*/
67882fd1 1915 tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], RRRN_T ? RRRN_T : -1);
dedc5eae
MF		 1916 break;
1917
1918 case 12: /*ST2n*/
67882fd1
MF		 1919 if (RRRN_T < 8) { /*MOVI.Nn*/
1920 tcg_gen_movi_i32(cpu_R[RRRN_S],
1921 RRRN_R | (RRRN_T << 4) |
1922 ((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
1923 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
bd57fb91
MF		 1924 TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ;
1925
1926 gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0,
1927 4 + (RRRN_R | ((RRRN_T & 3) << 4)));
67882fd1 1928 }
dedc5eae
MF		 1929 break;
1930
1931 case 13: /*ST3n*/
67882fd1
MF		 1932 switch (RRRN_R) {
1933 case 0: /*MOV.Nn*/
1934 tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
1935 break;
1936
1937 case 15: /*S3*/
1938 switch (RRRN_T) {
1939 case 0: /*RET.Nn*/
1940 gen_jump(dc, cpu_R[0]);
1941 break;
1942
1943 case 1: /*RETW.Nn*/
91a5bb76 1944 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 1945 {
1946 TCGv_i32 tmp = tcg_const_i32(dc->pc);
b994e91b 1947 gen_advance_ccount(dc);
553e44f9
MF		 1948 gen_helper_retw(tmp, tmp);
1949 gen_jump(dc, tmp);
1950 tcg_temp_free(tmp);
1951 }
67882fd1
MF		 1952 break;
1953
1954 case 2: /*BREAK.Nn*/
91a5bb76 1955 TBD();
67882fd1
MF		 1956 break;
1957
1958 case 3: /*NOP.Nn*/
1959 break;
1960
1961 case 6: /*ILL.Nn*/
40643d7c 1962 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
67882fd1
MF		 1963 break;
1964
1965 default: /*reserved*/
91a5bb76 1966 RESERVED();
67882fd1
MF		 1967 break;
1968 }
1969 break;
1970
1971 default: /*reserved*/
91a5bb76 1972 RESERVED();
67882fd1
MF		 1973 break;
1974 }
dedc5eae
MF		 1975 break;
1976
1977 default: /*reserved*/
91a5bb76 1978 RESERVED();
dedc5eae
MF		 1979 break;
1980 }
1981
797d780b 1982 gen_check_loop_end(dc, 0);
dedc5eae 1983 dc->pc = dc->next_pc;
797d780b 1984
dedc5eae
MF		 1985 return;
1986
1987invalid_opcode:
1988 qemu_log("INVALID(pc = %08x)\n", dc->pc);
1989 dc->pc = dc->next_pc;
1990#undef HAS_OPTION
1991}
1992
1993static void check_breakpoint(CPUState *env, DisasContext *dc)
1994{
1995 CPUBreakpoint *bp;
1996
1997 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
1998 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
1999 if (bp->pc == dc->pc) {
2000 tcg_gen_movi_i32(cpu_pc, dc->pc);
b994e91b 2001 gen_exception(dc, EXCP_DEBUG);
dedc5eae
MF		 2002 dc->is_jmp = DISAS_UPDATE;
2003 }
2004 }
2005 }
2006}
2007
2008static void gen_intermediate_code_internal(
2009 CPUState *env, TranslationBlock *tb, int search_pc)
2010{
2011 DisasContext dc;
2012 int insn_count = 0;
2013 int j, lj = -1;
2014 uint16_t *gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2015 int max_insns = tb->cflags & CF_COUNT_MASK;
2016 uint32_t pc_start = tb->pc;
2017 uint32_t next_page_start =
2018 (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2019
2020 if (max_insns == 0) {
2021 max_insns = CF_COUNT_MASK;
2022 }
2023
2024 dc.config = env->config;
2025 dc.singlestep_enabled = env->singlestep_enabled;
2026 dc.tb = tb;
2027 dc.pc = pc_start;
f0a548b9
MF		 2028 dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
2029 dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring;
797d780b
MF		 2030 dc.lbeg = env->sregs[LBEG];
2031 dc.lend = env->sregs[LEND];
dedc5eae 2032 dc.is_jmp = DISAS_NEXT;
b994e91b 2033 dc.ccount_delta = 0;
dedc5eae 2034
6ad6dbf7 2035 init_litbase(&dc);
3580ecad
MF		 2036 init_sar_tracker(&dc);
2037
dedc5eae
MF		 2038 gen_icount_start();
2039
40643d7c
MF		 2040 if (env->singlestep_enabled && env->exception_taken) {
2041 env->exception_taken = 0;
2042 tcg_gen_movi_i32(cpu_pc, dc.pc);
b994e91b 2043 gen_exception(&dc, EXCP_DEBUG);
40643d7c
MF		 2044 }
2045
dedc5eae
MF		 2046 do {
2047 check_breakpoint(env, &dc);
2048
2049 if (search_pc) {
2050 j = gen_opc_ptr - gen_opc_buf;
2051 if (lj < j) {
2052 lj++;
2053 while (lj < j) {
2054 gen_opc_instr_start[lj++] = 0;
2055 }
2056 }
2057 gen_opc_pc[lj] = dc.pc;
2058 gen_opc_instr_start[lj] = 1;
2059 gen_opc_icount[lj] = insn_count;
2060 }
2061
2062 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
2063 tcg_gen_debug_insn_start(dc.pc);
2064 }
2065
b994e91b
MF		 2066 ++dc.ccount_delta;
2067
2068 if (insn_count + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
2069 gen_io_start();
2070 }
2071
dedc5eae
MF		 2072 disas_xtensa_insn(&dc);
2073 ++insn_count;
2074 if (env->singlestep_enabled) {
2075 tcg_gen_movi_i32(cpu_pc, dc.pc);
b994e91b 2076 gen_exception(&dc, EXCP_DEBUG);
dedc5eae
MF		 2077 break;
2078 }
2079 } while (dc.is_jmp == DISAS_NEXT &&
2080 insn_count < max_insns &&
2081 dc.pc < next_page_start &&
2082 gen_opc_ptr < gen_opc_end);
2083
6ad6dbf7 2084 reset_litbase(&dc);
3580ecad
MF		 2085 reset_sar_tracker(&dc);
2086
b994e91b
MF		 2087 if (tb->cflags & CF_LAST_IO) {
2088 gen_io_end();
2089 }
2090
dedc5eae
MF		 2091 if (dc.is_jmp == DISAS_NEXT) {
2092 gen_jumpi(&dc, dc.pc, 0);
2093 }
2094 gen_icount_end(tb, insn_count);
2095 *gen_opc_ptr = INDEX_op_end;
2096
2097 if (!search_pc) {
2098 tb->size = dc.pc - pc_start;
2099 tb->icount = insn_count;
2100 }
2328826b
MF		 2101}
2102
2103void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
2104{
dedc5eae 2105 gen_intermediate_code_internal(env, tb, 0);
2328826b
MF		 2106}
2107
2108void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
2109{
dedc5eae 2110 gen_intermediate_code_internal(env, tb, 1);
2328826b
MF		 2111}
2112
2113void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
2114 int flags)
2115{
2af3da91
MF		 2116 int i, j;
2117
2118 cpu_fprintf(f, "PC=%08x\n\n", env->pc);
2119
2120 for (i = j = 0; i < 256; ++i) {
2121 if (sregnames[i]) {
2122 cpu_fprintf(f, "%s=%08x%c", sregnames[i], env->sregs[i],
2123 (j++ % 4) == 3 ? '\n' : ' ');
2124 }
2125 }
2126
2127 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
2128
2129 for (i = j = 0; i < 256; ++i) {
2130 if (uregnames[i]) {
2131 cpu_fprintf(f, "%s=%08x%c", uregnames[i], env->uregs[i],
2132 (j++ % 4) == 3 ? '\n' : ' ');
2133 }
2134 }
2328826b 2135
2af3da91 2136 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
2328826b
MF		 2137
2138 for (i = 0; i < 16; ++i) {
2139 cpu_fprintf(f, "A%02d=%08x%c", i, env->regs[i],
2140 (i % 4) == 3 ? '\n' : ' ');
2141 }
553e44f9
MF		 2142
2143 cpu_fprintf(f, "\n");
2144
2145 for (i = 0; i < env->config->nareg; ++i) {
2146 cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i],
2147 (i % 4) == 3 ? '\n' : ' ');
2148 }
2328826b
MF		 2149}
2150
2151void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
2152{
2153 env->pc = gen_opc_pc[pc_pos];
2154}
QEMU mirror