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811d4cf4
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1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Andrzej Zaborowski
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
d4a9eb1f 24
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25#if defined(__ARM_ARCH_7__) || \
26 defined(__ARM_ARCH_7A__) || \
27 defined(__ARM_ARCH_7EM__) || \
28 defined(__ARM_ARCH_7M__) || \
29 defined(__ARM_ARCH_7R__)
30#define USE_ARMV7_INSTRUCTIONS
31#endif
32
33#if defined(USE_ARMV7_INSTRUCTIONS) || \
34 defined(__ARM_ARCH_6J__) || \
35 defined(__ARM_ARCH_6K__) || \
36 defined(__ARM_ARCH_6T2__) || \
37 defined(__ARM_ARCH_6Z__) || \
38 defined(__ARM_ARCH_6ZK__)
39#define USE_ARMV6_INSTRUCTIONS
40#endif
41
42#if defined(USE_ARMV6_INSTRUCTIONS) || \
43 defined(__ARM_ARCH_5T__) || \
44 defined(__ARM_ARCH_5TE__) || \
45 defined(__ARM_ARCH_5TEJ__)
46#define USE_ARMV5_INSTRUCTIONS
47#endif
48
49#ifdef USE_ARMV5_INSTRUCTIONS
50static const int use_armv5_instructions = 1;
51#else
52static const int use_armv5_instructions = 0;
53#endif
54#undef USE_ARMV5_INSTRUCTIONS
55
56#ifdef USE_ARMV6_INSTRUCTIONS
57static const int use_armv6_instructions = 1;
58#else
59static const int use_armv6_instructions = 0;
60#endif
61#undef USE_ARMV6_INSTRUCTIONS
62
63#ifdef USE_ARMV7_INSTRUCTIONS
64static const int use_armv7_instructions = 1;
65#else
66static const int use_armv7_instructions = 0;
67#endif
68#undef USE_ARMV7_INSTRUCTIONS
69
d4a9eb1f
BS
70#ifndef NDEBUG
71static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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72 "%r0",
73 "%r1",
74 "%r2",
75 "%r3",
76 "%r4",
77 "%r5",
78 "%r6",
79 "%r7",
80 "%r8",
81 "%r9",
82 "%r10",
83 "%r11",
84 "%r12",
85 "%r13",
86 "%r14",
e4a7d5e8 87 "%pc",
811d4cf4 88};
d4a9eb1f 89#endif
811d4cf4 90
d4a9eb1f 91static const int tcg_target_reg_alloc_order[] = {
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92 TCG_REG_R4,
93 TCG_REG_R5,
94 TCG_REG_R6,
95 TCG_REG_R7,
96 TCG_REG_R8,
97 TCG_REG_R9,
98 TCG_REG_R10,
99 TCG_REG_R11,
811d4cf4 100 TCG_REG_R13,
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101 TCG_REG_R0,
102 TCG_REG_R1,
103 TCG_REG_R2,
104 TCG_REG_R3,
105 TCG_REG_R12,
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106 TCG_REG_R14,
107};
108
d4a9eb1f 109static const int tcg_target_call_iarg_regs[4] = {
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110 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3
111};
d4a9eb1f 112static const int tcg_target_call_oarg_regs[2] = {
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113 TCG_REG_R0, TCG_REG_R1
114};
115
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116static inline void reloc_abs32(void *code_ptr, tcg_target_long target)
117{
118 *(uint32_t *) code_ptr = target;
119}
120
121static inline void reloc_pc24(void *code_ptr, tcg_target_long target)
122{
123 uint32_t offset = ((target - ((tcg_target_long) code_ptr + 8)) >> 2);
124
125 *(uint32_t *) code_ptr = ((*(uint32_t *) code_ptr) & ~0xffffff)
126 | (offset & 0xffffff);
127}
128
650bbb36 129static void patch_reloc(uint8_t *code_ptr, int type,
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130 tcg_target_long value, tcg_target_long addend)
131{
132 switch (type) {
133 case R_ARM_ABS32:
c69806ab 134 reloc_abs32(code_ptr, value);
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135 break;
136
137 case R_ARM_CALL:
138 case R_ARM_JUMP24:
139 default:
140 tcg_abort();
141
142 case R_ARM_PC24:
c69806ab 143 reloc_pc24(code_ptr, value);
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144 break;
145 }
146}
147
148/* maximum number of register used for input function arguments */
149static inline int tcg_target_get_call_iarg_regs_count(int flags)
150{
151 return 4;
152}
153
811d4cf4 154/* parse target specific constraints */
d4a9eb1f 155static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
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156{
157 const char *ct_str;
158
159 ct_str = *pct_str;
160 switch (ct_str[0]) {
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161 case 'I':
162 ct->ct |= TCG_CT_CONST_ARM;
163 break;
164
811d4cf4 165 case 'r':
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166 ct->ct |= TCG_CT_REG;
167 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
168 break;
169
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170 /* qemu_ld address */
171 case 'l':
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172 ct->ct |= TCG_CT_REG;
173 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
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174#ifdef CONFIG_SOFTMMU
175 /* r0 and r1 will be overwritten when reading the tlb entry,
176 so don't use these. */
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177 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
178 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
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179#if defined(CONFIG_TCG_PASS_AREG0) && (TARGET_LONG_BITS == 64)
180 /* If we're passing env to the helper as r0 and need a regpair
181 * for the address then r2 will be overwritten as we're setting
182 * up the args to the helper.
183 */
184 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
185#endif
67dcab73 186#endif
811d4cf4 187 break;
67dcab73 188 case 'L':
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189 ct->ct |= TCG_CT_REG;
190 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
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191#ifdef CONFIG_SOFTMMU
192 /* r1 is still needed to load data_reg or data_reg2,
193 so don't use it. */
d0660ed4 194 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
67dcab73 195#endif
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196 break;
197
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198 /* qemu_st address & data_reg */
199 case 's':
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200 ct->ct |= TCG_CT_REG;
201 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
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202 /* r0 and r1 will be overwritten when reading the tlb entry
203 (softmmu only) and doing the byte swapping, so don't
204 use these. */
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205 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
206 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
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207#if defined(CONFIG_SOFTMMU) && \
208 defined(CONFIG_TCG_PASS_AREG0) && (TARGET_LONG_BITS == 64)
209 /* Avoid clashes with registers being used for helper args */
210 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
211 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
212#endif
811d4cf4 213 break;
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214 /* qemu_st64 data_reg2 */
215 case 'S':
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216 ct->ct |= TCG_CT_REG;
217 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
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218 /* r0 and r1 will be overwritten when reading the tlb entry
219 (softmmu only) and doing the byte swapping, so don't
220 use these. */
811d4cf4 221 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
811d4cf4 222 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
67dcab73
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223#ifdef CONFIG_SOFTMMU
224 /* r2 is still needed to load data_reg, so don't use it. */
225 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
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226#if defined(CONFIG_TCG_PASS_AREG0) && (TARGET_LONG_BITS == 64)
227 /* Avoid clashes with registers being used for helper args */
228 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
229#endif
811d4cf4 230#endif
67dcab73 231 break;
811d4cf4 232
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233 default:
234 return -1;
235 }
236 ct_str++;
237 *pct_str = ct_str;
238
239 return 0;
240}
241
94953e6d
LD
242static inline uint32_t rotl(uint32_t val, int n)
243{
244 return (val << n) | (val >> (32 - n));
245}
246
247/* ARM immediates for ALU instructions are made of an unsigned 8-bit
248 right-rotated by an even amount between 0 and 30. */
249static inline int encode_imm(uint32_t imm)
250{
4e6f6d4c
LD
251 int shift;
252
94953e6d
LD
253 /* simple case, only lower bits */
254 if ((imm & ~0xff) == 0)
255 return 0;
256 /* then try a simple even shift */
257 shift = ctz32(imm) & ~1;
258 if (((imm >> shift) & ~0xff) == 0)
259 return 32 - shift;
260 /* now try harder with rotations */
261 if ((rotl(imm, 2) & ~0xff) == 0)
262 return 2;
263 if ((rotl(imm, 4) & ~0xff) == 0)
264 return 4;
265 if ((rotl(imm, 6) & ~0xff) == 0)
266 return 6;
267 /* imm can't be encoded */
268 return -1;
269}
cb4e581f
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270
271static inline int check_fit_imm(uint32_t imm)
272{
94953e6d 273 return encode_imm(imm) >= 0;
cb4e581f
LD
274}
275
811d4cf4
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276/* Test if a constant matches the constraint.
277 * TODO: define constraints for:
278 *
279 * ldr/str offset: between -0xfff and 0xfff
280 * ldrh/strh offset: between -0xff and 0xff
281 * mov operand2: values represented with x << (2 * y), x < 0x100
282 * add, sub, eor...: ditto
283 */
284static inline int tcg_target_const_match(tcg_target_long val,
285 const TCGArgConstraint *arg_ct)
286{
287 int ct;
288 ct = arg_ct->ct;
289 if (ct & TCG_CT_CONST)
290 return 1;
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LD
291 else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val))
292 return 1;
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293 else
294 return 0;
295}
296
297enum arm_data_opc_e {
298 ARITH_AND = 0x0,
299 ARITH_EOR = 0x1,
300 ARITH_SUB = 0x2,
301 ARITH_RSB = 0x3,
302 ARITH_ADD = 0x4,
303 ARITH_ADC = 0x5,
304 ARITH_SBC = 0x6,
305 ARITH_RSC = 0x7,
3979144c 306 ARITH_TST = 0x8,
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307 ARITH_CMP = 0xa,
308 ARITH_CMN = 0xb,
309 ARITH_ORR = 0xc,
310 ARITH_MOV = 0xd,
311 ARITH_BIC = 0xe,
312 ARITH_MVN = 0xf,
313};
314
3979144c
PB
315#define TO_CPSR(opc) \
316 ((opc == ARITH_CMP || opc == ARITH_CMN || opc == ARITH_TST) << 20)
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317
318#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
319#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20)
320#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40)
321#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60)
322#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10)
323#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30)
324#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50)
325#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70)
326
327enum arm_cond_code_e {
328 COND_EQ = 0x0,
329 COND_NE = 0x1,
330 COND_CS = 0x2, /* Unsigned greater or equal */
331 COND_CC = 0x3, /* Unsigned less than */
332 COND_MI = 0x4, /* Negative */
333 COND_PL = 0x5, /* Zero or greater */
334 COND_VS = 0x6, /* Overflow */
335 COND_VC = 0x7, /* No overflow */
336 COND_HI = 0x8, /* Unsigned greater than */
337 COND_LS = 0x9, /* Unsigned less or equal */
338 COND_GE = 0xa,
339 COND_LT = 0xb,
340 COND_GT = 0xc,
341 COND_LE = 0xd,
342 COND_AL = 0xe,
343};
344
345static const uint8_t tcg_cond_to_arm_cond[10] = {
346 [TCG_COND_EQ] = COND_EQ,
347 [TCG_COND_NE] = COND_NE,
348 [TCG_COND_LT] = COND_LT,
349 [TCG_COND_GE] = COND_GE,
350 [TCG_COND_LE] = COND_LE,
351 [TCG_COND_GT] = COND_GT,
352 /* unsigned */
353 [TCG_COND_LTU] = COND_CC,
354 [TCG_COND_GEU] = COND_CS,
355 [TCG_COND_LEU] = COND_LS,
356 [TCG_COND_GTU] = COND_HI,
357};
358
359static inline void tcg_out_bx(TCGContext *s, int cond, int rn)
360{
361 tcg_out32(s, (cond << 28) | 0x012fff10 | rn);
362}
363
364static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset)
365{
366 tcg_out32(s, (cond << 28) | 0x0a000000 |
367 (((offset - 8) >> 2) & 0x00ffffff));
368}
369
e936243a
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370static inline void tcg_out_b_noaddr(TCGContext *s, int cond)
371{
56779034
AJ
372 /* We pay attention here to not modify the branch target by skipping
373 the corresponding bytes. This ensure that caches and memory are
374 kept coherent during retranslation. */
e2542fe2 375#ifdef HOST_WORDS_BIGENDIAN
e936243a
AZ
376 tcg_out8(s, (cond << 4) | 0x0a);
377 s->code_ptr += 3;
378#else
379 s->code_ptr += 3;
380 tcg_out8(s, (cond << 4) | 0x0a);
381#endif
382}
383
811d4cf4
AZ
384static inline void tcg_out_bl(TCGContext *s, int cond, int32_t offset)
385{
386 tcg_out32(s, (cond << 28) | 0x0b000000 |
387 (((offset - 8) >> 2) & 0x00ffffff));
388}
389
23401b58
AJ
390static inline void tcg_out_blx(TCGContext *s, int cond, int rn)
391{
392 tcg_out32(s, (cond << 28) | 0x012fff30 | rn);
393}
394
24e838b7
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395static inline void tcg_out_blx_imm(TCGContext *s, int32_t offset)
396{
397 tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) |
398 (((offset - 8) >> 2) & 0x00ffffff));
399}
400
811d4cf4
AZ
401static inline void tcg_out_dat_reg(TCGContext *s,
402 int cond, int opc, int rd, int rn, int rm, int shift)
403{
404 tcg_out32(s, (cond << 28) | (0 << 25) | (opc << 21) | TO_CPSR(opc) |
405 (rn << 16) | (rd << 12) | shift | rm);
406}
407
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408static inline void tcg_out_mov_reg(TCGContext *s, int cond, int rd, int rm)
409{
410 /* Simple reg-reg move, optimising out the 'do nothing' case */
411 if (rd != rm) {
412 tcg_out_dat_reg(s, cond, ARITH_MOV, rd, 0, rm, SHIFT_IMM_LSL(0));
413 }
414}
415
811d4cf4
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416static inline void tcg_out_dat_reg2(TCGContext *s,
417 int cond, int opc0, int opc1, int rd0, int rd1,
418 int rn0, int rn1, int rm0, int rm1, int shift)
419{
0c9c3a9e
AZ
420 if (rd0 == rn1 || rd0 == rm1) {
421 tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
422 (rn0 << 16) | (8 << 12) | shift | rm0);
423 tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
424 (rn1 << 16) | (rd1 << 12) | shift | rm1);
425 tcg_out_dat_reg(s, cond, ARITH_MOV,
426 rd0, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
427 } else {
428 tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
429 (rn0 << 16) | (rd0 << 12) | shift | rm0);
430 tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
431 (rn1 << 16) | (rd1 << 12) | shift | rm1);
432 }
811d4cf4
AZ
433}
434
435static inline void tcg_out_dat_imm(TCGContext *s,
436 int cond, int opc, int rd, int rn, int im)
437{
3979144c 438 tcg_out32(s, (cond << 28) | (1 << 25) | (opc << 21) | TO_CPSR(opc) |
811d4cf4
AZ
439 (rn << 16) | (rd << 12) | im);
440}
441
442static inline void tcg_out_movi32(TCGContext *s,
0f11f25a 443 int cond, int rd, uint32_t arg)
811d4cf4 444{
811d4cf4
AZ
445 /* TODO: This is very suboptimal, we can easily have a constant
446 * pool somewhere after all the instructions. */
0f11f25a
AJ
447 if ((int)arg < 0 && (int)arg >= -0x100) {
448 tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, (~arg) & 0xff);
449 } else if (use_armv7_instructions) {
ac34fb5c
AJ
450 /* use movw/movt */
451 /* movw */
452 tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12)
453 | ((arg << 4) & 0x000f0000) | (arg & 0xfff));
0f11f25a 454 if (arg & 0xffff0000) {
ac34fb5c
AJ
455 /* movt */
456 tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12)
457 | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff));
ac34fb5c 458 }
0f11f25a
AJ
459 } else {
460 int opc = ARITH_MOV;
461 int rn = 0;
462
463 do {
464 int i, rot;
465
466 i = ctz32(arg) & ~1;
467 rot = ((32 - i) << 7) & 0xf00;
468 tcg_out_dat_imm(s, cond, opc, rd, rn, ((arg >> i) & 0xff) | rot);
469 arg &= ~(0xff << i);
470
471 opc = ARITH_ORR;
472 rn = rd;
473 } while (arg);
474 }
811d4cf4
AZ
475}
476
477static inline void tcg_out_mul32(TCGContext *s,
478 int cond, int rd, int rs, int rm)
479{
480 if (rd != rm)
481 tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
482 (rs << 8) | 0x90 | rm);
483 else if (rd != rs)
484 tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
485 (rm << 8) | 0x90 | rs);
486 else {
487 tcg_out32(s, (cond << 28) | ( 8 << 16) | (0 << 12) |
488 (rs << 8) | 0x90 | rm);
489 tcg_out_dat_reg(s, cond, ARITH_MOV,
c8d80cef 490 rd, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
811d4cf4
AZ
491 }
492}
493
494static inline void tcg_out_umull32(TCGContext *s,
495 int cond, int rd0, int rd1, int rs, int rm)
496{
497 if (rd0 != rm && rd1 != rm)
498 tcg_out32(s, (cond << 28) | 0x800090 |
499 (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
500 else if (rd0 != rs && rd1 != rs)
501 tcg_out32(s, (cond << 28) | 0x800090 |
502 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
503 else {
504 tcg_out_dat_reg(s, cond, ARITH_MOV,
505 TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));
506 tcg_out32(s, (cond << 28) | 0x800098 |
507 (rd1 << 16) | (rd0 << 12) | (rs << 8));
508 }
509}
510
511static inline void tcg_out_smull32(TCGContext *s,
512 int cond, int rd0, int rd1, int rs, int rm)
513{
514 if (rd0 != rm && rd1 != rm)
515 tcg_out32(s, (cond << 28) | 0xc00090 |
516 (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
517 else if (rd0 != rs && rd1 != rs)
518 tcg_out32(s, (cond << 28) | 0xc00090 |
519 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
520 else {
521 tcg_out_dat_reg(s, cond, ARITH_MOV,
522 TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));
523 tcg_out32(s, (cond << 28) | 0xc00098 |
524 (rd1 << 16) | (rd0 << 12) | (rs << 8));
525 }
526}
527
9517094f
AJ
528static inline void tcg_out_ext8s(TCGContext *s, int cond,
529 int rd, int rn)
530{
531 if (use_armv6_instructions) {
532 /* sxtb */
533 tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | rn);
534 } else {
e23886a9 535 tcg_out_dat_reg(s, cond, ARITH_MOV,
9517094f 536 rd, 0, rn, SHIFT_IMM_LSL(24));
e23886a9 537 tcg_out_dat_reg(s, cond, ARITH_MOV,
9517094f
AJ
538 rd, 0, rd, SHIFT_IMM_ASR(24));
539 }
540}
541
e854b6d3
AJ
542static inline void tcg_out_ext8u(TCGContext *s, int cond,
543 int rd, int rn)
544{
545 tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 0xff);
546}
547
9517094f
AJ
548static inline void tcg_out_ext16s(TCGContext *s, int cond,
549 int rd, int rn)
550{
551 if (use_armv6_instructions) {
552 /* sxth */
553 tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | rn);
554 } else {
e23886a9 555 tcg_out_dat_reg(s, cond, ARITH_MOV,
9517094f 556 rd, 0, rn, SHIFT_IMM_LSL(16));
e23886a9 557 tcg_out_dat_reg(s, cond, ARITH_MOV,
9517094f
AJ
558 rd, 0, rd, SHIFT_IMM_ASR(16));
559 }
560}
561
562static inline void tcg_out_ext16u(TCGContext *s, int cond,
563 int rd, int rn)
564{
565 if (use_armv6_instructions) {
566 /* uxth */
567 tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rn);
568 } else {
e23886a9 569 tcg_out_dat_reg(s, cond, ARITH_MOV,
9517094f 570 rd, 0, rn, SHIFT_IMM_LSL(16));
e23886a9 571 tcg_out_dat_reg(s, cond, ARITH_MOV,
9517094f
AJ
572 rd, 0, rd, SHIFT_IMM_LSR(16));
573 }
574}
575
67dcab73
AJ
576static inline void tcg_out_bswap16s(TCGContext *s, int cond, int rd, int rn)
577{
578 if (use_armv6_instructions) {
579 /* revsh */
580 tcg_out32(s, 0x06ff0fb0 | (cond << 28) | (rd << 12) | rn);
581 } else {
582 tcg_out_dat_reg(s, cond, ARITH_MOV,
583 TCG_REG_R8, 0, rn, SHIFT_IMM_LSL(24));
584 tcg_out_dat_reg(s, cond, ARITH_MOV,
585 TCG_REG_R8, 0, TCG_REG_R8, SHIFT_IMM_ASR(16));
586 tcg_out_dat_reg(s, cond, ARITH_ORR,
587 rd, TCG_REG_R8, rn, SHIFT_IMM_LSR(8));
588 }
589}
590
244b1e81
AJ
591static inline void tcg_out_bswap16(TCGContext *s, int cond, int rd, int rn)
592{
593 if (use_armv6_instructions) {
594 /* rev16 */
595 tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn);
596 } else {
597 tcg_out_dat_reg(s, cond, ARITH_MOV,
598 TCG_REG_R8, 0, rn, SHIFT_IMM_LSL(24));
599 tcg_out_dat_reg(s, cond, ARITH_MOV,
600 TCG_REG_R8, 0, TCG_REG_R8, SHIFT_IMM_LSR(16));
601 tcg_out_dat_reg(s, cond, ARITH_ORR,
602 rd, TCG_REG_R8, rn, SHIFT_IMM_LSR(8));
603 }
604}
605
606static inline void tcg_out_bswap32(TCGContext *s, int cond, int rd, int rn)
607{
608 if (use_armv6_instructions) {
609 /* rev */
610 tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn);
611 } else {
612 tcg_out_dat_reg(s, cond, ARITH_EOR,
613 TCG_REG_R8, rn, rn, SHIFT_IMM_ROR(16));
614 tcg_out_dat_imm(s, cond, ARITH_BIC,
615 TCG_REG_R8, TCG_REG_R8, 0xff | 0x800);
616 tcg_out_dat_reg(s, cond, ARITH_MOV,
617 rd, 0, rn, SHIFT_IMM_ROR(8));
618 tcg_out_dat_reg(s, cond, ARITH_EOR,
619 rd, rd, TCG_REG_R8, SHIFT_IMM_LSR(8));
620 }
621}
622
811d4cf4
AZ
623static inline void tcg_out_ld32_12(TCGContext *s, int cond,
624 int rd, int rn, tcg_target_long im)
625{
626 if (im >= 0)
627 tcg_out32(s, (cond << 28) | 0x05900000 |
628 (rn << 16) | (rd << 12) | (im & 0xfff));
629 else
630 tcg_out32(s, (cond << 28) | 0x05100000 |
631 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
632}
633
634static inline void tcg_out_st32_12(TCGContext *s, int cond,
635 int rd, int rn, tcg_target_long im)
636{
637 if (im >= 0)
638 tcg_out32(s, (cond << 28) | 0x05800000 |
639 (rn << 16) | (rd << 12) | (im & 0xfff));
640 else
641 tcg_out32(s, (cond << 28) | 0x05000000 |
642 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
643}
644
645static inline void tcg_out_ld32_r(TCGContext *s, int cond,
646 int rd, int rn, int rm)
647{
648 tcg_out32(s, (cond << 28) | 0x07900000 |
649 (rn << 16) | (rd << 12) | rm);
650}
651
652static inline void tcg_out_st32_r(TCGContext *s, int cond,
653 int rd, int rn, int rm)
654{
655 tcg_out32(s, (cond << 28) | 0x07800000 |
656 (rn << 16) | (rd << 12) | rm);
657}
658
3979144c
PB
659/* Register pre-increment with base writeback. */
660static inline void tcg_out_ld32_rwb(TCGContext *s, int cond,
661 int rd, int rn, int rm)
662{
663 tcg_out32(s, (cond << 28) | 0x07b00000 |
664 (rn << 16) | (rd << 12) | rm);
665}
666
667static inline void tcg_out_st32_rwb(TCGContext *s, int cond,
668 int rd, int rn, int rm)
669{
670 tcg_out32(s, (cond << 28) | 0x07a00000 |
671 (rn << 16) | (rd << 12) | rm);
672}
673
811d4cf4
AZ
674static inline void tcg_out_ld16u_8(TCGContext *s, int cond,
675 int rd, int rn, tcg_target_long im)
676{
677 if (im >= 0)
678 tcg_out32(s, (cond << 28) | 0x01d000b0 |
679 (rn << 16) | (rd << 12) |
680 ((im & 0xf0) << 4) | (im & 0xf));
681 else
682 tcg_out32(s, (cond << 28) | 0x015000b0 |
683 (rn << 16) | (rd << 12) |
684 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
685}
686
f694a27e 687static inline void tcg_out_st16_8(TCGContext *s, int cond,
811d4cf4
AZ
688 int rd, int rn, tcg_target_long im)
689{
690 if (im >= 0)
691 tcg_out32(s, (cond << 28) | 0x01c000b0 |
692 (rn << 16) | (rd << 12) |
693 ((im & 0xf0) << 4) | (im & 0xf));
694 else
695 tcg_out32(s, (cond << 28) | 0x014000b0 |
696 (rn << 16) | (rd << 12) |
697 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
698}
699
700static inline void tcg_out_ld16u_r(TCGContext *s, int cond,
701 int rd, int rn, int rm)
702{
703 tcg_out32(s, (cond << 28) | 0x019000b0 |
704 (rn << 16) | (rd << 12) | rm);
705}
706
f694a27e 707static inline void tcg_out_st16_r(TCGContext *s, int cond,
811d4cf4
AZ
708 int rd, int rn, int rm)
709{
710 tcg_out32(s, (cond << 28) | 0x018000b0 |
711 (rn << 16) | (rd << 12) | rm);
712}
713
714static inline void tcg_out_ld16s_8(TCGContext *s, int cond,
715 int rd, int rn, tcg_target_long im)
716{
717 if (im >= 0)
718 tcg_out32(s, (cond << 28) | 0x01d000f0 |
719 (rn << 16) | (rd << 12) |
720 ((im & 0xf0) << 4) | (im & 0xf));
721 else
722 tcg_out32(s, (cond << 28) | 0x015000f0 |
723 (rn << 16) | (rd << 12) |
724 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
725}
726
811d4cf4
AZ
727static inline void tcg_out_ld16s_r(TCGContext *s, int cond,
728 int rd, int rn, int rm)
729{
730 tcg_out32(s, (cond << 28) | 0x019000f0 |
731 (rn << 16) | (rd << 12) | rm);
732}
733
811d4cf4
AZ
734static inline void tcg_out_ld8_12(TCGContext *s, int cond,
735 int rd, int rn, tcg_target_long im)
736{
737 if (im >= 0)
738 tcg_out32(s, (cond << 28) | 0x05d00000 |
739 (rn << 16) | (rd << 12) | (im & 0xfff));
740 else
741 tcg_out32(s, (cond << 28) | 0x05500000 |
742 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
743}
744
745static inline void tcg_out_st8_12(TCGContext *s, int cond,
746 int rd, int rn, tcg_target_long im)
747{
748 if (im >= 0)
749 tcg_out32(s, (cond << 28) | 0x05c00000 |
750 (rn << 16) | (rd << 12) | (im & 0xfff));
751 else
752 tcg_out32(s, (cond << 28) | 0x05400000 |
753 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
754}
755
756static inline void tcg_out_ld8_r(TCGContext *s, int cond,
757 int rd, int rn, int rm)
758{
759 tcg_out32(s, (cond << 28) | 0x07d00000 |
760 (rn << 16) | (rd << 12) | rm);
761}
762
763static inline void tcg_out_st8_r(TCGContext *s, int cond,
764 int rd, int rn, int rm)
765{
766 tcg_out32(s, (cond << 28) | 0x07c00000 |
767 (rn << 16) | (rd << 12) | rm);
768}
769
770static inline void tcg_out_ld8s_8(TCGContext *s, int cond,
771 int rd, int rn, tcg_target_long im)
772{
773 if (im >= 0)
774 tcg_out32(s, (cond << 28) | 0x01d000d0 |
775 (rn << 16) | (rd << 12) |
776 ((im & 0xf0) << 4) | (im & 0xf));
777 else
778 tcg_out32(s, (cond << 28) | 0x015000d0 |
779 (rn << 16) | (rd << 12) |
780 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
781}
782
811d4cf4
AZ
783static inline void tcg_out_ld8s_r(TCGContext *s, int cond,
784 int rd, int rn, int rm)
785{
204c1674 786 tcg_out32(s, (cond << 28) | 0x019000d0 |
811d4cf4
AZ
787 (rn << 16) | (rd << 12) | rm);
788}
789
811d4cf4
AZ
790static inline void tcg_out_ld32u(TCGContext *s, int cond,
791 int rd, int rn, int32_t offset)
792{
793 if (offset > 0xfff || offset < -0xfff) {
794 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
795 tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_R8);
796 } else
797 tcg_out_ld32_12(s, cond, rd, rn, offset);
798}
799
800static inline void tcg_out_st32(TCGContext *s, int cond,
801 int rd, int rn, int32_t offset)
802{
803 if (offset > 0xfff || offset < -0xfff) {
804 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
805 tcg_out_st32_r(s, cond, rd, rn, TCG_REG_R8);
806 } else
807 tcg_out_st32_12(s, cond, rd, rn, offset);
808}
809
810static inline void tcg_out_ld16u(TCGContext *s, int cond,
811 int rd, int rn, int32_t offset)
812{
813 if (offset > 0xff || offset < -0xff) {
814 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
815 tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_R8);
816 } else
817 tcg_out_ld16u_8(s, cond, rd, rn, offset);
818}
819
820static inline void tcg_out_ld16s(TCGContext *s, int cond,
821 int rd, int rn, int32_t offset)
822{
823 if (offset > 0xff || offset < -0xff) {
824 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
825 tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_R8);
826 } else
827 tcg_out_ld16s_8(s, cond, rd, rn, offset);
828}
829
f694a27e 830static inline void tcg_out_st16(TCGContext *s, int cond,
811d4cf4
AZ
831 int rd, int rn, int32_t offset)
832{
833 if (offset > 0xff || offset < -0xff) {
834 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
f694a27e 835 tcg_out_st16_r(s, cond, rd, rn, TCG_REG_R8);
811d4cf4 836 } else
f694a27e 837 tcg_out_st16_8(s, cond, rd, rn, offset);
811d4cf4
AZ
838}
839
840static inline void tcg_out_ld8u(TCGContext *s, int cond,
841 int rd, int rn, int32_t offset)
842{
843 if (offset > 0xfff || offset < -0xfff) {
844 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
845 tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_R8);
846 } else
847 tcg_out_ld8_12(s, cond, rd, rn, offset);
848}
849
850static inline void tcg_out_ld8s(TCGContext *s, int cond,
851 int rd, int rn, int32_t offset)
852{
853 if (offset > 0xff || offset < -0xff) {
854 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
855 tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_R8);
856 } else
857 tcg_out_ld8s_8(s, cond, rd, rn, offset);
858}
859
f694a27e 860static inline void tcg_out_st8(TCGContext *s, int cond,
811d4cf4
AZ
861 int rd, int rn, int32_t offset)
862{
863 if (offset > 0xfff || offset < -0xfff) {
864 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
865 tcg_out_st8_r(s, cond, rd, rn, TCG_REG_R8);
866 } else
867 tcg_out_st8_12(s, cond, rd, rn, offset);
868}
869
222f23f5 870/* The _goto case is normally between TBs within the same code buffer,
5c84bd90 871 * and with the code buffer limited to 16MB we shouldn't need the long
222f23f5
DDAG
872 * case.
873 *
874 * .... except to the prologue that is in its own buffer.
875 */
811d4cf4
AZ
876static inline void tcg_out_goto(TCGContext *s, int cond, uint32_t addr)
877{
878 int32_t val;
879
24e838b7
PM
880 if (addr & 1) {
881 /* goto to a Thumb destination isn't supported */
882 tcg_abort();
883 }
884
811d4cf4
AZ
885 val = addr - (tcg_target_long) s->code_ptr;
886 if (val - 8 < 0x01fffffd && val - 8 > -0x01fffffd)
887 tcg_out_b(s, cond, val);
888 else {
811d4cf4 889 if (cond == COND_AL) {
c8d80cef 890 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
222f23f5 891 tcg_out32(s, addr);
811d4cf4
AZ
892 } else {
893 tcg_out_movi32(s, cond, TCG_REG_R8, val - 8);
894 tcg_out_dat_reg(s, cond, ARITH_ADD,
c8d80cef
AJ
895 TCG_REG_PC, TCG_REG_PC,
896 TCG_REG_R8, SHIFT_IMM_LSL(0));
811d4cf4 897 }
811d4cf4
AZ
898 }
899}
900
222f23f5
DDAG
901/* The call case is mostly used for helpers - so it's not unreasonable
902 * for them to be beyond branch range */
24e838b7 903static inline void tcg_out_call(TCGContext *s, uint32_t addr)
811d4cf4
AZ
904{
905 int32_t val;
906
811d4cf4 907 val = addr - (tcg_target_long) s->code_ptr;
24e838b7
PM
908 if (val - 8 < 0x02000000 && val - 8 >= -0x02000000) {
909 if (addr & 1) {
910 /* Use BLX if the target is in Thumb mode */
911 if (!use_armv5_instructions) {
912 tcg_abort();
913 }
914 tcg_out_blx_imm(s, val);
915 } else {
916 tcg_out_bl(s, COND_AL, val);
917 }
918 } else {
222f23f5
DDAG
919 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 4);
920 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
921 tcg_out32(s, addr);
811d4cf4 922 }
811d4cf4
AZ
923}
924
925static inline void tcg_out_callr(TCGContext *s, int cond, int arg)
926{
23401b58
AJ
927 if (use_armv5_instructions) {
928 tcg_out_blx(s, cond, arg);
929 } else {
930 tcg_out_dat_reg(s, cond, ARITH_MOV, TCG_REG_R14, 0,
931 TCG_REG_PC, SHIFT_IMM_LSL(0));
932 tcg_out_bx(s, cond, arg);
933 }
811d4cf4
AZ
934}
935
936static inline void tcg_out_goto_label(TCGContext *s, int cond, int label_index)
937{
938 TCGLabel *l = &s->labels[label_index];
939
940 if (l->has_value)
941 tcg_out_goto(s, cond, l->u.value);
942 else if (cond == COND_AL) {
c8d80cef 943 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
811d4cf4
AZ
944 tcg_out_reloc(s, s->code_ptr, R_ARM_ABS32, label_index, 31337);
945 s->code_ptr += 4;
946 } else {
947 /* Probably this should be preferred even for COND_AL... */
948 tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, label_index, 31337);
e936243a 949 tcg_out_b_noaddr(s, cond);
811d4cf4
AZ
950 }
951}
952
811d4cf4 953#ifdef CONFIG_SOFTMMU
79383c9c
BS
954
955#include "../../softmmu_defs.h"
811d4cf4 956
e141ab52
BS
957#ifdef CONFIG_TCG_PASS_AREG0
958/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
959 int mmu_idx) */
960static const void * const qemu_ld_helpers[4] = {
961 helper_ldb_mmu,
962 helper_ldw_mmu,
963 helper_ldl_mmu,
964 helper_ldq_mmu,
965};
966
967/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
968 uintxx_t val, int mmu_idx) */
969static const void * const qemu_st_helpers[4] = {
970 helper_stb_mmu,
971 helper_stw_mmu,
972 helper_stl_mmu,
973 helper_stq_mmu,
974};
975#else
976/* legacy helper signature: __ld_mmu(target_ulong addr, int
977 mmu_idx) */
811d4cf4
AZ
978static void *qemu_ld_helpers[4] = {
979 __ldb_mmu,
980 __ldw_mmu,
981 __ldl_mmu,
982 __ldq_mmu,
983};
984
e141ab52
BS
985/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
986 int mmu_idx) */
811d4cf4
AZ
987static void *qemu_st_helpers[4] = {
988 __stb_mmu,
989 __stw_mmu,
990 __stl_mmu,
991 __stq_mmu,
992};
993#endif
9716ef3b
PM
994
995/* Helper routines for marshalling helper function arguments into
996 * the correct registers and stack.
997 * argreg is where we want to put this argument, arg is the argument itself.
998 * Return value is the updated argreg ready for the next call.
999 * Note that argreg 0..3 is real registers, 4+ on stack.
1000 * When we reach the first stacked argument, we allocate space for it
1001 * and the following stacked arguments using "str r8, [sp, #-0x10]!".
1002 * Following arguments are filled in with "str r8, [sp, #0xNN]".
1003 * For more than 4 stacked arguments we'd need to know how much
1004 * space to allocate when we pushed the first stacked argument.
1005 * We don't need this, so don't implement it (and will assert if you try it.)
1006 *
1007 * We provide routines for arguments which are: immediate, 32 bit
1008 * value in register, 16 and 8 bit values in register (which must be zero
1009 * extended before use) and 64 bit value in a lo:hi register pair.
1010 */
1011#define DEFINE_TCG_OUT_ARG(NAME, ARGPARAM) \
1012 static TCGReg NAME(TCGContext *s, TCGReg argreg, ARGPARAM) \
1013 { \
1014 if (argreg < 4) { \
1015 TCG_OUT_ARG_GET_ARG(argreg); \
1016 } else if (argreg == 4) { \
1017 TCG_OUT_ARG_GET_ARG(TCG_REG_R8); \
1018 tcg_out32(s, (COND_AL << 28) | 0x052d8010); \
1019 } else { \
1020 assert(argreg < 8); \
1021 TCG_OUT_ARG_GET_ARG(TCG_REG_R8); \
1022 tcg_out32(s, (COND_AL << 28) | 0x058d8000 | (argreg - 4) * 4); \
1023 } \
1024 return argreg + 1; \
1025 }
1026
1027#define TCG_OUT_ARG_GET_ARG(A) tcg_out_dat_imm(s, COND_AL, ARITH_MOV, A, 0, arg)
1028DEFINE_TCG_OUT_ARG(tcg_out_arg_imm32, uint32_t arg)
1029#undef TCG_OUT_ARG_GET_ARG
1030#define TCG_OUT_ARG_GET_ARG(A) tcg_out_ext8u(s, COND_AL, A, arg)
1031DEFINE_TCG_OUT_ARG(tcg_out_arg_reg8, TCGReg arg)
1032#undef TCG_OUT_ARG_GET_ARG
1033#define TCG_OUT_ARG_GET_ARG(A) tcg_out_ext16u(s, COND_AL, A, arg)
1034DEFINE_TCG_OUT_ARG(tcg_out_arg_reg16, TCGReg arg)
1035#undef TCG_OUT_ARG_GET_ARG
1036
1037/* We don't use the macro for this one to avoid an unnecessary reg-reg
1038 * move when storing to the stack.
1039 */
1040static TCGReg tcg_out_arg_reg32(TCGContext *s, TCGReg argreg, TCGReg arg)
1041{
1042 if (argreg < 4) {
1043 tcg_out_mov_reg(s, COND_AL, argreg, arg);
1044 } else if (argreg == 4) {
1045 /* str arg, [sp, #-0x10]! */
1046 tcg_out32(s, (COND_AL << 28) | 0x052d0010 | (arg << 12));
1047 } else {
1048 assert(argreg < 8);
1049 /* str arg, [sp, #0xNN] */
1050 tcg_out32(s, (COND_AL << 28) | 0x058d0000 |
1051 (arg << 12) | (argreg - 4) * 4);
1052 }
1053 return argreg + 1;
1054}
1055
1056static inline TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg argreg,
1057 TCGReg arglo, TCGReg arghi)
1058{
1059 /* 64 bit arguments must go in even/odd register pairs
1060 * and in 8-aligned stack slots.
1061 */
1062 if (argreg & 1) {
1063 argreg++;
1064 }
1065 argreg = tcg_out_arg_reg32(s, argreg, arglo);
1066 argreg = tcg_out_arg_reg32(s, argreg, arghi);
1067 return argreg;
1068}
1069
1070static inline void tcg_out_arg_stacktidy(TCGContext *s, TCGReg argreg)
1071{
1072 /* Output any necessary post-call cleanup of the stack */
1073 if (argreg > 4) {
1074 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R13, TCG_REG_R13, 0x10);
1075 }
1076}
1077
e141ab52 1078#endif
811d4cf4 1079
3979144c
PB
1080#define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
1081
7e0d9562 1082static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
811d4cf4 1083{
67dcab73 1084 int addr_reg, data_reg, data_reg2, bswap;
811d4cf4
AZ
1085#ifdef CONFIG_SOFTMMU
1086 int mem_index, s_bits;
9716ef3b 1087 TCGReg argreg;
811d4cf4
AZ
1088# if TARGET_LONG_BITS == 64
1089 int addr_reg2;
1090# endif
811d4cf4 1091 uint32_t *label_ptr;
811d4cf4
AZ
1092#endif
1093
67dcab73
AJ
1094#ifdef TARGET_WORDS_BIGENDIAN
1095 bswap = 1;
1096#else
1097 bswap = 0;
1098#endif
811d4cf4
AZ
1099 data_reg = *args++;
1100 if (opc == 3)
1101 data_reg2 = *args++;
1102 else
d89c682f 1103 data_reg2 = 0; /* suppress warning */
811d4cf4 1104 addr_reg = *args++;
811d4cf4 1105#ifdef CONFIG_SOFTMMU
aef3a282
AZ
1106# if TARGET_LONG_BITS == 64
1107 addr_reg2 = *args++;
1108# endif
811d4cf4
AZ
1109 mem_index = *args;
1110 s_bits = opc & 3;
1111
91a3c1b0 1112 /* Should generate something like the following:
3979144c 1113 * shr r8, addr_reg, #TARGET_PAGE_BITS
91a3c1b0 1114 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
3979144c 1115 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
91a3c1b0
AZ
1116 */
1117# if CPU_TLB_BITS > 8
1118# error
1119# endif
c8d80cef
AJ
1120 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_R8,
1121 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
811d4cf4 1122 tcg_out_dat_imm(s, COND_AL, ARITH_AND,
c8d80cef
AJ
1123 TCG_REG_R0, TCG_REG_R8, CPU_TLB_SIZE - 1);
1124 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_AREG0,
1125 TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
91a3c1b0 1126 /* In the
9349b4f9 1127 * ldr r1 [r0, #(offsetof(CPUArchState, tlb_table[mem_index][0].addr_read))]
91a3c1b0
AZ
1128 * below, the offset is likely to exceed 12 bits if mem_index != 0 and
1129 * not exceed otherwise, so use an
9349b4f9 1130 * add r0, r0, #(mem_index * sizeof *CPUArchState.tlb_table)
91a3c1b0
AZ
1131 * before.
1132 */
225b4376 1133 if (mem_index)
c8d80cef 1134 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_REG_R0,
225b4376
AZ
1135 (mem_index << (TLB_SHIFT & 1)) |
1136 ((16 - (TLB_SHIFT >> 1)) << 8));
c8d80cef 1137 tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R0,
9349b4f9 1138 offsetof(CPUArchState, tlb_table[0][0].addr_read));
c8d80cef
AJ
1139 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R1,
1140 TCG_REG_R8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
3979144c
PB
1141 /* Check alignment. */
1142 if (s_bits)
1143 tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
1144 0, addr_reg, (1 << s_bits) - 1);
811d4cf4
AZ
1145# if TARGET_LONG_BITS == 64
1146 /* XXX: possibly we could use a block data load or writeback in
1147 * the first access. */
c8d80cef 1148 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
9349b4f9 1149 offsetof(CPUArchState, tlb_table[0][0].addr_read) + 4);
c8d80cef
AJ
1150 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1151 TCG_REG_R1, addr_reg2, SHIFT_IMM_LSL(0));
811d4cf4 1152# endif
c8d80cef 1153 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
9349b4f9 1154 offsetof(CPUArchState, tlb_table[0][0].addend));
811d4cf4
AZ
1155
1156 switch (opc) {
1157 case 0:
c8d80cef 1158 tcg_out_ld8_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
811d4cf4
AZ
1159 break;
1160 case 0 | 4:
c8d80cef 1161 tcg_out_ld8s_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
811d4cf4
AZ
1162 break;
1163 case 1:
c8d80cef 1164 tcg_out_ld16u_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
67dcab73
AJ
1165 if (bswap) {
1166 tcg_out_bswap16(s, COND_EQ, data_reg, data_reg);
1167 }
811d4cf4
AZ
1168 break;
1169 case 1 | 4:
67dcab73
AJ
1170 if (bswap) {
1171 tcg_out_ld16u_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1172 tcg_out_bswap16s(s, COND_EQ, data_reg, data_reg);
1173 } else {
1174 tcg_out_ld16s_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1175 }
811d4cf4
AZ
1176 break;
1177 case 2:
1178 default:
c8d80cef 1179 tcg_out_ld32_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
67dcab73
AJ
1180 if (bswap) {
1181 tcg_out_bswap32(s, COND_EQ, data_reg, data_reg);
1182 }
811d4cf4
AZ
1183 break;
1184 case 3:
67dcab73
AJ
1185 if (bswap) {
1186 tcg_out_ld32_rwb(s, COND_EQ, data_reg2, TCG_REG_R1, addr_reg);
1187 tcg_out_ld32_12(s, COND_EQ, data_reg, TCG_REG_R1, 4);
1188 tcg_out_bswap32(s, COND_EQ, data_reg2, data_reg2);
1189 tcg_out_bswap32(s, COND_EQ, data_reg, data_reg);
1190 } else {
1191 tcg_out_ld32_rwb(s, COND_EQ, data_reg, TCG_REG_R1, addr_reg);
1192 tcg_out_ld32_12(s, COND_EQ, data_reg2, TCG_REG_R1, 4);
1193 }
811d4cf4
AZ
1194 break;
1195 }
1196
1197 label_ptr = (void *) s->code_ptr;
c69806ab 1198 tcg_out_b_noaddr(s, COND_EQ);
811d4cf4 1199
811d4cf4 1200 /* TODO: move this code to where the constants pool will be */
9716ef3b
PM
1201 /* Note that this code relies on the constraints we set in arm_op_defs[]
1202 * to ensure that later arguments are not passed to us in registers we
1203 * trash by moving the earlier arguments into them.
1204 */
1205 argreg = TCG_REG_R0;
e141ab52 1206#ifdef CONFIG_TCG_PASS_AREG0
9716ef3b
PM
1207 argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0);
1208#endif
1209#if TARGET_LONG_BITS == 64
1210 argreg = tcg_out_arg_reg64(s, argreg, addr_reg, addr_reg2);
1211#else
1212 argreg = tcg_out_arg_reg32(s, argreg, addr_reg);
e141ab52 1213#endif
9716ef3b 1214 argreg = tcg_out_arg_imm32(s, argreg, mem_index);
24e838b7 1215 tcg_out_call(s, (tcg_target_long) qemu_ld_helpers[s_bits]);
9716ef3b 1216 tcg_out_arg_stacktidy(s, argreg);
811d4cf4
AZ
1217
1218 switch (opc) {
1219 case 0 | 4:
e854b6d3 1220 tcg_out_ext8s(s, COND_AL, data_reg, TCG_REG_R0);
811d4cf4
AZ
1221 break;
1222 case 1 | 4:
e854b6d3 1223 tcg_out_ext16s(s, COND_AL, data_reg, TCG_REG_R0);
811d4cf4
AZ
1224 break;
1225 case 0:
1226 case 1:
1227 case 2:
1228 default:
c8d80cef 1229 if (data_reg != TCG_REG_R0) {
7e0d9562 1230 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ
1231 data_reg, 0, TCG_REG_R0, SHIFT_IMM_LSL(0));
1232 }
811d4cf4
AZ
1233 break;
1234 case 3:
c8d80cef 1235 if (data_reg != TCG_REG_R0) {
7e0d9562 1236 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ
1237 data_reg, 0, TCG_REG_R0, SHIFT_IMM_LSL(0));
1238 }
1239 if (data_reg2 != TCG_REG_R1) {
7e0d9562 1240 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ
1241 data_reg2, 0, TCG_REG_R1, SHIFT_IMM_LSL(0));
1242 }
811d4cf4
AZ
1243 break;
1244 }
1245
c69806ab 1246 reloc_pc24(label_ptr, (tcg_target_long)s->code_ptr);
379f6698
PB
1247#else /* !CONFIG_SOFTMMU */
1248 if (GUEST_BASE) {
1249 uint32_t offset = GUEST_BASE;
1250 int i;
1251 int rot;
1252
1253 while (offset) {
1254 i = ctz32(offset) & ~1;
1255 rot = ((32 - i) << 7) & 0xf00;
1256
c8d80cef 1257 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R8, addr_reg,
379f6698 1258 ((offset >> i) & 0xff) | rot);
c8d80cef 1259 addr_reg = TCG_REG_R8;
379f6698
PB
1260 offset &= ~(0xff << i);
1261 }
1262 }
811d4cf4
AZ
1263 switch (opc) {
1264 case 0:
1265 tcg_out_ld8_12(s, COND_AL, data_reg, addr_reg, 0);
1266 break;
1267 case 0 | 4:
1268 tcg_out_ld8s_8(s, COND_AL, data_reg, addr_reg, 0);
1269 break;
1270 case 1:
1271 tcg_out_ld16u_8(s, COND_AL, data_reg, addr_reg, 0);
67dcab73
AJ
1272 if (bswap) {
1273 tcg_out_bswap16(s, COND_AL, data_reg, data_reg);
1274 }
811d4cf4
AZ
1275 break;
1276 case 1 | 4:
67dcab73
AJ
1277 if (bswap) {
1278 tcg_out_ld16u_8(s, COND_AL, data_reg, addr_reg, 0);
1279 tcg_out_bswap16s(s, COND_AL, data_reg, data_reg);
1280 } else {
1281 tcg_out_ld16s_8(s, COND_AL, data_reg, addr_reg, 0);
1282 }
811d4cf4
AZ
1283 break;
1284 case 2:
1285 default:
1286 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
67dcab73
AJ
1287 if (bswap) {
1288 tcg_out_bswap32(s, COND_AL, data_reg, data_reg);
1289 }
811d4cf4
AZ
1290 break;
1291 case 3:
eae6ce52
AZ
1292 /* TODO: use block load -
1293 * check that data_reg2 > data_reg or the other way */
419bafa5 1294 if (data_reg == addr_reg) {
67dcab73
AJ
1295 tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, bswap ? 0 : 4);
1296 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, bswap ? 4 : 0);
419bafa5 1297 } else {
67dcab73
AJ
1298 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, bswap ? 4 : 0);
1299 tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, bswap ? 0 : 4);
1300 }
1301 if (bswap) {
1302 tcg_out_bswap32(s, COND_AL, data_reg, data_reg);
1303 tcg_out_bswap32(s, COND_AL, data_reg2, data_reg2);
419bafa5 1304 }
811d4cf4
AZ
1305 break;
1306 }
1307#endif
1308}
1309
7e0d9562 1310static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
811d4cf4 1311{
67dcab73 1312 int addr_reg, data_reg, data_reg2, bswap;
811d4cf4
AZ
1313#ifdef CONFIG_SOFTMMU
1314 int mem_index, s_bits;
9716ef3b 1315 TCGReg argreg;
811d4cf4
AZ
1316# if TARGET_LONG_BITS == 64
1317 int addr_reg2;
1318# endif
811d4cf4 1319 uint32_t *label_ptr;
811d4cf4
AZ
1320#endif
1321
67dcab73
AJ
1322#ifdef TARGET_WORDS_BIGENDIAN
1323 bswap = 1;
1324#else
1325 bswap = 0;
1326#endif
811d4cf4
AZ
1327 data_reg = *args++;
1328 if (opc == 3)
1329 data_reg2 = *args++;
1330 else
d89c682f 1331 data_reg2 = 0; /* suppress warning */
811d4cf4 1332 addr_reg = *args++;
811d4cf4 1333#ifdef CONFIG_SOFTMMU
aef3a282
AZ
1334# if TARGET_LONG_BITS == 64
1335 addr_reg2 = *args++;
1336# endif
811d4cf4
AZ
1337 mem_index = *args;
1338 s_bits = opc & 3;
1339
91a3c1b0 1340 /* Should generate something like the following:
3979144c 1341 * shr r8, addr_reg, #TARGET_PAGE_BITS
91a3c1b0 1342 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
3979144c 1343 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
91a3c1b0 1344 */
811d4cf4 1345 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef 1346 TCG_REG_R8, 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
811d4cf4 1347 tcg_out_dat_imm(s, COND_AL, ARITH_AND,
c8d80cef
AJ
1348 TCG_REG_R0, TCG_REG_R8, CPU_TLB_SIZE - 1);
1349 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0,
1350 TCG_AREG0, TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
91a3c1b0 1351 /* In the
9349b4f9 1352 * ldr r1 [r0, #(offsetof(CPUArchState, tlb_table[mem_index][0].addr_write))]
91a3c1b0
AZ
1353 * below, the offset is likely to exceed 12 bits if mem_index != 0 and
1354 * not exceed otherwise, so use an
9349b4f9 1355 * add r0, r0, #(mem_index * sizeof *CPUArchState.tlb_table)
91a3c1b0
AZ
1356 * before.
1357 */
225b4376 1358 if (mem_index)
c8d80cef 1359 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_REG_R0,
225b4376
AZ
1360 (mem_index << (TLB_SHIFT & 1)) |
1361 ((16 - (TLB_SHIFT >> 1)) << 8));
c8d80cef 1362 tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R0,
9349b4f9 1363 offsetof(CPUArchState, tlb_table[0][0].addr_write));
c8d80cef
AJ
1364 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R1,
1365 TCG_REG_R8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
3979144c
PB
1366 /* Check alignment. */
1367 if (s_bits)
1368 tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
1369 0, addr_reg, (1 << s_bits) - 1);
811d4cf4
AZ
1370# if TARGET_LONG_BITS == 64
1371 /* XXX: possibly we could use a block data load or writeback in
1372 * the first access. */
c8d80cef 1373 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
9349b4f9 1374 offsetof(CPUArchState, tlb_table[0][0].addr_write) + 4);
c8d80cef
AJ
1375 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1376 TCG_REG_R1, addr_reg2, SHIFT_IMM_LSL(0));
811d4cf4 1377# endif
c8d80cef 1378 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
9349b4f9 1379 offsetof(CPUArchState, tlb_table[0][0].addend));
811d4cf4
AZ
1380
1381 switch (opc) {
1382 case 0:
c8d80cef 1383 tcg_out_st8_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
811d4cf4 1384 break;
811d4cf4 1385 case 1:
67dcab73
AJ
1386 if (bswap) {
1387 tcg_out_bswap16(s, COND_EQ, TCG_REG_R0, data_reg);
1388 tcg_out_st16_r(s, COND_EQ, TCG_REG_R0, addr_reg, TCG_REG_R1);
1389 } else {
1390 tcg_out_st16_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1391 }
811d4cf4
AZ
1392 break;
1393 case 2:
1394 default:
67dcab73
AJ
1395 if (bswap) {
1396 tcg_out_bswap32(s, COND_EQ, TCG_REG_R0, data_reg);
1397 tcg_out_st32_r(s, COND_EQ, TCG_REG_R0, addr_reg, TCG_REG_R1);
1398 } else {
1399 tcg_out_st32_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1400 }
811d4cf4
AZ
1401 break;
1402 case 3:
67dcab73
AJ
1403 if (bswap) {
1404 tcg_out_bswap32(s, COND_EQ, TCG_REG_R0, data_reg2);
1405 tcg_out_st32_rwb(s, COND_EQ, TCG_REG_R0, TCG_REG_R1, addr_reg);
1406 tcg_out_bswap32(s, COND_EQ, TCG_REG_R0, data_reg);
9a3abc21 1407 tcg_out_st32_12(s, COND_EQ, TCG_REG_R0, TCG_REG_R1, 4);
67dcab73
AJ
1408 } else {
1409 tcg_out_st32_rwb(s, COND_EQ, data_reg, TCG_REG_R1, addr_reg);
1410 tcg_out_st32_12(s, COND_EQ, data_reg2, TCG_REG_R1, 4);
1411 }
811d4cf4
AZ
1412 break;
1413 }
1414
1415 label_ptr = (void *) s->code_ptr;
c69806ab 1416 tcg_out_b_noaddr(s, COND_EQ);
811d4cf4 1417
811d4cf4 1418 /* TODO: move this code to where the constants pool will be */
9716ef3b
PM
1419 /* Note that this code relies on the constraints we set in arm_op_defs[]
1420 * to ensure that later arguments are not passed to us in registers we
1421 * trash by moving the earlier arguments into them.
1422 */
1423 argreg = TCG_REG_R0;
1424#ifdef CONFIG_TCG_PASS_AREG0
1425 argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0);
1426#endif
1427#if TARGET_LONG_BITS == 64
1428 argreg = tcg_out_arg_reg64(s, argreg, addr_reg, addr_reg2);
1429#else
1430 argreg = tcg_out_arg_reg32(s, argreg, addr_reg);
1431#endif
1432
811d4cf4
AZ
1433 switch (opc) {
1434 case 0:
9716ef3b 1435 argreg = tcg_out_arg_reg8(s, argreg, data_reg);
811d4cf4
AZ
1436 break;
1437 case 1:
9716ef3b 1438 argreg = tcg_out_arg_reg16(s, argreg, data_reg);
811d4cf4
AZ
1439 break;
1440 case 2:
9716ef3b 1441 argreg = tcg_out_arg_reg32(s, argreg, data_reg);
811d4cf4
AZ
1442 break;
1443 case 3:
9716ef3b 1444 argreg = tcg_out_arg_reg64(s, argreg, data_reg, data_reg2);
811d4cf4
AZ
1445 break;
1446 }
811d4cf4 1447
9716ef3b 1448 argreg = tcg_out_arg_imm32(s, argreg, mem_index);
24e838b7 1449 tcg_out_call(s, (tcg_target_long) qemu_st_helpers[s_bits]);
9716ef3b 1450 tcg_out_arg_stacktidy(s, argreg);
811d4cf4 1451
c69806ab 1452 reloc_pc24(label_ptr, (tcg_target_long)s->code_ptr);
379f6698
PB
1453#else /* !CONFIG_SOFTMMU */
1454 if (GUEST_BASE) {
1455 uint32_t offset = GUEST_BASE;
1456 int i;
1457 int rot;
1458
1459 while (offset) {
1460 i = ctz32(offset) & ~1;
1461 rot = ((32 - i) << 7) & 0xf00;
1462
67dcab73 1463 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R1, addr_reg,
379f6698 1464 ((offset >> i) & 0xff) | rot);
67dcab73 1465 addr_reg = TCG_REG_R1;
379f6698
PB
1466 offset &= ~(0xff << i);
1467 }
1468 }
811d4cf4
AZ
1469 switch (opc) {
1470 case 0:
1471 tcg_out_st8_12(s, COND_AL, data_reg, addr_reg, 0);
1472 break;
811d4cf4 1473 case 1:
67dcab73
AJ
1474 if (bswap) {
1475 tcg_out_bswap16(s, COND_AL, TCG_REG_R0, data_reg);
1476 tcg_out_st16_8(s, COND_AL, TCG_REG_R0, addr_reg, 0);
1477 } else {
1478 tcg_out_st16_8(s, COND_AL, data_reg, addr_reg, 0);
1479 }
811d4cf4
AZ
1480 break;
1481 case 2:
1482 default:
67dcab73
AJ
1483 if (bswap) {
1484 tcg_out_bswap32(s, COND_AL, TCG_REG_R0, data_reg);
1485 tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addr_reg, 0);
1486 } else {
1487 tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0);
1488 }
811d4cf4
AZ
1489 break;
1490 case 3:
eae6ce52
AZ
1491 /* TODO: use block store -
1492 * check that data_reg2 > data_reg or the other way */
67dcab73
AJ
1493 if (bswap) {
1494 tcg_out_bswap32(s, COND_AL, TCG_REG_R0, data_reg2);
1495 tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addr_reg, 0);
1496 tcg_out_bswap32(s, COND_AL, TCG_REG_R0, data_reg);
1497 tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addr_reg, 4);
1498 } else {
1499 tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0);
1500 tcg_out_st32_12(s, COND_AL, data_reg2, addr_reg, 4);
1501 }
811d4cf4
AZ
1502 break;
1503 }
1504#endif
1505}
1506
811d4cf4
AZ
1507static uint8_t *tb_ret_addr;
1508
a9751609 1509static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
811d4cf4
AZ
1510 const TCGArg *args, const int *const_args)
1511{
1512 int c;
1513
1514 switch (opc) {
1515 case INDEX_op_exit_tb:
fe33867b
AZ
1516 {
1517 uint8_t *ld_ptr = s->code_ptr;
1518 if (args[0] >> 8)
c8d80cef 1519 tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, TCG_REG_PC, 0);
fe33867b 1520 else
c8d80cef 1521 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R0, 0, args[0]);
fe33867b
AZ
1522 tcg_out_goto(s, COND_AL, (tcg_target_ulong) tb_ret_addr);
1523 if (args[0] >> 8) {
1524 *ld_ptr = (uint8_t) (s->code_ptr - ld_ptr) - 8;
1525 tcg_out32(s, args[0]);
1526 }
1527 }
811d4cf4
AZ
1528 break;
1529 case INDEX_op_goto_tb:
1530 if (s->tb_jmp_offset) {
1531 /* Direct jump method */
fe33867b 1532#if defined(USE_DIRECT_JUMP)
811d4cf4 1533 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
c69806ab 1534 tcg_out_b_noaddr(s, COND_AL);
811d4cf4 1535#else
c8d80cef 1536 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
811d4cf4
AZ
1537 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1538 tcg_out32(s, 0);
1539#endif
1540 } else {
1541 /* Indirect jump method */
1542#if 1
1543 c = (int) (s->tb_next + args[0]) - ((int) s->code_ptr + 8);
1544 if (c > 0xfff || c < -0xfff) {
1545 tcg_out_movi32(s, COND_AL, TCG_REG_R0,
1546 (tcg_target_long) (s->tb_next + args[0]));
c8d80cef 1547 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, 0);
811d4cf4 1548 } else
c8d80cef 1549 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, c);
811d4cf4 1550#else
c8d80cef
AJ
1551 tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, TCG_REG_PC, 0);
1552 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, 0);
811d4cf4
AZ
1553 tcg_out32(s, (tcg_target_long) (s->tb_next + args[0]));
1554#endif
1555 }
1556 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1557 break;
1558 case INDEX_op_call:
1559 if (const_args[0])
24e838b7 1560 tcg_out_call(s, args[0]);
811d4cf4
AZ
1561 else
1562 tcg_out_callr(s, COND_AL, args[0]);
1563 break;
1564 case INDEX_op_jmp:
1565 if (const_args[0])
1566 tcg_out_goto(s, COND_AL, args[0]);
1567 else
1568 tcg_out_bx(s, COND_AL, args[0]);
1569 break;
1570 case INDEX_op_br:
1571 tcg_out_goto_label(s, COND_AL, args[0]);
1572 break;
1573
1574 case INDEX_op_ld8u_i32:
1575 tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]);
1576 break;
1577 case INDEX_op_ld8s_i32:
1578 tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]);
1579 break;
1580 case INDEX_op_ld16u_i32:
1581 tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]);
1582 break;
1583 case INDEX_op_ld16s_i32:
1584 tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]);
1585 break;
1586 case INDEX_op_ld_i32:
1587 tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]);
1588 break;
1589 case INDEX_op_st8_i32:
f694a27e 1590 tcg_out_st8(s, COND_AL, args[0], args[1], args[2]);
811d4cf4
AZ
1591 break;
1592 case INDEX_op_st16_i32:
f694a27e 1593 tcg_out_st16(s, COND_AL, args[0], args[1], args[2]);
811d4cf4
AZ
1594 break;
1595 case INDEX_op_st_i32:
1596 tcg_out_st32(s, COND_AL, args[0], args[1], args[2]);
1597 break;
1598
1599 case INDEX_op_mov_i32:
1600 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1601 args[0], 0, args[1], SHIFT_IMM_LSL(0));
1602 break;
1603 case INDEX_op_movi_i32:
1604 tcg_out_movi32(s, COND_AL, args[0], args[1]);
1605 break;
1606 case INDEX_op_add_i32:
1607 c = ARITH_ADD;
1608 goto gen_arith;
1609 case INDEX_op_sub_i32:
1610 c = ARITH_SUB;
1611 goto gen_arith;
1612 case INDEX_op_and_i32:
1613 c = ARITH_AND;
1614 goto gen_arith;
932234f6
AJ
1615 case INDEX_op_andc_i32:
1616 c = ARITH_BIC;
1617 goto gen_arith;
811d4cf4
AZ
1618 case INDEX_op_or_i32:
1619 c = ARITH_ORR;
1620 goto gen_arith;
1621 case INDEX_op_xor_i32:
1622 c = ARITH_EOR;
1623 /* Fall through. */
1624 gen_arith:
94953e6d
LD
1625 if (const_args[2]) {
1626 int rot;
1627 rot = encode_imm(args[2]);
cb4e581f 1628 tcg_out_dat_imm(s, COND_AL, c,
94953e6d
LD
1629 args[0], args[1], rotl(args[2], rot) | (rot << 7));
1630 } else
cb4e581f
LD
1631 tcg_out_dat_reg(s, COND_AL, c,
1632 args[0], args[1], args[2], SHIFT_IMM_LSL(0));
811d4cf4
AZ
1633 break;
1634 case INDEX_op_add2_i32:
1635 tcg_out_dat_reg2(s, COND_AL, ARITH_ADD, ARITH_ADC,
1636 args[0], args[1], args[2], args[3],
1637 args[4], args[5], SHIFT_IMM_LSL(0));
1638 break;
1639 case INDEX_op_sub2_i32:
1640 tcg_out_dat_reg2(s, COND_AL, ARITH_SUB, ARITH_SBC,
1641 args[0], args[1], args[2], args[3],
1642 args[4], args[5], SHIFT_IMM_LSL(0));
1643 break;
650bbb36
AZ
1644 case INDEX_op_neg_i32:
1645 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0);
1646 break;
f878d2d2
LD
1647 case INDEX_op_not_i32:
1648 tcg_out_dat_reg(s, COND_AL,
1649 ARITH_MVN, args[0], 0, args[1], SHIFT_IMM_LSL(0));
1650 break;
811d4cf4
AZ
1651 case INDEX_op_mul_i32:
1652 tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]);
1653 break;
1654 case INDEX_op_mulu2_i32:
1655 tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]);
1656 break;
811d4cf4
AZ
1657 /* XXX: Perhaps args[2] & 0x1f is wrong */
1658 case INDEX_op_shl_i32:
1659 c = const_args[2] ?
1660 SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]);
1661 goto gen_shift32;
1662 case INDEX_op_shr_i32:
1663 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) :
1664 SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]);
1665 goto gen_shift32;
1666 case INDEX_op_sar_i32:
1667 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) :
1668 SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]);
293579e5
AJ
1669 goto gen_shift32;
1670 case INDEX_op_rotr_i32:
1671 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ROR(args[2] & 0x1f) :
1672 SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args[2]);
811d4cf4
AZ
1673 /* Fall through. */
1674 gen_shift32:
1675 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c);
1676 break;
1677
293579e5
AJ
1678 case INDEX_op_rotl_i32:
1679 if (const_args[2]) {
1680 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1],
1681 ((0x20 - args[2]) & 0x1f) ?
1682 SHIFT_IMM_ROR((0x20 - args[2]) & 0x1f) :
1683 SHIFT_IMM_LSL(0));
1684 } else {
1685 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_R8, args[1], 0x20);
1686 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1],
1687 SHIFT_REG_ROR(TCG_REG_R8));
1688 }
1689 break;
1690
811d4cf4 1691 case INDEX_op_brcond_i32:
023e77f8
AJ
1692 if (const_args[1]) {
1693 int rot;
1694 rot = encode_imm(args[1]);
c8d80cef
AJ
1695 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0,
1696 args[0], rotl(args[1], rot) | (rot << 7));
023e77f8
AJ
1697 } else {
1698 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1699 args[0], args[1], SHIFT_IMM_LSL(0));
1700 }
811d4cf4
AZ
1701 tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], args[3]);
1702 break;
1703 case INDEX_op_brcond2_i32:
1704 /* The resulting conditions are:
1705 * TCG_COND_EQ --> a0 == a2 && a1 == a3,
1706 * TCG_COND_NE --> (a0 != a2 && a1 == a3) || a1 != a3,
1707 * TCG_COND_LT(U) --> (a0 < a2 && a1 == a3) || a1 < a3,
1708 * TCG_COND_GE(U) --> (a0 >= a2 && a1 == a3) || (a1 >= a3 && a1 != a3),
1709 * TCG_COND_LE(U) --> (a0 <= a2 && a1 == a3) || (a1 <= a3 && a1 != a3),
1710 * TCG_COND_GT(U) --> (a0 > a2 && a1 == a3) || a1 > a3,
1711 */
1712 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1713 args[1], args[3], SHIFT_IMM_LSL(0));
1714 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1715 args[0], args[2], SHIFT_IMM_LSL(0));
1716 tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[4]], args[5]);
1717 break;
f72a6cd7 1718 case INDEX_op_setcond_i32:
023e77f8
AJ
1719 if (const_args[2]) {
1720 int rot;
1721 rot = encode_imm(args[2]);
c8d80cef
AJ
1722 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0,
1723 args[1], rotl(args[2], rot) | (rot << 7));
023e77f8
AJ
1724 } else {
1725 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1726 args[1], args[2], SHIFT_IMM_LSL(0));
1727 }
f72a6cd7
AJ
1728 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]],
1729 ARITH_MOV, args[0], 0, 1);
1730 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])],
1731 ARITH_MOV, args[0], 0, 0);
1732 break;
e0404769
AJ
1733 case INDEX_op_setcond2_i32:
1734 /* See brcond2_i32 comment */
1735 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1736 args[2], args[4], SHIFT_IMM_LSL(0));
1737 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1738 args[1], args[3], SHIFT_IMM_LSL(0));
1739 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[5]],
1740 ARITH_MOV, args[0], 0, 1);
1741 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[5])],
1742 ARITH_MOV, args[0], 0, 0);
b525f0a9 1743 break;
811d4cf4
AZ
1744
1745 case INDEX_op_qemu_ld8u:
7e0d9562 1746 tcg_out_qemu_ld(s, args, 0);
811d4cf4
AZ
1747 break;
1748 case INDEX_op_qemu_ld8s:
7e0d9562 1749 tcg_out_qemu_ld(s, args, 0 | 4);
811d4cf4
AZ
1750 break;
1751 case INDEX_op_qemu_ld16u:
7e0d9562 1752 tcg_out_qemu_ld(s, args, 1);
811d4cf4
AZ
1753 break;
1754 case INDEX_op_qemu_ld16s:
7e0d9562 1755 tcg_out_qemu_ld(s, args, 1 | 4);
811d4cf4 1756 break;
86feb1c8 1757 case INDEX_op_qemu_ld32:
7e0d9562 1758 tcg_out_qemu_ld(s, args, 2);
811d4cf4
AZ
1759 break;
1760 case INDEX_op_qemu_ld64:
7e0d9562 1761 tcg_out_qemu_ld(s, args, 3);
811d4cf4 1762 break;
650bbb36 1763
811d4cf4 1764 case INDEX_op_qemu_st8:
7e0d9562 1765 tcg_out_qemu_st(s, args, 0);
811d4cf4
AZ
1766 break;
1767 case INDEX_op_qemu_st16:
7e0d9562 1768 tcg_out_qemu_st(s, args, 1);
811d4cf4
AZ
1769 break;
1770 case INDEX_op_qemu_st32:
7e0d9562 1771 tcg_out_qemu_st(s, args, 2);
811d4cf4
AZ
1772 break;
1773 case INDEX_op_qemu_st64:
7e0d9562 1774 tcg_out_qemu_st(s, args, 3);
811d4cf4
AZ
1775 break;
1776
244b1e81
AJ
1777 case INDEX_op_bswap16_i32:
1778 tcg_out_bswap16(s, COND_AL, args[0], args[1]);
1779 break;
1780 case INDEX_op_bswap32_i32:
1781 tcg_out_bswap32(s, COND_AL, args[0], args[1]);
1782 break;
1783
811d4cf4 1784 case INDEX_op_ext8s_i32:
9517094f 1785 tcg_out_ext8s(s, COND_AL, args[0], args[1]);
811d4cf4
AZ
1786 break;
1787 case INDEX_op_ext16s_i32:
9517094f
AJ
1788 tcg_out_ext16s(s, COND_AL, args[0], args[1]);
1789 break;
1790 case INDEX_op_ext16u_i32:
1791 tcg_out_ext16u(s, COND_AL, args[0], args[1]);
811d4cf4
AZ
1792 break;
1793
1794 default:
1795 tcg_abort();
1796 }
1797}
1798
1799static const TCGTargetOpDef arm_op_defs[] = {
1800 { INDEX_op_exit_tb, { } },
1801 { INDEX_op_goto_tb, { } },
1802 { INDEX_op_call, { "ri" } },
1803 { INDEX_op_jmp, { "ri" } },
1804 { INDEX_op_br, { } },
1805
1806 { INDEX_op_mov_i32, { "r", "r" } },
1807 { INDEX_op_movi_i32, { "r" } },
1808
1809 { INDEX_op_ld8u_i32, { "r", "r" } },
1810 { INDEX_op_ld8s_i32, { "r", "r" } },
1811 { INDEX_op_ld16u_i32, { "r", "r" } },
1812 { INDEX_op_ld16s_i32, { "r", "r" } },
1813 { INDEX_op_ld_i32, { "r", "r" } },
1814 { INDEX_op_st8_i32, { "r", "r" } },
1815 { INDEX_op_st16_i32, { "r", "r" } },
1816 { INDEX_op_st_i32, { "r", "r" } },
1817
1818 /* TODO: "r", "r", "ri" */
cb4e581f
LD
1819 { INDEX_op_add_i32, { "r", "r", "rI" } },
1820 { INDEX_op_sub_i32, { "r", "r", "rI" } },
811d4cf4
AZ
1821 { INDEX_op_mul_i32, { "r", "r", "r" } },
1822 { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
cb4e581f 1823 { INDEX_op_and_i32, { "r", "r", "rI" } },
932234f6 1824 { INDEX_op_andc_i32, { "r", "r", "rI" } },
cb4e581f
LD
1825 { INDEX_op_or_i32, { "r", "r", "rI" } },
1826 { INDEX_op_xor_i32, { "r", "r", "rI" } },
650bbb36 1827 { INDEX_op_neg_i32, { "r", "r" } },
f878d2d2 1828 { INDEX_op_not_i32, { "r", "r" } },
811d4cf4
AZ
1829
1830 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1831 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1832 { INDEX_op_sar_i32, { "r", "r", "ri" } },
293579e5
AJ
1833 { INDEX_op_rotl_i32, { "r", "r", "ri" } },
1834 { INDEX_op_rotr_i32, { "r", "r", "ri" } },
811d4cf4 1835
023e77f8
AJ
1836 { INDEX_op_brcond_i32, { "r", "rI" } },
1837 { INDEX_op_setcond_i32, { "r", "r", "rI" } },
811d4cf4
AZ
1838
1839 /* TODO: "r", "r", "r", "r", "ri", "ri" */
1840 { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1841 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1842 { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
e0404769 1843 { INDEX_op_setcond2_i32, { "r", "r", "r", "r", "r" } },
811d4cf4 1844
26c5d372 1845#if TARGET_LONG_BITS == 32
67dcab73
AJ
1846 { INDEX_op_qemu_ld8u, { "r", "l" } },
1847 { INDEX_op_qemu_ld8s, { "r", "l" } },
1848 { INDEX_op_qemu_ld16u, { "r", "l" } },
1849 { INDEX_op_qemu_ld16s, { "r", "l" } },
1850 { INDEX_op_qemu_ld32, { "r", "l" } },
1851 { INDEX_op_qemu_ld64, { "L", "L", "l" } },
1852
1853 { INDEX_op_qemu_st8, { "s", "s" } },
1854 { INDEX_op_qemu_st16, { "s", "s" } },
1855 { INDEX_op_qemu_st32, { "s", "s" } },
bf5675ef 1856 { INDEX_op_qemu_st64, { "S", "S", "s" } },
26c5d372 1857#else
67dcab73
AJ
1858 { INDEX_op_qemu_ld8u, { "r", "l", "l" } },
1859 { INDEX_op_qemu_ld8s, { "r", "l", "l" } },
1860 { INDEX_op_qemu_ld16u, { "r", "l", "l" } },
1861 { INDEX_op_qemu_ld16s, { "r", "l", "l" } },
1862 { INDEX_op_qemu_ld32, { "r", "l", "l" } },
1863 { INDEX_op_qemu_ld64, { "L", "L", "l", "l" } },
1864
1865 { INDEX_op_qemu_st8, { "s", "s", "s" } },
1866 { INDEX_op_qemu_st16, { "s", "s", "s" } },
1867 { INDEX_op_qemu_st32, { "s", "s", "s" } },
bf5675ef 1868 { INDEX_op_qemu_st64, { "S", "S", "s", "s" } },
26c5d372 1869#endif
811d4cf4 1870
244b1e81
AJ
1871 { INDEX_op_bswap16_i32, { "r", "r" } },
1872 { INDEX_op_bswap32_i32, { "r", "r" } },
1873
811d4cf4
AZ
1874 { INDEX_op_ext8s_i32, { "r", "r" } },
1875 { INDEX_op_ext16s_i32, { "r", "r" } },
9517094f 1876 { INDEX_op_ext16u_i32, { "r", "r" } },
811d4cf4
AZ
1877
1878 { -1 },
1879};
1880
e4d58b41 1881static void tcg_target_init(TCGContext *s)
811d4cf4 1882{
20cb400d 1883#if !defined(CONFIG_USER_ONLY)
811d4cf4
AZ
1884 /* fail safe */
1885 if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1886 tcg_abort();
20cb400d 1887#endif
811d4cf4 1888
e4a7d5e8 1889 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
811d4cf4 1890 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
e4a7d5e8
AJ
1891 (1 << TCG_REG_R0) |
1892 (1 << TCG_REG_R1) |
1893 (1 << TCG_REG_R2) |
1894 (1 << TCG_REG_R3) |
1895 (1 << TCG_REG_R12) |
1896 (1 << TCG_REG_R14));
811d4cf4
AZ
1897
1898 tcg_regset_clear(s->reserved_regs);
811d4cf4
AZ
1899 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
1900 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R8);
e4a7d5e8 1901 tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC);
811d4cf4
AZ
1902
1903 tcg_add_target_add_op_defs(arm_op_defs);
9349b4f9 1904 tcg_set_frame(s, TCG_AREG0, offsetof(CPUArchState, temp_buf),
614f104d 1905 CPU_TEMP_BUF_NLONGS * sizeof(long));
811d4cf4
AZ
1906}
1907
2a534aff
RH
1908static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
1909 TCGReg arg1, tcg_target_long arg2)
811d4cf4
AZ
1910{
1911 tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
1912}
1913
2a534aff
RH
1914static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
1915 TCGReg arg1, tcg_target_long arg2)
811d4cf4
AZ
1916{
1917 tcg_out_st32(s, COND_AL, arg, arg1, arg2);
1918}
1919
2a534aff
RH
1920static inline void tcg_out_mov(TCGContext *s, TCGType type,
1921 TCGReg ret, TCGReg arg)
811d4cf4
AZ
1922{
1923 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, ret, 0, arg, SHIFT_IMM_LSL(0));
1924}
1925
1926static inline void tcg_out_movi(TCGContext *s, TCGType type,
2a534aff 1927 TCGReg ret, tcg_target_long arg)
811d4cf4
AZ
1928{
1929 tcg_out_movi32(s, COND_AL, ret, arg);
1930}
1931
e4d58b41 1932static void tcg_target_qemu_prologue(TCGContext *s)
811d4cf4 1933{
cea5f9a2
BS
1934 /* Calling convention requires us to save r4-r11 and lr;
1935 * save also r12 to maintain stack 8-alignment.
1936 */
1937
1938 /* stmdb sp!, { r4 - r12, lr } */
1939 tcg_out32(s, (COND_AL << 28) | 0x092d5ff0);
4e17eae9 1940
cea5f9a2 1941 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
811d4cf4 1942
cea5f9a2 1943 tcg_out_bx(s, COND_AL, tcg_target_call_iarg_regs[1]);
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AZ
1944 tb_ret_addr = s->code_ptr;
1945
cea5f9a2
BS
1946 /* ldmia sp!, { r4 - r12, pc } */
1947 tcg_out32(s, (COND_AL << 28) | 0x08bd9ff0);
811d4cf4 1948}