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tcg/arm: use ext* ops in qemu_ld
[mirror_qemu.git] / tcg / arm / tcg-target.c
CommitLineData
811d4cf4
AZ		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Andrzej Zaborowski
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
d4a9eb1f 24
ac34fb5c
AJ		 25#if defined(__ARM_ARCH_7__) || \
26 defined(__ARM_ARCH_7A__) || \
27 defined(__ARM_ARCH_7EM__) || \
28 defined(__ARM_ARCH_7M__) || \
29 defined(__ARM_ARCH_7R__)
30#define USE_ARMV7_INSTRUCTIONS
31#endif
32
33#if defined(USE_ARMV7_INSTRUCTIONS) || \
34 defined(__ARM_ARCH_6J__) || \
35 defined(__ARM_ARCH_6K__) || \
36 defined(__ARM_ARCH_6T2__) || \
37 defined(__ARM_ARCH_6Z__) || \
38 defined(__ARM_ARCH_6ZK__)
39#define USE_ARMV6_INSTRUCTIONS
40#endif
41
42#if defined(USE_ARMV6_INSTRUCTIONS) || \
43 defined(__ARM_ARCH_5T__) || \
44 defined(__ARM_ARCH_5TE__) || \
45 defined(__ARM_ARCH_5TEJ__)
46#define USE_ARMV5_INSTRUCTIONS
47#endif
48
49#ifdef USE_ARMV5_INSTRUCTIONS
50static const int use_armv5_instructions = 1;
51#else
52static const int use_armv5_instructions = 0;
53#endif
54#undef USE_ARMV5_INSTRUCTIONS
55
56#ifdef USE_ARMV6_INSTRUCTIONS
57static const int use_armv6_instructions = 1;
58#else
59static const int use_armv6_instructions = 0;
60#endif
61#undef USE_ARMV6_INSTRUCTIONS
62
63#ifdef USE_ARMV7_INSTRUCTIONS
64static const int use_armv7_instructions = 1;
65#else
66static const int use_armv7_instructions = 0;
67#endif
68#undef USE_ARMV7_INSTRUCTIONS
69
d4a9eb1f
BS		 70#ifndef NDEBUG
71static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
811d4cf4
AZ		 72 "%r0",
73 "%r1",
74 "%r2",
75 "%r3",
76 "%r4",
77 "%r5",
78 "%r6",
79 "%r7",
80 "%r8",
81 "%r9",
82 "%r10",
83 "%r11",
84 "%r12",
85 "%r13",
86 "%r14",
e4a7d5e8 87 "%pc",
811d4cf4 88};
d4a9eb1f 89#endif
811d4cf4 90
d4a9eb1f 91static const int tcg_target_reg_alloc_order[] = {
811d4cf4
AZ		 92 TCG_REG_R0,
93 TCG_REG_R1,
94 TCG_REG_R2,
95 TCG_REG_R3,
96 TCG_REG_R4,
97 TCG_REG_R5,
98 TCG_REG_R6,
99 TCG_REG_R7,
100 TCG_REG_R8,
101 TCG_REG_R9,
102 TCG_REG_R10,
103 TCG_REG_R11,
104 TCG_REG_R12,
105 TCG_REG_R13,
106 TCG_REG_R14,
107};
108
d4a9eb1f 109static const int tcg_target_call_iarg_regs[4] = {
811d4cf4
AZ		 110 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3
111};
d4a9eb1f 112static const int tcg_target_call_oarg_regs[2] = {
811d4cf4
AZ		 113 TCG_REG_R0, TCG_REG_R1
114};
115
650bbb36 116static void patch_reloc(uint8_t *code_ptr, int type,
811d4cf4
AZ		 117 tcg_target_long value, tcg_target_long addend)
118{
119 switch (type) {
120 case R_ARM_ABS32:
121 *(uint32_t *) code_ptr = value;
122 break;
123
124 case R_ARM_CALL:
125 case R_ARM_JUMP24:
126 default:
127 tcg_abort();
128
129 case R_ARM_PC24:
eae6ce52 130 *(uint32_t *) code_ptr = ((*(uint32_t *) code_ptr) & 0xff000000) |
e936243a 131 (((value - ((tcg_target_long) code_ptr + 8)) >> 2) & 0xffffff);
811d4cf4
AZ		 132 break;
133 }
134}
135
136/* maximum number of register used for input function arguments */
137static inline int tcg_target_get_call_iarg_regs_count(int flags)
138{
139 return 4;
140}
141
811d4cf4 142/* parse target specific constraints */
d4a9eb1f 143static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
811d4cf4
AZ		 144{
145 const char *ct_str;
146
147 ct_str = *pct_str;
148 switch (ct_str[0]) {
cb4e581f
LD		 149 case 'I':
150 ct->ct |= TCG_CT_CONST_ARM;
151 break;
152
811d4cf4
AZ		 153 case 'r':
154#ifndef CONFIG_SOFTMMU
155 case 'd':
156 case 'D':
157 case 'x':
158 case 'X':
159#endif
160 ct->ct |= TCG_CT_REG;
161 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
162 break;
163
164#ifdef CONFIG_SOFTMMU
d0660ed4 165 /* qemu_ld/st inputs (unless 'X', 'd' or 'D') */
811d4cf4
AZ		 166 case 'x':
167 ct->ct |= TCG_CT_REG;
168 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
811d4cf4
AZ		 169 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
170 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
811d4cf4
AZ		 171 break;
172
d0660ed4
AZ		 173 /* qemu_ld64 data_reg */
174 case 'd':
175 ct->ct |= TCG_CT_REG;
176 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
177 /* r1 is still needed to load data_reg2, so don't use it. */
178 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
179 break;
180
811d4cf4
AZ		 181 /* qemu_ld/st64 data_reg2 */
182 case 'D':
183 ct->ct |= TCG_CT_REG;
184 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
185 /* r0, r1 and optionally r2 will be overwritten by the address
186 * and the low word of data, so don't use these. */
187 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
188 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
189# if TARGET_LONG_BITS == 64
190 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
191# endif
192 break;
193
194# if TARGET_LONG_BITS == 64
195 /* qemu_ld/st addr_reg2 */
196 case 'X':
197 ct->ct |= TCG_CT_REG;
198 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
199 /* r0 will be overwritten by the low word of base, so don't use it. */
200 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
811d4cf4 201 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
811d4cf4
AZ		 202 break;
203# endif
204#endif
205
811d4cf4
AZ		 206 default:
207 return -1;
208 }
209 ct_str++;
210 *pct_str = ct_str;
211
212 return 0;
213}
214
94953e6d
LD		 215static inline uint32_t rotl(uint32_t val, int n)
216{
217 return (val << n) | (val >> (32 - n));
218}
219
220/* ARM immediates for ALU instructions are made of an unsigned 8-bit
221 right-rotated by an even amount between 0 and 30. */
222static inline int encode_imm(uint32_t imm)
223{
4e6f6d4c
LD		 224 int shift;
225
94953e6d
LD		 226 /* simple case, only lower bits */
227 if ((imm & ~0xff) == 0)
228 return 0;
229 /* then try a simple even shift */
230 shift = ctz32(imm) & ~1;
231 if (((imm >> shift) & ~0xff) == 0)
232 return 32 - shift;
233 /* now try harder with rotations */
234 if ((rotl(imm, 2) & ~0xff) == 0)
235 return 2;
236 if ((rotl(imm, 4) & ~0xff) == 0)
237 return 4;
238 if ((rotl(imm, 6) & ~0xff) == 0)
239 return 6;
240 /* imm can't be encoded */
241 return -1;
242}
cb4e581f
LD		 243
244static inline int check_fit_imm(uint32_t imm)
245{
94953e6d 246 return encode_imm(imm) >= 0;
cb4e581f
LD		 247}
248
811d4cf4
AZ		 249/* Test if a constant matches the constraint.
250 * TODO: define constraints for:
251 *
252 * ldr/str offset: between -0xfff and 0xfff
253 * ldrh/strh offset: between -0xff and 0xff
254 * mov operand2: values represented with x << (2 * y), x < 0x100
255 * add, sub, eor...: ditto
256 */
257static inline int tcg_target_const_match(tcg_target_long val,
258 const TCGArgConstraint *arg_ct)
259{
260 int ct;
261 ct = arg_ct->ct;
262 if (ct & TCG_CT_CONST)
263 return 1;
cb4e581f
LD		 264 else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val))
265 return 1;
811d4cf4
AZ		 266 else
267 return 0;
268}
269
270enum arm_data_opc_e {
271 ARITH_AND = 0x0,
272 ARITH_EOR = 0x1,
273 ARITH_SUB = 0x2,
274 ARITH_RSB = 0x3,
275 ARITH_ADD = 0x4,
276 ARITH_ADC = 0x5,
277 ARITH_SBC = 0x6,
278 ARITH_RSC = 0x7,
3979144c 279 ARITH_TST = 0x8,
811d4cf4
AZ		 280 ARITH_CMP = 0xa,
281 ARITH_CMN = 0xb,
282 ARITH_ORR = 0xc,
283 ARITH_MOV = 0xd,
284 ARITH_BIC = 0xe,
285 ARITH_MVN = 0xf,
286};
287
3979144c
PB		 288#define TO_CPSR(opc) \
289 ((opc == ARITH_CMP || opc == ARITH_CMN || opc == ARITH_TST) << 20)
811d4cf4
AZ		 290
291#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
292#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20)
293#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40)
294#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60)
295#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10)
296#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30)
297#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50)
298#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70)
299
300enum arm_cond_code_e {
301 COND_EQ = 0x0,
302 COND_NE = 0x1,
303 COND_CS = 0x2, /* Unsigned greater or equal */
304 COND_CC = 0x3, /* Unsigned less than */
305 COND_MI = 0x4, /* Negative */
306 COND_PL = 0x5, /* Zero or greater */
307 COND_VS = 0x6, /* Overflow */
308 COND_VC = 0x7, /* No overflow */
309 COND_HI = 0x8, /* Unsigned greater than */
310 COND_LS = 0x9, /* Unsigned less or equal */
311 COND_GE = 0xa,
312 COND_LT = 0xb,
313 COND_GT = 0xc,
314 COND_LE = 0xd,
315 COND_AL = 0xe,
316};
317
318static const uint8_t tcg_cond_to_arm_cond[10] = {
319 [TCG_COND_EQ] = COND_EQ,
320 [TCG_COND_NE] = COND_NE,
321 [TCG_COND_LT] = COND_LT,
322 [TCG_COND_GE] = COND_GE,
323 [TCG_COND_LE] = COND_LE,
324 [TCG_COND_GT] = COND_GT,
325 /* unsigned */
326 [TCG_COND_LTU] = COND_CC,
327 [TCG_COND_GEU] = COND_CS,
328 [TCG_COND_LEU] = COND_LS,
329 [TCG_COND_GTU] = COND_HI,
330};
331
332static inline void tcg_out_bx(TCGContext *s, int cond, int rn)
333{
334 tcg_out32(s, (cond << 28) | 0x012fff10 | rn);
335}
336
337static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset)
338{
339 tcg_out32(s, (cond << 28) | 0x0a000000 |
340 (((offset - 8) >> 2) & 0x00ffffff));
341}
342
e936243a
AZ		 343static inline void tcg_out_b_noaddr(TCGContext *s, int cond)
344{
e2542fe2 345#ifdef HOST_WORDS_BIGENDIAN
e936243a
AZ		 346 tcg_out8(s, (cond << 4) | 0x0a);
347 s->code_ptr += 3;
348#else
349 s->code_ptr += 3;
350 tcg_out8(s, (cond << 4) | 0x0a);
351#endif
352}
353
811d4cf4
AZ		 354static inline void tcg_out_bl(TCGContext *s, int cond, int32_t offset)
355{
356 tcg_out32(s, (cond << 28) | 0x0b000000 |
357 (((offset - 8) >> 2) & 0x00ffffff));
358}
359
23401b58
AJ		 360static inline void tcg_out_blx(TCGContext *s, int cond, int rn)
361{
362 tcg_out32(s, (cond << 28) | 0x012fff30 | rn);
363}
364
811d4cf4
AZ		 365static inline void tcg_out_dat_reg(TCGContext *s,
366 int cond, int opc, int rd, int rn, int rm, int shift)
367{
368 tcg_out32(s, (cond << 28) | (0 << 25) | (opc << 21) | TO_CPSR(opc) |
369 (rn << 16) | (rd << 12) | shift | rm);
370}
371
372static inline void tcg_out_dat_reg2(TCGContext *s,
373 int cond, int opc0, int opc1, int rd0, int rd1,
374 int rn0, int rn1, int rm0, int rm1, int shift)
375{
0c9c3a9e
AZ		 376 if (rd0 == rn1 || rd0 == rm1) {
377 tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
378 (rn0 << 16) | (8 << 12) | shift | rm0);
379 tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
380 (rn1 << 16) | (rd1 << 12) | shift | rm1);
381 tcg_out_dat_reg(s, cond, ARITH_MOV,
382 rd0, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
383 } else {
384 tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
385 (rn0 << 16) | (rd0 << 12) | shift | rm0);
386 tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
387 (rn1 << 16) | (rd1 << 12) | shift | rm1);
388 }
811d4cf4
AZ		 389}
390
391static inline void tcg_out_dat_imm(TCGContext *s,
392 int cond, int opc, int rd, int rn, int im)
393{
3979144c 394 tcg_out32(s, (cond << 28) | (1 << 25) | (opc << 21) | TO_CPSR(opc) |
811d4cf4
AZ		 395 (rn << 16) | (rd << 12) | im);
396}
397
398static inline void tcg_out_movi32(TCGContext *s,
399 int cond, int rd, int32_t arg)
400{
401 int offset = (uint32_t) arg - ((uint32_t) s->code_ptr + 8);
402
403 /* TODO: This is very suboptimal, we can easily have a constant
404 * pool somewhere after all the instructions. */
405
406 if (arg < 0 && arg > -0x100)
407 return tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, (~arg) & 0xff);
408
409 if (offset < 0x100 && offset > -0x100)
410 return offset >= 0 ?
411 tcg_out_dat_imm(s, cond, ARITH_ADD, rd, 15, offset) :
412 tcg_out_dat_imm(s, cond, ARITH_SUB, rd, 15, -offset);
413
ac34fb5c
AJ		 414 if (use_armv7_instructions) {
415 /* use movw/movt */
416 /* movw */
417 tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12)
418 | ((arg << 4) & 0x000f0000) | (arg & 0xfff));
419 if (arg & 0xffff0000)
420 /* movt */
421 tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12)
422 | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff));
423 } else {
424 tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, arg & 0xff);
425 if (arg & 0x0000ff00)
426 tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
427 ((arg >> 8) & 0xff) | 0xc00);
428 if (arg & 0x00ff0000)
429 tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
430 ((arg >> 16) & 0xff) | 0x800);
431 if (arg & 0xff000000)
432 tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
433 ((arg >> 24) & 0xff) | 0x400);
434 }
811d4cf4
AZ		 435}
436
437static inline void tcg_out_mul32(TCGContext *s,
438 int cond, int rd, int rs, int rm)
439{
440 if (rd != rm)
441 tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
442 (rs << 8) | 0x90 | rm);
443 else if (rd != rs)
444 tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
445 (rm << 8) | 0x90 | rs);
446 else {
447 tcg_out32(s, (cond << 28) | ( 8 << 16) | (0 << 12) |
448 (rs << 8) | 0x90 | rm);
449 tcg_out_dat_reg(s, cond, ARITH_MOV,
c8d80cef 450 rd, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
811d4cf4
AZ		 451 }
452}
453
454static inline void tcg_out_umull32(TCGContext *s,
455 int cond, int rd0, int rd1, int rs, int rm)
456{
457 if (rd0 != rm && rd1 != rm)
458 tcg_out32(s, (cond << 28) | 0x800090 |
459 (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
460 else if (rd0 != rs && rd1 != rs)
461 tcg_out32(s, (cond << 28) | 0x800090 |
462 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
463 else {
464 tcg_out_dat_reg(s, cond, ARITH_MOV,
465 TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));
466 tcg_out32(s, (cond << 28) | 0x800098 |
467 (rd1 << 16) | (rd0 << 12) | (rs << 8));
468 }
469}
470
471static inline void tcg_out_smull32(TCGContext *s,
472 int cond, int rd0, int rd1, int rs, int rm)
473{
474 if (rd0 != rm && rd1 != rm)
475 tcg_out32(s, (cond << 28) | 0xc00090 |
476 (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
477 else if (rd0 != rs && rd1 != rs)
478 tcg_out32(s, (cond << 28) | 0xc00090 |
479 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
480 else {
481 tcg_out_dat_reg(s, cond, ARITH_MOV,
482 TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));
483 tcg_out32(s, (cond << 28) | 0xc00098 |
484 (rd1 << 16) | (rd0 << 12) | (rs << 8));
485 }
486}
487
9517094f
AJ		 488static inline void tcg_out_ext8s(TCGContext *s, int cond,
489 int rd, int rn)
490{
491 if (use_armv6_instructions) {
492 /* sxtb */
493 tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | rn);
494 } else {
495 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
496 rd, 0, rn, SHIFT_IMM_LSL(24));
497 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
498 rd, 0, rd, SHIFT_IMM_ASR(24));
499 }
500}
501
e854b6d3
AJ		 502static inline void tcg_out_ext8u(TCGContext *s, int cond,
503 int rd, int rn)
504{
505 tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 0xff);
506}
507
9517094f
AJ		 508static inline void tcg_out_ext16s(TCGContext *s, int cond,
509 int rd, int rn)
510{
511 if (use_armv6_instructions) {
512 /* sxth */
513 tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | rn);
514 } else {
515 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
516 rd, 0, rn, SHIFT_IMM_LSL(16));
517 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
518 rd, 0, rd, SHIFT_IMM_ASR(16));
519 }
520}
521
522static inline void tcg_out_ext16u(TCGContext *s, int cond,
523 int rd, int rn)
524{
525 if (use_armv6_instructions) {
526 /* uxth */
527 tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rn);
528 } else {
529 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
530 rd, 0, rn, SHIFT_IMM_LSL(16));
531 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
532 rd, 0, rd, SHIFT_IMM_LSR(16));
533 }
534}
535
244b1e81
AJ		 536static inline void tcg_out_bswap16(TCGContext *s, int cond, int rd, int rn)
537{
538 if (use_armv6_instructions) {
539 /* rev16 */
540 tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn);
541 } else {
542 tcg_out_dat_reg(s, cond, ARITH_MOV,
543 TCG_REG_R8, 0, rn, SHIFT_IMM_LSL(24));
544 tcg_out_dat_reg(s, cond, ARITH_MOV,
545 TCG_REG_R8, 0, TCG_REG_R8, SHIFT_IMM_LSR(16));
546 tcg_out_dat_reg(s, cond, ARITH_ORR,
547 rd, TCG_REG_R8, rn, SHIFT_IMM_LSR(8));
548 }
549}
550
551static inline void tcg_out_bswap32(TCGContext *s, int cond, int rd, int rn)
552{
553 if (use_armv6_instructions) {
554 /* rev */
555 tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn);
556 } else {
557 tcg_out_dat_reg(s, cond, ARITH_EOR,
558 TCG_REG_R8, rn, rn, SHIFT_IMM_ROR(16));
559 tcg_out_dat_imm(s, cond, ARITH_BIC,
560 TCG_REG_R8, TCG_REG_R8, 0xff | 0x800);
561 tcg_out_dat_reg(s, cond, ARITH_MOV,
562 rd, 0, rn, SHIFT_IMM_ROR(8));
563 tcg_out_dat_reg(s, cond, ARITH_EOR,
564 rd, rd, TCG_REG_R8, SHIFT_IMM_LSR(8));
565 }
566}
567
811d4cf4
AZ		 568static inline void tcg_out_ld32_12(TCGContext *s, int cond,
569 int rd, int rn, tcg_target_long im)
570{
571 if (im >= 0)
572 tcg_out32(s, (cond << 28) | 0x05900000 |
573 (rn << 16) | (rd << 12) | (im & 0xfff));
574 else
575 tcg_out32(s, (cond << 28) | 0x05100000 |
576 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
577}
578
579static inline void tcg_out_st32_12(TCGContext *s, int cond,
580 int rd, int rn, tcg_target_long im)
581{
582 if (im >= 0)
583 tcg_out32(s, (cond << 28) | 0x05800000 |
584 (rn << 16) | (rd << 12) | (im & 0xfff));
585 else
586 tcg_out32(s, (cond << 28) | 0x05000000 |
587 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
588}
589
590static inline void tcg_out_ld32_r(TCGContext *s, int cond,
591 int rd, int rn, int rm)
592{
593 tcg_out32(s, (cond << 28) | 0x07900000 |
594 (rn << 16) | (rd << 12) | rm);
595}
596
597static inline void tcg_out_st32_r(TCGContext *s, int cond,
598 int rd, int rn, int rm)
599{
600 tcg_out32(s, (cond << 28) | 0x07800000 |
601 (rn << 16) | (rd << 12) | rm);
602}
603
3979144c
PB		 604/* Register pre-increment with base writeback. */
605static inline void tcg_out_ld32_rwb(TCGContext *s, int cond,
606 int rd, int rn, int rm)
607{
608 tcg_out32(s, (cond << 28) | 0x07b00000 |
609 (rn << 16) | (rd << 12) | rm);
610}
611
612static inline void tcg_out_st32_rwb(TCGContext *s, int cond,
613 int rd, int rn, int rm)
614{
615 tcg_out32(s, (cond << 28) | 0x07a00000 |
616 (rn << 16) | (rd << 12) | rm);
617}
618
811d4cf4
AZ		 619static inline void tcg_out_ld16u_8(TCGContext *s, int cond,
620 int rd, int rn, tcg_target_long im)
621{
622 if (im >= 0)
623 tcg_out32(s, (cond << 28) | 0x01d000b0 |
624 (rn << 16) | (rd << 12) |
625 ((im & 0xf0) << 4) | (im & 0xf));
626 else
627 tcg_out32(s, (cond << 28) | 0x015000b0 |
628 (rn << 16) | (rd << 12) |
629 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
630}
631
f694a27e 632static inline void tcg_out_st16_8(TCGContext *s, int cond,
811d4cf4
AZ		 633 int rd, int rn, tcg_target_long im)
634{
635 if (im >= 0)
636 tcg_out32(s, (cond << 28) | 0x01c000b0 |
637 (rn << 16) | (rd << 12) |
638 ((im & 0xf0) << 4) | (im & 0xf));
639 else
640 tcg_out32(s, (cond << 28) | 0x014000b0 |
641 (rn << 16) | (rd << 12) |
642 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
643}
644
645static inline void tcg_out_ld16u_r(TCGContext *s, int cond,
646 int rd, int rn, int rm)
647{
648 tcg_out32(s, (cond << 28) | 0x019000b0 |
649 (rn << 16) | (rd << 12) | rm);
650}
651
f694a27e 652static inline void tcg_out_st16_r(TCGContext *s, int cond,
811d4cf4
AZ		 653 int rd, int rn, int rm)
654{
655 tcg_out32(s, (cond << 28) | 0x018000b0 |
656 (rn << 16) | (rd << 12) | rm);
657}
658
659static inline void tcg_out_ld16s_8(TCGContext *s, int cond,
660 int rd, int rn, tcg_target_long im)
661{
662 if (im >= 0)
663 tcg_out32(s, (cond << 28) | 0x01d000f0 |
664 (rn << 16) | (rd << 12) |
665 ((im & 0xf0) << 4) | (im & 0xf));
666 else
667 tcg_out32(s, (cond << 28) | 0x015000f0 |
668 (rn << 16) | (rd << 12) |
669 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
670}
671
811d4cf4
AZ		 672static inline void tcg_out_ld16s_r(TCGContext *s, int cond,
673 int rd, int rn, int rm)
674{
675 tcg_out32(s, (cond << 28) | 0x019000f0 |
676 (rn << 16) | (rd << 12) | rm);
677}
678
811d4cf4
AZ		 679static inline void tcg_out_ld8_12(TCGContext *s, int cond,
680 int rd, int rn, tcg_target_long im)
681{
682 if (im >= 0)
683 tcg_out32(s, (cond << 28) | 0x05d00000 |
684 (rn << 16) | (rd << 12) | (im & 0xfff));
685 else
686 tcg_out32(s, (cond << 28) | 0x05500000 |
687 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
688}
689
690static inline void tcg_out_st8_12(TCGContext *s, int cond,
691 int rd, int rn, tcg_target_long im)
692{
693 if (im >= 0)
694 tcg_out32(s, (cond << 28) | 0x05c00000 |
695 (rn << 16) | (rd << 12) | (im & 0xfff));
696 else
697 tcg_out32(s, (cond << 28) | 0x05400000 |
698 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
699}
700
701static inline void tcg_out_ld8_r(TCGContext *s, int cond,
702 int rd, int rn, int rm)
703{
704 tcg_out32(s, (cond << 28) | 0x07d00000 |
705 (rn << 16) | (rd << 12) | rm);
706}
707
708static inline void tcg_out_st8_r(TCGContext *s, int cond,
709 int rd, int rn, int rm)
710{
711 tcg_out32(s, (cond << 28) | 0x07c00000 |
712 (rn << 16) | (rd << 12) | rm);
713}
714
715static inline void tcg_out_ld8s_8(TCGContext *s, int cond,
716 int rd, int rn, tcg_target_long im)
717{
718 if (im >= 0)
719 tcg_out32(s, (cond << 28) | 0x01d000d0 |
720 (rn << 16) | (rd << 12) |
721 ((im & 0xf0) << 4) | (im & 0xf));
722 else
723 tcg_out32(s, (cond << 28) | 0x015000d0 |
724 (rn << 16) | (rd << 12) |
725 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
726}
727
811d4cf4
AZ		 728static inline void tcg_out_ld8s_r(TCGContext *s, int cond,
729 int rd, int rn, int rm)
730{
204c1674 731 tcg_out32(s, (cond << 28) | 0x019000d0 |
811d4cf4
AZ		 732 (rn << 16) | (rd << 12) | rm);
733}
734
811d4cf4
AZ		 735static inline void tcg_out_ld32u(TCGContext *s, int cond,
736 int rd, int rn, int32_t offset)
737{
738 if (offset > 0xfff || offset < -0xfff) {
739 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
740 tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_R8);
741 } else
742 tcg_out_ld32_12(s, cond, rd, rn, offset);
743}
744
745static inline void tcg_out_st32(TCGContext *s, int cond,
746 int rd, int rn, int32_t offset)
747{
748 if (offset > 0xfff || offset < -0xfff) {
749 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
750 tcg_out_st32_r(s, cond, rd, rn, TCG_REG_R8);
751 } else
752 tcg_out_st32_12(s, cond, rd, rn, offset);
753}
754
755static inline void tcg_out_ld16u(TCGContext *s, int cond,
756 int rd, int rn, int32_t offset)
757{
758 if (offset > 0xff || offset < -0xff) {
759 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
760 tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_R8);
761 } else
762 tcg_out_ld16u_8(s, cond, rd, rn, offset);
763}
764
765static inline void tcg_out_ld16s(TCGContext *s, int cond,
766 int rd, int rn, int32_t offset)
767{
768 if (offset > 0xff || offset < -0xff) {
769 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
770 tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_R8);
771 } else
772 tcg_out_ld16s_8(s, cond, rd, rn, offset);
773}
774
f694a27e 775static inline void tcg_out_st16(TCGContext *s, int cond,
811d4cf4
AZ		 776 int rd, int rn, int32_t offset)
777{
778 if (offset > 0xff || offset < -0xff) {
779 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
f694a27e 780 tcg_out_st16_r(s, cond, rd, rn, TCG_REG_R8);
811d4cf4 781 } else
f694a27e 782 tcg_out_st16_8(s, cond, rd, rn, offset);
811d4cf4
AZ		 783}
784
785static inline void tcg_out_ld8u(TCGContext *s, int cond,
786 int rd, int rn, int32_t offset)
787{
788 if (offset > 0xfff || offset < -0xfff) {
789 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
790 tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_R8);
791 } else
792 tcg_out_ld8_12(s, cond, rd, rn, offset);
793}
794
795static inline void tcg_out_ld8s(TCGContext *s, int cond,
796 int rd, int rn, int32_t offset)
797{
798 if (offset > 0xff || offset < -0xff) {
799 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
800 tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_R8);
801 } else
802 tcg_out_ld8s_8(s, cond, rd, rn, offset);
803}
804
f694a27e 805static inline void tcg_out_st8(TCGContext *s, int cond,
811d4cf4
AZ		 806 int rd, int rn, int32_t offset)
807{
808 if (offset > 0xfff || offset < -0xfff) {
809 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
810 tcg_out_st8_r(s, cond, rd, rn, TCG_REG_R8);
811 } else
812 tcg_out_st8_12(s, cond, rd, rn, offset);
813}
814
815static inline void tcg_out_goto(TCGContext *s, int cond, uint32_t addr)
816{
817 int32_t val;
818
819 val = addr - (tcg_target_long) s->code_ptr;
820 if (val - 8 < 0x01fffffd && val - 8 > -0x01fffffd)
821 tcg_out_b(s, cond, val);
822 else {
823#if 1
824 tcg_abort();
825#else
826 if (cond == COND_AL) {
c8d80cef 827 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
811d4cf4
AZ		 828 tcg_out32(s, addr); /* XXX: This is l->u.value, can we use it? */
829 } else {
830 tcg_out_movi32(s, cond, TCG_REG_R8, val - 8);
831 tcg_out_dat_reg(s, cond, ARITH_ADD,
c8d80cef
AJ		 832 TCG_REG_PC, TCG_REG_PC,
833 TCG_REG_R8, SHIFT_IMM_LSL(0));
811d4cf4
AZ		 834 }
835#endif
836 }
837}
838
839static inline void tcg_out_call(TCGContext *s, int cond, uint32_t addr)
840{
841 int32_t val;
842
811d4cf4
AZ		 843 val = addr - (tcg_target_long) s->code_ptr;
844 if (val < 0x01fffffd && val > -0x01fffffd)
845 tcg_out_bl(s, cond, val);
846 else {
847#if 1
848 tcg_abort();
849#else
850 if (cond == COND_AL) {
c8d80cef
AJ		 851 tcg_out_dat_imm(s, cond, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 4);
852 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
811d4cf4
AZ		 853 tcg_out32(s, addr); /* XXX: This is l->u.value, can we use it? */
854 } else {
855 tcg_out_movi32(s, cond, TCG_REG_R9, addr);
c8d80cef
AJ		 856 tcg_out_dat_reg(s, cond, ARITH_MOV, TCG_REG_R14, 0,
857 TCG_REG_PC, SHIFT_IMM_LSL(0));
811d4cf4
AZ		 858 tcg_out_bx(s, cond, TCG_REG_R9);
859 }
860#endif
861 }
811d4cf4
AZ		 862}
863
864static inline void tcg_out_callr(TCGContext *s, int cond, int arg)
865{
23401b58
AJ		 866 if (use_armv5_instructions) {
867 tcg_out_blx(s, cond, arg);
868 } else {
869 tcg_out_dat_reg(s, cond, ARITH_MOV, TCG_REG_R14, 0,
870 TCG_REG_PC, SHIFT_IMM_LSL(0));
871 tcg_out_bx(s, cond, arg);
872 }
811d4cf4
AZ		 873}
874
875static inline void tcg_out_goto_label(TCGContext *s, int cond, int label_index)
876{
877 TCGLabel *l = &s->labels[label_index];
878
879 if (l->has_value)
880 tcg_out_goto(s, cond, l->u.value);
881 else if (cond == COND_AL) {
c8d80cef 882 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
811d4cf4
AZ		 883 tcg_out_reloc(s, s->code_ptr, R_ARM_ABS32, label_index, 31337);
884 s->code_ptr += 4;
885 } else {
886 /* Probably this should be preferred even for COND_AL... */
887 tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, label_index, 31337);
e936243a 888 tcg_out_b_noaddr(s, cond);
811d4cf4
AZ		 889 }
890}
891
811d4cf4 892#ifdef CONFIG_SOFTMMU
79383c9c
BS		 893
894#include "../../softmmu_defs.h"
811d4cf4
AZ		 895
896static void *qemu_ld_helpers[4] = {
897 __ldb_mmu,
898 __ldw_mmu,
899 __ldl_mmu,
900 __ldq_mmu,
901};
902
903static void *qemu_st_helpers[4] = {
904 __stb_mmu,
905 __stw_mmu,
906 __stl_mmu,
907 __stq_mmu,
908};
909#endif
910
3979144c
PB		 911#define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
912
7e0d9562 913static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
811d4cf4
AZ		 914{
915 int addr_reg, data_reg, data_reg2;
916#ifdef CONFIG_SOFTMMU
917 int mem_index, s_bits;
918# if TARGET_LONG_BITS == 64
919 int addr_reg2;
920# endif
811d4cf4 921 uint32_t *label_ptr;
811d4cf4
AZ		 922#endif
923
924 data_reg = *args++;
925 if (opc == 3)
926 data_reg2 = *args++;
927 else
d89c682f 928 data_reg2 = 0; /* suppress warning */
811d4cf4 929 addr_reg = *args++;
811d4cf4 930#ifdef CONFIG_SOFTMMU
aef3a282
AZ		 931# if TARGET_LONG_BITS == 64
932 addr_reg2 = *args++;
933# endif
811d4cf4
AZ		 934 mem_index = *args;
935 s_bits = opc & 3;
936
91a3c1b0 937 /* Should generate something like the following:
3979144c 938 * shr r8, addr_reg, #TARGET_PAGE_BITS
91a3c1b0 939 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
3979144c 940 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
91a3c1b0
AZ		 941 */
942# if CPU_TLB_BITS > 8
943# error
944# endif
c8d80cef
AJ		 945 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_R8,
946 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
811d4cf4 947 tcg_out_dat_imm(s, COND_AL, ARITH_AND,
c8d80cef
AJ		 948 TCG_REG_R0, TCG_REG_R8, CPU_TLB_SIZE - 1);
949 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_AREG0,
950 TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
91a3c1b0
AZ		 951 /* In the
952 * ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_read))]
953 * below, the offset is likely to exceed 12 bits if mem_index != 0 and
954 * not exceed otherwise, so use an
955 * add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
956 * before.
957 */
225b4376 958 if (mem_index)
c8d80cef 959 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_REG_R0,
225b4376
AZ		 960 (mem_index << (TLB_SHIFT & 1)) |
961 ((16 - (TLB_SHIFT >> 1)) << 8));
c8d80cef 962 tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R0,
225b4376 963 offsetof(CPUState, tlb_table[0][0].addr_read));
c8d80cef
AJ		 964 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R1,
965 TCG_REG_R8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
3979144c
PB		 966 /* Check alignment. */
967 if (s_bits)
968 tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
969 0, addr_reg, (1 << s_bits) - 1);
811d4cf4
AZ		 970# if TARGET_LONG_BITS == 64
971 /* XXX: possibly we could use a block data load or writeback in
972 * the first access. */
c8d80cef 973 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
225b4376 974 offsetof(CPUState, tlb_table[0][0].addr_read) + 4);
c8d80cef
AJ		 975 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
976 TCG_REG_R1, addr_reg2, SHIFT_IMM_LSL(0));
811d4cf4 977# endif
c8d80cef 978 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
225b4376 979 offsetof(CPUState, tlb_table[0][0].addend));
811d4cf4
AZ		 980
981 switch (opc) {
982 case 0:
c8d80cef 983 tcg_out_ld8_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
811d4cf4
AZ		 984 break;
985 case 0 | 4:
c8d80cef 986 tcg_out_ld8s_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
811d4cf4
AZ		 987 break;
988 case 1:
c8d80cef 989 tcg_out_ld16u_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
811d4cf4
AZ		 990 break;
991 case 1 | 4:
c8d80cef 992 tcg_out_ld16s_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
811d4cf4
AZ		 993 break;
994 case 2:
995 default:
c8d80cef 996 tcg_out_ld32_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
811d4cf4
AZ		 997 break;
998 case 3:
c8d80cef
AJ		 999 tcg_out_ld32_rwb(s, COND_EQ, data_reg, TCG_REG_R1, addr_reg);
1000 tcg_out_ld32_12(s, COND_EQ, data_reg2, TCG_REG_R1, 4);
811d4cf4
AZ		 1001 break;
1002 }
1003
1004 label_ptr = (void *) s->code_ptr;
1005 tcg_out_b(s, COND_EQ, 8);
811d4cf4 1006
811d4cf4 1007 /* TODO: move this code to where the constants pool will be */
c8d80cef 1008 if (addr_reg != TCG_REG_R0) {
7e0d9562 1009 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1010 TCG_REG_R0, 0, addr_reg, SHIFT_IMM_LSL(0));
1011 }
811d4cf4 1012# if TARGET_LONG_BITS == 32
7e0d9562 1013 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R1, 0, mem_index);
811d4cf4 1014# else
c8d80cef 1015 if (addr_reg2 != TCG_REG_R1) {
7e0d9562 1016 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1017 TCG_REG_R1, 0, addr_reg2, SHIFT_IMM_LSL(0));
1018 }
7e0d9562 1019 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R2, 0, mem_index);
811d4cf4 1020# endif
7e0d9562 1021 tcg_out_bl(s, COND_AL, (tcg_target_long) qemu_ld_helpers[s_bits] -
811d4cf4
AZ		 1022 (tcg_target_long) s->code_ptr);
1023
1024 switch (opc) {
1025 case 0 | 4:
e854b6d3 1026 tcg_out_ext8s(s, COND_AL, data_reg, TCG_REG_R0);
811d4cf4
AZ		 1027 break;
1028 case 1 | 4:
e854b6d3 1029 tcg_out_ext16s(s, COND_AL, data_reg, TCG_REG_R0);
811d4cf4
AZ		 1030 break;
1031 case 0:
1032 case 1:
1033 case 2:
1034 default:
c8d80cef 1035 if (data_reg != TCG_REG_R0) {
7e0d9562 1036 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1037 data_reg, 0, TCG_REG_R0, SHIFT_IMM_LSL(0));
1038 }
811d4cf4
AZ		 1039 break;
1040 case 3:
c8d80cef 1041 if (data_reg != TCG_REG_R0) {
7e0d9562 1042 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1043 data_reg, 0, TCG_REG_R0, SHIFT_IMM_LSL(0));
1044 }
1045 if (data_reg2 != TCG_REG_R1) {
7e0d9562 1046 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1047 data_reg2, 0, TCG_REG_R1, SHIFT_IMM_LSL(0));
1048 }
811d4cf4
AZ		 1049 break;
1050 }
1051
811d4cf4 1052 *label_ptr += ((void *) s->code_ptr - (void *) label_ptr - 8) >> 2;
379f6698
PB		 1053#else /* !CONFIG_SOFTMMU */
1054 if (GUEST_BASE) {
1055 uint32_t offset = GUEST_BASE;
1056 int i;
1057 int rot;
1058
1059 while (offset) {
1060 i = ctz32(offset) & ~1;
1061 rot = ((32 - i) << 7) & 0xf00;
1062
c8d80cef 1063 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R8, addr_reg,
379f6698 1064 ((offset >> i) & 0xff) | rot);
c8d80cef 1065 addr_reg = TCG_REG_R8;
379f6698
PB		 1066 offset &= ~(0xff << i);
1067 }
1068 }
811d4cf4
AZ		 1069 switch (opc) {
1070 case 0:
1071 tcg_out_ld8_12(s, COND_AL, data_reg, addr_reg, 0);
1072 break;
1073 case 0 | 4:
1074 tcg_out_ld8s_8(s, COND_AL, data_reg, addr_reg, 0);
1075 break;
1076 case 1:
1077 tcg_out_ld16u_8(s, COND_AL, data_reg, addr_reg, 0);
1078 break;
1079 case 1 | 4:
1080 tcg_out_ld16s_8(s, COND_AL, data_reg, addr_reg, 0);
1081 break;
1082 case 2:
1083 default:
1084 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
1085 break;
1086 case 3:
eae6ce52
AZ		 1087 /* TODO: use block load -
1088 * check that data_reg2 > data_reg or the other way */
419bafa5
AJ		 1089 if (data_reg == addr_reg) {
1090 tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, 4);
1091 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
1092 } else {
1093 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
1094 tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, 4);
1095 }
811d4cf4
AZ		 1096 break;
1097 }
1098#endif
1099}
1100
7e0d9562 1101static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
811d4cf4
AZ		 1102{
1103 int addr_reg, data_reg, data_reg2;
1104#ifdef CONFIG_SOFTMMU
1105 int mem_index, s_bits;
1106# if TARGET_LONG_BITS == 64
1107 int addr_reg2;
1108# endif
811d4cf4 1109 uint32_t *label_ptr;
811d4cf4
AZ		 1110#endif
1111
1112 data_reg = *args++;
1113 if (opc == 3)
1114 data_reg2 = *args++;
1115 else
d89c682f 1116 data_reg2 = 0; /* suppress warning */
811d4cf4 1117 addr_reg = *args++;
811d4cf4 1118#ifdef CONFIG_SOFTMMU
aef3a282
AZ		 1119# if TARGET_LONG_BITS == 64
1120 addr_reg2 = *args++;
1121# endif
811d4cf4
AZ		 1122 mem_index = *args;
1123 s_bits = opc & 3;
1124
91a3c1b0 1125 /* Should generate something like the following:
3979144c 1126 * shr r8, addr_reg, #TARGET_PAGE_BITS
91a3c1b0 1127 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
3979144c 1128 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
91a3c1b0 1129 */
811d4cf4 1130 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef 1131 TCG_REG_R8, 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
811d4cf4 1132 tcg_out_dat_imm(s, COND_AL, ARITH_AND,
c8d80cef
AJ		 1133 TCG_REG_R0, TCG_REG_R8, CPU_TLB_SIZE - 1);
1134 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0,
1135 TCG_AREG0, TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
91a3c1b0
AZ		 1136 /* In the
1137 * ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_write))]
1138 * below, the offset is likely to exceed 12 bits if mem_index != 0 and
1139 * not exceed otherwise, so use an
1140 * add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
1141 * before.
1142 */
225b4376 1143 if (mem_index)
c8d80cef 1144 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_REG_R0,
225b4376
AZ		 1145 (mem_index << (TLB_SHIFT & 1)) |
1146 ((16 - (TLB_SHIFT >> 1)) << 8));
c8d80cef 1147 tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R0,
225b4376 1148 offsetof(CPUState, tlb_table[0][0].addr_write));
c8d80cef
AJ		 1149 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R1,
1150 TCG_REG_R8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
3979144c
PB		 1151 /* Check alignment. */
1152 if (s_bits)
1153 tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
1154 0, addr_reg, (1 << s_bits) - 1);
811d4cf4
AZ		 1155# if TARGET_LONG_BITS == 64
1156 /* XXX: possibly we could use a block data load or writeback in
1157 * the first access. */
c8d80cef
AJ		 1158 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
1159 offsetof(CPUState, tlb_table[0][0].addr_write) + 4);
1160 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1161 TCG_REG_R1, addr_reg2, SHIFT_IMM_LSL(0));
811d4cf4 1162# endif
c8d80cef 1163 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
225b4376 1164 offsetof(CPUState, tlb_table[0][0].addend));
811d4cf4
AZ		 1165
1166 switch (opc) {
1167 case 0:
c8d80cef 1168 tcg_out_st8_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
811d4cf4 1169 break;
811d4cf4 1170 case 1:
c8d80cef 1171 tcg_out_st16_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
811d4cf4
AZ		 1172 break;
1173 case 2:
1174 default:
c8d80cef 1175 tcg_out_st32_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
811d4cf4
AZ		 1176 break;
1177 case 3:
c8d80cef
AJ		 1178 tcg_out_st32_rwb(s, COND_EQ, data_reg, TCG_REG_R1, addr_reg);
1179 tcg_out_st32_12(s, COND_EQ, data_reg2, TCG_REG_R1, 4);
811d4cf4
AZ		 1180 break;
1181 }
1182
1183 label_ptr = (void *) s->code_ptr;
1184 tcg_out_b(s, COND_EQ, 8);
811d4cf4 1185
811d4cf4 1186 /* TODO: move this code to where the constants pool will be */
c8d80cef 1187 if (addr_reg != TCG_REG_R0) {
7e0d9562 1188 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1189 TCG_REG_R0, 0, addr_reg, SHIFT_IMM_LSL(0));
1190 }
811d4cf4
AZ		 1191# if TARGET_LONG_BITS == 32
1192 switch (opc) {
1193 case 0:
e854b6d3 1194 tcg_out_ext8u(s, COND_AL, TCG_REG_R1, data_reg);
7e0d9562 1195 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R2, 0, mem_index);
811d4cf4
AZ		 1196 break;
1197 case 1:
e854b6d3 1198 tcg_out_ext16u(s, COND_AL, TCG_REG_R1, data_reg);
7e0d9562 1199 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R2, 0, mem_index);
811d4cf4
AZ		 1200 break;
1201 case 2:
c8d80cef 1202 if (data_reg != TCG_REG_R1) {
7e0d9562 1203 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1204 TCG_REG_R1, 0, data_reg, SHIFT_IMM_LSL(0));
1205 }
7e0d9562 1206 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R2, 0, mem_index);
811d4cf4
AZ		 1207 break;
1208 case 3:
c8d80cef 1209 if (data_reg != TCG_REG_R1) {
7e0d9562 1210 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1211 TCG_REG_R1, 0, data_reg, SHIFT_IMM_LSL(0));
1212 }
1213 if (data_reg2 != TCG_REG_R2) {
7e0d9562 1214 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1215 TCG_REG_R2, 0, data_reg2, SHIFT_IMM_LSL(0));
1216 }
7e0d9562 1217 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R3, 0, mem_index);
811d4cf4
AZ		 1218 break;
1219 }
1220# else
c8d80cef 1221 if (addr_reg2 != TCG_REG_R1) {
7e0d9562 1222 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1223 TCG_REG_R1, 0, addr_reg2, SHIFT_IMM_LSL(0));
1224 }
811d4cf4
AZ		 1225 switch (opc) {
1226 case 0:
e854b6d3 1227 tcg_out_ext8u(s, COND_AL, TCG_REG_R2, data_reg);
7e0d9562 1228 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R3, 0, mem_index);
811d4cf4
AZ		 1229 break;
1230 case 1:
e854b6d3 1231 tcg_out_ext16u(s, COND_AL, TCG_REG_R2, data_reg);
7e0d9562 1232 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R3, 0, mem_index);
811d4cf4
AZ		 1233 break;
1234 case 2:
c8d80cef 1235 if (data_reg != TCG_REG_R2) {
7e0d9562 1236 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1237 TCG_REG_R2, 0, data_reg, SHIFT_IMM_LSL(0));
1238 }
7e0d9562 1239 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R3, 0, mem_index);
811d4cf4
AZ		 1240 break;
1241 case 3:
7e0d9562
AJ		 1242 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R8, 0, mem_index);
1243 tcg_out32(s, (COND_AL << 28) | 0x052d8010); /* str r8, [sp, #-0x10]! */
c8d80cef 1244 if (data_reg != TCG_REG_R2) {
7e0d9562 1245 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1246 TCG_REG_R2, 0, data_reg, SHIFT_IMM_LSL(0));
1247 }
1248 if (data_reg2 != TCG_REG_R3) {
7e0d9562 1249 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1250 TCG_REG_R3, 0, data_reg2, SHIFT_IMM_LSL(0));
1251 }
811d4cf4
AZ		 1252 break;
1253 }
1254# endif
1255
7e0d9562 1256 tcg_out_bl(s, COND_AL, (tcg_target_long) qemu_st_helpers[s_bits] -
811d4cf4 1257 (tcg_target_long) s->code_ptr);
811d4cf4
AZ		 1258# if TARGET_LONG_BITS == 64
1259 if (opc == 3)
7e0d9562 1260 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R13, TCG_REG_R13, 0x10);
811d4cf4
AZ		 1261# endif
1262
811d4cf4 1263 *label_ptr += ((void *) s->code_ptr - (void *) label_ptr - 8) >> 2;
379f6698
PB		 1264#else /* !CONFIG_SOFTMMU */
1265 if (GUEST_BASE) {
1266 uint32_t offset = GUEST_BASE;
1267 int i;
1268 int rot;
1269
1270 while (offset) {
1271 i = ctz32(offset) & ~1;
1272 rot = ((32 - i) << 7) & 0xf00;
1273
c8d80cef 1274 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R8, addr_reg,
379f6698 1275 ((offset >> i) & 0xff) | rot);
c8d80cef 1276 addr_reg = TCG_REG_R8;
379f6698
PB		 1277 offset &= ~(0xff << i);
1278 }
1279 }
811d4cf4
AZ		 1280 switch (opc) {
1281 case 0:
1282 tcg_out_st8_12(s, COND_AL, data_reg, addr_reg, 0);
1283 break;
811d4cf4 1284 case 1:
f694a27e 1285 tcg_out_st16_8(s, COND_AL, data_reg, addr_reg, 0);
811d4cf4
AZ		 1286 break;
1287 case 2:
1288 default:
1289 tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0);
1290 break;
1291 case 3:
eae6ce52
AZ		 1292 /* TODO: use block store -
1293 * check that data_reg2 > data_reg or the other way */
811d4cf4
AZ		 1294 tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0);
1295 tcg_out_st32_12(s, COND_AL, data_reg2, addr_reg, 4);
1296 break;
1297 }
1298#endif
1299}
1300
811d4cf4
AZ		 1301static uint8_t *tb_ret_addr;
1302
a9751609 1303static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
811d4cf4
AZ		 1304 const TCGArg *args, const int *const_args)
1305{
1306 int c;
1307
1308 switch (opc) {
1309 case INDEX_op_exit_tb:
fe33867b
AZ		 1310 {
1311 uint8_t *ld_ptr = s->code_ptr;
1312 if (args[0] >> 8)
c8d80cef 1313 tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, TCG_REG_PC, 0);
fe33867b 1314 else
c8d80cef 1315 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R0, 0, args[0]);
fe33867b
AZ		 1316 tcg_out_goto(s, COND_AL, (tcg_target_ulong) tb_ret_addr);
1317 if (args[0] >> 8) {
1318 *ld_ptr = (uint8_t) (s->code_ptr - ld_ptr) - 8;
1319 tcg_out32(s, args[0]);
1320 }
1321 }
811d4cf4
AZ		 1322 break;
1323 case INDEX_op_goto_tb:
1324 if (s->tb_jmp_offset) {
1325 /* Direct jump method */
fe33867b 1326#if defined(USE_DIRECT_JUMP)
811d4cf4
AZ		 1327 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1328 tcg_out_b(s, COND_AL, 8);
1329#else
c8d80cef 1330 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
811d4cf4
AZ		 1331 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1332 tcg_out32(s, 0);
1333#endif
1334 } else {
1335 /* Indirect jump method */
1336#if 1
1337 c = (int) (s->tb_next + args[0]) - ((int) s->code_ptr + 8);
1338 if (c > 0xfff || c < -0xfff) {
1339 tcg_out_movi32(s, COND_AL, TCG_REG_R0,
1340 (tcg_target_long) (s->tb_next + args[0]));
c8d80cef 1341 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, 0);
811d4cf4 1342 } else
c8d80cef 1343 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, c);
811d4cf4 1344#else
c8d80cef
AJ		 1345 tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, TCG_REG_PC, 0);
1346 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, 0);
811d4cf4
AZ		 1347 tcg_out32(s, (tcg_target_long) (s->tb_next + args[0]));
1348#endif
1349 }
1350 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1351 break;
1352 case INDEX_op_call:
1353 if (const_args[0])
1354 tcg_out_call(s, COND_AL, args[0]);
1355 else
1356 tcg_out_callr(s, COND_AL, args[0]);
1357 break;
1358 case INDEX_op_jmp:
1359 if (const_args[0])
1360 tcg_out_goto(s, COND_AL, args[0]);
1361 else
1362 tcg_out_bx(s, COND_AL, args[0]);
1363 break;
1364 case INDEX_op_br:
1365 tcg_out_goto_label(s, COND_AL, args[0]);
1366 break;
1367
1368 case INDEX_op_ld8u_i32:
1369 tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]);
1370 break;
1371 case INDEX_op_ld8s_i32:
1372 tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]);
1373 break;
1374 case INDEX_op_ld16u_i32:
1375 tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]);
1376 break;
1377 case INDEX_op_ld16s_i32:
1378 tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]);
1379 break;
1380 case INDEX_op_ld_i32:
1381 tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]);
1382 break;
1383 case INDEX_op_st8_i32:
f694a27e 1384 tcg_out_st8(s, COND_AL, args[0], args[1], args[2]);
811d4cf4
AZ		 1385 break;
1386 case INDEX_op_st16_i32:
f694a27e 1387 tcg_out_st16(s, COND_AL, args[0], args[1], args[2]);
811d4cf4
AZ		 1388 break;
1389 case INDEX_op_st_i32:
1390 tcg_out_st32(s, COND_AL, args[0], args[1], args[2]);
1391 break;
1392
1393 case INDEX_op_mov_i32:
1394 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1395 args[0], 0, args[1], SHIFT_IMM_LSL(0));
1396 break;
1397 case INDEX_op_movi_i32:
1398 tcg_out_movi32(s, COND_AL, args[0], args[1]);
1399 break;
1400 case INDEX_op_add_i32:
1401 c = ARITH_ADD;
1402 goto gen_arith;
1403 case INDEX_op_sub_i32:
1404 c = ARITH_SUB;
1405 goto gen_arith;
1406 case INDEX_op_and_i32:
1407 c = ARITH_AND;
1408 goto gen_arith;
932234f6
AJ		 1409 case INDEX_op_andc_i32:
1410 c = ARITH_BIC;
1411 goto gen_arith;
811d4cf4
AZ		 1412 case INDEX_op_or_i32:
1413 c = ARITH_ORR;
1414 goto gen_arith;
1415 case INDEX_op_xor_i32:
1416 c = ARITH_EOR;
1417 /* Fall through. */
1418 gen_arith:
94953e6d
LD		 1419 if (const_args[2]) {
1420 int rot;
1421 rot = encode_imm(args[2]);
cb4e581f 1422 tcg_out_dat_imm(s, COND_AL, c,
94953e6d
LD		 1423 args[0], args[1], rotl(args[2], rot) | (rot << 7));
1424 } else
cb4e581f
LD		 1425 tcg_out_dat_reg(s, COND_AL, c,
1426 args[0], args[1], args[2], SHIFT_IMM_LSL(0));
811d4cf4
AZ		 1427 break;
1428 case INDEX_op_add2_i32:
1429 tcg_out_dat_reg2(s, COND_AL, ARITH_ADD, ARITH_ADC,
1430 args[0], args[1], args[2], args[3],
1431 args[4], args[5], SHIFT_IMM_LSL(0));
1432 break;
1433 case INDEX_op_sub2_i32:
1434 tcg_out_dat_reg2(s, COND_AL, ARITH_SUB, ARITH_SBC,
1435 args[0], args[1], args[2], args[3],
1436 args[4], args[5], SHIFT_IMM_LSL(0));
1437 break;
650bbb36
AZ		 1438 case INDEX_op_neg_i32:
1439 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0);
1440 break;
f878d2d2
LD		 1441 case INDEX_op_not_i32:
1442 tcg_out_dat_reg(s, COND_AL,
1443 ARITH_MVN, args[0], 0, args[1], SHIFT_IMM_LSL(0));
1444 break;
811d4cf4
AZ		 1445 case INDEX_op_mul_i32:
1446 tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]);
1447 break;
1448 case INDEX_op_mulu2_i32:
1449 tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]);
1450 break;
811d4cf4
AZ		 1451 /* XXX: Perhaps args[2] & 0x1f is wrong */
1452 case INDEX_op_shl_i32:
1453 c = const_args[2] ?
1454 SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]);
1455 goto gen_shift32;
1456 case INDEX_op_shr_i32:
1457 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) :
1458 SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]);
1459 goto gen_shift32;
1460 case INDEX_op_sar_i32:
1461 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) :
1462 SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]);
293579e5
AJ		 1463 goto gen_shift32;
1464 case INDEX_op_rotr_i32:
1465 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ROR(args[2] & 0x1f) :
1466 SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args[2]);
811d4cf4
AZ		 1467 /* Fall through. */
1468 gen_shift32:
1469 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c);
1470 break;
1471
293579e5
AJ		 1472 case INDEX_op_rotl_i32:
1473 if (const_args[2]) {
1474 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1],
1475 ((0x20 - args[2]) & 0x1f) ?
1476 SHIFT_IMM_ROR((0x20 - args[2]) & 0x1f) :
1477 SHIFT_IMM_LSL(0));
1478 } else {
1479 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_R8, args[1], 0x20);
1480 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1],
1481 SHIFT_REG_ROR(TCG_REG_R8));
1482 }
1483 break;
1484
811d4cf4 1485 case INDEX_op_brcond_i32:
023e77f8
AJ		 1486 if (const_args[1]) {
1487 int rot;
1488 rot = encode_imm(args[1]);
c8d80cef
AJ		 1489 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0,
1490 args[0], rotl(args[1], rot) | (rot << 7));
023e77f8
AJ		 1491 } else {
1492 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1493 args[0], args[1], SHIFT_IMM_LSL(0));
1494 }
811d4cf4
AZ		 1495 tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], args[3]);
1496 break;
1497 case INDEX_op_brcond2_i32:
1498 /* The resulting conditions are:
1499 * TCG_COND_EQ --> a0 == a2 && a1 == a3,
1500 * TCG_COND_NE --> (a0 != a2 && a1 == a3) || a1 != a3,
1501 * TCG_COND_LT(U) --> (a0 < a2 && a1 == a3) || a1 < a3,
1502 * TCG_COND_GE(U) --> (a0 >= a2 && a1 == a3) || (a1 >= a3 && a1 != a3),
1503 * TCG_COND_LE(U) --> (a0 <= a2 && a1 == a3) || (a1 <= a3 && a1 != a3),
1504 * TCG_COND_GT(U) --> (a0 > a2 && a1 == a3) || a1 > a3,
1505 */
1506 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1507 args[1], args[3], SHIFT_IMM_LSL(0));
1508 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1509 args[0], args[2], SHIFT_IMM_LSL(0));
1510 tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[4]], args[5]);
1511 break;
f72a6cd7 1512 case INDEX_op_setcond_i32:
023e77f8
AJ		 1513 if (const_args[2]) {
1514 int rot;
1515 rot = encode_imm(args[2]);
c8d80cef
AJ		 1516 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0,
1517 args[1], rotl(args[2], rot) | (rot << 7));
023e77f8
AJ		 1518 } else {
1519 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1520 args[1], args[2], SHIFT_IMM_LSL(0));
1521 }
f72a6cd7
AJ		 1522 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]],
1523 ARITH_MOV, args[0], 0, 1);
1524 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])],
1525 ARITH_MOV, args[0], 0, 0);
1526 break;
e0404769
AJ		 1527 case INDEX_op_setcond2_i32:
1528 /* See brcond2_i32 comment */
1529 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1530 args[2], args[4], SHIFT_IMM_LSL(0));
1531 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1532 args[1], args[3], SHIFT_IMM_LSL(0));
1533 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[5]],
1534 ARITH_MOV, args[0], 0, 1);
1535 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[5])],
1536 ARITH_MOV, args[0], 0, 0);
b525f0a9 1537 break;
811d4cf4
AZ		 1538
1539 case INDEX_op_qemu_ld8u:
7e0d9562 1540 tcg_out_qemu_ld(s, args, 0);
811d4cf4
AZ		 1541 break;
1542 case INDEX_op_qemu_ld8s:
7e0d9562 1543 tcg_out_qemu_ld(s, args, 0 | 4);
811d4cf4
AZ		 1544 break;
1545 case INDEX_op_qemu_ld16u:
7e0d9562 1546 tcg_out_qemu_ld(s, args, 1);
811d4cf4
AZ		 1547 break;
1548 case INDEX_op_qemu_ld16s:
7e0d9562 1549 tcg_out_qemu_ld(s, args, 1 | 4);
811d4cf4 1550 break;
86feb1c8 1551 case INDEX_op_qemu_ld32:
7e0d9562 1552 tcg_out_qemu_ld(s, args, 2);
811d4cf4
AZ		 1553 break;
1554 case INDEX_op_qemu_ld64:
7e0d9562 1555 tcg_out_qemu_ld(s, args, 3);
811d4cf4 1556 break;
650bbb36 1557
811d4cf4 1558 case INDEX_op_qemu_st8:
7e0d9562 1559 tcg_out_qemu_st(s, args, 0);
811d4cf4
AZ		 1560 break;
1561 case INDEX_op_qemu_st16:
7e0d9562 1562 tcg_out_qemu_st(s, args, 1);
811d4cf4
AZ		 1563 break;
1564 case INDEX_op_qemu_st32:
7e0d9562 1565 tcg_out_qemu_st(s, args, 2);
811d4cf4
AZ		 1566 break;
1567 case INDEX_op_qemu_st64:
7e0d9562 1568 tcg_out_qemu_st(s, args, 3);
811d4cf4
AZ		 1569 break;
1570
244b1e81
AJ		 1571 case INDEX_op_bswap16_i32:
1572 tcg_out_bswap16(s, COND_AL, args[0], args[1]);
1573 break;
1574 case INDEX_op_bswap32_i32:
1575 tcg_out_bswap32(s, COND_AL, args[0], args[1]);
1576 break;
1577
811d4cf4 1578 case INDEX_op_ext8s_i32:
9517094f 1579 tcg_out_ext8s(s, COND_AL, args[0], args[1]);
811d4cf4
AZ		 1580 break;
1581 case INDEX_op_ext16s_i32:
9517094f
AJ		 1582 tcg_out_ext16s(s, COND_AL, args[0], args[1]);
1583 break;
1584 case INDEX_op_ext16u_i32:
1585 tcg_out_ext16u(s, COND_AL, args[0], args[1]);
811d4cf4
AZ		 1586 break;
1587
1588 default:
1589 tcg_abort();
1590 }
1591}
1592
1593static const TCGTargetOpDef arm_op_defs[] = {
1594 { INDEX_op_exit_tb, { } },
1595 { INDEX_op_goto_tb, { } },
1596 { INDEX_op_call, { "ri" } },
1597 { INDEX_op_jmp, { "ri" } },
1598 { INDEX_op_br, { } },
1599
1600 { INDEX_op_mov_i32, { "r", "r" } },
1601 { INDEX_op_movi_i32, { "r" } },
1602
1603 { INDEX_op_ld8u_i32, { "r", "r" } },
1604 { INDEX_op_ld8s_i32, { "r", "r" } },
1605 { INDEX_op_ld16u_i32, { "r", "r" } },
1606 { INDEX_op_ld16s_i32, { "r", "r" } },
1607 { INDEX_op_ld_i32, { "r", "r" } },
1608 { INDEX_op_st8_i32, { "r", "r" } },
1609 { INDEX_op_st16_i32, { "r", "r" } },
1610 { INDEX_op_st_i32, { "r", "r" } },
1611
1612 /* TODO: "r", "r", "ri" */
cb4e581f
LD		 1613 { INDEX_op_add_i32, { "r", "r", "rI" } },
1614 { INDEX_op_sub_i32, { "r", "r", "rI" } },
811d4cf4
AZ		 1615 { INDEX_op_mul_i32, { "r", "r", "r" } },
1616 { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
cb4e581f 1617 { INDEX_op_and_i32, { "r", "r", "rI" } },
932234f6 1618 { INDEX_op_andc_i32, { "r", "r", "rI" } },
cb4e581f
LD		 1619 { INDEX_op_or_i32, { "r", "r", "rI" } },
1620 { INDEX_op_xor_i32, { "r", "r", "rI" } },
650bbb36 1621 { INDEX_op_neg_i32, { "r", "r" } },
f878d2d2 1622 { INDEX_op_not_i32, { "r", "r" } },
811d4cf4
AZ		 1623
1624 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1625 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1626 { INDEX_op_sar_i32, { "r", "r", "ri" } },
293579e5
AJ		 1627 { INDEX_op_rotl_i32, { "r", "r", "ri" } },
1628 { INDEX_op_rotr_i32, { "r", "r", "ri" } },
811d4cf4 1629
023e77f8
AJ		 1630 { INDEX_op_brcond_i32, { "r", "rI" } },
1631 { INDEX_op_setcond_i32, { "r", "r", "rI" } },
811d4cf4
AZ		 1632
1633 /* TODO: "r", "r", "r", "r", "ri", "ri" */
1634 { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1635 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1636 { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
e0404769 1637 { INDEX_op_setcond2_i32, { "r", "r", "r", "r", "r" } },
811d4cf4 1638
26c5d372
AJ		 1639#if TARGET_LONG_BITS == 32
1640 { INDEX_op_qemu_ld8u, { "r", "x" } },
1641 { INDEX_op_qemu_ld8s, { "r", "x" } },
1642 { INDEX_op_qemu_ld16u, { "r", "x" } },
1643 { INDEX_op_qemu_ld16s, { "r", "x" } },
1584c845 1644 { INDEX_op_qemu_ld32, { "r", "x" } },
26c5d372
AJ		 1645 { INDEX_op_qemu_ld64, { "d", "r", "x" } },
1646
1647 { INDEX_op_qemu_st8, { "x", "x" } },
1648 { INDEX_op_qemu_st16, { "x", "x" } },
1649 { INDEX_op_qemu_st32, { "x", "x" } },
1650 { INDEX_op_qemu_st64, { "x", "D", "x" } },
1651#else
811d4cf4
AZ		 1652 { INDEX_op_qemu_ld8u, { "r", "x", "X" } },
1653 { INDEX_op_qemu_ld8s, { "r", "x", "X" } },
1654 { INDEX_op_qemu_ld16u, { "r", "x", "X" } },
1655 { INDEX_op_qemu_ld16s, { "r", "x", "X" } },
86feb1c8 1656 { INDEX_op_qemu_ld32, { "r", "x", "X" } },
d0660ed4 1657 { INDEX_op_qemu_ld64, { "d", "r", "x", "X" } },
811d4cf4 1658
3979144c
PB		 1659 { INDEX_op_qemu_st8, { "x", "x", "X" } },
1660 { INDEX_op_qemu_st16, { "x", "x", "X" } },
1661 { INDEX_op_qemu_st32, { "x", "x", "X" } },
1662 { INDEX_op_qemu_st64, { "x", "D", "x", "X" } },
26c5d372 1663#endif
811d4cf4 1664
244b1e81
AJ		 1665 { INDEX_op_bswap16_i32, { "r", "r" } },
1666 { INDEX_op_bswap32_i32, { "r", "r" } },
1667
811d4cf4
AZ		 1668 { INDEX_op_ext8s_i32, { "r", "r" } },
1669 { INDEX_op_ext16s_i32, { "r", "r" } },
9517094f 1670 { INDEX_op_ext16u_i32, { "r", "r" } },
811d4cf4
AZ		 1671
1672 { -1 },
1673};
1674
1675void tcg_target_init(TCGContext *s)
1676{
20cb400d 1677#if !defined(CONFIG_USER_ONLY)
811d4cf4
AZ		 1678 /* fail safe */
1679 if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1680 tcg_abort();
20cb400d 1681#endif
811d4cf4 1682
e4a7d5e8 1683 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
811d4cf4 1684 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
e4a7d5e8
AJ		 1685 (1 << TCG_REG_R0) |
1686 (1 << TCG_REG_R1) |
1687 (1 << TCG_REG_R2) |
1688 (1 << TCG_REG_R3) |
1689 (1 << TCG_REG_R12) |
1690 (1 << TCG_REG_R14));
811d4cf4
AZ		 1691
1692 tcg_regset_clear(s->reserved_regs);
811d4cf4
AZ		 1693 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
1694 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R8);
e4a7d5e8 1695 tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC);
811d4cf4
AZ		 1696
1697 tcg_add_target_add_op_defs(arm_op_defs);
1698}
1699
1700static inline void tcg_out_ld(TCGContext *s, TCGType type, int arg,
1701 int arg1, tcg_target_long arg2)
1702{
1703 tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
1704}
1705
1706static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
1707 int arg1, tcg_target_long arg2)
1708{
1709 tcg_out_st32(s, COND_AL, arg, arg1, arg2);
1710}
1711
2d69f359 1712static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
811d4cf4
AZ		 1713{
1714 if (val > 0)
1715 if (val < 0x100)
1716 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, reg, reg, val);
1717 else
1718 tcg_abort();
1719 else if (val < 0) {
1720 if (val > -0x100)
1721 tcg_out_dat_imm(s, COND_AL, ARITH_SUB, reg, reg, -val);
1722 else
1723 tcg_abort();
1724 }
1725}
1726
1727static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
1728{
1729 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, ret, 0, arg, SHIFT_IMM_LSL(0));
1730}
1731
1732static inline void tcg_out_movi(TCGContext *s, TCGType type,
1733 int ret, tcg_target_long arg)
1734{
1735 tcg_out_movi32(s, COND_AL, ret, arg);
1736}
1737
1738void tcg_target_qemu_prologue(TCGContext *s)
1739{
9e97d8e9
AJ		 1740 /* There is no need to save r7, it is used to store the address
1741 of the env structure and is not modified by GCC. */
4e17eae9 1742
9e97d8e9
AJ		 1743 /* stmdb sp!, { r4 - r6, r8 - r11, lr } */
1744 tcg_out32(s, (COND_AL << 28) | 0x092d4f70);
811d4cf4
AZ		 1745
1746 tcg_out_bx(s, COND_AL, TCG_REG_R0);
1747 tb_ret_addr = s->code_ptr;
1748
9e97d8e9
AJ		 1749 /* ldmia sp!, { r4 - r6, r8 - r11, pc } */
1750 tcg_out32(s, (COND_AL << 28) | 0x08bd8f70);
811d4cf4 1751}
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