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Clean up MMIO TLB handling.
[mirror_qemu.git] / tcg / ppc / tcg-target.c
CommitLineData
2662e13f
FB		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25static uint8_t *tb_ret_addr;
26
2662e13f
FB		 27#define FAST_PATH
28#if TARGET_PHYS_ADDR_BITS <= 32
29#define ADDEND_OFFSET 0
30#else
31#define ADDEND_OFFSET 4
32#endif
33
34static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
35 "r0",
36 "r1",
37 "rp",
38 "r3",
39 "r4",
40 "r5",
41 "r6",
42 "r7",
43 "r8",
44 "r9",
45 "r10",
46 "r11",
47 "r12",
48 "r13",
49 "r14",
50 "r15",
51 "r16",
52 "r17",
53 "r18",
54 "r19",
55 "r20",
56 "r21",
57 "r22",
58 "r23",
59 "r24",
60 "r25",
61 "r26",
62 "r27",
63 "r28",
64 "r29",
65 "r30",
66 "r31"
67};
68
69static const int tcg_target_reg_alloc_order[] = {
70 TCG_REG_R0,
71 TCG_REG_R1,
72 TCG_REG_R2,
73 TCG_REG_R3,
74 TCG_REG_R4,
75 TCG_REG_R5,
76 TCG_REG_R6,
77 TCG_REG_R7,
78 TCG_REG_R8,
79 TCG_REG_R9,
80 TCG_REG_R10,
81 TCG_REG_R11,
82 TCG_REG_R12,
83 TCG_REG_R13,
84 TCG_REG_R14,
85 TCG_REG_R15,
86 TCG_REG_R16,
87 TCG_REG_R17,
88 TCG_REG_R18,
89 TCG_REG_R19,
90 TCG_REG_R20,
91 TCG_REG_R21,
92 TCG_REG_R22,
93 TCG_REG_R23,
94 TCG_REG_R24,
95 TCG_REG_R25,
96 TCG_REG_R26,
97 TCG_REG_R27,
98 TCG_REG_R28,
99 TCG_REG_R29,
100 TCG_REG_R30,
101 TCG_REG_R31
102};
103
104static const int tcg_target_call_iarg_regs[] = {
105 TCG_REG_R3,
106 TCG_REG_R4,
107 TCG_REG_R5,
108 TCG_REG_R6,
109 TCG_REG_R7,
110 TCG_REG_R8,
111 TCG_REG_R9,
112 TCG_REG_R10
113};
114
115static const int tcg_target_call_oarg_regs[2] = {
116 TCG_REG_R3,
117 TCG_REG_R4
118};
119
120static const int tcg_target_callee_save_regs[] = {
121 TCG_REG_R13, /* sould r13 be saved? */
122 TCG_REG_R14,
123 TCG_REG_R15,
124 TCG_REG_R16,
125 TCG_REG_R17,
126 TCG_REG_R18,
127 TCG_REG_R19,
128 TCG_REG_R20,
129 TCG_REG_R21,
130 TCG_REG_R22,
131 TCG_REG_R23,
132 TCG_REG_R28,
133 TCG_REG_R29,
134 TCG_REG_R30,
135 TCG_REG_R31
136};
137
138static uint32_t reloc_pc24_val (void *pc, tcg_target_long target)
139{
932a6909
FB		 140 tcg_target_long disp;
141
142 disp = target - (tcg_target_long) pc;
143 if ((disp << 6) >> 6 != disp)
144 tcg_abort ();
145
146 return disp & 0x3fffffc;
2662e13f
FB		 147}
148
149static void reloc_pc24 (void *pc, tcg_target_long target)
150{
151 *(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
152 | reloc_pc24_val (pc, target);
153}
154
155static uint16_t reloc_pc14_val (void *pc, tcg_target_long target)
156{
932a6909
FB		 157 tcg_target_long disp;
158
159 disp = target - (tcg_target_long) pc;
160 if (disp != (int16_t) disp)
161 tcg_abort ();
162
163 return disp & 0xfffc;
2662e13f
FB		 164}
165
166static void reloc_pc14 (void *pc, tcg_target_long target)
167{
168 *(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)
169 | reloc_pc14_val (pc, target);
170}
171
172static void patch_reloc(uint8_t *code_ptr, int type,
173 tcg_target_long value, tcg_target_long addend)
174{
175 value += addend;
176 switch (type) {
177 case R_PPC_REL14:
178 reloc_pc14 (code_ptr, value);
179 break;
180 case R_PPC_REL24:
181 reloc_pc24 (code_ptr, value);
182 break;
183 default:
184 tcg_abort();
185 }
186}
187
188/* maximum number of register used for input function arguments */
189static int tcg_target_get_call_iarg_regs_count(int flags)
190{
191 return sizeof (tcg_target_call_iarg_regs) / sizeof (tcg_target_call_iarg_regs[0]);
192}
193
194/* parse target specific constraints */
195static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
196{
197 const char *ct_str;
198
199 ct_str = *pct_str;
200 switch (ct_str[0]) {
201 case 'r':
202 ct->ct |= TCG_CT_REG;
203 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
204 break;
205 case 'L': /* qemu_ld constraint */
206 ct->ct |= TCG_CT_REG;
207 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
208 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
209 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
210 break;
211 case 'K': /* qemu_st[8..32] constraint */
212 ct->ct |= TCG_CT_REG;
213 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
214 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
215 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
216 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
217#if TARGET_LONG_BITS == 64
218 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
219#endif
220 break;
221 case 'M': /* qemu_st64 constraint */
222 ct->ct |= TCG_CT_REG;
223 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
224 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
225 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
226 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
227 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
228 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
229 break;
2662e13f
FB		 230 default:
231 return -1;
232 }
233 ct_str++;
234 *pct_str = ct_str;
235 return 0;
236}
237
238/* test if a constant matches the constraint */
239static int tcg_target_const_match(tcg_target_long val,
240 const TCGArgConstraint *arg_ct)
241{
242 int ct;
243
244 ct = arg_ct->ct;
245 if (ct & TCG_CT_CONST)
246 return 1;
2662e13f
FB		 247 return 0;
248}
249
250#define OPCD(opc) ((opc)<<26)
251#define XO31(opc) (OPCD(31)|((opc)<<1))
252#define XO19(opc) (OPCD(19)|((opc)<<1))
253
254#define B OPCD(18)
255#define BC OPCD(16)
256#define LBZ OPCD(34)
257#define LHZ OPCD(40)
258#define LHA OPCD(42)
259#define LWZ OPCD(32)
260#define STB OPCD(38)
261#define STH OPCD(44)
262#define STW OPCD(36)
263
264#define ADDI OPCD(14)
265#define ADDIS OPCD(15)
266#define ORI OPCD(24)
267#define ORIS OPCD(25)
268#define XORI OPCD(26)
269#define XORIS OPCD(27)
270#define ANDI OPCD(28)
271#define ANDIS OPCD(29)
272#define MULLI OPCD( 7)
273#define CMPLI OPCD(10)
274#define CMPI OPCD(11)
275
276#define LWZU OPCD(33)
277#define STWU OPCD(37)
278
279#define RLWINM OPCD(21)
280
281#define BCLR XO19(16)
282#define BCCTR XO19(528)
283#define CRAND XO19(257)
284
285#define EXTSB XO31(954)
286#define EXTSH XO31(922)
287#define ADD XO31(266)
288#define ADDE XO31(138)
289#define ADDC XO31( 10)
290#define AND XO31( 28)
291#define SUBF XO31( 40)
292#define SUBFC XO31( 8)
293#define SUBFE XO31(136)
294#define OR XO31(444)
295#define XOR XO31(316)
296#define MULLW XO31(235)
297#define MULHWU XO31( 11)
298#define DIVW XO31(491)
299#define DIVWU XO31(459)
300#define CMP XO31( 0)
301#define CMPL XO31( 32)
302#define LHBRX XO31(790)
303#define LWBRX XO31(534)
304#define STHBRX XO31(918)
305#define STWBRX XO31(662)
306#define MFSPR XO31(339)
307#define MTSPR XO31(467)
308#define SRAWI XO31(824)
309#define NEG XO31(104)
310
311#define LBZX XO31( 87)
312#define LHZX XO31(276)
313#define LHAX XO31(343)
314#define LWZX XO31( 23)
315#define STBX XO31(215)
316#define STHX XO31(407)
317#define STWX XO31(151)
318
319#define SPR(a,b) ((((a)<<5)|(b))<<11)
320#define LR SPR(8, 0)
321#define CTR SPR(9, 0)
322
323#define SLW XO31( 24)
324#define SRW XO31(536)
325#define SRAW XO31(792)
326
327#define LMW OPCD(46)
328#define STMW OPCD(47)
329
330#define TW XO31(4)
331#define TRAP (TW | TO (31))
332
333#define RT(r) ((r)<<21)
334#define RS(r) ((r)<<21)
335#define RA(r) ((r)<<16)
336#define RB(r) ((r)<<11)
337#define TO(t) ((t)<<21)
338#define SH(s) ((s)<<11)
339#define MB(b) ((b)<<6)
340#define ME(e) ((e)<<1)
341#define BO(o) ((o)<<21)
342
343#define LK 1
344
345#define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
346#define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
347
348#define BF(n) ((n)<<23)
349#define BI(n, c) (((c)+((n)*4))<<16)
350#define BT(n, c) (((c)+((n)*4))<<21)
351#define BA(n, c) (((c)+((n)*4))<<16)
352#define BB(n, c) (((c)+((n)*4))<<11)
353
354#define BO_COND_TRUE BO (12)
355#define BO_COND_FALSE BO (4)
356#define BO_ALWAYS BO (20)
357
358enum {
359 CR_LT,
360 CR_GT,
361 CR_EQ,
362 CR_SO
363};
364
365static const uint32_t tcg_to_bc[10] = {
366 [TCG_COND_EQ] = BC | BI (7, CR_EQ) | BO_COND_TRUE,
367 [TCG_COND_NE] = BC | BI (7, CR_EQ) | BO_COND_FALSE,
368 [TCG_COND_LT] = BC | BI (7, CR_LT) | BO_COND_TRUE,
369 [TCG_COND_GE] = BC | BI (7, CR_LT) | BO_COND_FALSE,
370 [TCG_COND_LE] = BC | BI (7, CR_GT) | BO_COND_FALSE,
371 [TCG_COND_GT] = BC | BI (7, CR_GT) | BO_COND_TRUE,
372 [TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,
373 [TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,
374 [TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,
375 [TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
376};
377
378static void tcg_out_mov(TCGContext *s, int ret, int arg)
379{
380 tcg_out32 (s, OR | SAB (arg, ret, arg));
381}
382
383static void tcg_out_movi(TCGContext *s, TCGType type,
384 int ret, tcg_target_long arg)
385{
386 if (arg == (int16_t) arg)
387 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
388 else {
389 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
390 if (arg & 0xffff)
0a878c47 391 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
2662e13f
FB		 392 }
393}
394
395static void tcg_out_ldst (TCGContext *s, int ret, int addr,
396 int offset, int op1, int op2)
397{
398 if (offset == (int16_t) offset)
399 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
400 else {
401 tcg_out_movi (s, TCG_TYPE_I32, 0, offset);
402 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
403 }
404}
405
932a6909
FB		 406static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target)
407{
408 tcg_target_long disp;
409
410 disp = target - (tcg_target_long) s->code_ptr;
411 if ((disp << 6) >> 6 == disp)
412 tcg_out32 (s, B | disp | mask);
413 else {
414 tcg_out_movi (s, TCG_TYPE_I32, 0, (tcg_target_long) target);
415 tcg_out32 (s, MTSPR | RS (0) | CTR);
416 tcg_out32 (s, BCCTR | BO_ALWAYS | mask);
417 }
418}
419
2662e13f
FB		 420#if defined(CONFIG_SOFTMMU)
421extern void __ldb_mmu(void);
422extern void __ldw_mmu(void);
423extern void __ldl_mmu(void);
424extern void __ldq_mmu(void);
425
426extern void __stb_mmu(void);
427extern void __stw_mmu(void);
428extern void __stl_mmu(void);
429extern void __stq_mmu(void);
430
431static void *qemu_ld_helpers[4] = {
432 __ldb_mmu,
433 __ldw_mmu,
434 __ldl_mmu,
435 __ldq_mmu,
436};
437
438static void *qemu_st_helpers[4] = {
439 __stb_mmu,
440 __stw_mmu,
441 __stl_mmu,
442 __stq_mmu,
443};
444#endif
445
446static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
447{
448 int addr_reg, data_reg, data_reg2, r0, mem_index, s_bits, bswap;
449#ifdef CONFIG_SOFTMMU
450 int r1, r2;
451 void *label1_ptr, *label2_ptr;
452#endif
453#if TARGET_LONG_BITS == 64
454 int addr_reg2;
455#endif
456
457 data_reg = *args++;
458 if (opc == 3)
459 data_reg2 = *args++;
460 else
461 data_reg2 = 0;
462 addr_reg = *args++;
463#if TARGET_LONG_BITS == 64
464 addr_reg2 = *args++;
465#endif
466 mem_index = *args;
467 s_bits = opc & 3;
468
469#ifdef CONFIG_SOFTMMU
470 r0 = 3;
471 r1 = 4;
472 r2 = 0;
473
474 tcg_out32 (s, (RLWINM
475 | RA (r0)
476 | RS (addr_reg)
477 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
478 | MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
479 | ME (31 - CPU_TLB_ENTRY_BITS)
480 )
481 );
482 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
483 tcg_out32 (s, (LWZU
484 | RT (r1)
485 | RA (r0)
486 | offsetof (CPUState, tlb_table[mem_index][0].addr_read)
487 )
488 );
489 tcg_out32 (s, (RLWINM
490 | RA (r2)
491 | RS (addr_reg)
492 | SH (0)
493 | MB ((32 - s_bits) & 31)
494 | ME (31 - TARGET_PAGE_BITS)
495 )
496 );
497
498 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1));
499#if TARGET_LONG_BITS == 64
500 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
501 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
502 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
503#endif
504
505 label1_ptr = s->code_ptr;
506#ifdef FAST_PATH
507 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
508#endif
509
510 /* slow path */
511#if TARGET_LONG_BITS == 32
512 tcg_out_mov (s, 3, addr_reg);
513 tcg_out_movi (s, TCG_TYPE_I32, 4, mem_index);
514#else
515 tcg_out_mov (s, 3, addr_reg2);
516 tcg_out_mov (s, 4, addr_reg);
517 tcg_out_movi (s, TCG_TYPE_I32, 5, mem_index);
518#endif
519
932a6909 520 tcg_out_b (s, LK, (tcg_target_long) qemu_ld_helpers[s_bits]);
2662e13f
FB		 521 switch (opc) {
522 case 0|4:
523 tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
524 break;
525 case 1|4:
526 tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
527 break;
528 case 0:
529 case 1:
530 case 2:
531 if (data_reg != 3)
532 tcg_out_mov (s, data_reg, 3);
533 break;
534 case 3:
535 if (data_reg == 3) {
536 if (data_reg2 == 4) {
537 tcg_out_mov (s, 0, 4);
538 tcg_out_mov (s, 4, 3);
539 tcg_out_mov (s, 3, 0);
540 }
541 else {
542 tcg_out_mov (s, data_reg2, 3);
543 tcg_out_mov (s, 3, 4);
544 }
545 }
546 else {
547 if (data_reg != 4) tcg_out_mov (s, data_reg, 4);
548 if (data_reg2 != 3) tcg_out_mov (s, data_reg2, 3);
549 }
550 break;
551 }
552 label2_ptr = s->code_ptr;
553 tcg_out32 (s, B);
554
555 /* label1: fast path */
556#ifdef FAST_PATH
557 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
558#endif
559
560 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
561 tcg_out32 (s, (LWZ
562 | RT (r0)
563 | RA (r0)
564 | (ADDEND_OFFSET + offsetof (CPUTLBEntry, addend)
565 - offsetof (CPUTLBEntry, addr_read))
566 ));
567 /* r0 = env->tlb_table[mem_index][index].addend */
568 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
569 /* r0 = env->tlb_table[mem_index][index].addend + addr */
570
571#else /* !CONFIG_SOFTMMU */
572 r0 = addr_reg;
573#endif
574
575#ifdef TARGET_WORDS_BIGENDIAN
576 bswap = 0;
577#else
578 bswap = 1;
579#endif
580 switch (opc) {
581 default:
582 case 0:
583 tcg_out32 (s, LBZ | RT (data_reg) | RA (r0));
584 break;
585 case 0|4:
586 tcg_out32 (s, LBZ | RT (data_reg) | RA (r0));
587 tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg));
588 break;
589 case 1:
590 if (bswap) tcg_out32 (s, LHBRX | RT (data_reg) | RB (r0));
591 else tcg_out32 (s, LHZ | RT (data_reg) | RA (r0));
592 break;
593 case 1|4:
594 if (bswap) {
595 tcg_out32 (s, LHBRX | RT (data_reg) | RB (r0));
596 tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg));
597 }
598 else tcg_out32 (s, LHA | RT (data_reg) | RA (r0));
599 break;
600 case 2:
601 if (bswap) tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
602 else tcg_out32 (s, LWZ | RT (data_reg)| RA (r0));
603 break;
604 case 3:
605 if (bswap) {
606 if (r0 == data_reg) {
607 tcg_out32 (s, LWBRX | RT (0) | RB (r0));
608 tcg_out32 (s, ADDI | RT (r0) | RA (r0) | 4);
609 tcg_out32 (s, LWBRX | RT (data_reg2) | RB (r0));
610 tcg_out_mov (s, data_reg, 0);
611 }
612 else {
613 tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
614 tcg_out32 (s, ADDI | RT (r0) | RA (r0) | 4);
615 tcg_out32 (s, LWBRX | RT (data_reg2) | RB (r0));
616 }
617 }
618 else {
619 if (r0 == data_reg2) {
620 tcg_out32 (s, LWZ | RT (0) | RA (r0));
621 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
622 tcg_out_mov (s, data_reg2, 0);
623 }
624 else {
625 tcg_out32 (s, LWZ | RT (data_reg2) | RA (r0));
626 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
627 }
628 }
629 break;
630 }
631
632#ifdef CONFIG_SOFTMMU
633 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
634#endif
635}
636
637static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
638{
639 int addr_reg, r0, r1, data_reg, data_reg2, mem_index, bswap;
640#ifdef CONFIG_SOFTMMU
641 int r2, ir;
642 void *label1_ptr, *label2_ptr;
643#endif
644#if TARGET_LONG_BITS == 64
645 int addr_reg2;
646#endif
647
648 data_reg = *args++;
649 if (opc == 3)
650 data_reg2 = *args++;
651 else
652 data_reg2 = 0;
653 addr_reg = *args++;
654#if TARGET_LONG_BITS == 64
655 addr_reg2 = *args++;
656#endif
657 mem_index = *args;
658
659#ifdef CONFIG_SOFTMMU
660 r0 = 3;
661 r1 = 4;
662 r2 = 0;
663
664 tcg_out32 (s, (RLWINM
665 | RA (r0)
666 | RS (addr_reg)
667 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
668 | MB (32 - (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS))
669 | ME (31 - CPU_TLB_ENTRY_BITS)
670 )
671 );
672 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
673 tcg_out32 (s, (LWZU
674 | RT (r1)
675 | RA (r0)
676 | offsetof (CPUState, tlb_table[mem_index][0].addr_write)
677 )
678 );
679 tcg_out32 (s, (RLWINM
680 | RA (r2)
681 | RS (addr_reg)
682 | SH (0)
683 | MB ((32 - opc) & 31)
684 | ME (31 - TARGET_PAGE_BITS)
685 )
686 );
687
688 tcg_out32 (s, CMP | (7 << 23) | RA (r2) | RB (r1));
689#if TARGET_LONG_BITS == 64
690 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
691 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
692 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
693#endif
694
695 label1_ptr = s->code_ptr;
696#ifdef FAST_PATH
697 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
698#endif
699
700 /* slow path */
701#if TARGET_LONG_BITS == 32
702 tcg_out_mov (s, 3, addr_reg);
703 ir = 4;
704#else
705 tcg_out_mov (s, 3, addr_reg2);
706 tcg_out_mov (s, 4, addr_reg);
707 ir = 5;
708#endif
709
710 switch (opc) {
711 case 0:
712 tcg_out32 (s, (RLWINM
713 | RA (ir)
714 | RS (data_reg)
715 | SH (0)
716 | MB (24)
717 | ME (31)));
718 break;
719 case 1:
720 tcg_out32 (s, (RLWINM
721 | RA (ir)
722 | RS (data_reg)
723 | SH (0)
724 | MB (16)
725 | ME (31)));
726 break;
727 case 2:
728 tcg_out_mov (s, ir, data_reg);
729 break;
730 case 3:
731 tcg_out_mov (s, 5, data_reg2);
732 tcg_out_mov (s, 6, data_reg);
733 ir = 6;
734 break;
735 }
736 ir++;
737
738 tcg_out_movi (s, TCG_TYPE_I32, ir, mem_index);
932a6909 739 tcg_out_b (s, LK, (tcg_target_long) qemu_st_helpers[opc]);
2662e13f
FB		 740 label2_ptr = s->code_ptr;
741 tcg_out32 (s, B);
742
743 /* label1: fast path */
744#ifdef FAST_PATH
745 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
746#endif
747
748 tcg_out32 (s, (LWZ
749 | RT (r0)
750 | RA (r0)
751 | (ADDEND_OFFSET + offsetof (CPUTLBEntry, addend)
752 - offsetof (CPUTLBEntry, addr_write))
753 ));
754 /* r0 = env->tlb_table[mem_index][index].addend */
755 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
756 /* r0 = env->tlb_table[mem_index][index].addend + addr */
757
758#else /* !CONFIG_SOFTMMU */
759 r1 = 4;
760 r0 = addr_reg;
761#endif
762
763#ifdef TARGET_WORDS_BIGENDIAN
764 bswap = 0;
765#else
766 bswap = 1;
767#endif
768 switch (opc) {
769 case 0:
770 tcg_out32 (s, STB | RS (data_reg) | RA (r0));
771 break;
772 case 1:
773 if (bswap) tcg_out32 (s, STHBRX | RS (data_reg) | RA (0) | RB (r0));
774 else tcg_out32 (s, STH | RS (data_reg) | RA (r0));
775 break;
776 case 2:
777 if (bswap) tcg_out32 (s, STWBRX | RS (data_reg) | RA (0) | RB (r0));
778 else tcg_out32 (s, STW | RS (data_reg) | RA (r0));
779 break;
780 case 3:
781 if (bswap) {
782 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
783 tcg_out32 (s, STWBRX | RS (data_reg) | RA (0) | RB (r0));
784 tcg_out32 (s, STWBRX | RS (data_reg2) | RA (0) | RB (r1));
785 }
786 else {
787 tcg_out32 (s, STW | RS (data_reg2) | RA (r0));
788 tcg_out32 (s, STW | RS (data_reg) | RA (r0) | 4);
789 }
790 break;
791 }
792
793#ifdef CONFIG_SOFTMMU
794 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
795#endif
796}
797
798void tcg_target_qemu_prologue (TCGContext *s)
799{
800 int i, frame_size;
801
802 frame_size = 0
803 + 4 /* back chain */
804 + 4 /* LR */
805 + TCG_STATIC_CALL_ARGS_SIZE
806 + ARRAY_SIZE (tcg_target_callee_save_regs) * 4
807 ;
808 frame_size = (frame_size + 15) & ~15;
809
810 tcg_out32 (s, MFSPR | RT (0) | LR);
811 tcg_out32 (s, STWU | RS (1) | RA (1) | (-frame_size & 0xffff));
812 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
813 tcg_out32 (s, (STW
814 | RS (tcg_target_callee_save_regs[i])
815 | RA (1)
816 | (i * 4 + 8 + TCG_STATIC_CALL_ARGS_SIZE)
817 )
818 );
819 tcg_out32 (s, STW | RS (0) | RA (1) | (frame_size - 4));
820
821 tcg_out32 (s, MTSPR | RS (3) | CTR);
822 tcg_out32 (s, BCCTR | BO_ALWAYS);
823 tb_ret_addr = s->code_ptr;
824
825 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
826 tcg_out32 (s, (LWZ
827 | RT (tcg_target_callee_save_regs[i])
828 | RA (1)
829 | (i * 4 + 8 + TCG_STATIC_CALL_ARGS_SIZE)
830 )
831 );
832 tcg_out32 (s, LWZ | RT (0) | RA (1) | (frame_size - 4));
833 tcg_out32 (s, MTSPR | RS (0) | LR);
834 tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size);
835 tcg_out32 (s, BCLR | BO_ALWAYS);
836}
837
838static void tcg_out_ld (TCGContext *s, TCGType type, int ret, int arg1,
839 tcg_target_long arg2)
840{
841 tcg_out_ldst (s, ret, arg1, arg2, LWZ, LWZX);
842}
843
844static void tcg_out_st (TCGContext *s, TCGType type, int arg, int arg1,
845 tcg_target_long arg2)
846{
847 tcg_out_ldst (s, arg, arg1, arg2, STW, STWX);
848}
849
850static void ppc_addi (TCGContext *s, int rt, int ra, tcg_target_long si)
851{
852 if (!si && rt == ra)
853 return;
854
855 if (si == (int16_t) si)
856 tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff));
857 else {
858 uint16_t h = ((si >> 16) & 0xffff) + ((uint16_t) si >> 15);
859 tcg_out32 (s, ADDIS | RT (rt) | RA (ra) | h);
860 tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff));
861 }
862}
863
864static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
865{
866 ppc_addi (s, reg, reg, val);
867}
868
869static void tcg_out_brcond(TCGContext *s, int cond,
870 TCGArg arg1, TCGArg arg2, int const_arg2,
871 int label_index)
872{
873 TCGLabel *l = &s->labels[label_index];
874 int imm;
875 uint32_t op;
876
2662e13f 877 switch (cond) {
f3f478a7
FB		 878 case TCG_COND_EQ:
879 case TCG_COND_NE:
880 if (const_arg2) {
881 if ((int16_t) arg2 == arg2) {
882 op = CMPI;
883 imm = 1;
884 break;
885 }
886 else if ((uint16_t) arg2 == arg2) {
887 op = CMPLI;
888 imm = 1;
889 break;
890 }
891 }
892 op = CMPL;
893 imm = 0;
894 break;
895
896 case TCG_COND_LT:
897 case TCG_COND_GE:
898 case TCG_COND_LE:
899 case TCG_COND_GT:
900 if (const_arg2) {
901 if ((int16_t) arg2 == arg2) {
902 op = CMPI;
903 imm = 1;
904 break;
905 }
906 }
907 op = CMP;
908 imm = 0;
909 break;
910
911 case TCG_COND_LTU:
912 case TCG_COND_GEU:
913 case TCG_COND_LEU:
914 case TCG_COND_GTU:
915 if (const_arg2) {
916 if ((uint16_t) arg2 == arg2) {
917 op = CMPLI;
918 imm = 1;
919 break;
920 }
921 }
922 op = CMPL;
923 imm = 0;
924 break;
925
2662e13f
FB		 926 default:
927 tcg_abort ();
928 }
929 op |= BF (7);
930
931 if (imm)
932 tcg_out32 (s, op | RA (arg1) | (arg2 & 0xffff));
933 else {
934 if (const_arg2) {
935 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
936 tcg_out32 (s, op | RA (arg1) | RB (0));
937 }
938 else
939 tcg_out32 (s, op | RA (arg1) | RB (arg2));
940 }
941
0a878c47 942 if (l->has_value)
2662e13f
FB		 943 tcg_out32 (s, tcg_to_bc[cond] | reloc_pc14_val (s->code_ptr,
944 l->u.value));
2662e13f 945 else {
0a878c47 946 uint16_t val = *(uint16_t *) &s->code_ptr[2];
947
948 /* Thanks to Andrzej Zaborowski */
949 tcg_out32 (s, tcg_to_bc[cond] | (val & 0xfffc));
2662e13f
FB		 950 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL14, label_index, 0);
951 }
952}
953
954/* brcond2 is taken verbatim from i386 tcg-target */
955/* XXX: we implement it at the target level to avoid having to
956 handle cross basic blocks temporaries */
957static void tcg_out_brcond2(TCGContext *s,
958 const TCGArg *args, const int *const_args)
959{
960 int label_next;
961 label_next = gen_new_label();
962 switch(args[4]) {
963 case TCG_COND_EQ:
964 tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2], label_next);
965 tcg_out_brcond(s, TCG_COND_EQ, args[1], args[3], const_args[3], args[5]);
966 break;
967 case TCG_COND_NE:
968 tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2], args[5]);
969 tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], args[5]);
970 break;
971 case TCG_COND_LT:
972 tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3], args[5]);
973 tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
974 tcg_out_brcond(s, TCG_COND_LT, args[0], args[2], const_args[2], args[5]);
975 break;
976 case TCG_COND_LE:
977 tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3], args[5]);
978 tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
979 tcg_out_brcond(s, TCG_COND_LE, args[0], args[2], const_args[2], args[5]);
980 break;
981 case TCG_COND_GT:
982 tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3], args[5]);
983 tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
984 tcg_out_brcond(s, TCG_COND_GT, args[0], args[2], const_args[2], args[5]);
985 break;
986 case TCG_COND_GE:
987 tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3], args[5]);
988 tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
989 tcg_out_brcond(s, TCG_COND_GE, args[0], args[2], const_args[2], args[5]);
990 break;
991 case TCG_COND_LTU:
992 tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3], args[5]);
993 tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
994 tcg_out_brcond(s, TCG_COND_LTU, args[0], args[2], const_args[2], args[5]);
995 break;
996 case TCG_COND_LEU:
997 tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3], args[5]);
998 tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
999 tcg_out_brcond(s, TCG_COND_LEU, args[0], args[2], const_args[2], args[5]);
1000 break;
1001 case TCG_COND_GTU:
1002 tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3], args[5]);
1003 tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
1004 tcg_out_brcond(s, TCG_COND_GTU, args[0], args[2], const_args[2], args[5]);
1005 break;
1006 case TCG_COND_GEU:
1007 tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3], args[5]);
1008 tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
1009 tcg_out_brcond(s, TCG_COND_GEU, args[0], args[2], const_args[2], args[5]);
1010 break;
1011 default:
1012 tcg_abort();
1013 }
1014 tcg_out_label(s, label_next, (tcg_target_long)s->code_ptr);
1015}
1016
1017static void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
1018 const int *const_args)
1019{
1020 switch (opc) {
1021 case INDEX_op_exit_tb:
1022 tcg_out_movi (s, TCG_TYPE_I32, TCG_REG_R3, args[0]);
932a6909 1023 tcg_out_b (s, 0, (tcg_target_long) tb_ret_addr);
2662e13f
FB		 1024 break;
1025 case INDEX_op_goto_tb:
1026 if (s->tb_jmp_offset) {
1027 /* direct jump method */
932a6909 1028
2662e13f 1029 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
0a878c47 1030 s->code_ptr += 16;
932a6909
FB		 1031 }
1032 else {
2662e13f
FB		 1033 tcg_abort ();
1034 }
1035 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1036 break;
1037 case INDEX_op_br:
1038 {
1039 TCGLabel *l = &s->labels[args[0]];
1040
1041 if (l->has_value) {
932a6909 1042 tcg_out_b (s, 0, l->u.value);
2662e13f
FB		 1043 }
1044 else {
0a878c47 1045 uint32_t val = *(uint32_t *) s->code_ptr;
1046
1047 /* Thanks to Andrzej Zaborowski */
1048 tcg_out32 (s, B | (val & 0x3fffffc));
2662e13f
FB		 1049 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL24, args[0], 0);
1050 }
1051 }
1052 break;
1053 case INDEX_op_call:
1054 if (const_args[0]) {
932a6909 1055 tcg_out_b (s, LK, args[0]);
2662e13f
FB		 1056 }
1057 else {
1058 tcg_out32 (s, MTSPR | RS (args[0]) | LR);
1059 tcg_out32 (s, BCLR | BO_ALWAYS | LK);
1060 }
1061 break;
1062 case INDEX_op_jmp:
1063 if (const_args[0]) {
932a6909 1064 tcg_out_b (s, 0, args[0]);
2662e13f
FB		 1065 }
1066 else {
1067 tcg_out32 (s, MTSPR | RS (args[0]) | CTR);
1068 tcg_out32 (s, BCCTR | BO_ALWAYS);
1069 }
1070 break;
1071 case INDEX_op_movi_i32:
1072 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1073 break;
1074 case INDEX_op_ld8u_i32:
1075 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1076 break;
1077 case INDEX_op_ld8s_i32:
1078 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1079 tcg_out32 (s, EXTSB | RS (args[0]) | RA (args[0]));
1080 break;
1081 case INDEX_op_ld16u_i32:
1082 tcg_out_ldst (s, args[0], args[1], args[2], LHZ, LHZX);
1083 break;
1084 case INDEX_op_ld16s_i32:
1085 tcg_out_ldst (s, args[0], args[1], args[2], LHA, LHAX);
1086 break;
1087 case INDEX_op_ld_i32:
1088 tcg_out_ldst (s, args[0], args[1], args[2], LWZ, LWZX);
1089 break;
1090 case INDEX_op_st8_i32:
1091 tcg_out_ldst (s, args[0], args[1], args[2], STB, STBX);
1092 break;
1093 case INDEX_op_st16_i32:
1094 tcg_out_ldst (s, args[0], args[1], args[2], STH, STHX);
1095 break;
1096 case INDEX_op_st_i32:
1097 tcg_out_ldst (s, args[0], args[1], args[2], STW, STWX);
1098 break;
1099
1100 case INDEX_op_add_i32:
1101 if (const_args[2])
1102 ppc_addi (s, args[0], args[1], args[2]);
1103 else
1104 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1105 break;
1106 case INDEX_op_sub_i32:
1107 if (const_args[2])
1108 ppc_addi (s, args[0], args[1], -args[2]);
1109 else
1110 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1111 break;
1112
1113 case INDEX_op_and_i32:
1114 if (const_args[2]) {
1115 if (!args[2])
1116 tcg_out_movi (s, TCG_TYPE_I32, args[0], 0);
1117 else {
1118 if ((args[2] & 0xffff) == args[2])
1119 tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | args[2]);
1120 else if ((args[2] & 0xffff0000) == args[2])
1121 tcg_out32 (s, ANDIS | RS (args[1]) | RA (args[0])
1122 | ((args[2] >> 16) & 0xffff));
1123 else if (args[2] == 0xffffffff) {
1124 if (args[0] != args[1])
1125 tcg_out_mov (s, args[0], args[1]);
1126 }
1127 else {
1128 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1129 tcg_out32 (s, AND | SAB (args[1], args[0], 0));
1130 }
1131 }
1132 }
1133 else
1134 tcg_out32 (s, AND | SAB (args[1], args[0], args[2]));
1135 break;
1136 case INDEX_op_or_i32:
1137 if (const_args[2]) {
1138 if (args[2]) {
1139 if (args[2] & 0xffff) {
932a6909
FB		 1140 tcg_out32 (s, ORI | RS (args[1]) | RA (args[0])
1141 | (args[2] & 0xffff));
2662e13f
FB		 1142 if (args[2] >> 16)
1143 tcg_out32 (s, ORIS | RS (args[0]) | RA (args[0])
1144 | ((args[2] >> 16) & 0xffff));
1145 }
1146 else {
1147 tcg_out32 (s, ORIS | RS (args[1]) | RA (args[0])
1148 | ((args[2] >> 16) & 0xffff));
1149 }
1150 }
1151 else {
1152 if (args[0] != args[1])
1153 tcg_out_mov (s, args[0], args[1]);
1154 }
1155 }
1156 else
1157 tcg_out32 (s, OR | SAB (args[1], args[0], args[2]));
1158 break;
1159 case INDEX_op_xor_i32:
1160 if (const_args[2]) {
1161 if (args[2]) {
1162 if ((args[2] & 0xffff) == args[2])
1163 tcg_out32 (s, XORI | RS (args[1]) | RA (args[0])
1164 | (args[2] & 0xffff));
1165 else if ((args[2] & 0xffff0000) == args[2])
1166 tcg_out32 (s, XORIS | RS (args[1]) | RA (args[0])
1167 | ((args[2] >> 16) & 0xffff));
1168 else {
1169 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1170 tcg_out32 (s, XOR | SAB (args[1], args[0], 0));
1171 }
1172 }
1173 else {
1174 if (args[0] != args[1])
1175 tcg_out_mov (s, args[0], args[1]);
1176 }
1177 }
1178 else
1179 tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
1180 break;
1181
1182 case INDEX_op_mul_i32:
1183 if (const_args[2]) {
1184 if (args[2] == (int16_t) args[2])
1185 tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1])
1186 | (args[2] & 0xffff));
1187 else {
1188 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1189 tcg_out32 (s, MULLW | TAB (args[0], args[1], 0));
1190 }
1191 }
1192 else
1193 tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2]));
1194 break;
1195 case INDEX_op_mulu2_i32:
1196 if (args[0] == args[2] || args[0] == args[3]) {
1197 tcg_out32 (s, MULLW | TAB (0, args[2], args[3]));
1198 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1199 tcg_out_mov (s, args[0], 0);
1200 }
1201 else {
1202 tcg_out32 (s, MULLW | TAB (args[0], args[2], args[3]));
1203 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1204 }
1205 break;
1206 case INDEX_op_div2_i32:
1207 if (args[0] == args[2] || args[0] == args[3]) {
1208 tcg_out32 (s, DIVW | TAB (0, args[2], args[3]));
0a878c47 1209 tcg_out32 (s, MTSPR | RS (0) | CTR);
2662e13f 1210 tcg_out32 (s, MULLW | TAB (0, 0, args[3]));
0a878c47 1211 tcg_out32 (s, SUBF | TAB (args[1], 0, args[2]));
1212 tcg_out32 (s, MFSPR | RT (args[0]) | CTR);
2662e13f
FB		 1213 }
1214 else {
1215 tcg_out32 (s, DIVW | TAB (args[0], args[2], args[3]));
1216 tcg_out32 (s, MULLW | TAB (0, args[0], args[3]));
1217 tcg_out32 (s, SUBF | TAB (args[1], 0, args[2]));
1218 }
1219 break;
1220 case INDEX_op_divu2_i32:
1221 if (args[0] == args[2] || args[0] == args[3]) {
1222 tcg_out32 (s, DIVWU | TAB (0, args[2], args[3]));
0a878c47 1223 tcg_out32 (s, MTSPR | RS (0) | CTR);
2662e13f 1224 tcg_out32 (s, MULLW | TAB (0, 0, args[3]));
0a878c47 1225 tcg_out32 (s, SUBF | TAB (args[1], 0, args[2]));
1226 tcg_out32 (s, MFSPR | RT (args[0]) | CTR);
2662e13f
FB		 1227 }
1228 else {
1229 tcg_out32 (s, DIVWU | TAB (args[0], args[2], args[3]));
1230 tcg_out32 (s, MULLW | TAB (0, args[0], args[3]));
1231 tcg_out32 (s, SUBF | TAB (args[1], 0, args[2]));
1232 }
1233 break;
1234
1235 case INDEX_op_shl_i32:
1236 if (const_args[2]) {
1237 if (args[2])
1238 tcg_out32 (s, (RLWINM
1239 | RA (args[0])
1240 | RS (args[1])
1241 | SH (args[2])
1242 | MB (0)
1243 | ME (31 - args[2])
1244 )
1245 );
1246 else
1247 tcg_out_mov (s, args[0], args[1]);
1248 }
1249 else
1250 tcg_out32 (s, SLW | SAB (args[1], args[0], args[2]));
1251 break;
1252 case INDEX_op_shr_i32:
1253 if (const_args[2]) {
1254 if (args[2])
1255 tcg_out32 (s, (RLWINM
1256 | RA (args[0])
1257 | RS (args[1])
1258 | SH (32 - args[2])
1259 | MB (args[2])
1260 | ME (31)
1261 )
1262 );
1263 else
1264 tcg_out_mov (s, args[0], args[1]);
1265 }
1266 else
1267 tcg_out32 (s, SRW | SAB (args[1], args[0], args[2]));
1268 break;
1269 case INDEX_op_sar_i32:
1270 if (const_args[2])
1271 tcg_out32 (s, SRAWI | RS (args[1]) | RA (args[0]) | SH (args[2]));
1272 else
1273 tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2]));
1274 break;
1275
1276 case INDEX_op_add2_i32:
1277 if (args[0] == args[3] || args[0] == args[5]) {
1278 tcg_out32 (s, ADDC | TAB (0, args[2], args[4]));
1279 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1280 tcg_out_mov (s, args[0], 0);
1281 }
1282 else {
1283 tcg_out32 (s, ADDC | TAB (args[0], args[2], args[4]));
1284 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1285 }
1286 break;
1287 case INDEX_op_sub2_i32:
1288 if (args[0] == args[3] || args[0] == args[5]) {
1289 tcg_out32 (s, SUBFC | TAB (0, args[4], args[2]));
1290 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1291 tcg_out_mov (s, args[0], 0);
1292 }
1293 else {
1294 tcg_out32 (s, SUBFC | TAB (args[0], args[4], args[2]));
1295 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1296 }
1297 break;
1298
1299 case INDEX_op_brcond_i32:
1300 /*
1301 args[0] = r0
1302 args[1] = r1
1303 args[2] = cond
1304 args[3] = r1 is const
1305 args[4] = label_index
1306 */
1307 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3]);
1308 break;
1309 case INDEX_op_brcond2_i32:
1310 tcg_out_brcond2(s, args, const_args);
1311 break;
1312
1313 case INDEX_op_neg_i32:
1314 tcg_out32 (s, NEG | RT (args[0]) | RA (args[1]));
1315 break;
1316
1317 case INDEX_op_qemu_ld8u:
1318 tcg_out_qemu_ld(s, args, 0);
1319 break;
1320 case INDEX_op_qemu_ld8s:
1321 tcg_out_qemu_ld(s, args, 0 | 4);
1322 break;
1323 case INDEX_op_qemu_ld16u:
1324 tcg_out_qemu_ld(s, args, 1);
1325 break;
1326 case INDEX_op_qemu_ld16s:
1327 tcg_out_qemu_ld(s, args, 1 | 4);
1328 break;
1329 case INDEX_op_qemu_ld32u:
1330 tcg_out_qemu_ld(s, args, 2);
1331 break;
1332 case INDEX_op_qemu_ld64:
1333 tcg_out_qemu_ld(s, args, 3);
1334 break;
1335 case INDEX_op_qemu_st8:
1336 tcg_out_qemu_st(s, args, 0);
1337 break;
1338 case INDEX_op_qemu_st16:
1339 tcg_out_qemu_st(s, args, 1);
1340 break;
1341 case INDEX_op_qemu_st32:
1342 tcg_out_qemu_st(s, args, 2);
1343 break;
1344 case INDEX_op_qemu_st64:
1345 tcg_out_qemu_st(s, args, 3);
1346 break;
1347
1348 default:
1349 tcg_dump_ops (s, stderr);
1350 tcg_abort ();
1351 }
1352}
1353
1354static const TCGTargetOpDef ppc_op_defs[] = {
1355 { INDEX_op_exit_tb, { } },
1356 { INDEX_op_goto_tb, { } },
932a6909
FB		 1357 { INDEX_op_call, { "ri" } },
1358 { INDEX_op_jmp, { "ri" } },
2662e13f
FB		 1359 { INDEX_op_br, { } },
1360
1361 { INDEX_op_mov_i32, { "r", "r" } },
1362 { INDEX_op_movi_i32, { "r" } },
1363 { INDEX_op_ld8u_i32, { "r", "r" } },
1364 { INDEX_op_ld8s_i32, { "r", "r" } },
1365 { INDEX_op_ld16u_i32, { "r", "r" } },
1366 { INDEX_op_ld16s_i32, { "r", "r" } },
1367 { INDEX_op_ld_i32, { "r", "r" } },
1368 { INDEX_op_st8_i32, { "r", "r" } },
1369 { INDEX_op_st16_i32, { "r", "r" } },
1370 { INDEX_op_st_i32, { "r", "r" } },
1371
1372 { INDEX_op_add_i32, { "r", "r", "ri" } },
1373 { INDEX_op_mul_i32, { "r", "r", "ri" } },
1374 { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
1375 { INDEX_op_div2_i32, { "r", "r", "r", "r", "r" } },
1376 { INDEX_op_divu2_i32, { "r", "r", "r", "r", "r" } },
1377 { INDEX_op_sub_i32, { "r", "r", "ri" } },
1378 { INDEX_op_and_i32, { "r", "r", "ri" } },
1379 { INDEX_op_or_i32, { "r", "r", "ri" } },
1380 { INDEX_op_xor_i32, { "r", "r", "ri" } },
1381
1382 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1383 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1384 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1385
1386 { INDEX_op_brcond_i32, { "r", "ri" } },
1387
1388 { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1389 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1390 { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
1391
1392 { INDEX_op_neg_i32, { "r", "r" } },
1393
1394#if TARGET_LONG_BITS == 32
1395 { INDEX_op_qemu_ld8u, { "r", "L" } },
1396 { INDEX_op_qemu_ld8s, { "r", "L" } },
1397 { INDEX_op_qemu_ld16u, { "r", "L" } },
1398 { INDEX_op_qemu_ld16s, { "r", "L" } },
1399 { INDEX_op_qemu_ld32u, { "r", "L" } },
1400 { INDEX_op_qemu_ld32s, { "r", "L" } },
1401 { INDEX_op_qemu_ld64, { "r", "r", "L" } },
1402
1403 { INDEX_op_qemu_st8, { "K", "K" } },
1404 { INDEX_op_qemu_st16, { "K", "K" } },
1405 { INDEX_op_qemu_st32, { "K", "K" } },
1406 { INDEX_op_qemu_st64, { "M", "M", "M" } },
1407#else
1408 { INDEX_op_qemu_ld8u, { "r", "L", "L" } },
1409 { INDEX_op_qemu_ld8s, { "r", "L", "L" } },
1410 { INDEX_op_qemu_ld16u, { "r", "L", "L" } },
1411 { INDEX_op_qemu_ld16s, { "r", "L", "L" } },
1412 { INDEX_op_qemu_ld32u, { "r", "L", "L" } },
1413 { INDEX_op_qemu_ld32s, { "r", "L", "L" } },
1414 { INDEX_op_qemu_ld64, { "r", "L", "L", "L" } },
1415
1416 { INDEX_op_qemu_st8, { "K", "K", "K" } },
1417 { INDEX_op_qemu_st16, { "K", "K", "K" } },
1418 { INDEX_op_qemu_st32, { "K", "K", "K" } },
1419 { INDEX_op_qemu_st64, { "M", "M", "M", "M" } },
1420#endif
1421
1422 { -1 },
1423};
1424
1425void tcg_target_init(TCGContext *s)
1426{
1427 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1428 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1429 (1 << TCG_REG_R0) |
1430 (1 << TCG_REG_R3) |
1431 (1 << TCG_REG_R4) |
1432 (1 << TCG_REG_R5) |
1433 (1 << TCG_REG_R6) |
1434 (1 << TCG_REG_R7) |
1435 (1 << TCG_REG_R8) |
1436 (1 << TCG_REG_R9) |
1437 (1 << TCG_REG_R10) |
1438 (1 << TCG_REG_R11) |
1439 (1 << TCG_REG_R12)
1440 );
1441
1442 tcg_regset_clear(s->reserved_regs);
1443 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);
1444 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1);
1445 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2);
1446
1447 tcg_add_target_add_op_defs(ppc_op_defs);
1448}
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