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Split TLB addend and target_phys_addr_t
[mirror_qemu.git] / tcg / ppc / tcg-target.c
CommitLineData
2662e13f
FB		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25static uint8_t *tb_ret_addr;
26
6ec85236 27#ifdef _CALL_DARWIN
bf6bca52 28#define LINKAGE_AREA_SIZE 24
2946898b 29#define LR_OFFSET 8
6ec85236 30#elif defined _CALL_AIX
b29fe3ed 31#define LINKAGE_AREA_SIZE 52
32#define LR_OFFSET 8
f9bf2987 33#else
34#define LINKAGE_AREA_SIZE 8
2946898b 35#define LR_OFFSET 4
f9bf2987 36#endif
37
2662e13f 38#define FAST_PATH
35f6b599 39
f6548c0a 40#ifndef GUEST_BASE
41#define GUEST_BASE 0
42#endif
43
44#ifdef CONFIG_USE_GUEST_BASE
45#define TCG_GUEST_BASE_REG 30
46#else
47#define TCG_GUEST_BASE_REG 0
48#endif
49
d4a9eb1f 50#ifndef NDEBUG
2662e13f
FB		 51static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
52 "r0",
53 "r1",
54 "rp",
55 "r3",
56 "r4",
57 "r5",
58 "r6",
59 "r7",
60 "r8",
61 "r9",
62 "r10",
63 "r11",
64 "r12",
65 "r13",
66 "r14",
67 "r15",
68 "r16",
69 "r17",
70 "r18",
71 "r19",
72 "r20",
73 "r21",
74 "r22",
75 "r23",
76 "r24",
77 "r25",
78 "r26",
79 "r27",
80 "r28",
81 "r29",
82 "r30",
83 "r31"
84};
d4a9eb1f 85#endif
2662e13f
FB		 86
87static const int tcg_target_reg_alloc_order[] = {
a35e86c5 88 TCG_REG_R14,
89 TCG_REG_R15,
90 TCG_REG_R16,
91 TCG_REG_R17,
92 TCG_REG_R18,
93 TCG_REG_R19,
94 TCG_REG_R20,
95 TCG_REG_R21,
96 TCG_REG_R22,
97 TCG_REG_R23,
98 TCG_REG_R28,
99 TCG_REG_R29,
100 TCG_REG_R30,
101 TCG_REG_R31,
6ec85236 102#ifdef _CALL_DARWIN
f9bf2987 103 TCG_REG_R2,
104#endif
2662e13f
FB		 105 TCG_REG_R3,
106 TCG_REG_R4,
107 TCG_REG_R5,
108 TCG_REG_R6,
109 TCG_REG_R7,
110 TCG_REG_R8,
111 TCG_REG_R9,
112 TCG_REG_R10,
6ec85236 113#ifndef _CALL_DARWIN
2662e13f 114 TCG_REG_R11,
f9bf2987 115#endif
2662e13f 116 TCG_REG_R12,
6ec85236 117#ifndef _CALL_SYSV
2662e13f 118 TCG_REG_R13,
5db3ee79 119#endif
2662e13f
FB		 120 TCG_REG_R24,
121 TCG_REG_R25,
122 TCG_REG_R26,
a35e86c5 123 TCG_REG_R27
2662e13f
FB		 124};
125
126static const int tcg_target_call_iarg_regs[] = {
127 TCG_REG_R3,
128 TCG_REG_R4,
129 TCG_REG_R5,
130 TCG_REG_R6,
131 TCG_REG_R7,
132 TCG_REG_R8,
133 TCG_REG_R9,
134 TCG_REG_R10
135};
136
137static const int tcg_target_call_oarg_regs[2] = {
138 TCG_REG_R3,
139 TCG_REG_R4
140};
141
142static const int tcg_target_callee_save_regs[] = {
6ec85236 143#ifdef _CALL_DARWIN
f9bf2987 144 TCG_REG_R11,
145 TCG_REG_R13,
b29fe3ed 146#endif
6ec85236 147#ifdef _CALL_AIX
b29fe3ed 148 TCG_REG_R13,
f9bf2987 149#endif
2662e13f
FB		 150 TCG_REG_R14,
151 TCG_REG_R15,
152 TCG_REG_R16,
153 TCG_REG_R17,
154 TCG_REG_R18,
155 TCG_REG_R19,
156 TCG_REG_R20,
157 TCG_REG_R21,
158 TCG_REG_R22,
159 TCG_REG_R23,
eb2eb1dc 160 TCG_REG_R24,
161 TCG_REG_R25,
162 TCG_REG_R26,
163 /* TCG_REG_R27, */ /* currently used for the global env, so no
164 need to save */
2662e13f
FB		 165 TCG_REG_R28,
166 TCG_REG_R29,
167 TCG_REG_R30,
168 TCG_REG_R31
169};
170
171static uint32_t reloc_pc24_val (void *pc, tcg_target_long target)
172{
932a6909
FB		 173 tcg_target_long disp;
174
175 disp = target - (tcg_target_long) pc;
176 if ((disp << 6) >> 6 != disp)
177 tcg_abort ();
178
179 return disp & 0x3fffffc;
2662e13f
FB		 180}
181
182static void reloc_pc24 (void *pc, tcg_target_long target)
183{
184 *(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
185 | reloc_pc24_val (pc, target);
186}
187
188static uint16_t reloc_pc14_val (void *pc, tcg_target_long target)
189{
932a6909
FB		 190 tcg_target_long disp;
191
192 disp = target - (tcg_target_long) pc;
193 if (disp != (int16_t) disp)
194 tcg_abort ();
195
196 return disp & 0xfffc;
2662e13f
FB		 197}
198
199static void reloc_pc14 (void *pc, tcg_target_long target)
200{
201 *(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)
202 | reloc_pc14_val (pc, target);
203}
204
205static void patch_reloc(uint8_t *code_ptr, int type,
206 tcg_target_long value, tcg_target_long addend)
207{
208 value += addend;
209 switch (type) {
210 case R_PPC_REL14:
211 reloc_pc14 (code_ptr, value);
212 break;
213 case R_PPC_REL24:
214 reloc_pc24 (code_ptr, value);
215 break;
216 default:
217 tcg_abort();
218 }
219}
220
221/* maximum number of register used for input function arguments */
222static int tcg_target_get_call_iarg_regs_count(int flags)
223{
b1503cda 224 return ARRAY_SIZE (tcg_target_call_iarg_regs);
2662e13f
FB		 225}
226
227/* parse target specific constraints */
228static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
229{
230 const char *ct_str;
231
232 ct_str = *pct_str;
233 switch (ct_str[0]) {
398ce98e 234 case 'A': case 'B': case 'C': case 'D':
235 ct->ct |= TCG_CT_REG;
236 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
237 break;
2662e13f
FB		 238 case 'r':
239 ct->ct |= TCG_CT_REG;
240 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
241 break;
70fa887c 242#ifdef CONFIG_SOFTMMU
2662e13f
FB		 243 case 'L': /* qemu_ld constraint */
244 ct->ct |= TCG_CT_REG;
245 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
246 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
247 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
248 break;
249 case 'K': /* qemu_st[8..32] constraint */
250 ct->ct |= TCG_CT_REG;
251 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
252 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
253 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
254 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
255#if TARGET_LONG_BITS == 64
256 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
257#endif
258 break;
259 case 'M': /* qemu_st64 constraint */
260 ct->ct |= TCG_CT_REG;
261 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
262 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
263 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
264 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
265 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
266 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
267 break;
70fa887c 268#else
269 case 'L':
270 case 'K':
271 ct->ct |= TCG_CT_REG;
272 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
273 break;
274 case 'M':
275 ct->ct |= TCG_CT_REG;
276 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
277 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
278 break;
279#endif
2662e13f
FB		 280 default:
281 return -1;
282 }
283 ct_str++;
284 *pct_str = ct_str;
285 return 0;
286}
287
288/* test if a constant matches the constraint */
289static int tcg_target_const_match(tcg_target_long val,
290 const TCGArgConstraint *arg_ct)
291{
292 int ct;
293
294 ct = arg_ct->ct;
295 if (ct & TCG_CT_CONST)
296 return 1;
2662e13f
FB		 297 return 0;
298}
299
300#define OPCD(opc) ((opc)<<26)
301#define XO31(opc) (OPCD(31)|((opc)<<1))
302#define XO19(opc) (OPCD(19)|((opc)<<1))
303
304#define B OPCD(18)
305#define BC OPCD(16)
306#define LBZ OPCD(34)
307#define LHZ OPCD(40)
308#define LHA OPCD(42)
309#define LWZ OPCD(32)
310#define STB OPCD(38)
311#define STH OPCD(44)
312#define STW OPCD(36)
313
b0809bf7 314#define ADDIC OPCD(12)
2662e13f
FB		 315#define ADDI OPCD(14)
316#define ADDIS OPCD(15)
317#define ORI OPCD(24)
318#define ORIS OPCD(25)
319#define XORI OPCD(26)
320#define XORIS OPCD(27)
321#define ANDI OPCD(28)
322#define ANDIS OPCD(29)
323#define MULLI OPCD( 7)
324#define CMPLI OPCD(10)
325#define CMPI OPCD(11)
d616cf1d 326#define SUBFIC OPCD( 8)
2662e13f
FB		 327
328#define LWZU OPCD(33)
329#define STWU OPCD(37)
330
331#define RLWINM OPCD(21)
65fe043e 332#define RLWNM OPCD(23)
2662e13f 333
c596defd 334#define BCLR XO19( 16)
2662e13f
FB		 335#define BCCTR XO19(528)
336#define CRAND XO19(257)
c596defd 337#define CRANDC XO19(129)
338#define CRNAND XO19(225)
339#define CROR XO19(449)
b0809bf7 340#define CRNOR XO19( 33)
2662e13f
FB		 341
342#define EXTSB XO31(954)
343#define EXTSH XO31(922)
344#define ADD XO31(266)
345#define ADDE XO31(138)
346#define ADDC XO31( 10)
347#define AND XO31( 28)
348#define SUBF XO31( 40)
349#define SUBFC XO31( 8)
350#define SUBFE XO31(136)
351#define OR XO31(444)
352#define XOR XO31(316)
353#define MULLW XO31(235)
354#define MULHWU XO31( 11)
355#define DIVW XO31(491)
356#define DIVWU XO31(459)
357#define CMP XO31( 0)
358#define CMPL XO31( 32)
359#define LHBRX XO31(790)
360#define LWBRX XO31(534)
361#define STHBRX XO31(918)
362#define STWBRX XO31(662)
363#define MFSPR XO31(339)
364#define MTSPR XO31(467)
365#define SRAWI XO31(824)
366#define NEG XO31(104)
b0809bf7 367#define MFCR XO31( 19)
368#define CNTLZW XO31( 26)
65fe043e 369#define NOR XO31(124)
370#define ANDC XO31( 60)
371#define ORC XO31(412)
2662e13f
FB		 372
373#define LBZX XO31( 87)
4f4a67ae 374#define LHZX XO31(279)
2662e13f
FB		 375#define LHAX XO31(343)
376#define LWZX XO31( 23)
377#define STBX XO31(215)
378#define STHX XO31(407)
379#define STWX XO31(151)
380
381#define SPR(a,b) ((((a)<<5)|(b))<<11)
382#define LR SPR(8, 0)
383#define CTR SPR(9, 0)
384
385#define SLW XO31( 24)
386#define SRW XO31(536)
387#define SRAW XO31(792)
388
2662e13f
FB		 389#define TW XO31(4)
390#define TRAP (TW | TO (31))
391
392#define RT(r) ((r)<<21)
393#define RS(r) ((r)<<21)
394#define RA(r) ((r)<<16)
395#define RB(r) ((r)<<11)
396#define TO(t) ((t)<<21)
397#define SH(s) ((s)<<11)
398#define MB(b) ((b)<<6)
399#define ME(e) ((e)<<1)
400#define BO(o) ((o)<<21)
401
402#define LK 1
403
404#define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
405#define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
406
407#define BF(n) ((n)<<23)
408#define BI(n, c) (((c)+((n)*4))<<16)
409#define BT(n, c) (((c)+((n)*4))<<21)
410#define BA(n, c) (((c)+((n)*4))<<16)
411#define BB(n, c) (((c)+((n)*4))<<11)
412
413#define BO_COND_TRUE BO (12)
414#define BO_COND_FALSE BO (4)
415#define BO_ALWAYS BO (20)
416
417enum {
418 CR_LT,
419 CR_GT,
420 CR_EQ,
421 CR_SO
422};
423
424static const uint32_t tcg_to_bc[10] = {
425 [TCG_COND_EQ] = BC | BI (7, CR_EQ) | BO_COND_TRUE,
426 [TCG_COND_NE] = BC | BI (7, CR_EQ) | BO_COND_FALSE,
427 [TCG_COND_LT] = BC | BI (7, CR_LT) | BO_COND_TRUE,
428 [TCG_COND_GE] = BC | BI (7, CR_LT) | BO_COND_FALSE,
429 [TCG_COND_LE] = BC | BI (7, CR_GT) | BO_COND_FALSE,
430 [TCG_COND_GT] = BC | BI (7, CR_GT) | BO_COND_TRUE,
431 [TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,
432 [TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,
433 [TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,
434 [TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
435};
436
437static void tcg_out_mov(TCGContext *s, int ret, int arg)
438{
439 tcg_out32 (s, OR | SAB (arg, ret, arg));
440}
441
442static void tcg_out_movi(TCGContext *s, TCGType type,
443 int ret, tcg_target_long arg)
444{
445 if (arg == (int16_t) arg)
446 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
447 else {
448 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
449 if (arg & 0xffff)
0a878c47 450 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
2662e13f
FB		 451 }
452}
453
454static void tcg_out_ldst (TCGContext *s, int ret, int addr,
455 int offset, int op1, int op2)
456{
457 if (offset == (int16_t) offset)
458 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
459 else {
460 tcg_out_movi (s, TCG_TYPE_I32, 0, offset);
461 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
462 }
463}
464
932a6909
FB		 465static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target)
466{
467 tcg_target_long disp;
468
469 disp = target - (tcg_target_long) s->code_ptr;
470 if ((disp << 6) >> 6 == disp)
8c5e95d8 471 tcg_out32 (s, B | (disp & 0x3fffffc) | mask);
932a6909
FB		 472 else {
473 tcg_out_movi (s, TCG_TYPE_I32, 0, (tcg_target_long) target);
474 tcg_out32 (s, MTSPR | RS (0) | CTR);
475 tcg_out32 (s, BCCTR | BO_ALWAYS | mask);
476 }
477}
478
b29fe3ed 479static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg)
480{
6ec85236 481#ifdef _CALL_AIX
b29fe3ed 482 int reg;
483
484 if (const_arg) {
485 reg = 2;
486 tcg_out_movi (s, TCG_TYPE_I32, reg, arg);
487 }
488 else reg = arg;
489
490 tcg_out32 (s, LWZ | RT (0) | RA (reg));
491 tcg_out32 (s, MTSPR | RA (0) | CTR);
492 tcg_out32 (s, LWZ | RT (2) | RA (reg) | 4);
493 tcg_out32 (s, BCCTR | BO_ALWAYS | LK);
d9370327 494#else
495 if (const_arg) {
496 tcg_out_b (s, LK, arg);
497 }
498 else {
499 tcg_out32 (s, MTSPR | RS (arg) | LR);
500 tcg_out32 (s, BCLR | BO_ALWAYS | LK);
501 }
b29fe3ed 502#endif
d9370327 503}
b29fe3ed 504
2662e13f 505#if defined(CONFIG_SOFTMMU)
79383c9c
BS		 506
507#include "../../softmmu_defs.h"
2662e13f
FB		 508
509static void *qemu_ld_helpers[4] = {
510 __ldb_mmu,
511 __ldw_mmu,
512 __ldl_mmu,
513 __ldq_mmu,
514};
515
516static void *qemu_st_helpers[4] = {
517 __stb_mmu,
518 __stw_mmu,
519 __stl_mmu,
520 __stq_mmu,
521};
522#endif
523
524static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
525{
f6548c0a 526 int addr_reg, data_reg, data_reg2, r0, r1, rbase, mem_index, s_bits, bswap;
2662e13f 527#ifdef CONFIG_SOFTMMU
f8edcbaa 528 int r2;
2662e13f
FB		 529 void *label1_ptr, *label2_ptr;
530#endif
531#if TARGET_LONG_BITS == 64
532 int addr_reg2;
533#endif
534
535 data_reg = *args++;
536 if (opc == 3)
537 data_reg2 = *args++;
538 else
539 data_reg2 = 0;
540 addr_reg = *args++;
541#if TARGET_LONG_BITS == 64
542 addr_reg2 = *args++;
543#endif
544 mem_index = *args;
545 s_bits = opc & 3;
546
547#ifdef CONFIG_SOFTMMU
548 r0 = 3;
549 r1 = 4;
550 r2 = 0;
f6548c0a 551 rbase = 0;
2662e13f
FB		 552
553 tcg_out32 (s, (RLWINM
554 | RA (r0)
555 | RS (addr_reg)
556 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
557 | MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
558 | ME (31 - CPU_TLB_ENTRY_BITS)
559 )
560 );
561 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
562 tcg_out32 (s, (LWZU
563 | RT (r1)
564 | RA (r0)
565 | offsetof (CPUState, tlb_table[mem_index][0].addr_read)
566 )
567 );
568 tcg_out32 (s, (RLWINM
569 | RA (r2)
570 | RS (addr_reg)
571 | SH (0)
572 | MB ((32 - s_bits) & 31)
573 | ME (31 - TARGET_PAGE_BITS)
574 )
575 );
576
577 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1));
578#if TARGET_LONG_BITS == 64
579 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
580 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
581 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
582#endif
583
584 label1_ptr = s->code_ptr;
585#ifdef FAST_PATH
586 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
587#endif
588
589 /* slow path */
590#if TARGET_LONG_BITS == 32
591 tcg_out_mov (s, 3, addr_reg);
592 tcg_out_movi (s, TCG_TYPE_I32, 4, mem_index);
593#else
594 tcg_out_mov (s, 3, addr_reg2);
595 tcg_out_mov (s, 4, addr_reg);
596 tcg_out_movi (s, TCG_TYPE_I32, 5, mem_index);
597#endif
598
b29fe3ed 599 tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1);
2662e13f
FB		 600 switch (opc) {
601 case 0|4:
602 tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
603 break;
604 case 1|4:
605 tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
606 break;
607 case 0:
608 case 1:
609 case 2:
610 if (data_reg != 3)
611 tcg_out_mov (s, data_reg, 3);
612 break;
613 case 3:
614 if (data_reg == 3) {
615 if (data_reg2 == 4) {
616 tcg_out_mov (s, 0, 4);
617 tcg_out_mov (s, 4, 3);
618 tcg_out_mov (s, 3, 0);
619 }
620 else {
621 tcg_out_mov (s, data_reg2, 3);
622 tcg_out_mov (s, 3, 4);
623 }
624 }
625 else {
626 if (data_reg != 4) tcg_out_mov (s, data_reg, 4);
627 if (data_reg2 != 3) tcg_out_mov (s, data_reg2, 3);
628 }
629 break;
630 }
631 label2_ptr = s->code_ptr;
632 tcg_out32 (s, B);
633
634 /* label1: fast path */
635#ifdef FAST_PATH
636 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
637#endif
638
639 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
640 tcg_out32 (s, (LWZ
641 | RT (r0)
642 | RA (r0)
355b1943 643 | (offsetof (CPUTLBEntry, addend)
2662e13f
FB		 644 - offsetof (CPUTLBEntry, addr_read))
645 ));
646 /* r0 = env->tlb_table[mem_index][index].addend */
647 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
648 /* r0 = env->tlb_table[mem_index][index].addend + addr */
649
650#else /* !CONFIG_SOFTMMU */
651 r0 = addr_reg;
f8edcbaa 652 r1 = 3;
f6548c0a 653 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
2662e13f
FB		 654#endif
655
656#ifdef TARGET_WORDS_BIGENDIAN
657 bswap = 0;
658#else
659 bswap = 1;
660#endif
f6548c0a 661
2662e13f
FB		 662 switch (opc) {
663 default:
664 case 0:
f6548c0a 665 tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
2662e13f
FB		 666 break;
667 case 0|4:
f6548c0a 668 tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
2662e13f
FB		 669 tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg));
670 break;
671 case 1:
f6548c0a 672 if (bswap)
673 tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
674 else
675 tcg_out32 (s, LHZX | TAB (data_reg, rbase, r0));
2662e13f
FB		 676 break;
677 case 1|4:
678 if (bswap) {
f6548c0a 679 tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
2662e13f
FB		 680 tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg));
681 }
f6548c0a 682 else tcg_out32 (s, LHAX | TAB (data_reg, rbase, r0));
2662e13f
FB		 683 break;
684 case 2:
f6548c0a 685 if (bswap)
686 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
687 else
688 tcg_out32 (s, LWZX | TAB (data_reg, rbase, r0));
2662e13f
FB		 689 break;
690 case 3:
691 if (bswap) {
f6548c0a 692 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
693 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
694 tcg_out32 (s, LWBRX | TAB (data_reg2, rbase, r1));
2662e13f
FB		 695 }
696 else {
f6548c0a 697#ifdef CONFIG_USE_GUEST_BASE
698 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
699 tcg_out32 (s, LWZX | TAB (data_reg2, rbase, r0));
700 tcg_out32 (s, LWZX | TAB (data_reg, rbase, r1));
701#else
2662e13f
FB		 702 if (r0 == data_reg2) {
703 tcg_out32 (s, LWZ | RT (0) | RA (r0));
704 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
705 tcg_out_mov (s, data_reg2, 0);
706 }
707 else {
708 tcg_out32 (s, LWZ | RT (data_reg2) | RA (r0));
709 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
710 }
f6548c0a 711#endif
2662e13f
FB		 712 }
713 break;
714 }
715
716#ifdef CONFIG_SOFTMMU
717 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
718#endif
719}
720
721static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
722{
f6548c0a 723 int addr_reg, r0, r1, data_reg, data_reg2, mem_index, bswap, rbase;
2662e13f
FB		 724#ifdef CONFIG_SOFTMMU
725 int r2, ir;
726 void *label1_ptr, *label2_ptr;
727#endif
728#if TARGET_LONG_BITS == 64
729 int addr_reg2;
730#endif
731
732 data_reg = *args++;
733 if (opc == 3)
734 data_reg2 = *args++;
735 else
736 data_reg2 = 0;
737 addr_reg = *args++;
738#if TARGET_LONG_BITS == 64
739 addr_reg2 = *args++;
740#endif
741 mem_index = *args;
742
743#ifdef CONFIG_SOFTMMU
744 r0 = 3;
745 r1 = 4;
746 r2 = 0;
f6548c0a 747 rbase = 0;
2662e13f
FB		 748
749 tcg_out32 (s, (RLWINM
750 | RA (r0)
751 | RS (addr_reg)
752 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
753 | MB (32 - (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS))
754 | ME (31 - CPU_TLB_ENTRY_BITS)
755 )
756 );
757 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
758 tcg_out32 (s, (LWZU
759 | RT (r1)
760 | RA (r0)
761 | offsetof (CPUState, tlb_table[mem_index][0].addr_write)
762 )
763 );
764 tcg_out32 (s, (RLWINM
765 | RA (r2)
766 | RS (addr_reg)
767 | SH (0)
768 | MB ((32 - opc) & 31)
769 | ME (31 - TARGET_PAGE_BITS)
770 )
771 );
772
773 tcg_out32 (s, CMP | (7 << 23) | RA (r2) | RB (r1));
774#if TARGET_LONG_BITS == 64
775 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
776 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
777 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
778#endif
779
780 label1_ptr = s->code_ptr;
781#ifdef FAST_PATH
782 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
783#endif
784
785 /* slow path */
786#if TARGET_LONG_BITS == 32
787 tcg_out_mov (s, 3, addr_reg);
788 ir = 4;
789#else
790 tcg_out_mov (s, 3, addr_reg2);
791 tcg_out_mov (s, 4, addr_reg);
f9bf2987 792#ifdef TCG_TARGET_CALL_ALIGN_ARGS
2662e13f 793 ir = 5;
f9bf2987 794#else
795 ir = 4;
796#endif
2662e13f
FB		 797#endif
798
799 switch (opc) {
800 case 0:
801 tcg_out32 (s, (RLWINM
802 | RA (ir)
803 | RS (data_reg)
804 | SH (0)
805 | MB (24)
806 | ME (31)));
807 break;
808 case 1:
809 tcg_out32 (s, (RLWINM
810 | RA (ir)
811 | RS (data_reg)
812 | SH (0)
813 | MB (16)
814 | ME (31)));
815 break;
816 case 2:
817 tcg_out_mov (s, ir, data_reg);
818 break;
819 case 3:
f9bf2987 820#ifdef TCG_TARGET_CALL_ALIGN_ARGS
821 ir = 5;
822#endif
823 tcg_out_mov (s, ir++, data_reg2);
824 tcg_out_mov (s, ir, data_reg);
2662e13f
FB		 825 break;
826 }
827 ir++;
828
829 tcg_out_movi (s, TCG_TYPE_I32, ir, mem_index);
b29fe3ed 830 tcg_out_call (s, (tcg_target_long) qemu_st_helpers[opc], 1);
2662e13f
FB		 831 label2_ptr = s->code_ptr;
832 tcg_out32 (s, B);
833
834 /* label1: fast path */
835#ifdef FAST_PATH
836 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
837#endif
838
839 tcg_out32 (s, (LWZ
840 | RT (r0)
841 | RA (r0)
355b1943 842 | (offsetof (CPUTLBEntry, addend)
2662e13f
FB		 843 - offsetof (CPUTLBEntry, addr_write))
844 ));
845 /* r0 = env->tlb_table[mem_index][index].addend */
846 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
847 /* r0 = env->tlb_table[mem_index][index].addend + addr */
848
849#else /* !CONFIG_SOFTMMU */
2662e13f 850 r0 = addr_reg;
f6548c0a 851 r1 = 3;
a71836de 852 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
2662e13f
FB		 853#endif
854
855#ifdef TARGET_WORDS_BIGENDIAN
856 bswap = 0;
857#else
858 bswap = 1;
859#endif
860 switch (opc) {
861 case 0:
f6548c0a 862 tcg_out32 (s, STBX | SAB (data_reg, rbase, r0));
2662e13f
FB		 863 break;
864 case 1:
f6548c0a 865 if (bswap)
866 tcg_out32 (s, STHBRX | SAB (data_reg, rbase, r0));
867 else
868 tcg_out32 (s, STHX | SAB (data_reg, rbase, r0));
2662e13f
FB		 869 break;
870 case 2:
f6548c0a 871 if (bswap)
872 tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
873 else
874 tcg_out32 (s, STWX | SAB (data_reg, rbase, r0));
2662e13f
FB		 875 break;
876 case 3:
877 if (bswap) {
878 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
f6548c0a 879 tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
880 tcg_out32 (s, STWBRX | SAB (data_reg2, rbase, r1));
2662e13f
FB		 881 }
882 else {
f6548c0a 883#ifdef CONFIG_USE_GUEST_BASE
884 tcg_out32 (s, STWX | SAB (data_reg2, rbase, r0));
885 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
886 tcg_out32 (s, STWX | SAB (data_reg, rbase, r1));
887#else
2662e13f
FB		 888 tcg_out32 (s, STW | RS (data_reg2) | RA (r0));
889 tcg_out32 (s, STW | RS (data_reg) | RA (r0) | 4);
f6548c0a 890#endif
2662e13f
FB		 891 }
892 break;
893 }
894
895#ifdef CONFIG_SOFTMMU
896 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
897#endif
898}
899
900void tcg_target_qemu_prologue (TCGContext *s)
901{
0d5bd363 902 int i, frame_size;
2662e13f
FB		 903
904 frame_size = 0
f9bf2987 905 + LINKAGE_AREA_SIZE
2662e13f
FB		 906 + TCG_STATIC_CALL_ARGS_SIZE
907 + ARRAY_SIZE (tcg_target_callee_save_regs) * 4
908 ;
909 frame_size = (frame_size + 15) & ~15;
910
6ec85236 911#ifdef _CALL_AIX
b29fe3ed 912 {
913 uint32_t addr;
914
915 /* First emit adhoc function descriptor */
916 addr = (uint32_t) s->code_ptr + 12;
917 tcg_out32 (s, addr); /* entry point */
918 s->code_ptr += 8; /* skip TOC and environment pointer */
919 }
920#endif
2662e13f
FB		 921 tcg_out32 (s, MFSPR | RT (0) | LR);
922 tcg_out32 (s, STWU | RS (1) | RA (1) | (-frame_size & 0xffff));
923 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
924 tcg_out32 (s, (STW
925 | RS (tcg_target_callee_save_regs[i])
926 | RA (1)
f9bf2987 927 | (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE)
2662e13f
FB		 928 )
929 );
2946898b 930 tcg_out32 (s, STW | RS (0) | RA (1) | (frame_size + LR_OFFSET));
2662e13f 931
f6548c0a 932#ifdef CONFIG_USE_GUEST_BASE
933 tcg_out_movi (s, TCG_TYPE_I32, TCG_GUEST_BASE_REG, GUEST_BASE);
934#endif
935
2662e13f
FB		 936 tcg_out32 (s, MTSPR | RS (3) | CTR);
937 tcg_out32 (s, BCCTR | BO_ALWAYS);
938 tb_ret_addr = s->code_ptr;
939
940 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
941 tcg_out32 (s, (LWZ
942 | RT (tcg_target_callee_save_regs[i])
943 | RA (1)
f9bf2987 944 | (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE)
2662e13f
FB		 945 )
946 );
2946898b 947 tcg_out32 (s, LWZ | RT (0) | RA (1) | (frame_size + LR_OFFSET));
2662e13f
FB		 948 tcg_out32 (s, MTSPR | RS (0) | LR);
949 tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size);
950 tcg_out32 (s, BCLR | BO_ALWAYS);
951}
952
953static void tcg_out_ld (TCGContext *s, TCGType type, int ret, int arg1,
954 tcg_target_long arg2)
955{
956 tcg_out_ldst (s, ret, arg1, arg2, LWZ, LWZX);
957}
958
959static void tcg_out_st (TCGContext *s, TCGType type, int arg, int arg1,
960 tcg_target_long arg2)
961{
962 tcg_out_ldst (s, arg, arg1, arg2, STW, STWX);
963}
964
965static void ppc_addi (TCGContext *s, int rt, int ra, tcg_target_long si)
966{
967 if (!si && rt == ra)
968 return;
969
970 if (si == (int16_t) si)
971 tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff));
972 else {
973 uint16_t h = ((si >> 16) & 0xffff) + ((uint16_t) si >> 15);
974 tcg_out32 (s, ADDIS | RT (rt) | RA (ra) | h);
975 tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff));
976 }
977}
978
979static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
980{
981 ppc_addi (s, reg, reg, val);
982}
983
c596defd 984static void tcg_out_cmp (TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
985 int const_arg2, int cr)
2662e13f 986{
2662e13f
FB		 987 int imm;
988 uint32_t op;
989
2662e13f 990 switch (cond) {
f3f478a7
FB		 991 case TCG_COND_EQ:
992 case TCG_COND_NE:
993 if (const_arg2) {
994 if ((int16_t) arg2 == arg2) {
995 op = CMPI;
996 imm = 1;
997 break;
998 }
999 else if ((uint16_t) arg2 == arg2) {
1000 op = CMPLI;
1001 imm = 1;
1002 break;
1003 }
1004 }
1005 op = CMPL;
1006 imm = 0;
1007 break;
1008
1009 case TCG_COND_LT:
1010 case TCG_COND_GE:
1011 case TCG_COND_LE:
1012 case TCG_COND_GT:
1013 if (const_arg2) {
1014 if ((int16_t) arg2 == arg2) {
1015 op = CMPI;
1016 imm = 1;
1017 break;
1018 }
1019 }
1020 op = CMP;
1021 imm = 0;
1022 break;
1023
1024 case TCG_COND_LTU:
1025 case TCG_COND_GEU:
1026 case TCG_COND_LEU:
1027 case TCG_COND_GTU:
1028 if (const_arg2) {
1029 if ((uint16_t) arg2 == arg2) {
1030 op = CMPLI;
1031 imm = 1;
1032 break;
1033 }
1034 }
1035 op = CMPL;
1036 imm = 0;
1037 break;
1038
2662e13f
FB		 1039 default:
1040 tcg_abort ();
1041 }
c596defd 1042 op |= BF (cr);
2662e13f
FB		 1043
1044 if (imm)
1045 tcg_out32 (s, op | RA (arg1) | (arg2 & 0xffff));
1046 else {
1047 if (const_arg2) {
1048 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
1049 tcg_out32 (s, op | RA (arg1) | RB (0));
1050 }
1051 else
1052 tcg_out32 (s, op | RA (arg1) | RB (arg2));
1053 }
1054
c596defd 1055}
1056
1057static void tcg_out_bc (TCGContext *s, int bc, int label_index)
1058{
1059 TCGLabel *l = &s->labels[label_index];
1060
0a878c47 1061 if (l->has_value)
c596defd 1062 tcg_out32 (s, bc | reloc_pc14_val (s->code_ptr, l->u.value));
2662e13f 1063 else {
0a878c47 1064 uint16_t val = *(uint16_t *) &s->code_ptr[2];
1065
1066 /* Thanks to Andrzej Zaborowski */
c596defd 1067 tcg_out32 (s, bc | (val & 0xfffc));
2662e13f
FB		 1068 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL14, label_index, 0);
1069 }
1070}
1071
b0809bf7 1072static void tcg_out_cr7eq_from_cond (TCGContext *s, const TCGArg *args,
1073 const int *const_args)
c596defd 1074{
8a56e840
RH		 1075 TCGCond cond = args[4];
1076 int op;
c596defd 1077 struct { int bit1; int bit2; int cond2; } bits[] = {
1078 [TCG_COND_LT ] = { CR_LT, CR_LT, TCG_COND_LT },
1079 [TCG_COND_LE ] = { CR_LT, CR_GT, TCG_COND_LT },
1080 [TCG_COND_GT ] = { CR_GT, CR_GT, TCG_COND_GT },
1081 [TCG_COND_GE ] = { CR_GT, CR_LT, TCG_COND_GT },
1082 [TCG_COND_LTU] = { CR_LT, CR_LT, TCG_COND_LTU },
1083 [TCG_COND_LEU] = { CR_LT, CR_GT, TCG_COND_LTU },
1084 [TCG_COND_GTU] = { CR_GT, CR_GT, TCG_COND_GTU },
1085 [TCG_COND_GEU] = { CR_GT, CR_LT, TCG_COND_GTU },
1086 }, *b = &bits[cond];
1087
1088 switch (cond) {
2662e13f 1089 case TCG_COND_EQ:
2662e13f 1090 case TCG_COND_NE:
e924c485 1091 op = (cond == TCG_COND_EQ) ? CRAND : CRNAND;
1092 tcg_out_cmp (s, cond, args[0], args[2], const_args[2], 6);
1093 tcg_out_cmp (s, cond, args[1], args[3], const_args[3], 7);
1094 tcg_out32 (s, op | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
2662e13f
FB		 1095 break;
1096 case TCG_COND_LT:
2662e13f 1097 case TCG_COND_LE:
2662e13f 1098 case TCG_COND_GT:
2662e13f 1099 case TCG_COND_GE:
2662e13f 1100 case TCG_COND_LTU:
2662e13f 1101 case TCG_COND_LEU:
2662e13f 1102 case TCG_COND_GTU:
2662e13f 1103 case TCG_COND_GEU:
c596defd 1104 op = (b->bit1 != b->bit2) ? CRANDC : CRAND;
1105 tcg_out_cmp (s, b->cond2, args[1], args[3], const_args[3], 5);
1106 tcg_out_cmp (s, TCG_COND_EQ, args[1], args[3], const_args[3], 6);
1107 tcg_out_cmp (s, cond, args[0], args[2], const_args[2], 7);
1108 tcg_out32 (s, op | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, b->bit2));
1109 tcg_out32 (s, CROR | BT (7, CR_EQ) | BA (5, b->bit1) | BB (7, CR_EQ));
2662e13f
FB		 1110 break;
1111 default:
1112 tcg_abort();
1113 }
b0809bf7 1114}
1115
8a56e840 1116static void tcg_out_setcond (TCGContext *s, TCGCond cond, TCGArg arg0,
b0809bf7 1117 TCGArg arg1, TCGArg arg2, int const_arg2)
1118{
1119 int crop, sh, arg;
1120
1121 switch (cond) {
1122 case TCG_COND_EQ:
1123 if (const_arg2) {
1124 if (!arg2) {
1125 arg = arg1;
1126 }
1127 else {
1128 arg = 0;
1129 if ((uint16_t) arg2 == arg2) {
1130 tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
1131 }
1132 else {
1133 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
1134 tcg_out32 (s, XOR | SAB (arg1, 0, 0));
1135 }
1136 }
1137 }
1138 else {
1139 arg = 0;
1140 tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
1141 }
1142 tcg_out32 (s, CNTLZW | RS (arg) | RA (0));
1143 tcg_out32 (s, (RLWINM
1144 | RA (arg0)
1145 | RS (0)
1146 | SH (27)
1147 | MB (5)
1148 | ME (31)
1149 )
1150 );
27a7797b 1151 break;
b0809bf7 1152
1153 case TCG_COND_NE:
1154 if (const_arg2) {
1155 if (!arg2) {
1156 arg = arg1;
1157 }
1158 else {
1159 arg = 0;
1160 if ((uint16_t) arg2 == arg2) {
1161 tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
1162 }
1163 else {
1164 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
1165 tcg_out32 (s, XOR | SAB (arg1, 0, 0));
1166 }
1167 }
1168 }
1169 else {
1170 arg = 0;
1171 tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
1172 }
1173
1174 if (arg == arg1 && arg1 == arg0) {
1175 tcg_out32 (s, ADDIC | RT (0) | RA (arg) | 0xffff);
1176 tcg_out32 (s, SUBFE | TAB (arg0, 0, arg));
1177 }
1178 else {
1179 tcg_out32 (s, ADDIC | RT (arg0) | RA (arg) | 0xffff);
1180 tcg_out32 (s, SUBFE | TAB (arg0, arg0, arg));
1181 }
27a7797b 1182 break;
1183
1184 case TCG_COND_GT:
1185 case TCG_COND_GTU:
1186 sh = 30;
1187 crop = 0;
1188 goto crtest;
b0809bf7 1189
b0809bf7 1190 case TCG_COND_LT:
27a7797b 1191 case TCG_COND_LTU:
b0809bf7 1192 sh = 29;
1193 crop = 0;
27a7797b 1194 goto crtest;
b0809bf7 1195
b0809bf7 1196 case TCG_COND_GE:
27a7797b 1197 case TCG_COND_GEU:
b0809bf7 1198 sh = 31;
1199 crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_LT) | BB (7, CR_LT);
27a7797b 1200 goto crtest;
b0809bf7 1201
b0809bf7 1202 case TCG_COND_LE:
27a7797b 1203 case TCG_COND_LEU:
b0809bf7 1204 sh = 31;
1205 crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_GT) | BB (7, CR_GT);
27a7797b 1206 crtest:
1207 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7);
1208 if (crop) tcg_out32 (s, crop);
1209 tcg_out32 (s, MFCR | RT (0));
1210 tcg_out32 (s, (RLWINM
1211 | RA (arg0)
1212 | RS (0)
1213 | SH (sh)
1214 | MB (31)
1215 | ME (31)
1216 )
1217 );
b0809bf7 1218 break;
1219
1220 default:
1221 tcg_abort ();
1222 }
b0809bf7 1223}
1224
1225static void tcg_out_setcond2 (TCGContext *s, const TCGArg *args,
1226 const int *const_args)
1227{
1228 tcg_out_cr7eq_from_cond (s, args + 1, const_args + 1);
1229 tcg_out32 (s, MFCR | RT (0));
1230 tcg_out32 (s, (RLWINM
1231 | RA (args[0])
1232 | RS (0)
1233 | SH (31)
1234 | MB (31)
1235 | ME (31)
1236 )
1237 );
1238}
1239
8a56e840 1240static void tcg_out_brcond (TCGContext *s, TCGCond cond,
b0809bf7 1241 TCGArg arg1, TCGArg arg2, int const_arg2,
1242 int label_index)
1243{
1244 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7);
1245 tcg_out_bc (s, tcg_to_bc[cond], label_index);
1246}
1247
1248/* XXX: we implement it at the target level to avoid having to
1249 handle cross basic blocks temporaries */
1250static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
1251 const int *const_args)
1252{
1253 tcg_out_cr7eq_from_cond (s, args, const_args);
1254 tcg_out_bc (s, (BC | BI (7, CR_EQ) | BO_COND_TRUE), args[5]);
2662e13f
FB		 1255}
1256
52781543 1257void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr)
1258{
1259 uint32_t *ptr;
1260 long disp = addr - jmp_addr;
1261 unsigned long patch_size;
1262
1263 ptr = (uint32_t *)jmp_addr;
1264
1265 if ((disp << 6) >> 6 != disp) {
1266 ptr[0] = 0x3c000000 | (addr >> 16); /* lis 0,addr@ha */
1267 ptr[1] = 0x60000000 | (addr & 0xffff); /* la 0,addr@l(0) */
1268 ptr[2] = 0x7c0903a6; /* mtctr 0 */
1269 ptr[3] = 0x4e800420; /* brctr */
1270 patch_size = 16;
1271 } else {
1272 /* patch the branch destination */
1273 if (disp != 16) {
1274 *ptr = 0x48000000 | (disp & 0x03fffffc); /* b disp */
1275 patch_size = 4;
1276 } else {
1277 ptr[0] = 0x60000000; /* nop */
1278 ptr[1] = 0x60000000;
1279 ptr[2] = 0x60000000;
1280 ptr[3] = 0x60000000;
1281 patch_size = 16;
1282 }
1283 }
1284 /* flush icache */
1285 flush_icache_range(jmp_addr, jmp_addr + patch_size);
1286}
1287
a9751609 1288static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
2662e13f
FB		 1289 const int *const_args)
1290{
1291 switch (opc) {
1292 case INDEX_op_exit_tb:
1293 tcg_out_movi (s, TCG_TYPE_I32, TCG_REG_R3, args[0]);
932a6909 1294 tcg_out_b (s, 0, (tcg_target_long) tb_ret_addr);
2662e13f
FB		 1295 break;
1296 case INDEX_op_goto_tb:
1297 if (s->tb_jmp_offset) {
1298 /* direct jump method */
932a6909 1299
2662e13f 1300 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
0a878c47 1301 s->code_ptr += 16;
932a6909
FB		 1302 }
1303 else {
2662e13f
FB		 1304 tcg_abort ();
1305 }
1306 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1307 break;
1308 case INDEX_op_br:
1309 {
1310 TCGLabel *l = &s->labels[args[0]];
1311
1312 if (l->has_value) {
932a6909 1313 tcg_out_b (s, 0, l->u.value);
2662e13f
FB		 1314 }
1315 else {
0a878c47 1316 uint32_t val = *(uint32_t *) s->code_ptr;
1317
1318 /* Thanks to Andrzej Zaborowski */
1319 tcg_out32 (s, B | (val & 0x3fffffc));
2662e13f
FB		 1320 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL24, args[0], 0);
1321 }
1322 }
1323 break;
1324 case INDEX_op_call:
b29fe3ed 1325 tcg_out_call (s, args[0], const_args[0]);
2662e13f
FB		 1326 break;
1327 case INDEX_op_jmp:
1328 if (const_args[0]) {
932a6909 1329 tcg_out_b (s, 0, args[0]);
2662e13f
FB		 1330 }
1331 else {
1332 tcg_out32 (s, MTSPR | RS (args[0]) | CTR);
1333 tcg_out32 (s, BCCTR | BO_ALWAYS);
1334 }
1335 break;
1336 case INDEX_op_movi_i32:
1337 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1338 break;
1339 case INDEX_op_ld8u_i32:
1340 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1341 break;
1342 case INDEX_op_ld8s_i32:
1343 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1344 tcg_out32 (s, EXTSB | RS (args[0]) | RA (args[0]));
1345 break;
1346 case INDEX_op_ld16u_i32:
1347 tcg_out_ldst (s, args[0], args[1], args[2], LHZ, LHZX);
1348 break;
1349 case INDEX_op_ld16s_i32:
1350 tcg_out_ldst (s, args[0], args[1], args[2], LHA, LHAX);
1351 break;
1352 case INDEX_op_ld_i32:
1353 tcg_out_ldst (s, args[0], args[1], args[2], LWZ, LWZX);
1354 break;
1355 case INDEX_op_st8_i32:
1356 tcg_out_ldst (s, args[0], args[1], args[2], STB, STBX);
1357 break;
1358 case INDEX_op_st16_i32:
1359 tcg_out_ldst (s, args[0], args[1], args[2], STH, STHX);
1360 break;
1361 case INDEX_op_st_i32:
1362 tcg_out_ldst (s, args[0], args[1], args[2], STW, STWX);
1363 break;
1364
1365 case INDEX_op_add_i32:
1366 if (const_args[2])
1367 ppc_addi (s, args[0], args[1], args[2]);
1368 else
1369 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1370 break;
1371 case INDEX_op_sub_i32:
1372 if (const_args[2])
1373 ppc_addi (s, args[0], args[1], -args[2]);
1374 else
1375 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1376 break;
1377
1378 case INDEX_op_and_i32:
1379 if (const_args[2]) {
c45851c4 1380 uint32_t c;
1381
1382 c = args[2];
1383
1384 if (!c) {
1385 tcg_out_movi (s, TCG_TYPE_I32, args[0], 0);
1386 break;
1387 }
1388#ifdef __PPU__
1389 uint32_t t, n;
1390 int mb, me;
1391
1392 n = c ^ -(c & 1);
1393 t = n + (n & -n);
1394
1395 if ((t & (t - 1)) == 0) {
1396 int lzc, tzc;
1397
1398 if ((c & 0x80000001) == 0x80000001) {
1399 lzc = clz32 (n);
1400 tzc = ctz32 (n);
1401
1402 mb = 32 - tzc;
1403 me = lzc - 1;
1404 }
1405 else {
1406 lzc = clz32 (c);
1407 tzc = ctz32 (c);
1408
1409 mb = lzc;
1410 me = 31 - tzc;
1411 }
1412
1413 tcg_out32 (s, (RLWINM
1414 | RA (args[0])
1415 | RS (args[1])
1416 | SH (0)
1417 | MB (mb)
1418 | ME (me)
1419 )
1420 );
1421 }
1422 else
1423#endif /* !__PPU__ */
1424 {
1425 if ((c & 0xffff) == c)
1426 tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | c);
1427 else if ((c & 0xffff0000) == c)
1428 tcg_out32 (s, ANDIS | RS (args[1]) | RA (args[0])
1429 | ((c >> 16) & 0xffff));
1430 else {
1431 tcg_out_movi (s, TCG_TYPE_I32, 0, c);
1432 tcg_out32 (s, AND | SAB (args[1], args[0], 0));
1433 }
2662e13f
FB		 1434 }
1435 }
1436 else
1437 tcg_out32 (s, AND | SAB (args[1], args[0], args[2]));
1438 break;
1439 case INDEX_op_or_i32:
1440 if (const_args[2]) {
000a2d86 1441 if (args[2] & 0xffff) {
1442 tcg_out32 (s, ORI | RS (args[1]) | RA (args[0])
1443 | (args[2] & 0xffff));
1444 if (args[2] >> 16)
1445 tcg_out32 (s, ORIS | RS (args[0]) | RA (args[0])
2662e13f 1446 | ((args[2] >> 16) & 0xffff));
2662e13f
FB		 1447 }
1448 else {
000a2d86 1449 tcg_out32 (s, ORIS | RS (args[1]) | RA (args[0])
1450 | ((args[2] >> 16) & 0xffff));
2662e13f
FB		 1451 }
1452 }
1453 else
1454 tcg_out32 (s, OR | SAB (args[1], args[0], args[2]));
1455 break;
1456 case INDEX_op_xor_i32:
1457 if (const_args[2]) {
000a2d86 1458 if ((args[2] & 0xffff) == args[2])
1459 tcg_out32 (s, XORI | RS (args[1]) | RA (args[0])
1460 | (args[2] & 0xffff));
1461 else if ((args[2] & 0xffff0000) == args[2])
1462 tcg_out32 (s, XORIS | RS (args[1]) | RA (args[0])
1463 | ((args[2] >> 16) & 0xffff));
2662e13f 1464 else {
000a2d86 1465 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1466 tcg_out32 (s, XOR | SAB (args[1], args[0], 0));
2662e13f
FB		 1467 }
1468 }
1469 else
1470 tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
1471 break;
65fe043e 1472 case INDEX_op_andc_i32:
1473 tcg_out32 (s, ANDC | SAB (args[1], args[0], args[2]));
1474 break;
1475 case INDEX_op_orc_i32:
1476 tcg_out32 (s, ORC | SAB (args[1], args[0], args[2]));
1477 break;
2662e13f
FB		 1478
1479 case INDEX_op_mul_i32:
1480 if (const_args[2]) {
1481 if (args[2] == (int16_t) args[2])
1482 tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1])
1483 | (args[2] & 0xffff));
1484 else {
1485 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1486 tcg_out32 (s, MULLW | TAB (args[0], args[1], 0));
1487 }
1488 }
1489 else
1490 tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2]));
1491 break;
77b73de6 1492
1493 case INDEX_op_div_i32:
1494 tcg_out32 (s, DIVW | TAB (args[0], args[1], args[2]));
1495 break;
1496
1497 case INDEX_op_divu_i32:
1498 tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
1499 break;
1500
1501 case INDEX_op_rem_i32:
1502 tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
1503 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1504 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1505 break;
1506
1507 case INDEX_op_remu_i32:
1508 tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
1509 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1510 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1511 break;
1512
2662e13f
FB		 1513 case INDEX_op_mulu2_i32:
1514 if (args[0] == args[2] || args[0] == args[3]) {
1515 tcg_out32 (s, MULLW | TAB (0, args[2], args[3]));
1516 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1517 tcg_out_mov (s, args[0], 0);
1518 }
1519 else {
1520 tcg_out32 (s, MULLW | TAB (args[0], args[2], args[3]));
1521 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1522 }
1523 break;
2662e13f
FB		 1524
1525 case INDEX_op_shl_i32:
1526 if (const_args[2]) {
000a2d86 1527 tcg_out32 (s, (RLWINM
1528 | RA (args[0])
1529 | RS (args[1])
1530 | SH (args[2])
1531 | MB (0)
1532 | ME (31 - args[2])
1533 )
1534 );
2662e13f
FB		 1535 }
1536 else
1537 tcg_out32 (s, SLW | SAB (args[1], args[0], args[2]));
1538 break;
1539 case INDEX_op_shr_i32:
1540 if (const_args[2]) {
000a2d86 1541 tcg_out32 (s, (RLWINM
1542 | RA (args[0])
1543 | RS (args[1])
1544 | SH (32 - args[2])
1545 | MB (args[2])
1546 | ME (31)
1547 )
1548 );
2662e13f
FB		 1549 }
1550 else
1551 tcg_out32 (s, SRW | SAB (args[1], args[0], args[2]));
1552 break;
1553 case INDEX_op_sar_i32:
1554 if (const_args[2])
1555 tcg_out32 (s, SRAWI | RS (args[1]) | RA (args[0]) | SH (args[2]));
1556 else
1557 tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2]));
1558 break;
65fe043e 1559 case INDEX_op_rotl_i32:
1560 {
1561 int op = 0
1562 | RA (args[0])
1563 | RS (args[1])
1564 | MB (0)
1565 | ME (31)
1566 | (const_args[2] ? RLWINM | SH (args[2])
1567 : RLWNM | RB (args[2]))
1568 ;
1569 tcg_out32 (s, op);
1570 }
1571 break;
1572 case INDEX_op_rotr_i32:
1573 if (const_args[2]) {
1574 if (!args[2]) {
98b8d951 1575 tcg_out_mov (s, args[0], args[1]);
65fe043e 1576 }
1577 else {
1578 tcg_out32 (s, RLWINM
1579 | RA (args[0])
1580 | RS (args[1])
1581 | SH (32 - args[2])
1582 | MB (0)
1583 | ME (31)
1584 );
1585 }
1586 }
1587 else {
d616cf1d 1588 tcg_out32 (s, SUBFIC | RT (0) | RA (args[2]) | 32);
65fe043e 1589 tcg_out32 (s, RLWNM
1590 | RA (args[0])
1591 | RS (args[1])
1592 | RB (0)
1593 | MB (0)
1594 | ME (31)
1595 );
1596 }
1597 break;
2662e13f
FB		 1598
1599 case INDEX_op_add2_i32:
1600 if (args[0] == args[3] || args[0] == args[5]) {
1601 tcg_out32 (s, ADDC | TAB (0, args[2], args[4]));
1602 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1603 tcg_out_mov (s, args[0], 0);
1604 }
1605 else {
1606 tcg_out32 (s, ADDC | TAB (args[0], args[2], args[4]));
1607 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1608 }
1609 break;
1610 case INDEX_op_sub2_i32:
1611 if (args[0] == args[3] || args[0] == args[5]) {
1612 tcg_out32 (s, SUBFC | TAB (0, args[4], args[2]));
1613 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1614 tcg_out_mov (s, args[0], 0);
1615 }
1616 else {
1617 tcg_out32 (s, SUBFC | TAB (args[0], args[4], args[2]));
1618 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1619 }
1620 break;
1621
1622 case INDEX_op_brcond_i32:
1623 /*
1624 args[0] = r0
1625 args[1] = r1
1626 args[2] = cond
1627 args[3] = r1 is const
1628 args[4] = label_index
1629 */
1630 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3]);
1631 break;
1632 case INDEX_op_brcond2_i32:
1633 tcg_out_brcond2(s, args, const_args);
1634 break;
1635
1636 case INDEX_op_neg_i32:
1637 tcg_out32 (s, NEG | RT (args[0]) | RA (args[1]));
1638 break;
1639
65fe043e 1640 case INDEX_op_not_i32:
36368cf0 1641 tcg_out32 (s, NOR | SAB (args[1], args[0], args[1]));
65fe043e 1642 break;
1643
2662e13f
FB		 1644 case INDEX_op_qemu_ld8u:
1645 tcg_out_qemu_ld(s, args, 0);
1646 break;
1647 case INDEX_op_qemu_ld8s:
1648 tcg_out_qemu_ld(s, args, 0 | 4);
1649 break;
1650 case INDEX_op_qemu_ld16u:
1651 tcg_out_qemu_ld(s, args, 1);
1652 break;
1653 case INDEX_op_qemu_ld16s:
1654 tcg_out_qemu_ld(s, args, 1 | 4);
1655 break;
86feb1c8 1656 case INDEX_op_qemu_ld32:
2662e13f
FB		 1657 tcg_out_qemu_ld(s, args, 2);
1658 break;
1659 case INDEX_op_qemu_ld64:
1660 tcg_out_qemu_ld(s, args, 3);
1661 break;
1662 case INDEX_op_qemu_st8:
1663 tcg_out_qemu_st(s, args, 0);
1664 break;
1665 case INDEX_op_qemu_st16:
1666 tcg_out_qemu_st(s, args, 1);
1667 break;
1668 case INDEX_op_qemu_st32:
1669 tcg_out_qemu_st(s, args, 2);
1670 break;
1671 case INDEX_op_qemu_st64:
1672 tcg_out_qemu_st(s, args, 3);
1673 break;
1674
e46b9681 1675 case INDEX_op_ext8s_i32:
1676 tcg_out32 (s, EXTSB | RS (args[1]) | RA (args[0]));
1677 break;
65fe043e 1678 case INDEX_op_ext8u_i32:
1679 tcg_out32 (s, RLWINM
1680 | RA (args[0])
1681 | RS (args[1])
1682 | SH (0)
1683 | MB (24)
1684 | ME (31)
1685 );
1686 break;
e46b9681 1687 case INDEX_op_ext16s_i32:
1688 tcg_out32 (s, EXTSH | RS (args[1]) | RA (args[0]));
1689 break;
65fe043e 1690 case INDEX_op_ext16u_i32:
1691 tcg_out32 (s, RLWINM
1692 | RA (args[0])
1693 | RS (args[1])
1694 | SH (0)
1695 | MB (16)
1696 | ME (31)
1697 );
1698 break;
e46b9681 1699
b0809bf7 1700 case INDEX_op_setcond_i32:
1701 tcg_out_setcond (s, args[3], args[0], args[1], args[2], const_args[2]);
1702 break;
1703 case INDEX_op_setcond2_i32:
1704 tcg_out_setcond2 (s, args, const_args);
1705 break;
1706
2662e13f
FB		 1707 default:
1708 tcg_dump_ops (s, stderr);
1709 tcg_abort ();
1710 }
1711}
1712
1713static const TCGTargetOpDef ppc_op_defs[] = {
1714 { INDEX_op_exit_tb, { } },
1715 { INDEX_op_goto_tb, { } },
932a6909
FB		 1716 { INDEX_op_call, { "ri" } },
1717 { INDEX_op_jmp, { "ri" } },
2662e13f
FB		 1718 { INDEX_op_br, { } },
1719
1720 { INDEX_op_mov_i32, { "r", "r" } },
1721 { INDEX_op_movi_i32, { "r" } },
1722 { INDEX_op_ld8u_i32, { "r", "r" } },
1723 { INDEX_op_ld8s_i32, { "r", "r" } },
1724 { INDEX_op_ld16u_i32, { "r", "r" } },
1725 { INDEX_op_ld16s_i32, { "r", "r" } },
1726 { INDEX_op_ld_i32, { "r", "r" } },
1727 { INDEX_op_st8_i32, { "r", "r" } },
1728 { INDEX_op_st16_i32, { "r", "r" } },
1729 { INDEX_op_st_i32, { "r", "r" } },
1730
1731 { INDEX_op_add_i32, { "r", "r", "ri" } },
1732 { INDEX_op_mul_i32, { "r", "r", "ri" } },
77b73de6 1733 { INDEX_op_div_i32, { "r", "r", "r" } },
1734 { INDEX_op_divu_i32, { "r", "r", "r" } },
1735 { INDEX_op_rem_i32, { "r", "r", "r" } },
1736 { INDEX_op_remu_i32, { "r", "r", "r" } },
2662e13f 1737 { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
2662e13f
FB		 1738 { INDEX_op_sub_i32, { "r", "r", "ri" } },
1739 { INDEX_op_and_i32, { "r", "r", "ri" } },
1740 { INDEX_op_or_i32, { "r", "r", "ri" } },
1741 { INDEX_op_xor_i32, { "r", "r", "ri" } },
1742
1743 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1744 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1745 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1746
65fe043e 1747 { INDEX_op_rotl_i32, { "r", "r", "ri" } },
1748 { INDEX_op_rotr_i32, { "r", "r", "ri" } },
1749
2662e13f
FB		 1750 { INDEX_op_brcond_i32, { "r", "ri" } },
1751
1752 { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1753 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1754 { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
1755
1756 { INDEX_op_neg_i32, { "r", "r" } },
65fe043e 1757 { INDEX_op_not_i32, { "r", "r" } },
1758
1759 { INDEX_op_andc_i32, { "r", "r", "r" } },
1760 { INDEX_op_orc_i32, { "r", "r", "r" } },
2662e13f 1761
b0809bf7 1762 { INDEX_op_setcond_i32, { "r", "r", "ri" } },
1763 { INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },
1764
2662e13f
FB		 1765#if TARGET_LONG_BITS == 32
1766 { INDEX_op_qemu_ld8u, { "r", "L" } },
1767 { INDEX_op_qemu_ld8s, { "r", "L" } },
1768 { INDEX_op_qemu_ld16u, { "r", "L" } },
1769 { INDEX_op_qemu_ld16s, { "r", "L" } },
86feb1c8 1770 { INDEX_op_qemu_ld32, { "r", "L" } },
2662e13f
FB		 1771 { INDEX_op_qemu_ld64, { "r", "r", "L" } },
1772
1773 { INDEX_op_qemu_st8, { "K", "K" } },
1774 { INDEX_op_qemu_st16, { "K", "K" } },
1775 { INDEX_op_qemu_st32, { "K", "K" } },
1776 { INDEX_op_qemu_st64, { "M", "M", "M" } },
1777#else
1778 { INDEX_op_qemu_ld8u, { "r", "L", "L" } },
1779 { INDEX_op_qemu_ld8s, { "r", "L", "L" } },
1780 { INDEX_op_qemu_ld16u, { "r", "L", "L" } },
1781 { INDEX_op_qemu_ld16s, { "r", "L", "L" } },
86feb1c8 1782 { INDEX_op_qemu_ld32, { "r", "L", "L" } },
2662e13f
FB		 1783 { INDEX_op_qemu_ld64, { "r", "L", "L", "L" } },
1784
1785 { INDEX_op_qemu_st8, { "K", "K", "K" } },
1786 { INDEX_op_qemu_st16, { "K", "K", "K" } },
1787 { INDEX_op_qemu_st32, { "K", "K", "K" } },
1788 { INDEX_op_qemu_st64, { "M", "M", "M", "M" } },
1789#endif
1790
e46b9681 1791 { INDEX_op_ext8s_i32, { "r", "r" } },
65fe043e 1792 { INDEX_op_ext8u_i32, { "r", "r" } },
e46b9681 1793 { INDEX_op_ext16s_i32, { "r", "r" } },
65fe043e 1794 { INDEX_op_ext16u_i32, { "r", "r" } },
e46b9681 1795
2662e13f
FB		 1796 { -1 },
1797};
1798
1799void tcg_target_init(TCGContext *s)
1800{
1801 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1802 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1803 (1 << TCG_REG_R0) |
6ec85236 1804#ifdef _CALL_DARWIN
f9bf2987 1805 (1 << TCG_REG_R2) |
1806#endif
2662e13f
FB		 1807 (1 << TCG_REG_R3) |
1808 (1 << TCG_REG_R4) |
1809 (1 << TCG_REG_R5) |
1810 (1 << TCG_REG_R6) |
1811 (1 << TCG_REG_R7) |
1812 (1 << TCG_REG_R8) |
1813 (1 << TCG_REG_R9) |
1814 (1 << TCG_REG_R10) |
1815 (1 << TCG_REG_R11) |
1816 (1 << TCG_REG_R12)
1817 );
1818
1819 tcg_regset_clear(s->reserved_regs);
1820 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);
1821 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1);
6ec85236 1822#ifndef _CALL_DARWIN
2662e13f 1823 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2);
f9bf2987 1824#endif
6ec85236 1825#ifdef _CALL_SYSV
5db3ee79 1826 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13);
1827#endif
f6548c0a 1828#ifdef CONFIG_USE_GUEST_BASE
1829 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
1830#endif
2662e13f
FB		 1831
1832 tcg_add_target_add_op_defs(ppc_op_defs);
1833}
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