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tcg/aarch64: Use softmmu fast path for unaligned accesses
[mirror_qemu.git] / tcg / ppc / tcg-target.c
CommitLineData
810260a8 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
9ecefc84
RH		 25#include "tcg-be-ldst.h"
26
ffcfbece
RH		 27#if defined _CALL_DARWIN || defined __APPLE__
28#define TCG_TARGET_CALL_DARWIN
29#endif
7f25c469
RH		 30#ifdef _CALL_SYSV
31# define TCG_TARGET_CALL_ALIGN_ARGS 1
32#endif
ffcfbece 33
dfca1778
RH		 34/* For some memory operations, we need a scratch that isn't R0. For the AIX
35 calling convention, we can re-use the TOC register since we'll be reloading
36 it at every call. Otherwise R12 will do nicely as neither a call-saved
37 register nor a parameter register. */
38#ifdef _CALL_AIX
39# define TCG_REG_TMP1 TCG_REG_R2
40#else
41# define TCG_REG_TMP1 TCG_REG_R12
42#endif
43
a84ac4cb
RH		 44/* For the 64-bit target, we don't like the 5 insn sequence needed to build
45 full 64-bit addresses. Better to have a base register to which we can
46 apply a 32-bit displacement.
47
48 There are generally three items of interest:
49 (1) helper functions in the main executable,
50 (2) TranslationBlock data structures,
51 (3) the return address in the epilogue.
52
53 For user-only, we USE_STATIC_CODE_GEN_BUFFER, so the code_gen_buffer
54 will be inside the main executable, and thus near enough to make a
55 pointer to the epilogue be within 2GB of all helper functions.
56
57 For softmmu, we'll let the kernel choose the address of code_gen_buffer,
58 and odds are it'll be somewhere close to the main malloc arena, and so
59 a pointer to the epilogue will be within 2GB of the TranslationBlocks.
60
61 For --enable-pie, everything will be kinda near everything else,
62 somewhere in high memory.
63
64 Thus we choose to keep the return address in a call-saved register. */
65#define TCG_REG_RA TCG_REG_R31
66#define USE_REG_RA (TCG_TARGET_REG_BITS == 64)
67
de3d636d
RH		 68/* Shorthand for size of a pointer. Avoid promotion to unsigned. */
69#define SZP ((int)sizeof(void *))
70
4c3831a0
RH		 71/* Shorthand for size of a register. */
72#define SZR (TCG_TARGET_REG_BITS / 8)
73
3d582c61
RH		 74#define TCG_CT_CONST_S16 0x100
75#define TCG_CT_CONST_U16 0x200
76#define TCG_CT_CONST_S32 0x400
77#define TCG_CT_CONST_U32 0x800
78#define TCG_CT_CONST_ZERO 0x1000
6c858762 79#define TCG_CT_CONST_MONE 0x2000
fe6f943f 80
e083c4a2 81static tcg_insn_unit *tb_ret_addr;
810260a8 82
f6548c0a 83#ifndef GUEST_BASE
84#define GUEST_BASE 0
85#endif
86
cd629de1 87#include "elf.h"
1e6e9aca
RH		 88static bool have_isa_2_06;
89#define HAVE_ISA_2_06 have_isa_2_06
90#define HAVE_ISEL have_isa_2_06
49d9870a 91
f6548c0a 92#ifdef CONFIG_USE_GUEST_BASE
93#define TCG_GUEST_BASE_REG 30
94#else
95#define TCG_GUEST_BASE_REG 0
96#endif
97
d4a9eb1f 98#ifndef NDEBUG
810260a8 99static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
100 "r0",
101 "r1",
98926b0a 102 "r2",
810260a8 103 "r3",
104 "r4",
105 "r5",
106 "r6",
107 "r7",
108 "r8",
109 "r9",
110 "r10",
111 "r11",
112 "r12",
113 "r13",
114 "r14",
115 "r15",
116 "r16",
117 "r17",
118 "r18",
119 "r19",
120 "r20",
121 "r21",
122 "r22",
123 "r23",
124 "r24",
125 "r25",
126 "r26",
127 "r27",
128 "r28",
129 "r29",
130 "r30",
131 "r31"
132};
d4a9eb1f 133#endif
810260a8 134
135static const int tcg_target_reg_alloc_order[] = {
5e1702b0 136 TCG_REG_R14, /* call saved registers */
810260a8 137 TCG_REG_R15,
138 TCG_REG_R16,
139 TCG_REG_R17,
140 TCG_REG_R18,
141 TCG_REG_R19,
142 TCG_REG_R20,
143 TCG_REG_R21,
144 TCG_REG_R22,
145 TCG_REG_R23,
5e1702b0
RH		 146 TCG_REG_R24,
147 TCG_REG_R25,
148 TCG_REG_R26,
149 TCG_REG_R27,
810260a8 150 TCG_REG_R28,
151 TCG_REG_R29,
152 TCG_REG_R30,
153 TCG_REG_R31,
5e1702b0
RH		 154 TCG_REG_R12, /* call clobbered, non-arguments */
155 TCG_REG_R11,
dfca1778
RH		 156 TCG_REG_R2,
157 TCG_REG_R13,
5e1702b0 158 TCG_REG_R10, /* call clobbered, arguments */
810260a8 159 TCG_REG_R9,
5e1702b0
RH		 160 TCG_REG_R8,
161 TCG_REG_R7,
162 TCG_REG_R6,
163 TCG_REG_R5,
164 TCG_REG_R4,
165 TCG_REG_R3,
810260a8 166};
167
168static const int tcg_target_call_iarg_regs[] = {
169 TCG_REG_R3,
170 TCG_REG_R4,
171 TCG_REG_R5,
172 TCG_REG_R6,
173 TCG_REG_R7,
174 TCG_REG_R8,
175 TCG_REG_R9,
176 TCG_REG_R10
177};
178
be9c4183 179static const int tcg_target_call_oarg_regs[] = {
dfca1778
RH		 180 TCG_REG_R3,
181 TCG_REG_R4
810260a8 182};
183
184static const int tcg_target_callee_save_regs[] = {
dfca1778 185#ifdef TCG_TARGET_CALL_DARWIN
5d7ff5bb
AF		 186 TCG_REG_R11,
187#endif
810260a8 188 TCG_REG_R14,
189 TCG_REG_R15,
190 TCG_REG_R16,
191 TCG_REG_R17,
192 TCG_REG_R18,
193 TCG_REG_R19,
194 TCG_REG_R20,
195 TCG_REG_R21,
196 TCG_REG_R22,
197 TCG_REG_R23,
095271d4 198 TCG_REG_R24,
199 TCG_REG_R25,
200 TCG_REG_R26,
cea5f9a2 201 TCG_REG_R27, /* currently used for the global env */
810260a8 202 TCG_REG_R28,
203 TCG_REG_R29,
204 TCG_REG_R30,
205 TCG_REG_R31
206};
207
b0940da0
RH		 208static inline bool in_range_b(tcg_target_long target)
209{
210 return target == sextract64(target, 0, 26);
211}
212
e083c4a2 213static uint32_t reloc_pc24_val(tcg_insn_unit *pc, tcg_insn_unit *target)
810260a8 214{
e083c4a2 215 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
b0940da0 216 assert(in_range_b(disp));
810260a8 217 return disp & 0x3fffffc;
218}
219
e083c4a2 220static void reloc_pc24(tcg_insn_unit *pc, tcg_insn_unit *target)
810260a8 221{
e083c4a2 222 *pc = (*pc & ~0x3fffffc) | reloc_pc24_val(pc, target);
810260a8 223}
224
e083c4a2 225static uint16_t reloc_pc14_val(tcg_insn_unit *pc, tcg_insn_unit *target)
810260a8 226{
e083c4a2
RH		 227 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
228 assert(disp == (int16_t) disp);
810260a8 229 return disp & 0xfffc;
230}
231
e083c4a2 232static void reloc_pc14(tcg_insn_unit *pc, tcg_insn_unit *target)
810260a8 233{
e083c4a2 234 *pc = (*pc & ~0xfffc) | reloc_pc14_val(pc, target);
810260a8 235}
236
c7ca6a2b
RH		 237static inline void tcg_out_b_noaddr(TCGContext *s, int insn)
238{
e083c4a2 239 unsigned retrans = *s->code_ptr & 0x3fffffc;
c7ca6a2b
RH		 240 tcg_out32(s, insn | retrans);
241}
242
243static inline void tcg_out_bc_noaddr(TCGContext *s, int insn)
244{
e083c4a2 245 unsigned retrans = *s->code_ptr & 0xfffc;
c7ca6a2b
RH		 246 tcg_out32(s, insn | retrans);
247}
248
e083c4a2 249static void patch_reloc(tcg_insn_unit *code_ptr, int type,
541dd4ce 250 intptr_t value, intptr_t addend)
810260a8 251{
e083c4a2
RH		 252 tcg_insn_unit *target = (tcg_insn_unit *)value;
253
254 assert(addend == 0);
810260a8 255 switch (type) {
256 case R_PPC_REL14:
e083c4a2 257 reloc_pc14(code_ptr, target);
810260a8 258 break;
259 case R_PPC_REL24:
e083c4a2 260 reloc_pc24(code_ptr, target);
810260a8 261 break;
262 default:
541dd4ce 263 tcg_abort();
810260a8 264 }
265}
266
810260a8 267/* parse target specific constraints */
541dd4ce 268static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
810260a8 269{
270 const char *ct_str;
271
272 ct_str = *pct_str;
273 switch (ct_str[0]) {
274 case 'A': case 'B': case 'C': case 'D':
275 ct->ct |= TCG_CT_REG;
541dd4ce 276 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
810260a8 277 break;
278 case 'r':
279 ct->ct |= TCG_CT_REG;
541dd4ce 280 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
810260a8 281 break;
282 case 'L': /* qemu_ld constraint */
283 ct->ct |= TCG_CT_REG;
541dd4ce
RH		 284 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
285 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
735ee40d 286#ifdef CONFIG_SOFTMMU
541dd4ce
RH		 287 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
288 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
735ee40d 289#endif
810260a8 290 break;
c070355d 291 case 'S': /* qemu_st constraint */
810260a8 292 ct->ct |= TCG_CT_REG;
541dd4ce
RH		 293 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
294 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
735ee40d 295#ifdef CONFIG_SOFTMMU
541dd4ce
RH		 296 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
297 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
298 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
735ee40d 299#endif
810260a8 300 break;
3d582c61
RH		 301 case 'I':
302 ct->ct |= TCG_CT_CONST_S16;
303 break;
304 case 'J':
305 ct->ct |= TCG_CT_CONST_U16;
306 break;
6c858762
RH		 307 case 'M':
308 ct->ct |= TCG_CT_CONST_MONE;
309 break;
3d582c61
RH		 310 case 'T':
311 ct->ct |= TCG_CT_CONST_S32;
312 break;
313 case 'U':
fe6f943f 314 ct->ct |= TCG_CT_CONST_U32;
315 break;
3d582c61
RH		 316 case 'Z':
317 ct->ct |= TCG_CT_CONST_ZERO;
318 break;
810260a8 319 default:
320 return -1;
321 }
322 ct_str++;
323 *pct_str = ct_str;
324 return 0;
325}
326
327/* test if a constant matches the constraint */
f6c6afc1 328static int tcg_target_const_match(tcg_target_long val, TCGType type,
541dd4ce 329 const TCGArgConstraint *arg_ct)
810260a8 330{
3d582c61
RH		 331 int ct = arg_ct->ct;
332 if (ct & TCG_CT_CONST) {
333 return 1;
1194dcba
RH		 334 }
335
336 /* The only 32-bit constraint we use aside from
337 TCG_CT_CONST is TCG_CT_CONST_S16. */
338 if (type == TCG_TYPE_I32) {
339 val = (int32_t)val;
340 }
341
342 if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
3d582c61
RH		 343 return 1;
344 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
810260a8 345 return 1;
3d582c61 346 } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
fe6f943f 347 return 1;
3d582c61
RH		 348 } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
349 return 1;
350 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
351 return 1;
6c858762
RH		 352 } else if ((ct & TCG_CT_CONST_MONE) && val == -1) {
353 return 1;
3d582c61 354 }
810260a8 355 return 0;
356}
357
358#define OPCD(opc) ((opc)<<26)
359#define XO19(opc) (OPCD(19)|((opc)<<1))
8a94cfb0
AB		 360#define MD30(opc) (OPCD(30)|((opc)<<2))
361#define MDS30(opc) (OPCD(30)|((opc)<<1))
810260a8 362#define XO31(opc) (OPCD(31)|((opc)<<1))
363#define XO58(opc) (OPCD(58)|(opc))
364#define XO62(opc) (OPCD(62)|(opc))
365
366#define B OPCD( 18)
367#define BC OPCD( 16)
368#define LBZ OPCD( 34)
369#define LHZ OPCD( 40)
370#define LHA OPCD( 42)
371#define LWZ OPCD( 32)
372#define STB OPCD( 38)
373#define STH OPCD( 44)
374#define STW OPCD( 36)
375
376#define STD XO62( 0)
377#define STDU XO62( 1)
378#define STDX XO31(149)
379
380#define LD XO58( 0)
381#define LDX XO31( 21)
382#define LDU XO58( 1)
301f6d90 383#define LWA XO58( 2)
810260a8 384#define LWAX XO31(341)
385
1cd62ae9 386#define ADDIC OPCD( 12)
810260a8 387#define ADDI OPCD( 14)
388#define ADDIS OPCD( 15)
389#define ORI OPCD( 24)
390#define ORIS OPCD( 25)
391#define XORI OPCD( 26)
392#define XORIS OPCD( 27)
393#define ANDI OPCD( 28)
394#define ANDIS OPCD( 29)
395#define MULLI OPCD( 7)
396#define CMPLI OPCD( 10)
397#define CMPI OPCD( 11)
148bdd23 398#define SUBFIC OPCD( 8)
810260a8 399
400#define LWZU OPCD( 33)
401#define STWU OPCD( 37)
402
313d91c7 403#define RLWIMI OPCD( 20)
810260a8 404#define RLWINM OPCD( 21)
313d91c7 405#define RLWNM OPCD( 23)
810260a8 406
8a94cfb0
AB		 407#define RLDICL MD30( 0)
408#define RLDICR MD30( 1)
409#define RLDIMI MD30( 3)
410#define RLDCL MDS30( 8)
810260a8 411
412#define BCLR XO19( 16)
413#define BCCTR XO19(528)
414#define CRAND XO19(257)
415#define CRANDC XO19(129)
416#define CRNAND XO19(225)
417#define CROR XO19(449)
1cd62ae9 418#define CRNOR XO19( 33)
810260a8 419
420#define EXTSB XO31(954)
421#define EXTSH XO31(922)
422#define EXTSW XO31(986)
423#define ADD XO31(266)
424#define ADDE XO31(138)
6c858762
RH		 425#define ADDME XO31(234)
426#define ADDZE XO31(202)
810260a8 427#define ADDC XO31( 10)
428#define AND XO31( 28)
429#define SUBF XO31( 40)
430#define SUBFC XO31( 8)
431#define SUBFE XO31(136)
6c858762
RH		 432#define SUBFME XO31(232)
433#define SUBFZE XO31(200)
810260a8 434#define OR XO31(444)
435#define XOR XO31(316)
436#define MULLW XO31(235)
8fa391a0 437#define MULHW XO31( 75)
810260a8 438#define MULHWU XO31( 11)
439#define DIVW XO31(491)
440#define DIVWU XO31(459)
441#define CMP XO31( 0)
442#define CMPL XO31( 32)
443#define LHBRX XO31(790)
444#define LWBRX XO31(534)
49d9870a 445#define LDBRX XO31(532)
810260a8 446#define STHBRX XO31(918)
447#define STWBRX XO31(662)
49d9870a 448#define STDBRX XO31(660)
810260a8 449#define MFSPR XO31(339)
450#define MTSPR XO31(467)
451#define SRAWI XO31(824)
452#define NEG XO31(104)
1cd62ae9 453#define MFCR XO31( 19)
6995a4a0 454#define MFOCRF (MFCR | (1u << 20))
157f2662 455#define NOR XO31(124)
1cd62ae9 456#define CNTLZW XO31( 26)
457#define CNTLZD XO31( 58)
ce1010d6
RH		 458#define ANDC XO31( 60)
459#define ORC XO31(412)
460#define EQV XO31(284)
461#define NAND XO31(476)
70fac59a 462#define ISEL XO31( 15)
810260a8 463
464#define MULLD XO31(233)
465#define MULHD XO31( 73)
466#define MULHDU XO31( 9)
467#define DIVD XO31(489)
468#define DIVDU XO31(457)
469
470#define LBZX XO31( 87)
4f4a67ae 471#define LHZX XO31(279)
810260a8 472#define LHAX XO31(343)
473#define LWZX XO31( 23)
474#define STBX XO31(215)
475#define STHX XO31(407)
476#define STWX XO31(151)
477
541dd4ce 478#define SPR(a, b) ((((a)<<5)|(b))<<11)
810260a8 479#define LR SPR(8, 0)
480#define CTR SPR(9, 0)
481
482#define SLW XO31( 24)
483#define SRW XO31(536)
484#define SRAW XO31(792)
485
486#define SLD XO31( 27)
487#define SRD XO31(539)
488#define SRAD XO31(794)
fe6f943f 489#define SRADI XO31(413<<1)
810260a8 490
810260a8 491#define TW XO31( 4)
541dd4ce 492#define TRAP (TW | TO(31))
810260a8 493
a84ac4cb
RH		 494#define NOP ORI /* ori 0,0,0 */
495
810260a8 496#define RT(r) ((r)<<21)
497#define RS(r) ((r)<<21)
498#define RA(r) ((r)<<16)
499#define RB(r) ((r)<<11)
500#define TO(t) ((t)<<21)
501#define SH(s) ((s)<<11)
502#define MB(b) ((b)<<6)
503#define ME(e) ((e)<<1)
504#define BO(o) ((o)<<21)
505#define MB64(b) ((b)<<5)
6995a4a0 506#define FXM(b) (1 << (19 - (b)))
810260a8 507
508#define LK 1
509
2fd8eddc
RH		 510#define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
511#define SAB(s, a, b) (RS(s) | RA(a) | RB(b))
512#define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff))
513#define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff))
810260a8 514
515#define BF(n) ((n)<<23)
516#define BI(n, c) (((c)+((n)*4))<<16)
517#define BT(n, c) (((c)+((n)*4))<<21)
518#define BA(n, c) (((c)+((n)*4))<<16)
519#define BB(n, c) (((c)+((n)*4))<<11)
70fac59a 520#define BC_(n, c) (((c)+((n)*4))<<6)
810260a8 521
541dd4ce
RH		 522#define BO_COND_TRUE BO(12)
523#define BO_COND_FALSE BO( 4)
524#define BO_ALWAYS BO(20)
810260a8 525
526enum {
527 CR_LT,
528 CR_GT,
529 CR_EQ,
530 CR_SO
531};
532
0aed257f 533static const uint32_t tcg_to_bc[] = {
541dd4ce
RH		 534 [TCG_COND_EQ] = BC | BI(7, CR_EQ) | BO_COND_TRUE,
535 [TCG_COND_NE] = BC | BI(7, CR_EQ) | BO_COND_FALSE,
536 [TCG_COND_LT] = BC | BI(7, CR_LT) | BO_COND_TRUE,
537 [TCG_COND_GE] = BC | BI(7, CR_LT) | BO_COND_FALSE,
538 [TCG_COND_LE] = BC | BI(7, CR_GT) | BO_COND_FALSE,
539 [TCG_COND_GT] = BC | BI(7, CR_GT) | BO_COND_TRUE,
540 [TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE,
541 [TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE,
542 [TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE,
543 [TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE,
810260a8 544};
545
70fac59a
RH		 546/* The low bit here is set if the RA and RB fields must be inverted. */
547static const uint32_t tcg_to_isel[] = {
548 [TCG_COND_EQ] = ISEL | BC_(7, CR_EQ),
549 [TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1,
550 [TCG_COND_LT] = ISEL | BC_(7, CR_LT),
551 [TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1,
552 [TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1,
553 [TCG_COND_GT] = ISEL | BC_(7, CR_GT),
554 [TCG_COND_LTU] = ISEL | BC_(7, CR_LT),
555 [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1,
556 [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1,
557 [TCG_COND_GTU] = ISEL | BC_(7, CR_GT),
558};
559
a84ac4cb
RH		 560static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
561 TCGReg base, tcg_target_long offset);
562
796f1a68 563static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
810260a8 564{
796f1a68 565 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
f8b84129
RH		 566 if (ret != arg) {
567 tcg_out32(s, OR | SAB(arg, ret, arg));
568 }
810260a8 569}
570
aceac8d6
RH		 571static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs,
572 int sh, int mb)
810260a8 573{
a757e1ee 574 assert(TCG_TARGET_REG_BITS == 64);
541dd4ce
RH		 575 sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1);
576 mb = MB64((mb >> 5) | ((mb << 1) & 0x3f));
577 tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb);
810260a8 578}
579
9e555b73
RH		 580static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs,
581 int sh, int mb, int me)
582{
583 tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me));
584}
585
6e5e0602
RH		 586static inline void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src)
587{
588 tcg_out_rld(s, RLDICL, dst, src, 0, 32);
589}
590
a757e1ee
RH		 591static inline void tcg_out_shli32(TCGContext *s, TCGReg dst, TCGReg src, int c)
592{
593 tcg_out_rlw(s, RLWINM, dst, src, c, 0, 31 - c);
594}
595
0a9564b9
RH		 596static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c)
597{
598 tcg_out_rld(s, RLDICR, dst, src, c, 63 - c);
599}
600
a757e1ee
RH		 601static inline void tcg_out_shri32(TCGContext *s, TCGReg dst, TCGReg src, int c)
602{
603 tcg_out_rlw(s, RLWINM, dst, src, 32 - c, c, 31);
604}
605
5e916c28
RH		 606static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c)
607{
608 tcg_out_rld(s, RLDICL, dst, src, 64 - c, c);
609}
610
aceac8d6 611static void tcg_out_movi32(TCGContext *s, TCGReg ret, int32_t arg)
810260a8 612{
2fd8eddc
RH		 613 if (arg == (int16_t) arg) {
614 tcg_out32(s, ADDI | TAI(ret, 0, arg));
615 } else {
616 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
617 if (arg & 0xffff) {
618 tcg_out32(s, ORI | SAI(ret, ret, arg));
619 }
810260a8 620 }
621}
622
421233a1
RH		 623static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
624 tcg_target_long arg)
810260a8 625{
796f1a68 626 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
421233a1
RH		 627 if (type == TCG_TYPE_I32 || arg == (int32_t)arg) {
628 tcg_out_movi32(s, ret, arg);
629 } else if (arg == (uint32_t)arg && !(arg & 0x8000)) {
630 tcg_out32(s, ADDI | TAI(ret, 0, arg));
631 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
632 } else {
a84ac4cb
RH		 633 int32_t high;
634
635 if (USE_REG_RA) {
636 intptr_t diff = arg - (intptr_t)tb_ret_addr;
637 if (diff == (int32_t)diff) {
638 tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_RA, diff);
639 return;
640 }
641 }
642
643 high = arg >> 31 >> 1;
421233a1
RH		 644 tcg_out_movi32(s, ret, high);
645 if (high) {
0a9564b9 646 tcg_out_shli64(s, ret, ret, 32);
421233a1
RH		 647 }
648 if (arg & 0xffff0000) {
649 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
650 }
651 if (arg & 0xffff) {
652 tcg_out32(s, ORI | SAI(ret, ret, arg));
810260a8 653 }
654 }
655}
656
637af30c 657static bool mask_operand(uint32_t c, int *mb, int *me)
a9249dff
RH		 658{
659 uint32_t lsb, test;
660
661 /* Accept a bit pattern like:
662 0....01....1
663 1....10....0
664 0..01..10..0
665 Keep track of the transitions. */
666 if (c == 0 || c == -1) {
667 return false;
668 }
669 test = c;
670 lsb = test & -test;
671 test += lsb;
672 if (test & (test - 1)) {
673 return false;
674 }
675
676 *me = clz32(lsb);
677 *mb = test ? clz32(test & -test) + 1 : 0;
678 return true;
679}
680
637af30c
RH		 681static bool mask64_operand(uint64_t c, int *mb, int *me)
682{
683 uint64_t lsb;
684
685 if (c == 0) {
686 return false;
687 }
688
689 lsb = c & -c;
690 /* Accept 1..10..0. */
691 if (c == -lsb) {
692 *mb = 0;
693 *me = clz64(lsb);
694 return true;
695 }
696 /* Accept 0..01..1. */
697 if (lsb == 1 && (c & (c + 1)) == 0) {
698 *mb = clz64(c + 1) + 1;
699 *me = 63;
700 return true;
701 }
702 return false;
703}
704
a9249dff
RH		 705static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
706{
707 int mb, me;
708
709 if ((c & 0xffff) == c) {
710 tcg_out32(s, ANDI | SAI(src, dst, c));
711 return;
712 } else if ((c & 0xffff0000) == c) {
713 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
714 return;
715 } else if (mask_operand(c, &mb, &me)) {
716 tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me);
717 } else {
8327a470
RH		 718 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c);
719 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
a9249dff
RH		 720 }
721}
722
637af30c
RH		 723static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c)
724{
725 int mb, me;
726
a757e1ee 727 assert(TCG_TARGET_REG_BITS == 64);
637af30c
RH		 728 if ((c & 0xffff) == c) {
729 tcg_out32(s, ANDI | SAI(src, dst, c));
730 return;
731 } else if ((c & 0xffff0000) == c) {
732 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
733 return;
734 } else if (mask64_operand(c, &mb, &me)) {
735 if (mb == 0) {
736 tcg_out_rld(s, RLDICR, dst, src, 0, me);
737 } else {
738 tcg_out_rld(s, RLDICL, dst, src, 0, mb);
739 }
740 } else {
8327a470
RH		 741 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c);
742 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
637af30c
RH		 743 }
744}
745
dce74c57
RH		 746static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c,
747 int op_lo, int op_hi)
748{
749 if (c >> 16) {
750 tcg_out32(s, op_hi | SAI(src, dst, c >> 16));
751 src = dst;
752 }
753 if (c & 0xffff) {
754 tcg_out32(s, op_lo | SAI(src, dst, c));
755 src = dst;
756 }
757}
758
759static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
760{
761 tcg_out_zori32(s, dst, src, c, ORI, ORIS);
762}
763
764static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
765{
766 tcg_out_zori32(s, dst, src, c, XORI, XORIS);
767}
768
e083c4a2 769static void tcg_out_b(TCGContext *s, int mask, tcg_insn_unit *target)
5d7ff5bb 770{
e083c4a2 771 ptrdiff_t disp = tcg_pcrel_diff(s, target);
b0940da0 772 if (in_range_b(disp)) {
541dd4ce
RH		 773 tcg_out32(s, B | (disp & 0x3fffffc) | mask);
774 } else {
de3d636d 775 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, (uintptr_t)target);
8327a470 776 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR);
541dd4ce 777 tcg_out32(s, BCCTR | BO_ALWAYS | mask);
5d7ff5bb
AF		 778 }
779}
780
b18d5d2b
RH		 781static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
782 TCGReg base, tcg_target_long offset)
810260a8 783{
b18d5d2b 784 tcg_target_long orig = offset, l0, l1, extra = 0, align = 0;
de7761a3 785 bool is_store = false;
dfca1778 786 TCGReg rs = TCG_REG_TMP1;
b18d5d2b 787
b18d5d2b
RH		 788 switch (opi) {
789 case LD: case LWA:
790 align = 3;
791 /* FALLTHRU */
792 default:
793 if (rt != TCG_REG_R0) {
794 rs = rt;
de7761a3 795 break;
b18d5d2b
RH		 796 }
797 break;
798 case STD:
799 align = 3;
de7761a3 800 /* FALLTHRU */
b18d5d2b 801 case STB: case STH: case STW:
de7761a3 802 is_store = true;
b18d5d2b 803 break;
810260a8 804 }
810260a8 805
b18d5d2b
RH		 806 /* For unaligned, or very large offsets, use the indexed form. */
807 if (offset & align || offset != (int32_t)offset) {
d4cba13b
RH		 808 if (rs == base) {
809 rs = TCG_REG_R0;
810 }
811 tcg_debug_assert(!is_store || rs != rt);
de7761a3
RH		 812 tcg_out_movi(s, TCG_TYPE_PTR, rs, orig);
813 tcg_out32(s, opx | TAB(rt, base, rs));
b18d5d2b
RH		 814 return;
815 }
816
817 l0 = (int16_t)offset;
818 offset = (offset - l0) >> 16;
819 l1 = (int16_t)offset;
820
821 if (l1 < 0 && orig >= 0) {
822 extra = 0x4000;
823 l1 = (int16_t)(offset - 0x4000);
824 }
825 if (l1) {
826 tcg_out32(s, ADDIS | TAI(rs, base, l1));
827 base = rs;
828 }
829 if (extra) {
830 tcg_out32(s, ADDIS | TAI(rs, base, extra));
831 base = rs;
832 }
833 if (opi != ADDI || base != rt || l0 != 0) {
834 tcg_out32(s, opi | TAI(rt, base, l0));
828808f5 835 }
836}
837
d604f1a9
RH		 838static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
839 TCGReg arg1, intptr_t arg2)
840{
841 int opi, opx;
810260a8 842
a757e1ee 843 assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
d604f1a9
RH		 844 if (type == TCG_TYPE_I32) {
845 opi = LWZ, opx = LWZX;
846 } else {
847 opi = LD, opx = LDX;
848 }
849 tcg_out_mem_long(s, opi, opx, ret, arg1, arg2);
850}
fedee3e7 851
d604f1a9
RH		 852static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
853 TCGReg arg1, intptr_t arg2)
810260a8 854{
d604f1a9 855 int opi, opx;
fedee3e7 856
a757e1ee 857 assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
d604f1a9
RH		 858 if (type == TCG_TYPE_I32) {
859 opi = STW, opx = STWX;
fedee3e7 860 } else {
d604f1a9 861 opi = STD, opx = STDX;
fedee3e7 862 }
d604f1a9
RH		 863 tcg_out_mem_long(s, opi, opx, arg, arg1, arg2);
864}
810260a8 865
d604f1a9
RH		 866static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
867 int const_arg2, int cr, TCGType type)
868{
869 int imm;
870 uint32_t op;
810260a8 871
abcf61c4
RH		 872 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
873
d604f1a9
RH		 874 /* Simplify the comparisons below wrt CMPI. */
875 if (type == TCG_TYPE_I32) {
876 arg2 = (int32_t)arg2;
4a40e231 877 }
fedee3e7 878
d604f1a9
RH		 879 switch (cond) {
880 case TCG_COND_EQ:
881 case TCG_COND_NE:
882 if (const_arg2) {
883 if ((int16_t) arg2 == arg2) {
884 op = CMPI;
885 imm = 1;
886 break;
887 } else if ((uint16_t) arg2 == arg2) {
888 op = CMPLI;
889 imm = 1;
890 break;
891 }
892 }
893 op = CMPL;
894 imm = 0;
895 break;
fedee3e7 896
d604f1a9
RH		 897 case TCG_COND_LT:
898 case TCG_COND_GE:
899 case TCG_COND_LE:
900 case TCG_COND_GT:
901 if (const_arg2) {
902 if ((int16_t) arg2 == arg2) {
903 op = CMPI;
904 imm = 1;
905 break;
906 }
907 }
908 op = CMP;
909 imm = 0;
910 break;
fedee3e7 911
d604f1a9
RH		 912 case TCG_COND_LTU:
913 case TCG_COND_GEU:
914 case TCG_COND_LEU:
915 case TCG_COND_GTU:
916 if (const_arg2) {
917 if ((uint16_t) arg2 == arg2) {
918 op = CMPLI;
919 imm = 1;
920 break;
921 }
922 }
923 op = CMPL;
924 imm = 0;
925 break;
fedee3e7 926
d604f1a9
RH		 927 default:
928 tcg_abort();
fedee3e7 929 }
d604f1a9 930 op |= BF(cr) | ((type == TCG_TYPE_I64) << 21);
fedee3e7 931
d604f1a9
RH		 932 if (imm) {
933 tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff));
934 } else {
935 if (const_arg2) {
936 tcg_out_movi(s, type, TCG_REG_R0, arg2);
937 arg2 = TCG_REG_R0;
938 }
939 tcg_out32(s, op | RA(arg1) | RB(arg2));
940 }
810260a8 941}
942
d604f1a9
RH		 943static void tcg_out_setcond_eq0(TCGContext *s, TCGType type,
944 TCGReg dst, TCGReg src)
7f12d649 945{
a757e1ee
RH		 946 if (type == TCG_TYPE_I32) {
947 tcg_out32(s, CNTLZW | RS(src) | RA(dst));
948 tcg_out_shri32(s, dst, dst, 5);
949 } else {
950 tcg_out32(s, CNTLZD | RS(src) | RA(dst));
951 tcg_out_shri64(s, dst, dst, 6);
952 }
7f12d649
RH		 953}
954
d604f1a9 955static void tcg_out_setcond_ne0(TCGContext *s, TCGReg dst, TCGReg src)
7f12d649 956{
d604f1a9
RH		 957 /* X != 0 implies X + -1 generates a carry. Extra addition
958 trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */
959 if (dst != src) {
960 tcg_out32(s, ADDIC | TAI(dst, src, -1));
961 tcg_out32(s, SUBFE | TAB(dst, dst, src));
7f12d649 962 } else {
d604f1a9
RH		 963 tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1));
964 tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src));
7f12d649 965 }
d604f1a9 966}
7f12d649 967
d604f1a9
RH		 968static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2,
969 bool const_arg2)
970{
971 if (const_arg2) {
972 if ((uint32_t)arg2 == arg2) {
973 tcg_out_xori32(s, TCG_REG_R0, arg1, arg2);
974 } else {
975 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2);
976 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0));
977 }
978 } else {
979 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2));
980 }
981 return TCG_REG_R0;
7f12d649
RH		 982}
983
d604f1a9
RH		 984static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond,
985 TCGArg arg0, TCGArg arg1, TCGArg arg2,
986 int const_arg2)
7f12d649 987{
d604f1a9 988 int crop, sh;
7f12d649 989
a757e1ee
RH		 990 assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
991
d604f1a9
RH		 992 /* Ignore high bits of a potential constant arg2. */
993 if (type == TCG_TYPE_I32) {
994 arg2 = (uint32_t)arg2;
995 }
7f12d649 996
d604f1a9
RH		 997 /* Handle common and trivial cases before handling anything else. */
998 if (arg2 == 0) {
999 switch (cond) {
1000 case TCG_COND_EQ:
1001 tcg_out_setcond_eq0(s, type, arg0, arg1);
1002 return;
1003 case TCG_COND_NE:
a757e1ee 1004 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
d604f1a9
RH		 1005 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1006 arg1 = TCG_REG_R0;
1007 }
1008 tcg_out_setcond_ne0(s, arg0, arg1);
1009 return;
1010 case TCG_COND_GE:
1011 tcg_out32(s, NOR | SAB(arg1, arg0, arg1));
1012 arg1 = arg0;
1013 /* FALLTHRU */
1014 case TCG_COND_LT:
1015 /* Extract the sign bit. */
a757e1ee
RH		 1016 if (type == TCG_TYPE_I32) {
1017 tcg_out_shri32(s, arg0, arg1, 31);
1018 } else {
1019 tcg_out_shri64(s, arg0, arg1, 63);
1020 }
d604f1a9
RH		 1021 return;
1022 default:
1023 break;
1024 }
1025 }
7f12d649 1026
d604f1a9
RH		 1027 /* If we have ISEL, we can implement everything with 3 or 4 insns.
1028 All other cases below are also at least 3 insns, so speed up the
1029 code generator by not considering them and always using ISEL. */
1030 if (HAVE_ISEL) {
1031 int isel, tab;
7f12d649 1032
d604f1a9 1033 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
7f12d649 1034
d604f1a9 1035 isel = tcg_to_isel[cond];
7f12d649 1036
d604f1a9
RH		 1037 tcg_out_movi(s, type, arg0, 1);
1038 if (isel & 1) {
1039 /* arg0 = (bc ? 0 : 1) */
1040 tab = TAB(arg0, 0, arg0);
1041 isel &= ~1;
1042 } else {
1043 /* arg0 = (bc ? 1 : 0) */
1044 tcg_out_movi(s, type, TCG_REG_R0, 0);
1045 tab = TAB(arg0, arg0, TCG_REG_R0);
1046 }
1047 tcg_out32(s, isel | tab);
1048 return;
1049 }
49d9870a 1050
d604f1a9
RH		 1051 switch (cond) {
1052 case TCG_COND_EQ:
1053 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1054 tcg_out_setcond_eq0(s, type, arg0, arg1);
1055 return;
810260a8 1056
d604f1a9
RH		 1057 case TCG_COND_NE:
1058 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1059 /* Discard the high bits only once, rather than both inputs. */
a757e1ee 1060 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
d604f1a9
RH		 1061 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1062 arg1 = TCG_REG_R0;
1063 }
1064 tcg_out_setcond_ne0(s, arg0, arg1);
1065 return;
810260a8 1066
d604f1a9
RH		 1067 case TCG_COND_GT:
1068 case TCG_COND_GTU:
1069 sh = 30;
1070 crop = 0;
1071 goto crtest;
810260a8 1072
d604f1a9
RH		 1073 case TCG_COND_LT:
1074 case TCG_COND_LTU:
1075 sh = 29;
1076 crop = 0;
1077 goto crtest;
810260a8 1078
d604f1a9
RH		 1079 case TCG_COND_GE:
1080 case TCG_COND_GEU:
1081 sh = 31;
1082 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_LT) | BB(7, CR_LT);
1083 goto crtest;
810260a8 1084
d604f1a9
RH		 1085 case TCG_COND_LE:
1086 case TCG_COND_LEU:
1087 sh = 31;
1088 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_GT) | BB(7, CR_GT);
1089 crtest:
1090 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1091 if (crop) {
1092 tcg_out32(s, crop);
1093 }
1094 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1095 tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31);
1096 break;
1097
1098 default:
1099 tcg_abort();
1100 }
810260a8 1101}
1102
bec16311 1103static void tcg_out_bc(TCGContext *s, int bc, TCGLabel *l)
810260a8 1104{
d604f1a9
RH		 1105 if (l->has_value) {
1106 tcg_out32(s, bc | reloc_pc14_val(s->code_ptr, l->u.value_ptr));
49d9870a 1107 } else {
bec16311 1108 tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, l, 0);
d604f1a9 1109 tcg_out_bc_noaddr(s, bc);
810260a8 1110 }
810260a8 1111}
1112
d604f1a9
RH		 1113static void tcg_out_brcond(TCGContext *s, TCGCond cond,
1114 TCGArg arg1, TCGArg arg2, int const_arg2,
bec16311 1115 TCGLabel *l, TCGType type)
810260a8 1116{
d604f1a9 1117 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
bec16311 1118 tcg_out_bc(s, tcg_to_bc[cond], l);
d604f1a9 1119}
fa94c3be 1120
d604f1a9
RH		 1121static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond,
1122 TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1,
1123 TCGArg v2, bool const_c2)
1124{
1125 /* If for some reason both inputs are zero, don't produce bad code. */
1126 if (v1 == 0 && v2 == 0) {
1127 tcg_out_movi(s, type, dest, 0);
1128 return;
b9e946c7 1129 }
f6548c0a 1130
d604f1a9 1131 tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type);
a69abbe0 1132
d604f1a9
RH		 1133 if (HAVE_ISEL) {
1134 int isel = tcg_to_isel[cond];
810260a8 1135
d604f1a9
RH		 1136 /* Swap the V operands if the operation indicates inversion. */
1137 if (isel & 1) {
1138 int t = v1;
1139 v1 = v2;
1140 v2 = t;
1141 isel &= ~1;
1142 }
1143 /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */
1144 if (v2 == 0) {
1145 tcg_out_movi(s, type, TCG_REG_R0, 0);
1146 }
1147 tcg_out32(s, isel | TAB(dest, v1, v2));
1148 } else {
1149 if (dest == v2) {
1150 cond = tcg_invert_cond(cond);
1151 v2 = v1;
1152 } else if (dest != v1) {
1153 if (v1 == 0) {
1154 tcg_out_movi(s, type, dest, 0);
1155 } else {
1156 tcg_out_mov(s, type, dest, v1);
1157 }
1158 }
1159 /* Branch forward over one insn */
1160 tcg_out32(s, tcg_to_bc[cond] | 8);
1161 if (v2 == 0) {
1162 tcg_out_movi(s, type, dest, 0);
1163 } else {
1164 tcg_out_mov(s, type, dest, v2);
1165 }
29b69198 1166 }
810260a8 1167}
1168
abcf61c4
RH		 1169static void tcg_out_cmp2(TCGContext *s, const TCGArg *args,
1170 const int *const_args)
1171{
1172 static const struct { uint8_t bit1, bit2; } bits[] = {
1173 [TCG_COND_LT ] = { CR_LT, CR_LT },
1174 [TCG_COND_LE ] = { CR_LT, CR_GT },
1175 [TCG_COND_GT ] = { CR_GT, CR_GT },
1176 [TCG_COND_GE ] = { CR_GT, CR_LT },
1177 [TCG_COND_LTU] = { CR_LT, CR_LT },
1178 [TCG_COND_LEU] = { CR_LT, CR_GT },
1179 [TCG_COND_GTU] = { CR_GT, CR_GT },
1180 [TCG_COND_GEU] = { CR_GT, CR_LT },
1181 };
1182
1183 TCGCond cond = args[4], cond2;
1184 TCGArg al, ah, bl, bh;
1185 int blconst, bhconst;
1186 int op, bit1, bit2;
1187
1188 al = args[0];
1189 ah = args[1];
1190 bl = args[2];
1191 bh = args[3];
1192 blconst = const_args[2];
1193 bhconst = const_args[3];
1194
1195 switch (cond) {
1196 case TCG_COND_EQ:
1197 op = CRAND;
1198 goto do_equality;
1199 case TCG_COND_NE:
1200 op = CRNAND;
1201 do_equality:
1202 tcg_out_cmp(s, cond, al, bl, blconst, 6, TCG_TYPE_I32);
1203 tcg_out_cmp(s, cond, ah, bh, bhconst, 7, TCG_TYPE_I32);
1204 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
1205 break;
1206
1207 case TCG_COND_LT:
1208 case TCG_COND_LE:
1209 case TCG_COND_GT:
1210 case TCG_COND_GE:
1211 case TCG_COND_LTU:
1212 case TCG_COND_LEU:
1213 case TCG_COND_GTU:
1214 case TCG_COND_GEU:
1215 bit1 = bits[cond].bit1;
1216 bit2 = bits[cond].bit2;
1217 op = (bit1 != bit2 ? CRANDC : CRAND);
1218 cond2 = tcg_unsigned_cond(cond);
1219
1220 tcg_out_cmp(s, cond, ah, bh, bhconst, 6, TCG_TYPE_I32);
1221 tcg_out_cmp(s, cond2, al, bl, blconst, 7, TCG_TYPE_I32);
1222 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2));
1223 tcg_out32(s, CROR | BT(7, CR_EQ) | BA(6, bit1) | BB(7, CR_EQ));
1224 break;
1225
1226 default:
1227 tcg_abort();
1228 }
1229}
1230
1231static void tcg_out_setcond2(TCGContext *s, const TCGArg *args,
1232 const int *const_args)
1233{
1234 tcg_out_cmp2(s, args + 1, const_args + 1);
1235 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1236 tcg_out_rlw(s, RLWINM, args[0], TCG_REG_R0, 31, 31, 31);
1237}
1238
1239static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
1240 const int *const_args)
1241{
1242 tcg_out_cmp2(s, args, const_args);
bec16311 1243 tcg_out_bc(s, BC | BI(7, CR_EQ) | BO_COND_TRUE, arg_label(args[5]));
abcf61c4
RH		 1244}
1245
d604f1a9 1246void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr)
810260a8 1247{
d604f1a9 1248 TCGContext s;
b18d5d2b 1249
d604f1a9
RH		 1250 s.code_buf = s.code_ptr = (tcg_insn_unit *)jmp_addr;
1251 tcg_out_b(&s, 0, (tcg_insn_unit *)addr);
1252 flush_icache_range(jmp_addr, jmp_addr + tcg_current_code_size(&s));
810260a8 1253}
1254
d604f1a9 1255static void tcg_out_call(TCGContext *s, tcg_insn_unit *target)
810260a8 1256{
eaf7d1cf 1257#ifdef _CALL_AIX
d604f1a9
RH		 1258 /* Look through the descriptor. If the branch is in range, and we
1259 don't have to spend too much effort on building the toc. */
1260 void *tgt = ((void **)target)[0];
1261 uintptr_t toc = ((uintptr_t *)target)[1];
1262 intptr_t diff = tcg_pcrel_diff(s, tgt);
b18d5d2b 1263
d604f1a9 1264 if (in_range_b(diff) && toc == (uint32_t)toc) {
dfca1778 1265 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, toc);
d604f1a9 1266 tcg_out_b(s, LK, tgt);
541dd4ce 1267 } else {
d604f1a9
RH		 1268 /* Fold the low bits of the constant into the addresses below. */
1269 intptr_t arg = (intptr_t)target;
1270 int ofs = (int16_t)arg;
1271
1272 if (ofs + 8 < 0x8000) {
1273 arg -= ofs;
1274 } else {
1275 ofs = 0;
1276 }
dfca1778
RH		 1277 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, arg);
1278 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_TMP1, ofs);
d604f1a9 1279 tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR);
dfca1778 1280 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_TMP1, ofs + SZP);
d604f1a9 1281 tcg_out32(s, BCCTR | BO_ALWAYS | LK);
541dd4ce 1282 }
77e58d0d
UW		 1283#elif defined(_CALL_ELF) && _CALL_ELF == 2
1284 intptr_t diff;
1285
1286 /* In the ELFv2 ABI, we have to set up r12 to contain the destination
1287 address, which the callee uses to compute its TOC address. */
1288 /* FIXME: when the branch is in range, we could avoid r12 load if we
1289 knew that the destination uses the same TOC, and what its local
1290 entry point offset is. */
1291 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R12, (intptr_t)target);
1292
1293 diff = tcg_pcrel_diff(s, target);
1294 if (in_range_b(diff)) {
1295 tcg_out_b(s, LK, target);
1296 } else {
1297 tcg_out32(s, MTSPR | RS(TCG_REG_R12) | CTR);
1298 tcg_out32(s, BCCTR | BO_ALWAYS | LK);
1299 }
eaf7d1cf
RH		 1300#else
1301 tcg_out_b(s, LK, target);
d604f1a9 1302#endif
810260a8 1303}
1304
d604f1a9
RH		 1305static const uint32_t qemu_ldx_opc[16] = {
1306 [MO_UB] = LBZX,
1307 [MO_UW] = LHZX,
1308 [MO_UL] = LWZX,
1309 [MO_Q] = LDX,
1310 [MO_SW] = LHAX,
1311 [MO_SL] = LWAX,
1312 [MO_BSWAP | MO_UB] = LBZX,
1313 [MO_BSWAP | MO_UW] = LHBRX,
1314 [MO_BSWAP | MO_UL] = LWBRX,
1315 [MO_BSWAP | MO_Q] = LDBRX,
1316};
810260a8 1317
d604f1a9
RH		 1318static const uint32_t qemu_stx_opc[16] = {
1319 [MO_UB] = STBX,
1320 [MO_UW] = STHX,
1321 [MO_UL] = STWX,
1322 [MO_Q] = STDX,
1323 [MO_BSWAP | MO_UB] = STBX,
1324 [MO_BSWAP | MO_UW] = STHBRX,
1325 [MO_BSWAP | MO_UL] = STWBRX,
1326 [MO_BSWAP | MO_Q] = STDBRX,
1327};
991041a4 1328
d604f1a9
RH		 1329static const uint32_t qemu_exts_opc[4] = {
1330 EXTSB, EXTSH, EXTSW, 0
1331};
810260a8 1332
d604f1a9
RH		 1333#if defined (CONFIG_SOFTMMU)
1334/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
1335 * int mmu_idx, uintptr_t ra)
1336 */
1337static void * const qemu_ld_helpers[16] = {
1338 [MO_UB] = helper_ret_ldub_mmu,
1339 [MO_LEUW] = helper_le_lduw_mmu,
1340 [MO_LEUL] = helper_le_ldul_mmu,
1341 [MO_LEQ] = helper_le_ldq_mmu,
1342 [MO_BEUW] = helper_be_lduw_mmu,
1343 [MO_BEUL] = helper_be_ldul_mmu,
1344 [MO_BEQ] = helper_be_ldq_mmu,
1345};
810260a8 1346
d604f1a9
RH		 1347/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
1348 * uintxx_t val, int mmu_idx, uintptr_t ra)
1349 */
1350static void * const qemu_st_helpers[16] = {
1351 [MO_UB] = helper_ret_stb_mmu,
1352 [MO_LEUW] = helper_le_stw_mmu,
1353 [MO_LEUL] = helper_le_stl_mmu,
1354 [MO_LEQ] = helper_le_stq_mmu,
1355 [MO_BEUW] = helper_be_stw_mmu,
1356 [MO_BEUL] = helper_be_stl_mmu,
1357 [MO_BEQ] = helper_be_stq_mmu,
1358};
810260a8 1359
d604f1a9
RH		 1360/* Perform the TLB load and compare. Places the result of the comparison
1361 in CR7, loads the addend of the TLB into R3, and returns the register
1362 containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
1363
68d45bb6 1364static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp opc,
7f25c469 1365 TCGReg addrlo, TCGReg addrhi,
d604f1a9
RH		 1366 int mem_index, bool is_read)
1367{
1368 int cmp_off
1369 = (is_read
1370 ? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read)
1371 : offsetof(CPUArchState, tlb_table[mem_index][0].addr_write));
1372 int add_off = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
1373 TCGReg base = TCG_AREG0;
68d45bb6 1374 TCGMemOp s_bits = opc & MO_SIZE;
d604f1a9
RH		 1375
1376 /* Extract the page index, shifted into place for tlb index. */
7f25c469
RH		 1377 if (TCG_TARGET_REG_BITS == 64) {
1378 if (TARGET_LONG_BITS == 32) {
1379 /* Zero-extend the address into a place helpful for further use. */
1380 tcg_out_ext32u(s, TCG_REG_R4, addrlo);
1381 addrlo = TCG_REG_R4;
1382 } else {
1383 tcg_out_rld(s, RLDICL, TCG_REG_R3, addrlo,
1384 64 - TARGET_PAGE_BITS, 64 - CPU_TLB_BITS);
1385 }
810260a8 1386 }
810260a8 1387
d604f1a9
RH		 1388 /* Compensate for very large offsets. */
1389 if (add_off >= 0x8000) {
1390 /* Most target env are smaller than 32k; none are larger than 64k.
1391 Simplify the logic here merely to offset by 0x7ff0, giving us a
1392 range just shy of 64k. Check this assumption. */
1393 QEMU_BUILD_BUG_ON(offsetof(CPUArchState,
1394 tlb_table[NB_MMU_MODES - 1][1])
1395 > 0x7ff0 + 0x7fff);
dfca1778
RH		 1396 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, base, 0x7ff0));
1397 base = TCG_REG_TMP1;
d604f1a9
RH		 1398 cmp_off -= 0x7ff0;
1399 add_off -= 0x7ff0;
1400 }
1401
1402 /* Extraction and shifting, part 2. */
7f25c469
RH		 1403 if (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32) {
1404 tcg_out_rlw(s, RLWINM, TCG_REG_R3, addrlo,
d604f1a9
RH		 1405 32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
1406 32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS),
1407 31 - CPU_TLB_ENTRY_BITS);
4c314da6 1408 } else {
d604f1a9 1409 tcg_out_shli64(s, TCG_REG_R3, TCG_REG_R3, CPU_TLB_ENTRY_BITS);
810260a8 1410 }
810260a8 1411
d604f1a9 1412 tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, base));
1cd62ae9 1413
d604f1a9 1414 /* Load the tlb comparator. */
7f25c469
RH		 1415 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1416 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off);
dfca1778 1417 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off + 4);
7f25c469 1418 } else {
dfca1778 1419 tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off);
7f25c469 1420 }
d604f1a9
RH		 1421
1422 /* Load the TLB addend for use on the fast path. Do this asap
1423 to minimize any load use delay. */
4c3831a0 1424 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3, add_off);
d604f1a9 1425
68d45bb6 1426 /* Clear the non-page, non-alignment bits from the address */
7f25c469 1427 if (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32) {
68d45bb6
BH		 1428 /* We don't support unaligned accesses on 32-bits, preserve
1429 * the bottom bits and thus trigger a comparison failure on
1430 * unaligned accesses
1431 */
7f25c469 1432 tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0,
d604f1a9 1433 (32 - s_bits) & 31, 31 - TARGET_PAGE_BITS);
68d45bb6
BH		 1434 } else if (s_bits) {
1435 /* > byte access, we need to handle alignment */
1436 if ((opc & MO_AMASK) == MO_ALIGN) {
1437 /* Alignment required by the front-end, same as 32-bits */
1438 tcg_out_rld(s, RLDICL, TCG_REG_R0, addrlo,
1439 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - s_bits);
1440 tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0);
1441 } else {
1442 /* We support unaligned accesses, we need to make sure we fail
1443 * if we cross a page boundary. The trick is to add the
1444 * access_size-1 to the address before masking the low bits.
1445 * That will make the address overflow to the next page if we
1446 * cross a page boundary which will then force a mismatch of
1447 * the TLB compare since the next page cannot possibly be in
1448 * the same TLB index.
1449 */
1450 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, (1 << s_bits) - 1));
1451 tcg_out_rld(s, RLDICR, TCG_REG_R0, TCG_REG_R0,
1452 0, 63 - TARGET_PAGE_BITS);
1453 }
70fac59a 1454 } else {
68d45bb6
BH		 1455 /* Byte access, just chop off the bits below the page index */
1456 tcg_out_rld(s, RLDICR, TCG_REG_R0, addrlo, 0, 63 - TARGET_PAGE_BITS);
70fac59a 1457 }
d604f1a9 1458
7f25c469 1459 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
dfca1778
RH		 1460 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
1461 0, 7, TCG_TYPE_I32);
7f25c469
RH		 1462 tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32);
1463 tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
1464 } else {
dfca1778
RH		 1465 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
1466 0, 7, TCG_TYPE_TL);
7f25c469 1467 }
d604f1a9 1468
7f25c469 1469 return addrlo;
70fac59a 1470}
1cd62ae9 1471
d604f1a9
RH		 1472/* Record the context of a call to the out of line helper code for the slow
1473 path for a load or store, so that we can later generate the correct
1474 helper code. */
3972ef6f 1475static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
7f25c469
RH		 1476 TCGReg datalo_reg, TCGReg datahi_reg,
1477 TCGReg addrlo_reg, TCGReg addrhi_reg,
3972ef6f 1478 tcg_insn_unit *raddr, tcg_insn_unit *lptr)
70fac59a 1479{
d604f1a9
RH		 1480 TCGLabelQemuLdst *label = new_ldst_label(s);
1481
1482 label->is_ld = is_ld;
3972ef6f 1483 label->oi = oi;
7f25c469
RH		 1484 label->datalo_reg = datalo_reg;
1485 label->datahi_reg = datahi_reg;
1486 label->addrlo_reg = addrlo_reg;
1487 label->addrhi_reg = addrhi_reg;
d604f1a9 1488 label->raddr = raddr;
7f25c469 1489 label->label_ptr[0] = lptr;
70fac59a 1490}
1cd62ae9 1491
d604f1a9 1492static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
70fac59a 1493{
3972ef6f
RH		 1494 TCGMemOpIdx oi = lb->oi;
1495 TCGMemOp opc = get_memop(oi);
7f25c469 1496 TCGReg hi, lo, arg = TCG_REG_R3;
70fac59a 1497
d604f1a9 1498 reloc_pc14(lb->label_ptr[0], s->code_ptr);
70fac59a 1499
7f25c469 1500 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
1cd62ae9 1501
7f25c469
RH		 1502 lo = lb->addrlo_reg;
1503 hi = lb->addrhi_reg;
1504 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1505#ifdef TCG_TARGET_CALL_ALIGN_ARGS
1506 arg |= 1;
1507#endif
1508 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
1509 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
1510 } else {
1511 /* If the address needed to be zero-extended, we'll have already
1512 placed it in R4. The only remaining case is 64-bit guest. */
1513 tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
1514 }
752c1fdb 1515
3972ef6f 1516 tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
7f25c469 1517 tcg_out32(s, MFSPR | RT(arg) | LR);
70fac59a 1518
2b7ec66f 1519 tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]);
70fac59a 1520
7f25c469
RH		 1521 lo = lb->datalo_reg;
1522 hi = lb->datahi_reg;
1523 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
1524 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_REG_R4);
1525 tcg_out_mov(s, TCG_TYPE_I32, hi, TCG_REG_R3);
1526 } else if (opc & MO_SIGN) {
d604f1a9 1527 uint32_t insn = qemu_exts_opc[opc & MO_SIZE];
7f25c469 1528 tcg_out32(s, insn | RA(lo) | RS(TCG_REG_R3));
d604f1a9 1529 } else {
7f25c469 1530 tcg_out_mov(s, TCG_TYPE_REG, lo, TCG_REG_R3);
70fac59a
RH		 1531 }
1532
d604f1a9
RH		 1533 tcg_out_b(s, 0, lb->raddr);
1534}
70fac59a 1535
d604f1a9
RH		 1536static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1537{
3972ef6f
RH		 1538 TCGMemOpIdx oi = lb->oi;
1539 TCGMemOp opc = get_memop(oi);
d604f1a9 1540 TCGMemOp s_bits = opc & MO_SIZE;
7f25c469 1541 TCGReg hi, lo, arg = TCG_REG_R3;
1cd62ae9 1542
d604f1a9 1543 reloc_pc14(lb->label_ptr[0], s->code_ptr);
1cd62ae9 1544
7f25c469
RH		 1545 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
1546
1547 lo = lb->addrlo_reg;
1548 hi = lb->addrhi_reg;
1549 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1550#ifdef TCG_TARGET_CALL_ALIGN_ARGS
1551 arg |= 1;
1552#endif
1553 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
1554 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
1555 } else {
1556 /* If the address needed to be zero-extended, we'll have already
1557 placed it in R4. The only remaining case is 64-bit guest. */
1558 tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
1559 }
1cd62ae9 1560
7f25c469
RH		 1561 lo = lb->datalo_reg;
1562 hi = lb->datahi_reg;
1563 if (TCG_TARGET_REG_BITS == 32) {
1564 switch (s_bits) {
1565 case MO_64:
1566#ifdef TCG_TARGET_CALL_ALIGN_ARGS
1567 arg |= 1;
1568#endif
1569 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
1570 /* FALLTHRU */
1571 case MO_32:
1572 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
1573 break;
1574 default:
1575 tcg_out_rlw(s, RLWINM, arg++, lo, 0, 32 - (8 << s_bits), 31);
1576 break;
1577 }
1578 } else {
1579 if (s_bits == MO_64) {
1580 tcg_out_mov(s, TCG_TYPE_I64, arg++, lo);
1581 } else {
1582 tcg_out_rld(s, RLDICL, arg++, lo, 0, 64 - (8 << s_bits));
1583 }
1584 }
1cd62ae9 1585
3972ef6f 1586 tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
7f25c469 1587 tcg_out32(s, MFSPR | RT(arg) | LR);
1cd62ae9 1588
2b7ec66f 1589 tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
d604f1a9
RH		 1590
1591 tcg_out_b(s, 0, lb->raddr);
1cd62ae9 1592}
d604f1a9 1593#endif /* SOFTMMU */
1cd62ae9 1594
7f25c469 1595static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
810260a8 1596{
7f25c469
RH		 1597 TCGReg datalo, datahi, addrlo, rbase;
1598 TCGReg addrhi __attribute__((unused));
59227d5d 1599 TCGMemOpIdx oi;
7f25c469 1600 TCGMemOp opc, s_bits;
d604f1a9 1601#ifdef CONFIG_SOFTMMU
7f25c469 1602 int mem_index;
d604f1a9
RH		 1603 tcg_insn_unit *label_ptr;
1604#endif
810260a8 1605
7f25c469
RH		 1606 datalo = *args++;
1607 datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1608 addrlo = *args++;
1609 addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
59227d5d
RH		 1610 oi = *args++;
1611 opc = get_memop(oi);
7f25c469
RH		 1612 s_bits = opc & MO_SIZE;
1613
d604f1a9 1614#ifdef CONFIG_SOFTMMU
59227d5d 1615 mem_index = get_mmuidx(oi);
68d45bb6 1616 addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true);
d604f1a9
RH		 1617
1618 /* Load a pointer into the current opcode w/conditional branch-link. */
1619 label_ptr = s->code_ptr;
1620 tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
1621
1622 rbase = TCG_REG_R3;
1623#else /* !CONFIG_SOFTMMU */
1624 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
7f25c469 1625 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
dfca1778
RH		 1626 tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
1627 addrlo = TCG_REG_TMP1;
d604f1a9
RH		 1628 }
1629#endif
1630
7f25c469
RH		 1631 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
1632 if (opc & MO_BSWAP) {
1633 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1634 tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
1635 tcg_out32(s, LWBRX | TAB(datahi, rbase, TCG_REG_R0));
1636 } else if (rbase != 0) {
1637 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1638 tcg_out32(s, LWZX | TAB(datahi, rbase, addrlo));
1639 tcg_out32(s, LWZX | TAB(datalo, rbase, TCG_REG_R0));
1640 } else if (addrlo == datahi) {
1641 tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
1642 tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
1643 } else {
1644 tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
1645 tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
1646 }
541dd4ce 1647 } else {
2b7ec66f 1648 uint32_t insn = qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)];
7f25c469
RH		 1649 if (!HAVE_ISA_2_06 && insn == LDBRX) {
1650 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1651 tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
1652 tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0));
1653 tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0);
1654 } else if (insn) {
1655 tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
1656 } else {
1657 insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)];
1658 tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
1659 insn = qemu_exts_opc[s_bits];
1660 tcg_out32(s, insn | RA(datalo) | RS(datalo));
1661 }
810260a8 1662 }
810260a8 1663
d604f1a9 1664#ifdef CONFIG_SOFTMMU
3972ef6f
RH		 1665 add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi,
1666 s->code_ptr, label_ptr);
d604f1a9 1667#endif
810260a8 1668}
1669
7f25c469 1670static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
027ffea9 1671{
7f25c469
RH		 1672 TCGReg datalo, datahi, addrlo, rbase;
1673 TCGReg addrhi __attribute__((unused));
59227d5d 1674 TCGMemOpIdx oi;
7f25c469 1675 TCGMemOp opc, s_bits;
d604f1a9 1676#ifdef CONFIG_SOFTMMU
7f25c469 1677 int mem_index;
d604f1a9
RH		 1678 tcg_insn_unit *label_ptr;
1679#endif
027ffea9 1680
7f25c469
RH		 1681 datalo = *args++;
1682 datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1683 addrlo = *args++;
1684 addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
59227d5d
RH		 1685 oi = *args++;
1686 opc = get_memop(oi);
7f25c469
RH		 1687 s_bits = opc & MO_SIZE;
1688
d604f1a9 1689#ifdef CONFIG_SOFTMMU
59227d5d 1690 mem_index = get_mmuidx(oi);
68d45bb6 1691 addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false);
027ffea9 1692
d604f1a9
RH		 1693 /* Load a pointer into the current opcode w/conditional branch-link. */
1694 label_ptr = s->code_ptr;
1695 tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
027ffea9 1696
d604f1a9
RH		 1697 rbase = TCG_REG_R3;
1698#else /* !CONFIG_SOFTMMU */
1699 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
7f25c469 1700 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
dfca1778
RH		 1701 tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
1702 addrlo = TCG_REG_TMP1;
d604f1a9
RH		 1703 }
1704#endif
1705
7f25c469
RH		 1706 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
1707 if (opc & MO_BSWAP) {
1708 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1709 tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
1710 tcg_out32(s, STWBRX | SAB(datahi, rbase, TCG_REG_R0));
1711 } else if (rbase != 0) {
1712 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1713 tcg_out32(s, STWX | SAB(datahi, rbase, addrlo));
1714 tcg_out32(s, STWX | SAB(datalo, rbase, TCG_REG_R0));
1715 } else {
1716 tcg_out32(s, STW | TAI(datahi, addrlo, 0));
1717 tcg_out32(s, STW | TAI(datalo, addrlo, 4));
1718 }
027ffea9 1719 } else {
2b7ec66f 1720 uint32_t insn = qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)];
7f25c469
RH		 1721 if (!HAVE_ISA_2_06 && insn == STDBRX) {
1722 tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
dfca1778 1723 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, addrlo, 4));
7f25c469 1724 tcg_out_shri64(s, TCG_REG_R0, datalo, 32);
dfca1778 1725 tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_TMP1));
7f25c469
RH		 1726 } else {
1727 tcg_out32(s, insn | SAB(datalo, rbase, addrlo));
1728 }
027ffea9 1729 }
d604f1a9
RH		 1730
1731#ifdef CONFIG_SOFTMMU
3972ef6f
RH		 1732 add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi,
1733 s->code_ptr, label_ptr);
d604f1a9 1734#endif
027ffea9
RH		 1735}
1736
a921fddc
RH		 1737/* Parameters for function call generation, used in tcg.c. */
1738#define TCG_TARGET_STACK_ALIGN 16
a921fddc
RH		 1739#define TCG_TARGET_EXTEND_ARGS 1
1740
802ca56e
RH		 1741#ifdef _CALL_AIX
1742# define LINK_AREA_SIZE (6 * SZR)
1743# define LR_OFFSET (1 * SZR)
1744# define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR)
1045fc04
PM		 1745#elif defined(TCG_TARGET_CALL_DARWIN)
1746# define LINK_AREA_SIZE (6 * SZR)
1747# define LR_OFFSET (2 * SZR)
ffcfbece
RH		 1748#elif TCG_TARGET_REG_BITS == 64
1749# if defined(_CALL_ELF) && _CALL_ELF == 2
1750# define LINK_AREA_SIZE (4 * SZR)
1751# define LR_OFFSET (1 * SZR)
1752# endif
1753#else /* TCG_TARGET_REG_BITS == 32 */
1754# if defined(_CALL_SYSV)
ffcfbece
RH		 1755# define LINK_AREA_SIZE (2 * SZR)
1756# define LR_OFFSET (1 * SZR)
ffcfbece
RH		 1757# endif
1758#endif
1759#ifndef LR_OFFSET
1760# error "Unhandled abi"
1761#endif
1762#ifndef TCG_TARGET_CALL_STACK_OFFSET
a2a98f80 1763# define TCG_TARGET_CALL_STACK_OFFSET LINK_AREA_SIZE
802ca56e
RH		 1764#endif
1765
1766#define CPU_TEMP_BUF_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
1767#define REG_SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * SZR)
d604f1a9 1768
802ca56e
RH		 1769#define FRAME_SIZE ((TCG_TARGET_CALL_STACK_OFFSET \
1770 + TCG_STATIC_CALL_ARGS_SIZE \
1771 + CPU_TEMP_BUF_SIZE \
1772 + REG_SAVE_SIZE \
1773 + TCG_TARGET_STACK_ALIGN - 1) \
1774 & -TCG_TARGET_STACK_ALIGN)
1775
1776#define REG_SAVE_BOT (FRAME_SIZE - REG_SAVE_SIZE)
d604f1a9
RH		 1777
1778static void tcg_target_qemu_prologue(TCGContext *s)
810260a8 1779{
d604f1a9 1780 int i;
810260a8 1781
802ca56e 1782#ifdef _CALL_AIX
a84ac4cb
RH		 1783 void **desc = (void **)s->code_ptr;
1784 desc[0] = desc + 2; /* entry point */
1785 desc[1] = 0; /* environment pointer */
1786 s->code_ptr = (void *)(desc + 2); /* skip over descriptor */
d604f1a9
RH		 1787#endif
1788
a84ac4cb
RH		 1789 tcg_set_frame(s, TCG_REG_CALL_STACK, REG_SAVE_BOT - CPU_TEMP_BUF_SIZE,
1790 CPU_TEMP_BUF_SIZE);
1791
d604f1a9
RH		 1792 /* Prologue */
1793 tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR);
ffcfbece
RH		 1794 tcg_out32(s, (SZR == 8 ? STDU : STWU)
1795 | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE));
802ca56e 1796
d604f1a9 1797 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
4c3831a0
RH		 1798 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1799 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
d604f1a9 1800 }
802ca56e 1801 tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
d604f1a9
RH		 1802
1803#ifdef CONFIG_USE_GUEST_BASE
1804 if (GUEST_BASE) {
1805 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, GUEST_BASE);
1806 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
1807 }
1808#endif
1809
1810 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
1811 tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR);
a84ac4cb
RH		 1812
1813 if (USE_REG_RA) {
1814#ifdef _CALL_AIX
1815 /* Make the caller load the value as the TOC into R2. */
1816 tb_ret_addr = s->code_ptr + 2;
1817 desc[1] = tb_ret_addr;
1818 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_RA, TCG_REG_R2);
1819 tcg_out32(s, BCCTR | BO_ALWAYS);
1820#elif defined(_CALL_ELF) && _CALL_ELF == 2
1821 /* Compute from the incoming R12 value. */
1822 tb_ret_addr = s->code_ptr + 2;
1823 tcg_out32(s, ADDI | TAI(TCG_REG_RA, TCG_REG_R12,
1824 tcg_ptr_byte_diff(tb_ret_addr, s->code_buf)));
1825 tcg_out32(s, BCCTR | BO_ALWAYS);
1826#else
1827 /* Reserve max 5 insns for the constant load. */
1828 tb_ret_addr = s->code_ptr + 6;
1829 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)tb_ret_addr);
1830 tcg_out32(s, BCCTR | BO_ALWAYS);
1831 while (s->code_ptr < tb_ret_addr) {
1832 tcg_out32(s, NOP);
1833 }
1834#endif
1835 } else {
1836 tcg_out32(s, BCCTR | BO_ALWAYS);
1837 tb_ret_addr = s->code_ptr;
1838 }
d604f1a9
RH		 1839
1840 /* Epilogue */
a84ac4cb 1841 assert(tb_ret_addr == s->code_ptr);
d604f1a9 1842
802ca56e 1843 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
d604f1a9 1844 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
4c3831a0
RH		 1845 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1846 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
d604f1a9 1847 }
d604f1a9
RH		 1848 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR);
1849 tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE));
1850 tcg_out32(s, BCLR | BO_ALWAYS);
810260a8 1851}
1852
541dd4ce
RH		 1853static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
1854 const int *const_args)
810260a8 1855{
ee924fa6 1856 TCGArg a0, a1, a2;
e46b9681 1857 int c;
1858
810260a8 1859 switch (opc) {
1860 case INDEX_op_exit_tb:
a84ac4cb
RH		 1861 if (USE_REG_RA) {
1862 ptrdiff_t disp = tcg_pcrel_diff(s, tb_ret_addr);
1863
1864 /* If we can use a direct branch, otherwise use the value in RA.
1865 Note that the direct branch is always forward. If it's in
1866 range now, it'll still be in range after the movi. Don't
1867 bother about the 20 bytes where the test here fails but it
1868 would succeed below. */
1869 if (!in_range_b(disp)) {
1870 tcg_out32(s, MTSPR | RS(TCG_REG_RA) | CTR);
1871 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]);
1872 tcg_out32(s, BCCTR | BO_ALWAYS);
1873 break;
1874 }
1875 }
de3d636d 1876 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]);
e083c4a2 1877 tcg_out_b(s, 0, tb_ret_addr);
810260a8 1878 break;
1879 case INDEX_op_goto_tb:
1880 if (s->tb_jmp_offset) {
541dd4ce 1881 /* Direct jump method. */
e083c4a2
RH		 1882 s->tb_jmp_offset[args[0]] = tcg_current_code_size(s);
1883 s->code_ptr += 7;
541dd4ce
RH		 1884 } else {
1885 /* Indirect jump method. */
1886 tcg_abort();
810260a8 1887 }
e083c4a2 1888 s->tb_next_offset[args[0]] = tcg_current_code_size(s);
810260a8 1889 break;
1890 case INDEX_op_br:
1891 {
bec16311 1892 TCGLabel *l = arg_label(args[0]);
810260a8 1893
1894 if (l->has_value) {
e083c4a2 1895 tcg_out_b(s, 0, l->u.value_ptr);
541dd4ce 1896 } else {
bec16311 1897 tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, l, 0);
c7ca6a2b 1898 tcg_out_b_noaddr(s, B);
810260a8 1899 }
1900 }
1901 break;
810260a8 1902 case INDEX_op_ld8u_i32:
1903 case INDEX_op_ld8u_i64:
b18d5d2b 1904 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
810260a8 1905 break;
1906 case INDEX_op_ld8s_i32:
1907 case INDEX_op_ld8s_i64:
b18d5d2b 1908 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
541dd4ce 1909 tcg_out32(s, EXTSB | RS(args[0]) | RA(args[0]));
810260a8 1910 break;
1911 case INDEX_op_ld16u_i32:
1912 case INDEX_op_ld16u_i64:
b18d5d2b 1913 tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]);
810260a8 1914 break;
1915 case INDEX_op_ld16s_i32:
1916 case INDEX_op_ld16s_i64:
b18d5d2b 1917 tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]);
810260a8 1918 break;
1919 case INDEX_op_ld_i32:
1920 case INDEX_op_ld32u_i64:
b18d5d2b 1921 tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]);
810260a8 1922 break;
1923 case INDEX_op_ld32s_i64:
b18d5d2b 1924 tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]);
810260a8 1925 break;
1926 case INDEX_op_ld_i64:
b18d5d2b 1927 tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]);
810260a8 1928 break;
1929 case INDEX_op_st8_i32:
1930 case INDEX_op_st8_i64:
b18d5d2b 1931 tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]);
810260a8 1932 break;
1933 case INDEX_op_st16_i32:
1934 case INDEX_op_st16_i64:
b18d5d2b 1935 tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]);
810260a8 1936 break;
1937 case INDEX_op_st_i32:
1938 case INDEX_op_st32_i64:
b18d5d2b 1939 tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]);
810260a8 1940 break;
1941 case INDEX_op_st_i64:
b18d5d2b 1942 tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]);
810260a8 1943 break;
1944
1945 case INDEX_op_add_i32:
ee924fa6
RH		 1946 a0 = args[0], a1 = args[1], a2 = args[2];
1947 if (const_args[2]) {
ee924fa6 1948 do_addi_32:
b18d5d2b 1949 tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2);
ee924fa6
RH		 1950 } else {
1951 tcg_out32(s, ADD | TAB(a0, a1, a2));
1952 }
810260a8 1953 break;
1954 case INDEX_op_sub_i32:
ee924fa6 1955 a0 = args[0], a1 = args[1], a2 = args[2];
148bdd23
RH		 1956 if (const_args[1]) {
1957 if (const_args[2]) {
1958 tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2);
1959 } else {
1960 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
1961 }
1962 } else if (const_args[2]) {
ee924fa6
RH		 1963 a2 = -a2;
1964 goto do_addi_32;
1965 } else {
1966 tcg_out32(s, SUBF | TAB(a0, a2, a1));
1967 }
810260a8 1968 break;
1969
1970 case INDEX_op_and_i32:
37251b98 1971 a0 = args[0], a1 = args[1], a2 = args[2];
a9249dff 1972 if (const_args[2]) {
37251b98 1973 tcg_out_andi32(s, a0, a1, a2);
a9249dff 1974 } else {
37251b98 1975 tcg_out32(s, AND | SAB(a1, a0, a2));
a9249dff
RH		 1976 }
1977 break;
1978 case INDEX_op_and_i64:
37251b98 1979 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 1980 if (const_args[2]) {
37251b98 1981 tcg_out_andi64(s, a0, a1, a2);
637af30c 1982 } else {
37251b98 1983 tcg_out32(s, AND | SAB(a1, a0, a2));
810260a8 1984 }
810260a8 1985 break;
fe6f943f 1986 case INDEX_op_or_i64:
810260a8 1987 case INDEX_op_or_i32:
dce74c57 1988 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 1989 if (const_args[2]) {
dce74c57
RH		 1990 tcg_out_ori32(s, a0, a1, a2);
1991 } else {
1992 tcg_out32(s, OR | SAB(a1, a0, a2));
810260a8 1993 }
810260a8 1994 break;
fe6f943f 1995 case INDEX_op_xor_i64:
810260a8 1996 case INDEX_op_xor_i32:
dce74c57 1997 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 1998 if (const_args[2]) {
dce74c57
RH		 1999 tcg_out_xori32(s, a0, a1, a2);
2000 } else {
2001 tcg_out32(s, XOR | SAB(a1, a0, a2));
810260a8 2002 }
810260a8 2003 break;
ce1010d6 2004 case INDEX_op_andc_i32:
37251b98
RH		 2005 a0 = args[0], a1 = args[1], a2 = args[2];
2006 if (const_args[2]) {
2007 tcg_out_andi32(s, a0, a1, ~a2);
2008 } else {
2009 tcg_out32(s, ANDC | SAB(a1, a0, a2));
2010 }
2011 break;
ce1010d6 2012 case INDEX_op_andc_i64:
37251b98
RH		 2013 a0 = args[0], a1 = args[1], a2 = args[2];
2014 if (const_args[2]) {
2015 tcg_out_andi64(s, a0, a1, ~a2);
2016 } else {
2017 tcg_out32(s, ANDC | SAB(a1, a0, a2));
2018 }
ce1010d6
RH		 2019 break;
2020 case INDEX_op_orc_i32:
37251b98
RH		 2021 if (const_args[2]) {
2022 tcg_out_ori32(s, args[0], args[1], ~args[2]);
2023 break;
2024 }
2025 /* FALLTHRU */
ce1010d6
RH		 2026 case INDEX_op_orc_i64:
2027 tcg_out32(s, ORC | SAB(args[1], args[0], args[2]));
2028 break;
2029 case INDEX_op_eqv_i32:
37251b98
RH		 2030 if (const_args[2]) {
2031 tcg_out_xori32(s, args[0], args[1], ~args[2]);
2032 break;
2033 }
2034 /* FALLTHRU */
ce1010d6
RH		 2035 case INDEX_op_eqv_i64:
2036 tcg_out32(s, EQV | SAB(args[1], args[0], args[2]));
2037 break;
2038 case INDEX_op_nand_i32:
2039 case INDEX_op_nand_i64:
2040 tcg_out32(s, NAND | SAB(args[1], args[0], args[2]));
2041 break;
2042 case INDEX_op_nor_i32:
2043 case INDEX_op_nor_i64:
2044 tcg_out32(s, NOR | SAB(args[1], args[0], args[2]));
2045 break;
810260a8 2046
2047 case INDEX_op_mul_i32:
ef809300 2048 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 2049 if (const_args[2]) {
ef809300
RH		 2050 tcg_out32(s, MULLI | TAI(a0, a1, a2));
2051 } else {
2052 tcg_out32(s, MULLW | TAB(a0, a1, a2));
810260a8 2053 }
810260a8 2054 break;
2055
2056 case INDEX_op_div_i32:
541dd4ce 2057 tcg_out32(s, DIVW | TAB(args[0], args[1], args[2]));
810260a8 2058 break;
2059
2060 case INDEX_op_divu_i32:
541dd4ce 2061 tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2]));
810260a8 2062 break;
2063
810260a8 2064 case INDEX_op_shl_i32:
2065 if (const_args[2]) {
a757e1ee 2066 tcg_out_shli32(s, args[0], args[1], args[2]);
9e555b73 2067 } else {
541dd4ce 2068 tcg_out32(s, SLW | SAB(args[1], args[0], args[2]));
9e555b73 2069 }
810260a8 2070 break;
2071 case INDEX_op_shr_i32:
2072 if (const_args[2]) {
a757e1ee 2073 tcg_out_shri32(s, args[0], args[1], args[2]);
9e555b73 2074 } else {
541dd4ce 2075 tcg_out32(s, SRW | SAB(args[1], args[0], args[2]));
9e555b73 2076 }
810260a8 2077 break;
2078 case INDEX_op_sar_i32:
541dd4ce
RH		 2079 if (const_args[2]) {
2080 tcg_out32(s, SRAWI | RS(args[1]) | RA(args[0]) | SH(args[2]));
2081 } else {
2082 tcg_out32(s, SRAW | SAB(args[1], args[0], args[2]));
2083 }
810260a8 2084 break;
313d91c7
RH		 2085 case INDEX_op_rotl_i32:
2086 if (const_args[2]) {
2087 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31);
2088 } else {
2089 tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2])
2090 | MB(0) | ME(31));
2091 }
2092 break;
2093 case INDEX_op_rotr_i32:
2094 if (const_args[2]) {
2095 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31);
2096 } else {
8327a470
RH		 2097 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32));
2098 tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0)
313d91c7
RH		 2099 | MB(0) | ME(31));
2100 }
2101 break;
810260a8 2102
2103 case INDEX_op_brcond_i32:
4c314da6 2104 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
bec16311 2105 arg_label(args[3]), TCG_TYPE_I32);
e924bbec 2106 break;
810260a8 2107 case INDEX_op_brcond_i64:
4c314da6 2108 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
bec16311 2109 arg_label(args[3]), TCG_TYPE_I64);
810260a8 2110 break;
abcf61c4
RH		 2111 case INDEX_op_brcond2_i32:
2112 tcg_out_brcond2(s, args, const_args);
2113 break;
810260a8 2114
2115 case INDEX_op_neg_i32:
810260a8 2116 case INDEX_op_neg_i64:
541dd4ce 2117 tcg_out32(s, NEG | RT(args[0]) | RA(args[1]));
810260a8 2118 break;
2119
157f2662 2120 case INDEX_op_not_i32:
2121 case INDEX_op_not_i64:
541dd4ce 2122 tcg_out32(s, NOR | SAB(args[1], args[0], args[1]));
157f2662 2123 break;
2124
810260a8 2125 case INDEX_op_add_i64:
ee924fa6
RH		 2126 a0 = args[0], a1 = args[1], a2 = args[2];
2127 if (const_args[2]) {
ee924fa6 2128 do_addi_64:
b18d5d2b 2129 tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2);
ee924fa6
RH		 2130 } else {
2131 tcg_out32(s, ADD | TAB(a0, a1, a2));
2132 }
810260a8 2133 break;
2134 case INDEX_op_sub_i64:
ee924fa6 2135 a0 = args[0], a1 = args[1], a2 = args[2];
148bdd23
RH		 2136 if (const_args[1]) {
2137 if (const_args[2]) {
2138 tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2);
2139 } else {
2140 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
2141 }
2142 } else if (const_args[2]) {
ee924fa6
RH		 2143 a2 = -a2;
2144 goto do_addi_64;
2145 } else {
2146 tcg_out32(s, SUBF | TAB(a0, a2, a1));
2147 }
810260a8 2148 break;
2149
2150 case INDEX_op_shl_i64:
541dd4ce 2151 if (const_args[2]) {
0a9564b9 2152 tcg_out_shli64(s, args[0], args[1], args[2]);
541dd4ce
RH		 2153 } else {
2154 tcg_out32(s, SLD | SAB(args[1], args[0], args[2]));
2155 }
810260a8 2156 break;
2157 case INDEX_op_shr_i64:
541dd4ce 2158 if (const_args[2]) {
5e916c28 2159 tcg_out_shri64(s, args[0], args[1], args[2]);
541dd4ce
RH		 2160 } else {
2161 tcg_out32(s, SRD | SAB(args[1], args[0], args[2]));
2162 }
810260a8 2163 break;
2164 case INDEX_op_sar_i64:
fe6f943f 2165 if (const_args[2]) {
541dd4ce
RH		 2166 int sh = SH(args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1);
2167 tcg_out32(s, SRADI | RA(args[0]) | RS(args[1]) | sh);
2168 } else {
2169 tcg_out32(s, SRAD | SAB(args[1], args[0], args[2]));
fe6f943f 2170 }
810260a8 2171 break;
313d91c7
RH		 2172 case INDEX_op_rotl_i64:
2173 if (const_args[2]) {
2174 tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0);
2175 } else {
2176 tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0));
2177 }
2178 break;
2179 case INDEX_op_rotr_i64:
2180 if (const_args[2]) {
2181 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0);
2182 } else {
8327a470
RH		 2183 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64));
2184 tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0));
313d91c7
RH		 2185 }
2186 break;
810260a8 2187
2188 case INDEX_op_mul_i64:
ef809300
RH		 2189 a0 = args[0], a1 = args[1], a2 = args[2];
2190 if (const_args[2]) {
2191 tcg_out32(s, MULLI | TAI(a0, a1, a2));
2192 } else {
2193 tcg_out32(s, MULLD | TAB(a0, a1, a2));
2194 }
810260a8 2195 break;
2196 case INDEX_op_div_i64:
541dd4ce 2197 tcg_out32(s, DIVD | TAB(args[0], args[1], args[2]));
810260a8 2198 break;
2199 case INDEX_op_divu_i64:
541dd4ce 2200 tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2]));
810260a8 2201 break;
810260a8 2202
1768ec06 2203 case INDEX_op_qemu_ld_i32:
7f25c469
RH		 2204 tcg_out_qemu_ld(s, args, false);
2205 break;
1768ec06 2206 case INDEX_op_qemu_ld_i64:
7f25c469 2207 tcg_out_qemu_ld(s, args, true);
810260a8 2208 break;
1768ec06 2209 case INDEX_op_qemu_st_i32:
7f25c469
RH		 2210 tcg_out_qemu_st(s, args, false);
2211 break;
1768ec06 2212 case INDEX_op_qemu_st_i64:
7f25c469 2213 tcg_out_qemu_st(s, args, true);
810260a8 2214 break;
2215
e46b9681 2216 case INDEX_op_ext8s_i32:
2217 case INDEX_op_ext8s_i64:
2218 c = EXTSB;
2219 goto gen_ext;
2220 case INDEX_op_ext16s_i32:
2221 case INDEX_op_ext16s_i64:
2222 c = EXTSH;
2223 goto gen_ext;
4f2331e5 2224 case INDEX_op_ext_i32_i64:
e46b9681 2225 case INDEX_op_ext32s_i64:
2226 c = EXTSW;
2227 goto gen_ext;
2228 gen_ext:
541dd4ce 2229 tcg_out32(s, c | RS(args[1]) | RA(args[0]));
e46b9681 2230 break;
4f2331e5
AJ		 2231 case INDEX_op_extu_i32_i64:
2232 tcg_out_ext32u(s, args[0], args[1]);
2233 break;
e46b9681 2234
1cd62ae9 2235 case INDEX_op_setcond_i32:
541dd4ce
RH		 2236 tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
2237 const_args[2]);
1cd62ae9 2238 break;
2239 case INDEX_op_setcond_i64:
541dd4ce
RH		 2240 tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2],
2241 const_args[2]);
1cd62ae9 2242 break;
abcf61c4
RH		 2243 case INDEX_op_setcond2_i32:
2244 tcg_out_setcond2(s, args, const_args);
2245 break;
1cd62ae9 2246
5d221582
RH		 2247 case INDEX_op_bswap16_i32:
2248 case INDEX_op_bswap16_i64:
2249 a0 = args[0], a1 = args[1];
2250 /* a1 = abcd */
2251 if (a0 != a1) {
2252 /* a0 = (a1 r<< 24) & 0xff # 000c */
2253 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
2254 /* a0 = (a0 & ~0xff00) | (a1 r<< 8) & 0xff00 # 00dc */
2255 tcg_out_rlw(s, RLWIMI, a0, a1, 8, 16, 23);
2256 } else {
2257 /* r0 = (a1 r<< 8) & 0xff00 # 00d0 */
2258 tcg_out_rlw(s, RLWINM, TCG_REG_R0, a1, 8, 16, 23);
2259 /* a0 = (a1 r<< 24) & 0xff # 000c */
2260 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
2261 /* a0 = a0 | r0 # 00dc */
2262 tcg_out32(s, OR | SAB(TCG_REG_R0, a0, a0));
2263 }
2264 break;
2265
2266 case INDEX_op_bswap32_i32:
2267 case INDEX_op_bswap32_i64:
2268 /* Stolen from gcc's builtin_bswap32 */
2269 a1 = args[1];
2270 a0 = args[0] == a1 ? TCG_REG_R0 : args[0];
2271
2272 /* a1 = args[1] # abcd */
2273 /* a0 = rotate_left (a1, 8) # bcda */
2274 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
2275 /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */
2276 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
2277 /* a0 = (a0 & ~0x0000ff00) | ((a1 r<< 24) & 0x0000ff00) # dcba */
2278 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
2279
2280 if (a0 == TCG_REG_R0) {
de3d636d 2281 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
5d221582
RH		 2282 }
2283 break;
2284
68aebd45 2285 case INDEX_op_bswap64_i64:
8327a470 2286 a0 = args[0], a1 = args[1], a2 = TCG_REG_R0;
68aebd45 2287 if (a0 == a1) {
8327a470 2288 a0 = TCG_REG_R0;
68aebd45
RH		 2289 a2 = a1;
2290 }
2291
2292 /* a1 = # abcd efgh */
2293 /* a0 = rl32(a1, 8) # 0000 fghe */
2294 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
2295 /* a0 = dep(a0, rl32(a1, 24), 0xff000000) # 0000 hghe */
2296 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
2297 /* a0 = dep(a0, rl32(a1, 24), 0x0000ff00) # 0000 hgfe */
2298 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
2299
2300 /* a0 = rl64(a0, 32) # hgfe 0000 */
2301 /* a2 = rl64(a1, 32) # efgh abcd */
2302 tcg_out_rld(s, RLDICL, a0, a0, 32, 0);
2303 tcg_out_rld(s, RLDICL, a2, a1, 32, 0);
2304
2305 /* a0 = dep(a0, rl32(a2, 8), 0xffffffff) # hgfe bcda */
2306 tcg_out_rlw(s, RLWIMI, a0, a2, 8, 0, 31);
2307 /* a0 = dep(a0, rl32(a2, 24), 0xff000000) # hgfe dcda */
2308 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 0, 7);
2309 /* a0 = dep(a0, rl32(a2, 24), 0x0000ff00) # hgfe dcba */
2310 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 16, 23);
2311
2312 if (a0 == 0) {
de3d636d 2313 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
68aebd45
RH		 2314 }
2315 break;
2316
33de9ed2 2317 case INDEX_op_deposit_i32:
39dc85b9
RH		 2318 if (const_args[2]) {
2319 uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3];
2320 tcg_out_andi32(s, args[0], args[0], ~mask);
2321 } else {
2322 tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3],
2323 32 - args[3] - args[4], 31 - args[3]);
2324 }
33de9ed2
RH		 2325 break;
2326 case INDEX_op_deposit_i64:
39dc85b9
RH		 2327 if (const_args[2]) {
2328 uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3];
2329 tcg_out_andi64(s, args[0], args[0], ~mask);
2330 } else {
2331 tcg_out_rld(s, RLDIMI, args[0], args[2], args[3],
2332 64 - args[3] - args[4]);
2333 }
33de9ed2
RH		 2334 break;
2335
027ffea9
RH		 2336 case INDEX_op_movcond_i32:
2337 tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2],
2338 args[3], args[4], const_args[2]);
2339 break;
2340 case INDEX_op_movcond_i64:
2341 tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2],
2342 args[3], args[4], const_args[2]);
2343 break;
2344
796f1a68 2345#if TCG_TARGET_REG_BITS == 64
6c858762 2346 case INDEX_op_add2_i64:
796f1a68
RH		 2347#else
2348 case INDEX_op_add2_i32:
2349#endif
6c858762
RH		 2350 /* Note that the CA bit is defined based on the word size of the
2351 environment. So in 64-bit mode it's always carry-out of bit 63.
2352 The fallback code using deposit works just as well for 32-bit. */
2353 a0 = args[0], a1 = args[1];
84247357 2354 if (a0 == args[3] || (!const_args[5] && a0 == args[5])) {
6c858762
RH		 2355 a0 = TCG_REG_R0;
2356 }
84247357
AB		 2357 if (const_args[4]) {
2358 tcg_out32(s, ADDIC | TAI(a0, args[2], args[4]));
6c858762 2359 } else {
84247357 2360 tcg_out32(s, ADDC | TAB(a0, args[2], args[4]));
6c858762
RH		 2361 }
2362 if (const_args[5]) {
84247357 2363 tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3]));
6c858762 2364 } else {
84247357 2365 tcg_out32(s, ADDE | TAB(a1, args[3], args[5]));
6c858762
RH		 2366 }
2367 if (a0 != args[0]) {
de3d636d 2368 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
6c858762
RH		 2369 }
2370 break;
2371
796f1a68 2372#if TCG_TARGET_REG_BITS == 64
6c858762 2373 case INDEX_op_sub2_i64:
796f1a68
RH		 2374#else
2375 case INDEX_op_sub2_i32:
2376#endif
6c858762 2377 a0 = args[0], a1 = args[1];
b31284ce 2378 if (a0 == args[5] || (!const_args[3] && a0 == args[3])) {
6c858762
RH		 2379 a0 = TCG_REG_R0;
2380 }
2381 if (const_args[2]) {
b31284ce 2382 tcg_out32(s, SUBFIC | TAI(a0, args[4], args[2]));
6c858762 2383 } else {
b31284ce 2384 tcg_out32(s, SUBFC | TAB(a0, args[4], args[2]));
6c858762 2385 }
b31284ce
RH		 2386 if (const_args[3]) {
2387 tcg_out32(s, (args[3] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5]));
6c858762 2388 } else {
b31284ce 2389 tcg_out32(s, SUBFE | TAB(a1, args[5], args[3]));
6c858762
RH		 2390 }
2391 if (a0 != args[0]) {
de3d636d 2392 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
6c858762
RH		 2393 }
2394 break;
2395
abcf61c4
RH		 2396 case INDEX_op_muluh_i32:
2397 tcg_out32(s, MULHWU | TAB(args[0], args[1], args[2]));
2398 break;
8fa391a0
RH		 2399 case INDEX_op_mulsh_i32:
2400 tcg_out32(s, MULHW | TAB(args[0], args[1], args[2]));
2401 break;
32f5717f
RH		 2402 case INDEX_op_muluh_i64:
2403 tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2]));
2404 break;
2405 case INDEX_op_mulsh_i64:
2406 tcg_out32(s, MULHD | TAB(args[0], args[1], args[2]));
6645c147
RH		 2407 break;
2408
96d0ee7f
RH		 2409 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
2410 case INDEX_op_mov_i64:
2411 case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
2412 case INDEX_op_movi_i64:
2413 case INDEX_op_call: /* Always emitted via tcg_out_call. */
810260a8 2414 default:
541dd4ce 2415 tcg_abort();
810260a8 2416 }
2417}
2418
2419static const TCGTargetOpDef ppc_op_defs[] = {
2420 { INDEX_op_exit_tb, { } },
2421 { INDEX_op_goto_tb, { } },
810260a8 2422 { INDEX_op_br, { } },
2423
810260a8 2424 { INDEX_op_ld8u_i32, { "r", "r" } },
2425 { INDEX_op_ld8s_i32, { "r", "r" } },
2426 { INDEX_op_ld16u_i32, { "r", "r" } },
2427 { INDEX_op_ld16s_i32, { "r", "r" } },
2428 { INDEX_op_ld_i32, { "r", "r" } },
796f1a68 2429
810260a8 2430 { INDEX_op_st8_i32, { "r", "r" } },
810260a8 2431 { INDEX_op_st16_i32, { "r", "r" } },
810260a8 2432 { INDEX_op_st_i32, { "r", "r" } },
810260a8 2433
2434 { INDEX_op_add_i32, { "r", "r", "ri" } },
ef809300 2435 { INDEX_op_mul_i32, { "r", "r", "rI" } },
810260a8 2436 { INDEX_op_div_i32, { "r", "r", "r" } },
2437 { INDEX_op_divu_i32, { "r", "r", "r" } },
148bdd23 2438 { INDEX_op_sub_i32, { "r", "rI", "ri" } },
810260a8 2439 { INDEX_op_and_i32, { "r", "r", "ri" } },
2440 { INDEX_op_or_i32, { "r", "r", "ri" } },
2441 { INDEX_op_xor_i32, { "r", "r", "ri" } },
37251b98
RH		 2442 { INDEX_op_andc_i32, { "r", "r", "ri" } },
2443 { INDEX_op_orc_i32, { "r", "r", "ri" } },
2444 { INDEX_op_eqv_i32, { "r", "r", "ri" } },
ce1010d6
RH		 2445 { INDEX_op_nand_i32, { "r", "r", "r" } },
2446 { INDEX_op_nor_i32, { "r", "r", "r" } },
810260a8 2447
2448 { INDEX_op_shl_i32, { "r", "r", "ri" } },
2449 { INDEX_op_shr_i32, { "r", "r", "ri" } },
2450 { INDEX_op_sar_i32, { "r", "r", "ri" } },
313d91c7
RH		 2451 { INDEX_op_rotl_i32, { "r", "r", "ri" } },
2452 { INDEX_op_rotr_i32, { "r", "r", "ri" } },
810260a8 2453
810260a8 2454 { INDEX_op_neg_i32, { "r", "r" } },
157f2662 2455 { INDEX_op_not_i32, { "r", "r" } },
796f1a68
RH		 2456 { INDEX_op_ext8s_i32, { "r", "r" } },
2457 { INDEX_op_ext16s_i32, { "r", "r" } },
2458 { INDEX_op_bswap16_i32, { "r", "r" } },
2459 { INDEX_op_bswap32_i32, { "r", "r" } },
2460
2461 { INDEX_op_brcond_i32, { "r", "ri" } },
2462 { INDEX_op_setcond_i32, { "r", "r", "ri" } },
2463 { INDEX_op_movcond_i32, { "r", "r", "ri", "rZ", "rZ" } },
2464
2465 { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
2466
abcf61c4 2467 { INDEX_op_muluh_i32, { "r", "r", "r" } },
8fa391a0 2468 { INDEX_op_mulsh_i32, { "r", "r", "r" } },
abcf61c4 2469
796f1a68
RH		 2470#if TCG_TARGET_REG_BITS == 64
2471 { INDEX_op_ld8u_i64, { "r", "r" } },
2472 { INDEX_op_ld8s_i64, { "r", "r" } },
2473 { INDEX_op_ld16u_i64, { "r", "r" } },
2474 { INDEX_op_ld16s_i64, { "r", "r" } },
2475 { INDEX_op_ld32u_i64, { "r", "r" } },
2476 { INDEX_op_ld32s_i64, { "r", "r" } },
2477 { INDEX_op_ld_i64, { "r", "r" } },
2478
2479 { INDEX_op_st8_i64, { "r", "r" } },
2480 { INDEX_op_st16_i64, { "r", "r" } },
2481 { INDEX_op_st32_i64, { "r", "r" } },
2482 { INDEX_op_st_i64, { "r", "r" } },
810260a8 2483
ee924fa6 2484 { INDEX_op_add_i64, { "r", "r", "rT" } },
148bdd23 2485 { INDEX_op_sub_i64, { "r", "rI", "rT" } },
37251b98 2486 { INDEX_op_and_i64, { "r", "r", "ri" } },
3d582c61
RH		 2487 { INDEX_op_or_i64, { "r", "r", "rU" } },
2488 { INDEX_op_xor_i64, { "r", "r", "rU" } },
37251b98 2489 { INDEX_op_andc_i64, { "r", "r", "ri" } },
ce1010d6
RH		 2490 { INDEX_op_orc_i64, { "r", "r", "r" } },
2491 { INDEX_op_eqv_i64, { "r", "r", "r" } },
2492 { INDEX_op_nand_i64, { "r", "r", "r" } },
2493 { INDEX_op_nor_i64, { "r", "r", "r" } },
810260a8 2494
fe6f943f 2495 { INDEX_op_shl_i64, { "r", "r", "ri" } },
2496 { INDEX_op_shr_i64, { "r", "r", "ri" } },
2497 { INDEX_op_sar_i64, { "r", "r", "ri" } },
313d91c7
RH		 2498 { INDEX_op_rotl_i64, { "r", "r", "ri" } },
2499 { INDEX_op_rotr_i64, { "r", "r", "ri" } },
810260a8 2500
ef809300 2501 { INDEX_op_mul_i64, { "r", "r", "rI" } },
810260a8 2502 { INDEX_op_div_i64, { "r", "r", "r" } },
2503 { INDEX_op_divu_i64, { "r", "r", "r" } },
810260a8 2504
2505 { INDEX_op_neg_i64, { "r", "r" } },
157f2662 2506 { INDEX_op_not_i64, { "r", "r" } },
e46b9681 2507 { INDEX_op_ext8s_i64, { "r", "r" } },
2508 { INDEX_op_ext16s_i64, { "r", "r" } },
2509 { INDEX_op_ext32s_i64, { "r", "r" } },
4f2331e5
AJ		 2510 { INDEX_op_ext_i32_i64, { "r", "r" } },
2511 { INDEX_op_extu_i32_i64, { "r", "r" } },
5d221582 2512 { INDEX_op_bswap16_i64, { "r", "r" } },
5d221582 2513 { INDEX_op_bswap32_i64, { "r", "r" } },
68aebd45 2514 { INDEX_op_bswap64_i64, { "r", "r" } },
5d221582 2515
796f1a68
RH		 2516 { INDEX_op_brcond_i64, { "r", "ri" } },
2517 { INDEX_op_setcond_i64, { "r", "r", "ri" } },
2518 { INDEX_op_movcond_i64, { "r", "r", "ri", "rZ", "rZ" } },
2519
39dc85b9 2520 { INDEX_op_deposit_i64, { "r", "0", "rZ" } },
33de9ed2 2521
32f5717f
RH		 2522 { INDEX_op_mulsh_i64, { "r", "r", "r" } },
2523 { INDEX_op_muluh_i64, { "r", "r", "r" } },
796f1a68
RH		 2524#endif
2525
abcf61c4
RH		 2526#if TCG_TARGET_REG_BITS == 32
2527 { INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } },
2528 { INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },
2529#endif
2530
796f1a68
RH		 2531#if TCG_TARGET_REG_BITS == 64
2532 { INDEX_op_add2_i64, { "r", "r", "r", "r", "rI", "rZM" } },
2533 { INDEX_op_sub2_i64, { "r", "r", "rI", "rZM", "r", "r" } },
2534#else
2535 { INDEX_op_add2_i32, { "r", "r", "r", "r", "rI", "rZM" } },
2536 { INDEX_op_sub2_i32, { "r", "r", "rI", "rZM", "r", "r" } },
2537#endif
2538
2539#if TCG_TARGET_REG_BITS == 64
2540 { INDEX_op_qemu_ld_i32, { "r", "L" } },
2541 { INDEX_op_qemu_st_i32, { "S", "S" } },
2542 { INDEX_op_qemu_ld_i64, { "r", "L" } },
2543 { INDEX_op_qemu_st_i64, { "S", "S" } },
2544#elif TARGET_LONG_BITS == 32
2545 { INDEX_op_qemu_ld_i32, { "r", "L" } },
2546 { INDEX_op_qemu_st_i32, { "S", "S" } },
7f25c469 2547 { INDEX_op_qemu_ld_i64, { "L", "L", "L" } },
796f1a68
RH		 2548 { INDEX_op_qemu_st_i64, { "S", "S", "S" } },
2549#else
2550 { INDEX_op_qemu_ld_i32, { "r", "L", "L" } },
2551 { INDEX_op_qemu_st_i32, { "S", "S", "S" } },
7f25c469 2552 { INDEX_op_qemu_ld_i64, { "L", "L", "L", "L" } },
796f1a68
RH		 2553 { INDEX_op_qemu_st_i64, { "S", "S", "S", "S" } },
2554#endif
6c858762 2555
810260a8 2556 { -1 },
2557};
2558
541dd4ce 2559static void tcg_target_init(TCGContext *s)
810260a8 2560{
cd629de1 2561 unsigned long hwcap = qemu_getauxval(AT_HWCAP);
1e6e9aca
RH		 2562 if (hwcap & PPC_FEATURE_ARCH_2_06) {
2563 have_isa_2_06 = true;
2564 }
1e6e9aca 2565
541dd4ce
RH		 2566 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
2567 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
2568 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
810260a8 2569 (1 << TCG_REG_R0) |
5d7ff5bb 2570 (1 << TCG_REG_R2) |
810260a8 2571 (1 << TCG_REG_R3) |
2572 (1 << TCG_REG_R4) |
2573 (1 << TCG_REG_R5) |
2574 (1 << TCG_REG_R6) |
2575 (1 << TCG_REG_R7) |
2576 (1 << TCG_REG_R8) |
2577 (1 << TCG_REG_R9) |
2578 (1 << TCG_REG_R10) |
2579 (1 << TCG_REG_R11) |
5e1702b0 2580 (1 << TCG_REG_R12));
810260a8 2581
541dd4ce 2582 tcg_regset_clear(s->reserved_regs);
5e1702b0
RH		 2583 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */
2584 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */
dfca1778
RH		 2585#if defined(_CALL_SYSV)
2586 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* toc pointer */
5d7ff5bb 2587#endif
dfca1778 2588#if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS == 64
5e1702b0 2589 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
dfca1778
RH		 2590#endif
2591 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */
a84ac4cb
RH		 2592 if (USE_REG_RA) {
2593 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return addr */
2594 }
810260a8 2595
541dd4ce 2596 tcg_add_target_add_op_defs(ppc_op_defs);
810260a8 2597}
fa94c3be 2598
ffcfbece 2599#ifdef __ELF__
fa94c3be
RH		 2600typedef struct {
2601 DebugFrameCIE cie;
2602 DebugFrameFDEHeader fde;
2603 uint8_t fde_def_cfa[4];
2604 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2 + 3];
2605} DebugFrame;
2606
2607/* We're expecting a 2 byte uleb128 encoded value. */
2608QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
2609
ffcfbece
RH		 2610#if TCG_TARGET_REG_BITS == 64
2611# define ELF_HOST_MACHINE EM_PPC64
2612#else
2613# define ELF_HOST_MACHINE EM_PPC
2614#endif
fa94c3be
RH		 2615
2616static DebugFrame debug_frame = {
2617 .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
2618 .cie.id = -1,
2619 .cie.version = 1,
2620 .cie.code_align = 1,
802ca56e 2621 .cie.data_align = (-SZR & 0x7f), /* sleb128 -SZR */
fa94c3be
RH		 2622 .cie.return_column = 65,
2623
2624 /* Total FDE size does not include the "len" member. */
2625 .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset),
2626
2627 .fde_def_cfa = {
802ca56e 2628 12, TCG_REG_R1, /* DW_CFA_def_cfa r1, ... */
fa94c3be
RH		 2629 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2630 (FRAME_SIZE >> 7)
2631 },
2632 .fde_reg_ofs = {
802ca56e
RH		 2633 /* DW_CFA_offset_extended_sf, lr, LR_OFFSET */
2634 0x11, 65, (LR_OFFSET / -SZR) & 0x7f,
fa94c3be
RH		 2635 }
2636};
2637
2638void tcg_register_jit(void *buf, size_t buf_size)
2639{
2640 uint8_t *p = &debug_frame.fde_reg_ofs[3];
2641 int i;
2642
2643 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i, p += 2) {
2644 p[0] = 0x80 + tcg_target_callee_save_regs[i];
802ca56e 2645 p[1] = (FRAME_SIZE - (REG_SAVE_BOT + i * SZR)) / SZR;
fa94c3be
RH		 2646 }
2647
802ca56e 2648 debug_frame.fde.func_start = (uintptr_t)buf;
fa94c3be
RH		 2649 debug_frame.fde.func_len = buf_size;
2650
2651 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2652}
ffcfbece 2653#endif /* __ELF__ */
224f9fd4
RH		 2654
2655static size_t dcache_bsize = 16;
2656static size_t icache_bsize = 16;
2657
2658void flush_icache_range(uintptr_t start, uintptr_t stop)
2659{
2660 uintptr_t p, start1, stop1;
2661 size_t dsize = dcache_bsize;
2662 size_t isize = icache_bsize;
2663
2664 start1 = start & ~(dsize - 1);
2665 stop1 = (stop + dsize - 1) & ~(dsize - 1);
2666 for (p = start1; p < stop1; p += dsize) {
2667 asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");
2668 }
2669 asm volatile ("sync" : : : "memory");
2670
2671 start &= start & ~(isize - 1);
2672 stop1 = (stop + isize - 1) & ~(isize - 1);
2673 for (p = start1; p < stop1; p += isize) {
2674 asm volatile ("icbi 0,%0" : : "r"(p) : "memory");
2675 }
2676 asm volatile ("sync" : : : "memory");
2677 asm volatile ("isync" : : : "memory");
2678}
2679
2680#if defined _AIX
2681#include <sys/systemcfg.h>
2682
2683static void __attribute__((constructor)) tcg_cache_init(void)
2684{
2685 icache_bsize = _system_configuration.icache_line;
2686 dcache_bsize = _system_configuration.dcache_line;
2687}
2688
2689#elif defined __linux__
2690static void __attribute__((constructor)) tcg_cache_init(void)
2691{
2692 unsigned long dsize = qemu_getauxval(AT_DCACHEBSIZE);
2693 unsigned long isize = qemu_getauxval(AT_ICACHEBSIZE);
2694
2695 if (dsize == 0 || isize == 0) {
2696 if (dsize == 0) {
2697 fprintf(stderr, "getauxval AT_DCACHEBSIZE failed\n");
2698 }
2699 if (isize == 0) {
2700 fprintf(stderr, "getauxval AT_ICACHEBSIZE failed\n");
2701 }
2702 exit(1);
2703 }
2704 dcache_bsize = dsize;
2705 icache_bsize = isize;
2706}
2707
2708#elif defined __APPLE__
2709#include <stdio.h>
2710#include <sys/types.h>
2711#include <sys/sysctl.h>
2712
2713static void __attribute__((constructor)) tcg_cache_init(void)
2714{
2715 size_t len;
2716 unsigned cacheline;
2717 int name[2] = { CTL_HW, HW_CACHELINE };
2718
2719 len = sizeof(cacheline);
2720 if (sysctl(name, 2, &cacheline, &len, NULL, 0)) {
2721 perror("sysctl CTL_HW HW_CACHELINE failed");
2722 exit(1);
2723 }
2724 dcache_bsize = cacheline;
2725 icache_bsize = cacheline;
2726}
2727
2728#elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
2729#include <errno.h>
2730#include <stdio.h>
2731#include <stdlib.h>
2732#include <string.h>
2733#include <sys/types.h>
2734#include <sys/sysctl.h>
2735
2736static void __attribute__((constructor)) tcg_cache_init(void)
2737{
2738 size_t len = 4;
2739 unsigned cacheline;
2740
2741 if (sysctlbyname ("machdep.cacheline_size", &cacheline, &len, NULL, 0)) {
2742 fprintf(stderr, "sysctlbyname machdep.cacheline_size failed: %s\n",
2743 strerror(errno));
2744 exit(1);
2745 }
2746 dcache_bsize = cacheline;
2747 icache_bsize = cacheline;
2748}
2749#endif
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