]> git.proxmox.com Git - mirror_qemu.git/blame - tcg/ppc/tcg-target.c.inc
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
tcg/ppc: Split out tcg_out_sari{32,64}
[mirror_qemu.git] / tcg / ppc / tcg-target.c.inc
CommitLineData
810260a8 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
53c89efd 25#include "elf.h"
139c1837 26#include "../tcg-pool.c.inc"
53c89efd 27
ffcfbece
RH		 28#if defined _CALL_DARWIN || defined __APPLE__
29#define TCG_TARGET_CALL_DARWIN
30#endif
7f25c469
RH		 31#ifdef _CALL_SYSV
32# define TCG_TARGET_CALL_ALIGN_ARGS 1
33#endif
ffcfbece 34
dfca1778
RH		 35/* For some memory operations, we need a scratch that isn't R0. For the AIX
36 calling convention, we can re-use the TOC register since we'll be reloading
37 it at every call. Otherwise R12 will do nicely as neither a call-saved
38 register nor a parameter register. */
39#ifdef _CALL_AIX
40# define TCG_REG_TMP1 TCG_REG_R2
41#else
42# define TCG_REG_TMP1 TCG_REG_R12
43#endif
44
42281ec6
RH		 45#define TCG_VEC_TMP1 TCG_REG_V0
46#define TCG_VEC_TMP2 TCG_REG_V1
47
5964fca8
RH		 48#define TCG_REG_TB TCG_REG_R31
49#define USE_REG_TB (TCG_TARGET_REG_BITS == 64)
a84ac4cb 50
de3d636d
RH		 51/* Shorthand for size of a pointer. Avoid promotion to unsigned. */
52#define SZP ((int)sizeof(void *))
53
4c3831a0
RH		 54/* Shorthand for size of a register. */
55#define SZR (TCG_TARGET_REG_BITS / 8)
56
3d582c61
RH		 57#define TCG_CT_CONST_S16 0x100
58#define TCG_CT_CONST_U16 0x200
59#define TCG_CT_CONST_S32 0x400
60#define TCG_CT_CONST_U32 0x800
61#define TCG_CT_CONST_ZERO 0x1000
6c858762 62#define TCG_CT_CONST_MONE 0x2000
d0b07481 63#define TCG_CT_CONST_WSZ 0x4000
fe6f943f 64
85d251d7
RH		 65#define ALL_GENERAL_REGS 0xffffffffu
66#define ALL_VECTOR_REGS 0xffffffff00000000ull
67
68#ifdef CONFIG_SOFTMMU
69#define ALL_QLOAD_REGS \
70 (ALL_GENERAL_REGS & \
71 ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | (1 << TCG_REG_R5)))
72#define ALL_QSTORE_REGS \
73 (ALL_GENERAL_REGS & ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | \
74 (1 << TCG_REG_R5) | (1 << TCG_REG_R6)))
75#else
76#define ALL_QLOAD_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_R3))
77#define ALL_QSTORE_REGS ALL_QLOAD_REGS
78#endif
79
7d9dae0a 80TCGPowerISA have_isa;
63922f46 81static bool have_isel;
4b06c216 82bool have_altivec;
47c906ae 83bool have_vsx;
49d9870a 84
4cbea598 85#ifndef CONFIG_SOFTMMU
f6548c0a 86#define TCG_GUEST_BASE_REG 30
f6548c0a 87#endif
88
8d8fdbae 89#ifdef CONFIG_DEBUG_TCG
42281ec6
RH		 90static const char tcg_target_reg_names[TCG_TARGET_NB_REGS][4] = {
91 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
92 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
93 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
94 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
95 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
96 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
97 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
98 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
810260a8 99};
d4a9eb1f 100#endif
810260a8 101
102static const int tcg_target_reg_alloc_order[] = {
5e1702b0 103 TCG_REG_R14, /* call saved registers */
810260a8 104 TCG_REG_R15,
105 TCG_REG_R16,
106 TCG_REG_R17,
107 TCG_REG_R18,
108 TCG_REG_R19,
109 TCG_REG_R20,
110 TCG_REG_R21,
111 TCG_REG_R22,
112 TCG_REG_R23,
5e1702b0
RH		 113 TCG_REG_R24,
114 TCG_REG_R25,
115 TCG_REG_R26,
116 TCG_REG_R27,
810260a8 117 TCG_REG_R28,
118 TCG_REG_R29,
119 TCG_REG_R30,
120 TCG_REG_R31,
5e1702b0
RH		 121 TCG_REG_R12, /* call clobbered, non-arguments */
122 TCG_REG_R11,
dfca1778
RH		 123 TCG_REG_R2,
124 TCG_REG_R13,
5e1702b0 125 TCG_REG_R10, /* call clobbered, arguments */
810260a8 126 TCG_REG_R9,
5e1702b0
RH		 127 TCG_REG_R8,
128 TCG_REG_R7,
129 TCG_REG_R6,
130 TCG_REG_R5,
131 TCG_REG_R4,
132 TCG_REG_R3,
42281ec6
RH		 133
134 /* V0 and V1 reserved as temporaries; V20 - V31 are call-saved */
135 TCG_REG_V2, /* call clobbered, vectors */
136 TCG_REG_V3,
137 TCG_REG_V4,
138 TCG_REG_V5,
139 TCG_REG_V6,
140 TCG_REG_V7,
141 TCG_REG_V8,
142 TCG_REG_V9,
143 TCG_REG_V10,
144 TCG_REG_V11,
145 TCG_REG_V12,
146 TCG_REG_V13,
147 TCG_REG_V14,
148 TCG_REG_V15,
149 TCG_REG_V16,
150 TCG_REG_V17,
151 TCG_REG_V18,
152 TCG_REG_V19,
810260a8 153};
154
155static const int tcg_target_call_iarg_regs[] = {
156 TCG_REG_R3,
157 TCG_REG_R4,
158 TCG_REG_R5,
159 TCG_REG_R6,
160 TCG_REG_R7,
161 TCG_REG_R8,
162 TCG_REG_R9,
163 TCG_REG_R10
164};
165
be9c4183 166static const int tcg_target_call_oarg_regs[] = {
dfca1778
RH		 167 TCG_REG_R3,
168 TCG_REG_R4
810260a8 169};
170
171static const int tcg_target_callee_save_regs[] = {
dfca1778 172#ifdef TCG_TARGET_CALL_DARWIN
5d7ff5bb
AF		 173 TCG_REG_R11,
174#endif
810260a8 175 TCG_REG_R14,
176 TCG_REG_R15,
177 TCG_REG_R16,
178 TCG_REG_R17,
179 TCG_REG_R18,
180 TCG_REG_R19,
181 TCG_REG_R20,
182 TCG_REG_R21,
183 TCG_REG_R22,
184 TCG_REG_R23,
095271d4 185 TCG_REG_R24,
186 TCG_REG_R25,
187 TCG_REG_R26,
cea5f9a2 188 TCG_REG_R27, /* currently used for the global env */
810260a8 189 TCG_REG_R28,
190 TCG_REG_R29,
191 TCG_REG_R30,
192 TCG_REG_R31
193};
194
b0940da0
RH		 195static inline bool in_range_b(tcg_target_long target)
196{
197 return target == sextract64(target, 0, 26);
198}
199
d54401df
RH		 200static uint32_t reloc_pc24_val(const tcg_insn_unit *pc,
201 const tcg_insn_unit *target)
810260a8 202{
e083c4a2 203 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
eabb7b91 204 tcg_debug_assert(in_range_b(disp));
810260a8 205 return disp & 0x3fffffc;
206}
207
d54401df 208static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
810260a8 209{
d54401df
RH		 210 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
211 ptrdiff_t disp = tcg_ptr_byte_diff(target, src_rx);
212
d5132903 213 if (in_range_b(disp)) {
d54401df 214 *src_rw = (*src_rw & ~0x3fffffc) | (disp & 0x3fffffc);
d5132903
RH		 215 return true;
216 }
217 return false;
810260a8 218}
219
d54401df
RH		 220static uint16_t reloc_pc14_val(const tcg_insn_unit *pc,
221 const tcg_insn_unit *target)
810260a8 222{
e083c4a2 223 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
eabb7b91 224 tcg_debug_assert(disp == (int16_t) disp);
810260a8 225 return disp & 0xfffc;
226}
227
d54401df 228static bool reloc_pc14(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
810260a8 229{
d54401df
RH		 230 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
231 ptrdiff_t disp = tcg_ptr_byte_diff(target, src_rx);
232
d5132903 233 if (disp == (int16_t) disp) {
d54401df 234 *src_rw = (*src_rw & ~0xfffc) | (disp & 0xfffc);
d5132903
RH		 235 return true;
236 }
237 return false;
810260a8 238}
239
810260a8 240/* test if a constant matches the constraint */
a4fbbd77 241static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
810260a8 242{
3d582c61
RH		 243 if (ct & TCG_CT_CONST) {
244 return 1;
1194dcba
RH		 245 }
246
247 /* The only 32-bit constraint we use aside from
248 TCG_CT_CONST is TCG_CT_CONST_S16. */
249 if (type == TCG_TYPE_I32) {
250 val = (int32_t)val;
251 }
252
253 if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
3d582c61
RH		 254 return 1;
255 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
810260a8 256 return 1;
3d582c61 257 } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
fe6f943f 258 return 1;
3d582c61
RH		 259 } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
260 return 1;
261 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
262 return 1;
6c858762
RH		 263 } else if ((ct & TCG_CT_CONST_MONE) && val == -1) {
264 return 1;
d0b07481
RH		 265 } else if ((ct & TCG_CT_CONST_WSZ)
266 && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
267 return 1;
3d582c61 268 }
810260a8 269 return 0;
270}
271
272#define OPCD(opc) ((opc)<<26)
273#define XO19(opc) (OPCD(19)|((opc)<<1))
8a94cfb0
AB		 274#define MD30(opc) (OPCD(30)|((opc)<<2))
275#define MDS30(opc) (OPCD(30)|((opc)<<1))
810260a8 276#define XO31(opc) (OPCD(31)|((opc)<<1))
277#define XO58(opc) (OPCD(58)|(opc))
278#define XO62(opc) (OPCD(62)|(opc))
1838905e 279#define VX4(opc) (OPCD(4)|(opc))
810260a8 280
281#define B OPCD( 18)
282#define BC OPCD( 16)
283#define LBZ OPCD( 34)
284#define LHZ OPCD( 40)
285#define LHA OPCD( 42)
286#define LWZ OPCD( 32)
644f591a 287#define LWZUX XO31( 55)
810260a8 288#define STB OPCD( 38)
289#define STH OPCD( 44)
290#define STW OPCD( 36)
291
292#define STD XO62( 0)
293#define STDU XO62( 1)
294#define STDX XO31(149)
295
296#define LD XO58( 0)
297#define LDX XO31( 21)
298#define LDU XO58( 1)
644f591a 299#define LDUX XO31( 53)
301f6d90 300#define LWA XO58( 2)
810260a8 301#define LWAX XO31(341)
302
1cd62ae9 303#define ADDIC OPCD( 12)
810260a8 304#define ADDI OPCD( 14)
305#define ADDIS OPCD( 15)
306#define ORI OPCD( 24)
307#define ORIS OPCD( 25)
308#define XORI OPCD( 26)
309#define XORIS OPCD( 27)
310#define ANDI OPCD( 28)
311#define ANDIS OPCD( 29)
312#define MULLI OPCD( 7)
313#define CMPLI OPCD( 10)
314#define CMPI OPCD( 11)
148bdd23 315#define SUBFIC OPCD( 8)
810260a8 316
317#define LWZU OPCD( 33)
318#define STWU OPCD( 37)
319
313d91c7 320#define RLWIMI OPCD( 20)
810260a8 321#define RLWINM OPCD( 21)
313d91c7 322#define RLWNM OPCD( 23)
810260a8 323
8a94cfb0
AB		 324#define RLDICL MD30( 0)
325#define RLDICR MD30( 1)
326#define RLDIMI MD30( 3)
327#define RLDCL MDS30( 8)
810260a8 328
329#define BCLR XO19( 16)
330#define BCCTR XO19(528)
331#define CRAND XO19(257)
332#define CRANDC XO19(129)
333#define CRNAND XO19(225)
334#define CROR XO19(449)
1cd62ae9 335#define CRNOR XO19( 33)
810260a8 336
337#define EXTSB XO31(954)
338#define EXTSH XO31(922)
339#define EXTSW XO31(986)
340#define ADD XO31(266)
341#define ADDE XO31(138)
6c858762
RH		 342#define ADDME XO31(234)
343#define ADDZE XO31(202)
810260a8 344#define ADDC XO31( 10)
345#define AND XO31( 28)
346#define SUBF XO31( 40)
347#define SUBFC XO31( 8)
348#define SUBFE XO31(136)
6c858762
RH		 349#define SUBFME XO31(232)
350#define SUBFZE XO31(200)
810260a8 351#define OR XO31(444)
352#define XOR XO31(316)
353#define MULLW XO31(235)
8fa391a0 354#define MULHW XO31( 75)
810260a8 355#define MULHWU XO31( 11)
356#define DIVW XO31(491)
357#define DIVWU XO31(459)
358#define CMP XO31( 0)
359#define CMPL XO31( 32)
360#define LHBRX XO31(790)
361#define LWBRX XO31(534)
49d9870a 362#define LDBRX XO31(532)
810260a8 363#define STHBRX XO31(918)
364#define STWBRX XO31(662)
49d9870a 365#define STDBRX XO31(660)
810260a8 366#define MFSPR XO31(339)
367#define MTSPR XO31(467)
368#define SRAWI XO31(824)
369#define NEG XO31(104)
1cd62ae9 370#define MFCR XO31( 19)
6995a4a0 371#define MFOCRF (MFCR | (1u << 20))
157f2662 372#define NOR XO31(124)
1cd62ae9 373#define CNTLZW XO31( 26)
374#define CNTLZD XO31( 58)
d0b07481
RH		 375#define CNTTZW XO31(538)
376#define CNTTZD XO31(570)
33e75fb9
RH		 377#define CNTPOPW XO31(378)
378#define CNTPOPD XO31(506)
ce1010d6
RH		 379#define ANDC XO31( 60)
380#define ORC XO31(412)
381#define EQV XO31(284)
382#define NAND XO31(476)
70fac59a 383#define ISEL XO31( 15)
810260a8 384
385#define MULLD XO31(233)
386#define MULHD XO31( 73)
387#define MULHDU XO31( 9)
388#define DIVD XO31(489)
389#define DIVDU XO31(457)
390
391#define LBZX XO31( 87)
4f4a67ae 392#define LHZX XO31(279)
810260a8 393#define LHAX XO31(343)
394#define LWZX XO31( 23)
395#define STBX XO31(215)
396#define STHX XO31(407)
397#define STWX XO31(151)
398
7b4af5ee
PK		 399#define EIEIO XO31(854)
400#define HWSYNC XO31(598)
401#define LWSYNC (HWSYNC | (1u << 21))
402
541dd4ce 403#define SPR(a, b) ((((a)<<5)|(b))<<11)
810260a8 404#define LR SPR(8, 0)
405#define CTR SPR(9, 0)
406
407#define SLW XO31( 24)
408#define SRW XO31(536)
409#define SRAW XO31(792)
410
411#define SLD XO31( 27)
412#define SRD XO31(539)
413#define SRAD XO31(794)
fe6f943f 414#define SRADI XO31(413<<1)
810260a8 415
810260a8 416#define TW XO31( 4)
541dd4ce 417#define TRAP (TW | TO(31))
810260a8 418
a84ac4cb
RH		 419#define NOP ORI /* ori 0,0,0 */
420
6ef14d7e
RH		 421#define LVX XO31(103)
422#define LVEBX XO31(7)
423#define LVEHX XO31(39)
424#define LVEWX XO31(71)
47c906ae
RH		 425#define LXSDX (XO31(588) | 1) /* v2.06, force tx=1 */
426#define LXVDSX (XO31(332) | 1) /* v2.06, force tx=1 */
b2dda640 427#define LXSIWZX (XO31(12) | 1) /* v2.07, force tx=1 */
6e11cde1
RH		 428#define LXV (OPCD(61) | 8 | 1) /* v3.00, force tx=1 */
429#define LXSD (OPCD(57) | 2) /* v3.00 */
430#define LXVWSX (XO31(364) | 1) /* v3.00, force tx=1 */
6ef14d7e
RH		 431
432#define STVX XO31(231)
433#define STVEWX XO31(199)
47c906ae 434#define STXSDX (XO31(716) | 1) /* v2.06, force sx=1 */
b2dda640 435#define STXSIWX (XO31(140) | 1) /* v2.07, force sx=1 */
6e11cde1
RH		 436#define STXV (OPCD(61) | 8 | 5) /* v3.00, force sx=1 */
437#define STXSD (OPCD(61) | 2) /* v3.00 */
6ef14d7e 438
e9d1a53a
RH		 439#define VADDSBS VX4(768)
440#define VADDUBS VX4(512)
d6750811 441#define VADDUBM VX4(0)
e9d1a53a
RH		 442#define VADDSHS VX4(832)
443#define VADDUHS VX4(576)
d6750811 444#define VADDUHM VX4(64)
e9d1a53a
RH		 445#define VADDSWS VX4(896)
446#define VADDUWS VX4(640)
d6750811 447#define VADDUWM VX4(128)
64ff1c6d 448#define VADDUDM VX4(192) /* v2.07 */
d6750811 449
e9d1a53a
RH		 450#define VSUBSBS VX4(1792)
451#define VSUBUBS VX4(1536)
d6750811 452#define VSUBUBM VX4(1024)
e9d1a53a
RH		 453#define VSUBSHS VX4(1856)
454#define VSUBUHS VX4(1600)
d6750811 455#define VSUBUHM VX4(1088)
e9d1a53a
RH		 456#define VSUBSWS VX4(1920)
457#define VSUBUWS VX4(1664)
d6750811 458#define VSUBUWM VX4(1152)
64ff1c6d 459#define VSUBUDM VX4(1216) /* v2.07 */
d6750811 460
d7cd6a2f
RH		 461#define VNEGW (VX4(1538) | (6 << 16)) /* v3.00 */
462#define VNEGD (VX4(1538) | (7 << 16)) /* v3.00 */
463
e2382972
RH		 464#define VMAXSB VX4(258)
465#define VMAXSH VX4(322)
466#define VMAXSW VX4(386)
64ff1c6d 467#define VMAXSD VX4(450) /* v2.07 */
e2382972
RH		 468#define VMAXUB VX4(2)
469#define VMAXUH VX4(66)
470#define VMAXUW VX4(130)
64ff1c6d 471#define VMAXUD VX4(194) /* v2.07 */
e2382972
RH		 472#define VMINSB VX4(770)
473#define VMINSH VX4(834)
474#define VMINSW VX4(898)
64ff1c6d 475#define VMINSD VX4(962) /* v2.07 */
e2382972
RH		 476#define VMINUB VX4(514)
477#define VMINUH VX4(578)
478#define VMINUW VX4(642)
64ff1c6d 479#define VMINUD VX4(706) /* v2.07 */
e2382972 480
6ef14d7e
RH		 481#define VCMPEQUB VX4(6)
482#define VCMPEQUH VX4(70)
483#define VCMPEQUW VX4(134)
64ff1c6d 484#define VCMPEQUD VX4(199) /* v2.07 */
6ef14d7e
RH		 485#define VCMPGTSB VX4(774)
486#define VCMPGTSH VX4(838)
487#define VCMPGTSW VX4(902)
64ff1c6d 488#define VCMPGTSD VX4(967) /* v2.07 */
6ef14d7e
RH		 489#define VCMPGTUB VX4(518)
490#define VCMPGTUH VX4(582)
491#define VCMPGTUW VX4(646)
64ff1c6d 492#define VCMPGTUD VX4(711) /* v2.07 */
d7cd6a2f
RH		 493#define VCMPNEB VX4(7) /* v3.00 */
494#define VCMPNEH VX4(71) /* v3.00 */
495#define VCMPNEW VX4(135) /* v3.00 */
6ef14d7e 496
dabae097
RH		 497#define VSLB VX4(260)
498#define VSLH VX4(324)
499#define VSLW VX4(388)
64ff1c6d 500#define VSLD VX4(1476) /* v2.07 */
dabae097
RH		 501#define VSRB VX4(516)
502#define VSRH VX4(580)
503#define VSRW VX4(644)
64ff1c6d 504#define VSRD VX4(1732) /* v2.07 */
dabae097
RH		 505#define VSRAB VX4(772)
506#define VSRAH VX4(836)
507#define VSRAW VX4(900)
64ff1c6d 508#define VSRAD VX4(964) /* v2.07 */
d9897efa
RH		 509#define VRLB VX4(4)
510#define VRLH VX4(68)
511#define VRLW VX4(132)
64ff1c6d 512#define VRLD VX4(196) /* v2.07 */
d9897efa
RH		 513
514#define VMULEUB VX4(520)
515#define VMULEUH VX4(584)
64ff1c6d 516#define VMULEUW VX4(648) /* v2.07 */
d9897efa
RH		 517#define VMULOUB VX4(8)
518#define VMULOUH VX4(72)
64ff1c6d
RH		 519#define VMULOUW VX4(136) /* v2.07 */
520#define VMULUWM VX4(137) /* v2.07 */
73ebe95e 521#define VMULLD VX4(457) /* v3.10 */
d9897efa
RH		 522#define VMSUMUHM VX4(38)
523
524#define VMRGHB VX4(12)
525#define VMRGHH VX4(76)
526#define VMRGHW VX4(140)
527#define VMRGLB VX4(268)
528#define VMRGLH VX4(332)
529#define VMRGLW VX4(396)
530
531#define VPKUHUM VX4(14)
532#define VPKUWUM VX4(78)
dabae097 533
6ef14d7e
RH		 534#define VAND VX4(1028)
535#define VANDC VX4(1092)
536#define VNOR VX4(1284)
537#define VOR VX4(1156)
538#define VXOR VX4(1220)
64ff1c6d
RH		 539#define VEQV VX4(1668) /* v2.07 */
540#define VNAND VX4(1412) /* v2.07 */
541#define VORC VX4(1348) /* v2.07 */
6ef14d7e
RH		 542
543#define VSPLTB VX4(524)
544#define VSPLTH VX4(588)
545#define VSPLTW VX4(652)
546#define VSPLTISB VX4(780)
547#define VSPLTISH VX4(844)
548#define VSPLTISW VX4(908)
549
550#define VSLDOI VX4(44)
551
47c906ae
RH		 552#define XXPERMDI (OPCD(60) | (10 << 3) | 7) /* v2.06, force ax=bx=tx=1 */
553#define XXSEL (OPCD(60) | (3 << 4) | 0xf) /* v2.06, force ax=bx=cx=tx=1 */
b7ce3cff 554#define XXSPLTIB (OPCD(60) | (360 << 1) | 1) /* v3.00, force tx=1 */
47c906ae 555
7097312d
RH		 556#define MFVSRD (XO31(51) | 1) /* v2.07, force sx=1 */
557#define MFVSRWZ (XO31(115) | 1) /* v2.07, force sx=1 */
558#define MTVSRD (XO31(179) | 1) /* v2.07, force tx=1 */
559#define MTVSRWZ (XO31(243) | 1) /* v2.07, force tx=1 */
b7ce3cff
RH		 560#define MTVSRDD (XO31(435) | 1) /* v3.00, force tx=1 */
561#define MTVSRWS (XO31(403) | 1) /* v3.00, force tx=1 */
7097312d 562
810260a8 563#define RT(r) ((r)<<21)
564#define RS(r) ((r)<<21)
565#define RA(r) ((r)<<16)
566#define RB(r) ((r)<<11)
567#define TO(t) ((t)<<21)
568#define SH(s) ((s)<<11)
569#define MB(b) ((b)<<6)
570#define ME(e) ((e)<<1)
571#define BO(o) ((o)<<21)
572#define MB64(b) ((b)<<5)
6995a4a0 573#define FXM(b) (1 << (19 - (b)))
810260a8 574
b82f769c
RH		 575#define VRT(r) (((r) & 31) << 21)
576#define VRA(r) (((r) & 31) << 16)
577#define VRB(r) (((r) & 31) << 11)
578#define VRC(r) (((r) & 31) << 6)
579
810260a8 580#define LK 1
581
2fd8eddc
RH		 582#define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
583#define SAB(s, a, b) (RS(s) | RA(a) | RB(b))
584#define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff))
585#define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff))
810260a8 586
587#define BF(n) ((n)<<23)
588#define BI(n, c) (((c)+((n)*4))<<16)
589#define BT(n, c) (((c)+((n)*4))<<21)
590#define BA(n, c) (((c)+((n)*4))<<16)
591#define BB(n, c) (((c)+((n)*4))<<11)
70fac59a 592#define BC_(n, c) (((c)+((n)*4))<<6)
810260a8 593
541dd4ce
RH		 594#define BO_COND_TRUE BO(12)
595#define BO_COND_FALSE BO( 4)
596#define BO_ALWAYS BO(20)
810260a8 597
598enum {
599 CR_LT,
600 CR_GT,
601 CR_EQ,
602 CR_SO
603};
604
0aed257f 605static const uint32_t tcg_to_bc[] = {
541dd4ce
RH		 606 [TCG_COND_EQ] = BC | BI(7, CR_EQ) | BO_COND_TRUE,
607 [TCG_COND_NE] = BC | BI(7, CR_EQ) | BO_COND_FALSE,
608 [TCG_COND_LT] = BC | BI(7, CR_LT) | BO_COND_TRUE,
609 [TCG_COND_GE] = BC | BI(7, CR_LT) | BO_COND_FALSE,
610 [TCG_COND_LE] = BC | BI(7, CR_GT) | BO_COND_FALSE,
611 [TCG_COND_GT] = BC | BI(7, CR_GT) | BO_COND_TRUE,
612 [TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE,
613 [TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE,
614 [TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE,
615 [TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE,
810260a8 616};
617
70fac59a
RH		 618/* The low bit here is set if the RA and RB fields must be inverted. */
619static const uint32_t tcg_to_isel[] = {
620 [TCG_COND_EQ] = ISEL | BC_(7, CR_EQ),
621 [TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1,
622 [TCG_COND_LT] = ISEL | BC_(7, CR_LT),
623 [TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1,
624 [TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1,
625 [TCG_COND_GT] = ISEL | BC_(7, CR_GT),
626 [TCG_COND_LTU] = ISEL | BC_(7, CR_LT),
627 [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1,
628 [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1,
629 [TCG_COND_GTU] = ISEL | BC_(7, CR_GT),
630};
631
6ac17786 632static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
030ffe39
RH		 633 intptr_t value, intptr_t addend)
634{
d54401df 635 const tcg_insn_unit *target;
6ef14d7e
RH		 636 int16_t lo;
637 int32_t hi;
030ffe39
RH		 638
639 value += addend;
d54401df 640 target = (const tcg_insn_unit *)value;
030ffe39
RH		 641
642 switch (type) {
643 case R_PPC_REL14:
d5132903 644 return reloc_pc14(code_ptr, target);
030ffe39 645 case R_PPC_REL24:
d5132903 646 return reloc_pc24(code_ptr, target);
030ffe39 647 case R_PPC_ADDR16:
a7cdaf71
RH		 648 /*
649 * We are (slightly) abusing this relocation type. In particular,
650 * assert that the low 2 bits are zero, and do not modify them.
651 * That way we can use this with LD et al that have opcode bits
652 * in the low 2 bits of the insn.
653 */
654 if ((value & 3) || value != (int16_t)value) {
655 return false;
030ffe39 656 }
a7cdaf71 657 *code_ptr = (*code_ptr & ~0xfffc) | (value & 0xfffc);
030ffe39 658 break;
6ef14d7e
RH		 659 case R_PPC_ADDR32:
660 /*
661 * We are abusing this relocation type. Again, this points to
662 * a pair of insns, lis + load. This is an absolute address
663 * relocation for PPC32 so the lis cannot be removed.
664 */
665 lo = value;
666 hi = value - lo;
667 if (hi + lo != value) {
668 return false;
669 }
670 code_ptr[0] = deposit32(code_ptr[0], 0, 16, hi >> 16);
671 code_ptr[1] = deposit32(code_ptr[1], 0, 16, lo);
672 break;
030ffe39
RH		 673 default:
674 g_assert_not_reached();
675 }
6ac17786 676 return true;
030ffe39
RH		 677}
678
a84ac4cb
RH		 679static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
680 TCGReg base, tcg_target_long offset);
681
78113e83 682static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
810260a8 683{
6ef14d7e
RH		 684 if (ret == arg) {
685 return true;
686 }
687 switch (type) {
688 case TCG_TYPE_I64:
689 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
690 /* fallthru */
691 case TCG_TYPE_I32:
7097312d
RH		 692 if (ret < TCG_REG_V0) {
693 if (arg < TCG_REG_V0) {
694 tcg_out32(s, OR | SAB(arg, ret, arg));
695 break;
696 } else if (have_isa_2_07) {
697 tcg_out32(s, (type == TCG_TYPE_I32 ? MFVSRWZ : MFVSRD)
698 | VRT(arg) | RA(ret));
699 break;
700 } else {
701 /* Altivec does not support vector->integer moves. */
702 return false;
703 }
704 } else if (arg < TCG_REG_V0) {
705 if (have_isa_2_07) {
706 tcg_out32(s, (type == TCG_TYPE_I32 ? MTVSRWZ : MTVSRD)
707 | VRT(ret) | RA(arg));
708 break;
709 } else {
710 /* Altivec does not support integer->vector moves. */
711 return false;
712 }
6ef14d7e
RH		 713 }
714 /* fallthru */
715 case TCG_TYPE_V64:
716 case TCG_TYPE_V128:
717 tcg_debug_assert(ret >= TCG_REG_V0 && arg >= TCG_REG_V0);
718 tcg_out32(s, VOR | VRT(ret) | VRA(arg) | VRB(arg));
719 break;
720 default:
721 g_assert_not_reached();
f8b84129 722 }
78113e83 723 return true;
810260a8 724}
725
aceac8d6
RH		 726static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs,
727 int sh, int mb)
810260a8 728{
eabb7b91 729 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
541dd4ce
RH		 730 sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1);
731 mb = MB64((mb >> 5) | ((mb << 1) & 0x3f));
732 tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb);
810260a8 733}
734
9e555b73
RH		 735static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs,
736 int sh, int mb, int me)
737{
738 tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me));
739}
740
f4bf14f4
RH		 741static inline void tcg_out_ext8s(TCGContext *s, TCGReg dst, TCGReg src)
742{
743 tcg_out32(s, EXTSB | RA(dst) | RS(src));
744}
745
746static inline void tcg_out_ext16s(TCGContext *s, TCGReg dst, TCGReg src)
747{
748 tcg_out32(s, EXTSH | RA(dst) | RS(src));
749}
750
751static inline void tcg_out_ext32s(TCGContext *s, TCGReg dst, TCGReg src)
752{
753 tcg_out32(s, EXTSW | RA(dst) | RS(src));
754}
755
6e5e0602
RH		 756static inline void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src)
757{
758 tcg_out_rld(s, RLDICL, dst, src, 0, 32);
759}
760
a757e1ee
RH		 761static inline void tcg_out_shli32(TCGContext *s, TCGReg dst, TCGReg src, int c)
762{
763 tcg_out_rlw(s, RLWINM, dst, src, c, 0, 31 - c);
764}
765
0a9564b9
RH		 766static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c)
767{
768 tcg_out_rld(s, RLDICR, dst, src, c, 63 - c);
769}
770
05dd01fa
RH		 771static inline void tcg_out_sari32(TCGContext *s, TCGReg dst, TCGReg src, int c)
772{
773 /* Limit immediate shift count lest we create an illegal insn. */
774 tcg_out32(s, SRAWI | RA(dst) | RS(src) | SH(c & 31));
775}
776
a757e1ee
RH		 777static inline void tcg_out_shri32(TCGContext *s, TCGReg dst, TCGReg src, int c)
778{
779 tcg_out_rlw(s, RLWINM, dst, src, 32 - c, c, 31);
780}
781
5e916c28
RH		 782static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c)
783{
784 tcg_out_rld(s, RLDICL, dst, src, 64 - c, c);
785}
786
05dd01fa
RH		 787static inline void tcg_out_sari64(TCGContext *s, TCGReg dst, TCGReg src, int c)
788{
789 tcg_out32(s, SRADI | RA(dst) | RS(src) | SH(c & 0x1f) | ((c >> 4) & 2));
790}
791
77bfc7c0
RH		 792/* Emit a move into ret of arg, if it can be done in one insn. */
793static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg)
794{
795 if (arg == (int16_t)arg) {
796 tcg_out32(s, ADDI | TAI(ret, 0, arg));
797 return true;
798 }
799 if (arg == (int32_t)arg && (arg & 0xffff) == 0) {
800 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
801 return true;
802 }
803 return false;
804}
805
5964fca8
RH		 806static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
807 tcg_target_long arg, bool in_prologue)
810260a8 808{
5964fca8 809 intptr_t tb_diff;
77bfc7c0
RH		 810 tcg_target_long tmp;
811 int shift;
5964fca8
RH		 812
813 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
814
815 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
816 arg = (int32_t)arg;
817 }
818
819 /* Load 16-bit immediates with one insn. */
77bfc7c0 820 if (tcg_out_movi_one(s, ret, arg)) {
5964fca8
RH		 821 return;
822 }
823
824 /* Load addresses within the TB with one insn. */
e6dc7f81 825 tb_diff = tcg_tbrel_diff(s, (void *)arg);
5964fca8
RH		 826 if (!in_prologue && USE_REG_TB && tb_diff == (int16_t)tb_diff) {
827 tcg_out32(s, ADDI | TAI(ret, TCG_REG_TB, tb_diff));
828 return;
829 }
830
77bfc7c0
RH		 831 /* Load 32-bit immediates with two insns. Note that we've already
832 eliminated bare ADDIS, so we know both insns are required. */
5964fca8 833 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
2fd8eddc 834 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
77bfc7c0 835 tcg_out32(s, ORI | SAI(ret, ret, arg));
5964fca8 836 return;
810260a8 837 }
5964fca8 838 if (arg == (uint32_t)arg && !(arg & 0x8000)) {
421233a1
RH		 839 tcg_out32(s, ADDI | TAI(ret, 0, arg));
840 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
5964fca8
RH		 841 return;
842 }
a84ac4cb 843
77bfc7c0
RH		 844 /* Load masked 16-bit value. */
845 if (arg > 0 && (arg & 0x8000)) {
846 tmp = arg | 0x7fff;
847 if ((tmp & (tmp + 1)) == 0) {
848 int mb = clz64(tmp + 1) + 1;
849 tcg_out32(s, ADDI | TAI(ret, 0, arg));
850 tcg_out_rld(s, RLDICL, ret, ret, 0, mb);
851 return;
852 }
853 }
854
855 /* Load common masks with 2 insns. */
856 shift = ctz64(arg);
857 tmp = arg >> shift;
858 if (tmp == (int16_t)tmp) {
859 tcg_out32(s, ADDI | TAI(ret, 0, tmp));
860 tcg_out_shli64(s, ret, ret, shift);
861 return;
862 }
863 shift = clz64(arg);
864 if (tcg_out_movi_one(s, ret, arg << shift)) {
865 tcg_out_shri64(s, ret, ret, shift);
866 return;
867 }
868
5964fca8
RH		 869 /* Load addresses within 2GB of TB with 2 (or rarely 3) insns. */
870 if (!in_prologue && USE_REG_TB && tb_diff == (int32_t)tb_diff) {
871 tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_TB, tb_diff);
872 return;
873 }
a84ac4cb 874
53c89efd
RH		 875 /* Use the constant pool, if possible. */
876 if (!in_prologue && USE_REG_TB) {
877 new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr,
e6dc7f81 878 tcg_tbrel_diff(s, NULL));
a7cdaf71 879 tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0));
53c89efd
RH		 880 return;
881 }
882
77bfc7c0
RH		 883 tmp = arg >> 31 >> 1;
884 tcg_out_movi(s, TCG_TYPE_I32, ret, tmp);
885 if (tmp) {
5964fca8 886 tcg_out_shli64(s, ret, ret, 32);
810260a8 887 }
5964fca8
RH		 888 if (arg & 0xffff0000) {
889 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
890 }
891 if (arg & 0xffff) {
892 tcg_out32(s, ORI | SAI(ret, ret, arg));
893 }
894}
895
4e186175
RH		 896static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
897 TCGReg ret, int64_t val)
5964fca8 898{
6ef14d7e
RH		 899 uint32_t load_insn;
900 int rel, low;
901 intptr_t add;
902
4e186175
RH		 903 switch (vece) {
904 case MO_8:
905 low = (int8_t)val;
906 if (low >= -16 && low < 16) {
6ef14d7e
RH		 907 tcg_out32(s, VSPLTISB | VRT(ret) | ((val & 31) << 16));
908 return;
909 }
4e186175
RH		 910 if (have_isa_3_00) {
911 tcg_out32(s, XXSPLTIB | VRT(ret) | ((val & 0xff) << 11));
912 return;
913 }
914 break;
915
916 case MO_16:
917 low = (int16_t)val;
918 if (low >= -16 && low < 16) {
6ef14d7e
RH		 919 tcg_out32(s, VSPLTISH | VRT(ret) | ((val & 31) << 16));
920 return;
921 }
4e186175
RH		 922 break;
923
924 case MO_32:
925 low = (int32_t)val;
926 if (low >= -16 && low < 16) {
6ef14d7e
RH		 927 tcg_out32(s, VSPLTISW | VRT(ret) | ((val & 31) << 16));
928 return;
929 }
4e186175 930 break;
b7ce3cff 931 }
6ef14d7e
RH		 932
933 /*
934 * Otherwise we must load the value from the constant pool.
935 */
936 if (USE_REG_TB) {
937 rel = R_PPC_ADDR16;
e6dc7f81 938 add = tcg_tbrel_diff(s, NULL);
6ef14d7e
RH		 939 } else {
940 rel = R_PPC_ADDR32;
941 add = 0;
942 }
943
47c906ae
RH		 944 if (have_vsx) {
945 load_insn = type == TCG_TYPE_V64 ? LXSDX : LXVDSX;
946 load_insn |= VRT(ret) | RB(TCG_REG_TMP1);
947 if (TCG_TARGET_REG_BITS == 64) {
948 new_pool_label(s, val, rel, s->code_ptr, add);
949 } else {
4e186175 950 new_pool_l2(s, rel, s->code_ptr, add, val >> 32, val);
47c906ae 951 }
6ef14d7e 952 } else {
47c906ae
RH		 953 load_insn = LVX | VRT(ret) | RB(TCG_REG_TMP1);
954 if (TCG_TARGET_REG_BITS == 64) {
955 new_pool_l2(s, rel, s->code_ptr, add, val, val);
956 } else {
4e186175
RH		 957 new_pool_l4(s, rel, s->code_ptr, add,
958 val >> 32, val, val >> 32, val);
47c906ae 959 }
6ef14d7e
RH		 960 }
961
962 if (USE_REG_TB) {
963 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, 0, 0));
964 load_insn |= RA(TCG_REG_TB);
965 } else {
966 tcg_out32(s, ADDIS | TAI(TCG_REG_TMP1, 0, 0));
967 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, 0));
968 }
969 tcg_out32(s, load_insn);
4b06c216
RH		 970}
971
972static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
973 tcg_target_long arg)
974{
975 switch (type) {
976 case TCG_TYPE_I32:
977 case TCG_TYPE_I64:
978 tcg_debug_assert(ret < TCG_REG_V0);
979 tcg_out_movi_int(s, type, ret, arg, false);
980 break;
981
4b06c216
RH		 982 default:
983 g_assert_not_reached();
984 }
810260a8 985}
986
637af30c 987static bool mask_operand(uint32_t c, int *mb, int *me)
a9249dff
RH		 988{
989 uint32_t lsb, test;
990
991 /* Accept a bit pattern like:
992 0....01....1
993 1....10....0
994 0..01..10..0
995 Keep track of the transitions. */
996 if (c == 0 || c == -1) {
997 return false;
998 }
999 test = c;
1000 lsb = test & -test;
1001 test += lsb;
1002 if (test & (test - 1)) {
1003 return false;
1004 }
1005
1006 *me = clz32(lsb);
1007 *mb = test ? clz32(test & -test) + 1 : 0;
1008 return true;
1009}
1010
637af30c
RH		 1011static bool mask64_operand(uint64_t c, int *mb, int *me)
1012{
1013 uint64_t lsb;
1014
1015 if (c == 0) {
1016 return false;
1017 }
1018
1019 lsb = c & -c;
1020 /* Accept 1..10..0. */
1021 if (c == -lsb) {
1022 *mb = 0;
1023 *me = clz64(lsb);
1024 return true;
1025 }
1026 /* Accept 0..01..1. */
1027 if (lsb == 1 && (c & (c + 1)) == 0) {
1028 *mb = clz64(c + 1) + 1;
1029 *me = 63;
1030 return true;
1031 }
1032 return false;
1033}
1034
a9249dff
RH		 1035static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
1036{
1037 int mb, me;
1038
1e1df962
RH		 1039 if (mask_operand(c, &mb, &me)) {
1040 tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me);
1041 } else if ((c & 0xffff) == c) {
a9249dff
RH		 1042 tcg_out32(s, ANDI | SAI(src, dst, c));
1043 return;
1044 } else if ((c & 0xffff0000) == c) {
1045 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
1046 return;
a9249dff 1047 } else {
8327a470
RH		 1048 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c);
1049 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
a9249dff
RH		 1050 }
1051}
1052
637af30c
RH		 1053static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c)
1054{
1055 int mb, me;
1056
eabb7b91 1057 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
1e1df962 1058 if (mask64_operand(c, &mb, &me)) {
637af30c
RH		 1059 if (mb == 0) {
1060 tcg_out_rld(s, RLDICR, dst, src, 0, me);
1061 } else {
1062 tcg_out_rld(s, RLDICL, dst, src, 0, mb);
1063 }
1e1df962
RH		 1064 } else if ((c & 0xffff) == c) {
1065 tcg_out32(s, ANDI | SAI(src, dst, c));
1066 return;
1067 } else if ((c & 0xffff0000) == c) {
1068 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
1069 return;
637af30c 1070 } else {
8327a470
RH		 1071 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c);
1072 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
637af30c
RH		 1073 }
1074}
1075
dce74c57
RH		 1076static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c,
1077 int op_lo, int op_hi)
1078{
1079 if (c >> 16) {
1080 tcg_out32(s, op_hi | SAI(src, dst, c >> 16));
1081 src = dst;
1082 }
1083 if (c & 0xffff) {
1084 tcg_out32(s, op_lo | SAI(src, dst, c));
1085 src = dst;
1086 }
1087}
1088
1089static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
1090{
1091 tcg_out_zori32(s, dst, src, c, ORI, ORIS);
1092}
1093
1094static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
1095{
1096 tcg_out_zori32(s, dst, src, c, XORI, XORIS);
1097}
1098
2be7d76b 1099static void tcg_out_b(TCGContext *s, int mask, const tcg_insn_unit *target)
5d7ff5bb 1100{
e083c4a2 1101 ptrdiff_t disp = tcg_pcrel_diff(s, target);
b0940da0 1102 if (in_range_b(disp)) {
541dd4ce
RH		 1103 tcg_out32(s, B | (disp & 0x3fffffc) | mask);
1104 } else {
de3d636d 1105 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, (uintptr_t)target);
8327a470 1106 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR);
541dd4ce 1107 tcg_out32(s, BCCTR | BO_ALWAYS | mask);
5d7ff5bb
AF		 1108 }
1109}
1110
b18d5d2b
RH		 1111static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
1112 TCGReg base, tcg_target_long offset)
810260a8 1113{
b18d5d2b 1114 tcg_target_long orig = offset, l0, l1, extra = 0, align = 0;
6e11cde1 1115 bool is_int_store = false;
dfca1778 1116 TCGReg rs = TCG_REG_TMP1;
b18d5d2b 1117
b18d5d2b
RH		 1118 switch (opi) {
1119 case LD: case LWA:
1120 align = 3;
1121 /* FALLTHRU */
1122 default:
6ef14d7e 1123 if (rt > TCG_REG_R0 && rt < TCG_REG_V0) {
b18d5d2b 1124 rs = rt;
de7761a3 1125 break;
b18d5d2b
RH		 1126 }
1127 break;
6e11cde1
RH		 1128 case LXSD:
1129 case STXSD:
1130 align = 3;
1131 break;
1132 case LXV:
1133 case STXV:
1134 align = 15;
1135 break;
b18d5d2b
RH		 1136 case STD:
1137 align = 3;
de7761a3 1138 /* FALLTHRU */
b18d5d2b 1139 case STB: case STH: case STW:
6e11cde1 1140 is_int_store = true;
b18d5d2b 1141 break;
810260a8 1142 }
810260a8 1143
b18d5d2b 1144 /* For unaligned, or very large offsets, use the indexed form. */
6ef14d7e 1145 if (offset & align || offset != (int32_t)offset || opi == 0) {
d4cba13b
RH		 1146 if (rs == base) {
1147 rs = TCG_REG_R0;
1148 }
6e11cde1 1149 tcg_debug_assert(!is_int_store || rs != rt);
de7761a3 1150 tcg_out_movi(s, TCG_TYPE_PTR, rs, orig);
6ef14d7e 1151 tcg_out32(s, opx | TAB(rt & 31, base, rs));
b18d5d2b
RH		 1152 return;
1153 }
1154
1155 l0 = (int16_t)offset;
1156 offset = (offset - l0) >> 16;
1157 l1 = (int16_t)offset;
1158
1159 if (l1 < 0 && orig >= 0) {
1160 extra = 0x4000;
1161 l1 = (int16_t)(offset - 0x4000);
1162 }
1163 if (l1) {
1164 tcg_out32(s, ADDIS | TAI(rs, base, l1));
1165 base = rs;
1166 }
1167 if (extra) {
1168 tcg_out32(s, ADDIS | TAI(rs, base, extra));
1169 base = rs;
1170 }
1171 if (opi != ADDI || base != rt || l0 != 0) {
6ef14d7e 1172 tcg_out32(s, opi | TAI(rt & 31, base, l0));
828808f5 1173 }
1174}
1175
6ef14d7e
RH		 1176static void tcg_out_vsldoi(TCGContext *s, TCGReg ret,
1177 TCGReg va, TCGReg vb, int shb)
d604f1a9 1178{
6ef14d7e
RH		 1179 tcg_out32(s, VSLDOI | VRT(ret) | VRA(va) | VRB(vb) | (shb << 6));
1180}
810260a8 1181
6ef14d7e
RH		 1182static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
1183 TCGReg base, intptr_t offset)
1184{
1185 int shift;
1186
1187 switch (type) {
1188 case TCG_TYPE_I32:
1189 if (ret < TCG_REG_V0) {
1190 tcg_out_mem_long(s, LWZ, LWZX, ret, base, offset);
1191 break;
1192 }
b2dda640
RH		 1193 if (have_isa_2_07 && have_vsx) {
1194 tcg_out_mem_long(s, 0, LXSIWZX, ret, base, offset);
1195 break;
1196 }
6ef14d7e
RH		 1197 tcg_debug_assert((offset & 3) == 0);
1198 tcg_out_mem_long(s, 0, LVEWX, ret, base, offset);
1199 shift = (offset - 4) & 0xc;
1200 if (shift) {
1201 tcg_out_vsldoi(s, ret, ret, ret, shift);
1202 }
1203 break;
1204 case TCG_TYPE_I64:
1205 if (ret < TCG_REG_V0) {
1206 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
1207 tcg_out_mem_long(s, LD, LDX, ret, base, offset);
1208 break;
1209 }
1210 /* fallthru */
1211 case TCG_TYPE_V64:
1212 tcg_debug_assert(ret >= TCG_REG_V0);
47c906ae 1213 if (have_vsx) {
6e11cde1
RH		 1214 tcg_out_mem_long(s, have_isa_3_00 ? LXSD : 0, LXSDX,
1215 ret, base, offset);
47c906ae
RH		 1216 break;
1217 }
6ef14d7e
RH		 1218 tcg_debug_assert((offset & 7) == 0);
1219 tcg_out_mem_long(s, 0, LVX, ret, base, offset & -16);
1220 if (offset & 8) {
1221 tcg_out_vsldoi(s, ret, ret, ret, 8);
1222 }
1223 break;
1224 case TCG_TYPE_V128:
1225 tcg_debug_assert(ret >= TCG_REG_V0);
1226 tcg_debug_assert((offset & 15) == 0);
6e11cde1
RH		 1227 tcg_out_mem_long(s, have_isa_3_00 ? LXV : 0,
1228 LVX, ret, base, offset);
6ef14d7e
RH		 1229 break;
1230 default:
1231 g_assert_not_reached();
d604f1a9 1232 }
d604f1a9 1233}
fedee3e7 1234
6ef14d7e
RH		 1235static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
1236 TCGReg base, intptr_t offset)
810260a8 1237{
6ef14d7e 1238 int shift;
fedee3e7 1239
6ef14d7e
RH		 1240 switch (type) {
1241 case TCG_TYPE_I32:
1242 if (arg < TCG_REG_V0) {
1243 tcg_out_mem_long(s, STW, STWX, arg, base, offset);
1244 break;
1245 }
b2dda640
RH		 1246 if (have_isa_2_07 && have_vsx) {
1247 tcg_out_mem_long(s, 0, STXSIWX, arg, base, offset);
1248 break;
1249 }
1250 assert((offset & 3) == 0);
6ef14d7e
RH		 1251 tcg_debug_assert((offset & 3) == 0);
1252 shift = (offset - 4) & 0xc;
1253 if (shift) {
1254 tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, shift);
1255 arg = TCG_VEC_TMP1;
1256 }
1257 tcg_out_mem_long(s, 0, STVEWX, arg, base, offset);
1258 break;
1259 case TCG_TYPE_I64:
1260 if (arg < TCG_REG_V0) {
1261 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
1262 tcg_out_mem_long(s, STD, STDX, arg, base, offset);
1263 break;
1264 }
1265 /* fallthru */
1266 case TCG_TYPE_V64:
1267 tcg_debug_assert(arg >= TCG_REG_V0);
47c906ae 1268 if (have_vsx) {
6e11cde1
RH		 1269 tcg_out_mem_long(s, have_isa_3_00 ? STXSD : 0,
1270 STXSDX, arg, base, offset);
47c906ae
RH		 1271 break;
1272 }
6ef14d7e
RH		 1273 tcg_debug_assert((offset & 7) == 0);
1274 if (offset & 8) {
1275 tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, 8);
1276 arg = TCG_VEC_TMP1;
1277 }
1278 tcg_out_mem_long(s, 0, STVEWX, arg, base, offset);
1279 tcg_out_mem_long(s, 0, STVEWX, arg, base, offset + 4);
1280 break;
1281 case TCG_TYPE_V128:
1282 tcg_debug_assert(arg >= TCG_REG_V0);
6e11cde1
RH		 1283 tcg_out_mem_long(s, have_isa_3_00 ? STXV : 0,
1284 STVX, arg, base, offset);
6ef14d7e
RH		 1285 break;
1286 default:
1287 g_assert_not_reached();
fedee3e7 1288 }
d604f1a9 1289}
810260a8 1290
59d7c14e
RH		 1291static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
1292 TCGReg base, intptr_t ofs)
1293{
1294 return false;
1295}
1296
d604f1a9
RH		 1297static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
1298 int const_arg2, int cr, TCGType type)
1299{
1300 int imm;
1301 uint32_t op;
810260a8 1302
abcf61c4
RH		 1303 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
1304
d604f1a9
RH		 1305 /* Simplify the comparisons below wrt CMPI. */
1306 if (type == TCG_TYPE_I32) {
1307 arg2 = (int32_t)arg2;
4a40e231 1308 }
fedee3e7 1309
d604f1a9
RH		 1310 switch (cond) {
1311 case TCG_COND_EQ:
1312 case TCG_COND_NE:
1313 if (const_arg2) {
1314 if ((int16_t) arg2 == arg2) {
1315 op = CMPI;
1316 imm = 1;
1317 break;
1318 } else if ((uint16_t) arg2 == arg2) {
1319 op = CMPLI;
1320 imm = 1;
1321 break;
1322 }
1323 }
1324 op = CMPL;
1325 imm = 0;
1326 break;
fedee3e7 1327
d604f1a9
RH		 1328 case TCG_COND_LT:
1329 case TCG_COND_GE:
1330 case TCG_COND_LE:
1331 case TCG_COND_GT:
1332 if (const_arg2) {
1333 if ((int16_t) arg2 == arg2) {
1334 op = CMPI;
1335 imm = 1;
1336 break;
1337 }
1338 }
1339 op = CMP;
1340 imm = 0;
1341 break;
fedee3e7 1342
d604f1a9
RH		 1343 case TCG_COND_LTU:
1344 case TCG_COND_GEU:
1345 case TCG_COND_LEU:
1346 case TCG_COND_GTU:
1347 if (const_arg2) {
1348 if ((uint16_t) arg2 == arg2) {
1349 op = CMPLI;
1350 imm = 1;
1351 break;
1352 }
1353 }
1354 op = CMPL;
1355 imm = 0;
1356 break;
fedee3e7 1357
d604f1a9
RH		 1358 default:
1359 tcg_abort();
fedee3e7 1360 }
d604f1a9 1361 op |= BF(cr) | ((type == TCG_TYPE_I64) << 21);
fedee3e7 1362
d604f1a9
RH		 1363 if (imm) {
1364 tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff));
1365 } else {
1366 if (const_arg2) {
1367 tcg_out_movi(s, type, TCG_REG_R0, arg2);
1368 arg2 = TCG_REG_R0;
1369 }
1370 tcg_out32(s, op | RA(arg1) | RB(arg2));
1371 }
810260a8 1372}
1373
d604f1a9
RH		 1374static void tcg_out_setcond_eq0(TCGContext *s, TCGType type,
1375 TCGReg dst, TCGReg src)
7f12d649 1376{
a757e1ee
RH		 1377 if (type == TCG_TYPE_I32) {
1378 tcg_out32(s, CNTLZW | RS(src) | RA(dst));
1379 tcg_out_shri32(s, dst, dst, 5);
1380 } else {
1381 tcg_out32(s, CNTLZD | RS(src) | RA(dst));
1382 tcg_out_shri64(s, dst, dst, 6);
1383 }
7f12d649
RH		 1384}
1385
d604f1a9 1386static void tcg_out_setcond_ne0(TCGContext *s, TCGReg dst, TCGReg src)
7f12d649 1387{
d604f1a9
RH		 1388 /* X != 0 implies X + -1 generates a carry. Extra addition
1389 trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */
1390 if (dst != src) {
1391 tcg_out32(s, ADDIC | TAI(dst, src, -1));
1392 tcg_out32(s, SUBFE | TAB(dst, dst, src));
7f12d649 1393 } else {
d604f1a9
RH		 1394 tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1));
1395 tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src));
7f12d649 1396 }
d604f1a9 1397}
7f12d649 1398
d604f1a9
RH		 1399static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2,
1400 bool const_arg2)
1401{
1402 if (const_arg2) {
1403 if ((uint32_t)arg2 == arg2) {
1404 tcg_out_xori32(s, TCG_REG_R0, arg1, arg2);
1405 } else {
1406 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2);
1407 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0));
1408 }
1409 } else {
1410 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2));
1411 }
1412 return TCG_REG_R0;
7f12d649
RH		 1413}
1414
d604f1a9
RH		 1415static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond,
1416 TCGArg arg0, TCGArg arg1, TCGArg arg2,
1417 int const_arg2)
7f12d649 1418{
d604f1a9 1419 int crop, sh;
7f12d649 1420
eabb7b91 1421 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
a757e1ee 1422
d604f1a9
RH		 1423 /* Ignore high bits of a potential constant arg2. */
1424 if (type == TCG_TYPE_I32) {
1425 arg2 = (uint32_t)arg2;
1426 }
7f12d649 1427
d604f1a9
RH		 1428 /* Handle common and trivial cases before handling anything else. */
1429 if (arg2 == 0) {
1430 switch (cond) {
1431 case TCG_COND_EQ:
1432 tcg_out_setcond_eq0(s, type, arg0, arg1);
1433 return;
1434 case TCG_COND_NE:
a757e1ee 1435 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
d604f1a9
RH		 1436 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1437 arg1 = TCG_REG_R0;
1438 }
1439 tcg_out_setcond_ne0(s, arg0, arg1);
1440 return;
1441 case TCG_COND_GE:
1442 tcg_out32(s, NOR | SAB(arg1, arg0, arg1));
1443 arg1 = arg0;
1444 /* FALLTHRU */
1445 case TCG_COND_LT:
1446 /* Extract the sign bit. */
a757e1ee
RH		 1447 if (type == TCG_TYPE_I32) {
1448 tcg_out_shri32(s, arg0, arg1, 31);
1449 } else {
1450 tcg_out_shri64(s, arg0, arg1, 63);
1451 }
d604f1a9
RH		 1452 return;
1453 default:
1454 break;
1455 }
1456 }
7f12d649 1457
d604f1a9
RH		 1458 /* If we have ISEL, we can implement everything with 3 or 4 insns.
1459 All other cases below are also at least 3 insns, so speed up the
1460 code generator by not considering them and always using ISEL. */
63922f46 1461 if (have_isel) {
d604f1a9 1462 int isel, tab;
7f12d649 1463
d604f1a9 1464 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
7f12d649 1465
d604f1a9 1466 isel = tcg_to_isel[cond];
7f12d649 1467
d604f1a9
RH		 1468 tcg_out_movi(s, type, arg0, 1);
1469 if (isel & 1) {
1470 /* arg0 = (bc ? 0 : 1) */
1471 tab = TAB(arg0, 0, arg0);
1472 isel &= ~1;
1473 } else {
1474 /* arg0 = (bc ? 1 : 0) */
1475 tcg_out_movi(s, type, TCG_REG_R0, 0);
1476 tab = TAB(arg0, arg0, TCG_REG_R0);
1477 }
1478 tcg_out32(s, isel | tab);
1479 return;
1480 }
49d9870a 1481
d604f1a9
RH		 1482 switch (cond) {
1483 case TCG_COND_EQ:
1484 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1485 tcg_out_setcond_eq0(s, type, arg0, arg1);
1486 return;
810260a8 1487
d604f1a9
RH		 1488 case TCG_COND_NE:
1489 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1490 /* Discard the high bits only once, rather than both inputs. */
a757e1ee 1491 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
d604f1a9
RH		 1492 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1493 arg1 = TCG_REG_R0;
1494 }
1495 tcg_out_setcond_ne0(s, arg0, arg1);
1496 return;
810260a8 1497
d604f1a9
RH		 1498 case TCG_COND_GT:
1499 case TCG_COND_GTU:
1500 sh = 30;
1501 crop = 0;
1502 goto crtest;
810260a8 1503
d604f1a9
RH		 1504 case TCG_COND_LT:
1505 case TCG_COND_LTU:
1506 sh = 29;
1507 crop = 0;
1508 goto crtest;
810260a8 1509
d604f1a9
RH		 1510 case TCG_COND_GE:
1511 case TCG_COND_GEU:
1512 sh = 31;
1513 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_LT) | BB(7, CR_LT);
1514 goto crtest;
810260a8 1515
d604f1a9
RH		 1516 case TCG_COND_LE:
1517 case TCG_COND_LEU:
1518 sh = 31;
1519 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_GT) | BB(7, CR_GT);
1520 crtest:
1521 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1522 if (crop) {
1523 tcg_out32(s, crop);
1524 }
1525 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1526 tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31);
1527 break;
1528
1529 default:
1530 tcg_abort();
1531 }
810260a8 1532}
1533
bec16311 1534static void tcg_out_bc(TCGContext *s, int bc, TCGLabel *l)
810260a8 1535{
d604f1a9 1536 if (l->has_value) {
d54401df 1537 bc |= reloc_pc14_val(tcg_splitwx_to_rx(s->code_ptr), l->u.value_ptr);
49d9870a 1538 } else {
bec16311 1539 tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, l, 0);
810260a8 1540 }
f9c7246f 1541 tcg_out32(s, bc);
810260a8 1542}
1543
d604f1a9
RH		 1544static void tcg_out_brcond(TCGContext *s, TCGCond cond,
1545 TCGArg arg1, TCGArg arg2, int const_arg2,
bec16311 1546 TCGLabel *l, TCGType type)
810260a8 1547{
d604f1a9 1548 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
bec16311 1549 tcg_out_bc(s, tcg_to_bc[cond], l);
d604f1a9 1550}
fa94c3be 1551
d604f1a9
RH		 1552static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond,
1553 TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1,
1554 TCGArg v2, bool const_c2)
1555{
1556 /* If for some reason both inputs are zero, don't produce bad code. */
1557 if (v1 == 0 && v2 == 0) {
1558 tcg_out_movi(s, type, dest, 0);
1559 return;
b9e946c7 1560 }
f6548c0a 1561
d604f1a9 1562 tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type);
a69abbe0 1563
63922f46 1564 if (have_isel) {
d604f1a9 1565 int isel = tcg_to_isel[cond];
810260a8 1566
d604f1a9
RH		 1567 /* Swap the V operands if the operation indicates inversion. */
1568 if (isel & 1) {
1569 int t = v1;
1570 v1 = v2;
1571 v2 = t;
1572 isel &= ~1;
1573 }
1574 /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */
1575 if (v2 == 0) {
1576 tcg_out_movi(s, type, TCG_REG_R0, 0);
1577 }
1578 tcg_out32(s, isel | TAB(dest, v1, v2));
1579 } else {
1580 if (dest == v2) {
1581 cond = tcg_invert_cond(cond);
1582 v2 = v1;
1583 } else if (dest != v1) {
1584 if (v1 == 0) {
1585 tcg_out_movi(s, type, dest, 0);
1586 } else {
1587 tcg_out_mov(s, type, dest, v1);
1588 }
1589 }
1590 /* Branch forward over one insn */
1591 tcg_out32(s, tcg_to_bc[cond] | 8);
1592 if (v2 == 0) {
1593 tcg_out_movi(s, type, dest, 0);
1594 } else {
1595 tcg_out_mov(s, type, dest, v2);
1596 }
29b69198 1597 }
810260a8 1598}
1599
d0b07481
RH		 1600static void tcg_out_cntxz(TCGContext *s, TCGType type, uint32_t opc,
1601 TCGArg a0, TCGArg a1, TCGArg a2, bool const_a2)
1602{
1603 if (const_a2 && a2 == (type == TCG_TYPE_I32 ? 32 : 64)) {
1604 tcg_out32(s, opc | RA(a0) | RS(a1));
1605 } else {
1606 tcg_out_cmp(s, TCG_COND_EQ, a1, 0, 1, 7, type);
1607 /* Note that the only other valid constant for a2 is 0. */
63922f46 1608 if (have_isel) {
d0b07481
RH		 1609 tcg_out32(s, opc | RA(TCG_REG_R0) | RS(a1));
1610 tcg_out32(s, tcg_to_isel[TCG_COND_EQ] | TAB(a0, a2, TCG_REG_R0));
1611 } else if (!const_a2 && a0 == a2) {
1612 tcg_out32(s, tcg_to_bc[TCG_COND_EQ] | 8);
1613 tcg_out32(s, opc | RA(a0) | RS(a1));
1614 } else {
1615 tcg_out32(s, opc | RA(a0) | RS(a1));
1616 tcg_out32(s, tcg_to_bc[TCG_COND_NE] | 8);
1617 if (const_a2) {
1618 tcg_out_movi(s, type, a0, 0);
1619 } else {
1620 tcg_out_mov(s, type, a0, a2);
1621 }
1622 }
1623 }
1624}
1625
abcf61c4
RH		 1626static void tcg_out_cmp2(TCGContext *s, const TCGArg *args,
1627 const int *const_args)
1628{
1629 static const struct { uint8_t bit1, bit2; } bits[] = {
1630 [TCG_COND_LT ] = { CR_LT, CR_LT },
1631 [TCG_COND_LE ] = { CR_LT, CR_GT },
1632 [TCG_COND_GT ] = { CR_GT, CR_GT },
1633 [TCG_COND_GE ] = { CR_GT, CR_LT },
1634 [TCG_COND_LTU] = { CR_LT, CR_LT },
1635 [TCG_COND_LEU] = { CR_LT, CR_GT },
1636 [TCG_COND_GTU] = { CR_GT, CR_GT },
1637 [TCG_COND_GEU] = { CR_GT, CR_LT },
1638 };
1639
1640 TCGCond cond = args[4], cond2;
1641 TCGArg al, ah, bl, bh;
1642 int blconst, bhconst;
1643 int op, bit1, bit2;
1644
1645 al = args[0];
1646 ah = args[1];
1647 bl = args[2];
1648 bh = args[3];
1649 blconst = const_args[2];
1650 bhconst = const_args[3];
1651
1652 switch (cond) {
1653 case TCG_COND_EQ:
1654 op = CRAND;
1655 goto do_equality;
1656 case TCG_COND_NE:
1657 op = CRNAND;
1658 do_equality:
1659 tcg_out_cmp(s, cond, al, bl, blconst, 6, TCG_TYPE_I32);
1660 tcg_out_cmp(s, cond, ah, bh, bhconst, 7, TCG_TYPE_I32);
1661 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
1662 break;
1663
1664 case TCG_COND_LT:
1665 case TCG_COND_LE:
1666 case TCG_COND_GT:
1667 case TCG_COND_GE:
1668 case TCG_COND_LTU:
1669 case TCG_COND_LEU:
1670 case TCG_COND_GTU:
1671 case TCG_COND_GEU:
1672 bit1 = bits[cond].bit1;
1673 bit2 = bits[cond].bit2;
1674 op = (bit1 != bit2 ? CRANDC : CRAND);
1675 cond2 = tcg_unsigned_cond(cond);
1676
1677 tcg_out_cmp(s, cond, ah, bh, bhconst, 6, TCG_TYPE_I32);
1678 tcg_out_cmp(s, cond2, al, bl, blconst, 7, TCG_TYPE_I32);
1679 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2));
1680 tcg_out32(s, CROR | BT(7, CR_EQ) | BA(6, bit1) | BB(7, CR_EQ));
1681 break;
1682
1683 default:
1684 tcg_abort();
1685 }
1686}
1687
1688static void tcg_out_setcond2(TCGContext *s, const TCGArg *args,
1689 const int *const_args)
1690{
1691 tcg_out_cmp2(s, args + 1, const_args + 1);
1692 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1693 tcg_out_rlw(s, RLWINM, args[0], TCG_REG_R0, 31, 31, 31);
1694}
1695
1696static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
1697 const int *const_args)
1698{
1699 tcg_out_cmp2(s, args, const_args);
bec16311 1700 tcg_out_bc(s, BC | BI(7, CR_EQ) | BO_COND_TRUE, arg_label(args[5]));
abcf61c4
RH		 1701}
1702
7b4af5ee
PK		 1703static void tcg_out_mb(TCGContext *s, TCGArg a0)
1704{
1705 uint32_t insn = HWSYNC;
1706 a0 &= TCG_MO_ALL;
1707 if (a0 == TCG_MO_LD_LD) {
1708 insn = LWSYNC;
1709 } else if (a0 == TCG_MO_ST_ST) {
1710 insn = EIEIO;
1711 }
1712 tcg_out32(s, insn);
1713}
1714
1acbad0f
RH		 1715void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
1716 uintptr_t jmp_rw, uintptr_t addr)
810260a8 1717{
5964fca8
RH		 1718 if (TCG_TARGET_REG_BITS == 64) {
1719 tcg_insn_unit i1, i2;
1720 intptr_t tb_diff = addr - tc_ptr;
1acbad0f 1721 intptr_t br_diff = addr - (jmp_rx + 4);
5964fca8
RH		 1722 uint64_t pair;
1723
1724 /* This does not exercise the range of the branch, but we do
1725 still need to be able to load the new value of TCG_REG_TB.
1726 But this does still happen quite often. */
1727 if (tb_diff == (int16_t)tb_diff) {
1728 i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff);
1729 i2 = B | (br_diff & 0x3fffffc);
1730 } else {
1731 intptr_t lo = (int16_t)tb_diff;
1732 intptr_t hi = (int32_t)(tb_diff - lo);
1733 assert(tb_diff == hi + lo);
1734 i1 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16);
1735 i2 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo);
1736 }
5bfd75a3 1737#ifdef HOST_WORDS_BIGENDIAN
5964fca8 1738 pair = (uint64_t)i1 << 32 | i2;
5bfd75a3 1739#else
5964fca8 1740 pair = (uint64_t)i2 << 32 | i1;
5bfd75a3
RH		 1741#endif
1742
ba026602 1743 /* As per the enclosing if, this is ppc64. Avoid the _Static_assert
d73415a3 1744 within qatomic_set that would fail to build a ppc32 host. */
1acbad0f
RH		 1745 qatomic_set__nocheck((uint64_t *)jmp_rw, pair);
1746 flush_idcache_range(jmp_rx, jmp_rw, 8);
5964fca8 1747 } else {
1acbad0f 1748 intptr_t diff = addr - jmp_rx;
5964fca8 1749 tcg_debug_assert(in_range_b(diff));
1acbad0f
RH		 1750 qatomic_set((uint32_t *)jmp_rw, B | (diff & 0x3fffffc));
1751 flush_idcache_range(jmp_rx, jmp_rw, 4);
5964fca8 1752 }
399f1648 1753}
810260a8 1754
2be7d76b 1755static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target)
810260a8 1756{
eaf7d1cf 1757#ifdef _CALL_AIX
d604f1a9
RH		 1758 /* Look through the descriptor. If the branch is in range, and we
1759 don't have to spend too much effort on building the toc. */
2be7d76b
RH		 1760 const void *tgt = ((const void * const *)target)[0];
1761 uintptr_t toc = ((const uintptr_t *)target)[1];
d604f1a9 1762 intptr_t diff = tcg_pcrel_diff(s, tgt);
b18d5d2b 1763
d604f1a9 1764 if (in_range_b(diff) && toc == (uint32_t)toc) {
dfca1778 1765 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, toc);
d604f1a9 1766 tcg_out_b(s, LK, tgt);
541dd4ce 1767 } else {
d604f1a9
RH		 1768 /* Fold the low bits of the constant into the addresses below. */
1769 intptr_t arg = (intptr_t)target;
1770 int ofs = (int16_t)arg;
1771
1772 if (ofs + 8 < 0x8000) {
1773 arg -= ofs;
1774 } else {
1775 ofs = 0;
1776 }
dfca1778
RH		 1777 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, arg);
1778 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_TMP1, ofs);
d604f1a9 1779 tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR);
dfca1778 1780 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_TMP1, ofs + SZP);
d604f1a9 1781 tcg_out32(s, BCCTR | BO_ALWAYS | LK);
541dd4ce 1782 }
77e58d0d
UW		 1783#elif defined(_CALL_ELF) && _CALL_ELF == 2
1784 intptr_t diff;
1785
1786 /* In the ELFv2 ABI, we have to set up r12 to contain the destination
1787 address, which the callee uses to compute its TOC address. */
1788 /* FIXME: when the branch is in range, we could avoid r12 load if we
1789 knew that the destination uses the same TOC, and what its local
1790 entry point offset is. */
1791 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R12, (intptr_t)target);
1792
1793 diff = tcg_pcrel_diff(s, target);
1794 if (in_range_b(diff)) {
1795 tcg_out_b(s, LK, target);
1796 } else {
1797 tcg_out32(s, MTSPR | RS(TCG_REG_R12) | CTR);
1798 tcg_out32(s, BCCTR | BO_ALWAYS | LK);
1799 }
eaf7d1cf
RH		 1800#else
1801 tcg_out_b(s, LK, target);
d604f1a9 1802#endif
810260a8 1803}
1804
d604f1a9
RH		 1805static const uint32_t qemu_ldx_opc[16] = {
1806 [MO_UB] = LBZX,
1807 [MO_UW] = LHZX,
1808 [MO_UL] = LWZX,
1809 [MO_Q] = LDX,
1810 [MO_SW] = LHAX,
1811 [MO_SL] = LWAX,
1812 [MO_BSWAP | MO_UB] = LBZX,
1813 [MO_BSWAP | MO_UW] = LHBRX,
1814 [MO_BSWAP | MO_UL] = LWBRX,
1815 [MO_BSWAP | MO_Q] = LDBRX,
1816};
810260a8 1817
d604f1a9
RH		 1818static const uint32_t qemu_stx_opc[16] = {
1819 [MO_UB] = STBX,
1820 [MO_UW] = STHX,
1821 [MO_UL] = STWX,
1822 [MO_Q] = STDX,
1823 [MO_BSWAP | MO_UB] = STBX,
1824 [MO_BSWAP | MO_UW] = STHBRX,
1825 [MO_BSWAP | MO_UL] = STWBRX,
1826 [MO_BSWAP | MO_Q] = STDBRX,
1827};
991041a4 1828
d604f1a9
RH		 1829static const uint32_t qemu_exts_opc[4] = {
1830 EXTSB, EXTSH, EXTSW, 0
1831};
810260a8 1832
d604f1a9 1833#if defined (CONFIG_SOFTMMU)
139c1837 1834#include "../tcg-ldst.c.inc"
659ef5cb 1835
d604f1a9
RH		 1836/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
1837 * int mmu_idx, uintptr_t ra)
1838 */
1839static void * const qemu_ld_helpers[16] = {
1840 [MO_UB] = helper_ret_ldub_mmu,
1841 [MO_LEUW] = helper_le_lduw_mmu,
1842 [MO_LEUL] = helper_le_ldul_mmu,
1843 [MO_LEQ] = helper_le_ldq_mmu,
1844 [MO_BEUW] = helper_be_lduw_mmu,
1845 [MO_BEUL] = helper_be_ldul_mmu,
1846 [MO_BEQ] = helper_be_ldq_mmu,
1847};
810260a8 1848
d604f1a9
RH		 1849/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
1850 * uintxx_t val, int mmu_idx, uintptr_t ra)
1851 */
1852static void * const qemu_st_helpers[16] = {
1853 [MO_UB] = helper_ret_stb_mmu,
1854 [MO_LEUW] = helper_le_stw_mmu,
1855 [MO_LEUL] = helper_le_stl_mmu,
1856 [MO_LEQ] = helper_le_stq_mmu,
1857 [MO_BEUW] = helper_be_stw_mmu,
1858 [MO_BEUL] = helper_be_stl_mmu,
1859 [MO_BEQ] = helper_be_stq_mmu,
1860};
810260a8 1861
269bd5d8
RH		 1862/* We expect to use a 16-bit negative offset from ENV. */
1863QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
1864QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768);
1865
d604f1a9
RH		 1866/* Perform the TLB load and compare. Places the result of the comparison
1867 in CR7, loads the addend of the TLB into R3, and returns the register
1868 containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
1869
14776ab5 1870static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp opc,
7f25c469 1871 TCGReg addrlo, TCGReg addrhi,
d604f1a9
RH		 1872 int mem_index, bool is_read)
1873{
1874 int cmp_off
1875 = (is_read
644f591a
RH		 1876 ? offsetof(CPUTLBEntry, addr_read)
1877 : offsetof(CPUTLBEntry, addr_write));
269bd5d8
RH		 1878 int fast_off = TLB_MASK_TABLE_OFS(mem_index);
1879 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
1880 int table_off = fast_off + offsetof(CPUTLBDescFast, table);
85aa8081
RH		 1881 unsigned s_bits = opc & MO_SIZE;
1882 unsigned a_bits = get_alignment_bits(opc);
d604f1a9 1883
644f591a 1884 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
269bd5d8
RH		 1885 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0, mask_off);
1886 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, TCG_AREG0, table_off);
644f591a
RH		 1887
1888 /* Extract the page index, shifted into place for tlb index. */
1889 if (TCG_TARGET_REG_BITS == 32) {
1890 tcg_out_shri32(s, TCG_REG_TMP1, addrlo,
1891 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
4c314da6 1892 } else {
644f591a
RH		 1893 tcg_out_shri64(s, TCG_REG_TMP1, addrlo,
1894 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
810260a8 1895 }
644f591a 1896 tcg_out32(s, AND | SAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_TMP1));
810260a8 1897
644f591a
RH		 1898 /* Load the TLB comparator. */
1899 if (cmp_off == 0 && TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) {
1900 uint32_t lxu = (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32
1901 ? LWZUX : LDUX);
1902 tcg_out32(s, lxu | TAB(TCG_REG_TMP1, TCG_REG_R3, TCG_REG_R4));
7f25c469 1903 } else {
644f591a
RH		 1904 tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_R4));
1905 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1906 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off + 4);
1907 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off);
1908 } else {
1909 tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off);
1910 }
7f25c469 1911 }
d604f1a9
RH		 1912
1913 /* Load the TLB addend for use on the fast path. Do this asap
1914 to minimize any load use delay. */
644f591a
RH		 1915 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3,
1916 offsetof(CPUTLBEntry, addend));
d604f1a9 1917
68d45bb6 1918 /* Clear the non-page, non-alignment bits from the address */
85aa8081
RH		 1919 if (TCG_TARGET_REG_BITS == 32) {
1920 /* We don't support unaligned accesses on 32-bits.
1921 * Preserve the bottom bits and thus trigger a comparison
1922 * failure on unaligned accesses.
68d45bb6 1923 */
85aa8081 1924 if (a_bits < s_bits) {
1f00b27f
SS		 1925 a_bits = s_bits;
1926 }
7f25c469 1927 tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0,
1f00b27f 1928 (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS);
85aa8081
RH		 1929 } else {
1930 TCGReg t = addrlo;
1931
1932 /* If the access is unaligned, we need to make sure we fail if we
1933 * cross a page boundary. The trick is to add the access size-1
1934 * to the address before masking the low bits. That will make the
1935 * address overflow to the next page if we cross a page boundary,
1936 * which will then force a mismatch of the TLB compare.
1937 */
1938 if (a_bits < s_bits) {
1939 unsigned a_mask = (1 << a_bits) - 1;
1940 unsigned s_mask = (1 << s_bits) - 1;
1941 tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask));
1942 t = TCG_REG_R0;
1943 }
1944
1945 /* Mask the address for the requested alignment. */
1946 if (TARGET_LONG_BITS == 32) {
1947 tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0,
1948 (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS);
644f591a
RH		 1949 /* Zero-extend the address for use in the final address. */
1950 tcg_out_ext32u(s, TCG_REG_R4, addrlo);
1951 addrlo = TCG_REG_R4;
85aa8081
RH		 1952 } else if (a_bits == 0) {
1953 tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS);
1954 } else {
1955 tcg_out_rld(s, RLDICL, TCG_REG_R0, t,
1f00b27f 1956 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - a_bits);
68d45bb6 1957 tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0);
68d45bb6 1958 }
70fac59a 1959 }
d604f1a9 1960
7f25c469 1961 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
dfca1778
RH		 1962 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
1963 0, 7, TCG_TYPE_I32);
7f25c469
RH		 1964 tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32);
1965 tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
1966 } else {
dfca1778
RH		 1967 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
1968 0, 7, TCG_TYPE_TL);
7f25c469 1969 }
d604f1a9 1970
7f25c469 1971 return addrlo;
70fac59a 1972}
1cd62ae9 1973
d604f1a9
RH		 1974/* Record the context of a call to the out of line helper code for the slow
1975 path for a load or store, so that we can later generate the correct
1976 helper code. */
3972ef6f 1977static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
7f25c469
RH		 1978 TCGReg datalo_reg, TCGReg datahi_reg,
1979 TCGReg addrlo_reg, TCGReg addrhi_reg,
3972ef6f 1980 tcg_insn_unit *raddr, tcg_insn_unit *lptr)
70fac59a 1981{
d604f1a9
RH		 1982 TCGLabelQemuLdst *label = new_ldst_label(s);
1983
1984 label->is_ld = is_ld;
3972ef6f 1985 label->oi = oi;
7f25c469
RH		 1986 label->datalo_reg = datalo_reg;
1987 label->datahi_reg = datahi_reg;
1988 label->addrlo_reg = addrlo_reg;
1989 label->addrhi_reg = addrhi_reg;
e5e2e4c7 1990 label->raddr = tcg_splitwx_to_rx(raddr);
7f25c469 1991 label->label_ptr[0] = lptr;
70fac59a 1992}
1cd62ae9 1993
aeee05f5 1994static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
70fac59a 1995{
3972ef6f 1996 TCGMemOpIdx oi = lb->oi;
14776ab5 1997 MemOp opc = get_memop(oi);
7f25c469 1998 TCGReg hi, lo, arg = TCG_REG_R3;
70fac59a 1999
d54401df 2000 if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
aeee05f5
RH		 2001 return false;
2002 }
70fac59a 2003
7f25c469 2004 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
1cd62ae9 2005
7f25c469
RH		 2006 lo = lb->addrlo_reg;
2007 hi = lb->addrhi_reg;
2008 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
2009#ifdef TCG_TARGET_CALL_ALIGN_ARGS
2010 arg |= 1;
2011#endif
2012 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
2013 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
2014 } else {
2015 /* If the address needed to be zero-extended, we'll have already
2016 placed it in R4. The only remaining case is 64-bit guest. */
2017 tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
2018 }
752c1fdb 2019
3972ef6f 2020 tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
7f25c469 2021 tcg_out32(s, MFSPR | RT(arg) | LR);
70fac59a 2022
2b7ec66f 2023 tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]);
70fac59a 2024
7f25c469
RH		 2025 lo = lb->datalo_reg;
2026 hi = lb->datahi_reg;
2027 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
2028 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_REG_R4);
2029 tcg_out_mov(s, TCG_TYPE_I32, hi, TCG_REG_R3);
2030 } else if (opc & MO_SIGN) {
d604f1a9 2031 uint32_t insn = qemu_exts_opc[opc & MO_SIZE];
7f25c469 2032 tcg_out32(s, insn | RA(lo) | RS(TCG_REG_R3));
d604f1a9 2033 } else {
7f25c469 2034 tcg_out_mov(s, TCG_TYPE_REG, lo, TCG_REG_R3);
70fac59a
RH		 2035 }
2036
d604f1a9 2037 tcg_out_b(s, 0, lb->raddr);
aeee05f5 2038 return true;
d604f1a9 2039}
70fac59a 2040
aeee05f5 2041static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
d604f1a9 2042{
3972ef6f 2043 TCGMemOpIdx oi = lb->oi;
14776ab5
TN		 2044 MemOp opc = get_memop(oi);
2045 MemOp s_bits = opc & MO_SIZE;
7f25c469 2046 TCGReg hi, lo, arg = TCG_REG_R3;
1cd62ae9 2047
d54401df 2048 if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
aeee05f5
RH		 2049 return false;
2050 }
1cd62ae9 2051
7f25c469
RH		 2052 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
2053
2054 lo = lb->addrlo_reg;
2055 hi = lb->addrhi_reg;
2056 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
2057#ifdef TCG_TARGET_CALL_ALIGN_ARGS
2058 arg |= 1;
2059#endif
2060 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
2061 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
2062 } else {
2063 /* If the address needed to be zero-extended, we'll have already
2064 placed it in R4. The only remaining case is 64-bit guest. */
2065 tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
2066 }
1cd62ae9 2067
7f25c469
RH		 2068 lo = lb->datalo_reg;
2069 hi = lb->datahi_reg;
2070 if (TCG_TARGET_REG_BITS == 32) {
2071 switch (s_bits) {
2072 case MO_64:
2073#ifdef TCG_TARGET_CALL_ALIGN_ARGS
2074 arg |= 1;
2075#endif
2076 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
2077 /* FALLTHRU */
2078 case MO_32:
2079 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
2080 break;
2081 default:
2082 tcg_out_rlw(s, RLWINM, arg++, lo, 0, 32 - (8 << s_bits), 31);
2083 break;
2084 }
2085 } else {
2086 if (s_bits == MO_64) {
2087 tcg_out_mov(s, TCG_TYPE_I64, arg++, lo);
2088 } else {
2089 tcg_out_rld(s, RLDICL, arg++, lo, 0, 64 - (8 << s_bits));
2090 }
2091 }
1cd62ae9 2092
3972ef6f 2093 tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
7f25c469 2094 tcg_out32(s, MFSPR | RT(arg) | LR);
1cd62ae9 2095
2b7ec66f 2096 tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
d604f1a9
RH		 2097
2098 tcg_out_b(s, 0, lb->raddr);
aeee05f5 2099 return true;
1cd62ae9 2100}
d604f1a9 2101#endif /* SOFTMMU */
1cd62ae9 2102
7f25c469 2103static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
810260a8 2104{
7f25c469
RH		 2105 TCGReg datalo, datahi, addrlo, rbase;
2106 TCGReg addrhi __attribute__((unused));
59227d5d 2107 TCGMemOpIdx oi;
14776ab5 2108 MemOp opc, s_bits;
d604f1a9 2109#ifdef CONFIG_SOFTMMU
7f25c469 2110 int mem_index;
d604f1a9
RH		 2111 tcg_insn_unit *label_ptr;
2112#endif
810260a8 2113
7f25c469
RH		 2114 datalo = *args++;
2115 datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
2116 addrlo = *args++;
2117 addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
59227d5d
RH		 2118 oi = *args++;
2119 opc = get_memop(oi);
7f25c469
RH		 2120 s_bits = opc & MO_SIZE;
2121
d604f1a9 2122#ifdef CONFIG_SOFTMMU
59227d5d 2123 mem_index = get_mmuidx(oi);
68d45bb6 2124 addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true);
d604f1a9
RH		 2125
2126 /* Load a pointer into the current opcode w/conditional branch-link. */
2127 label_ptr = s->code_ptr;
f9c7246f 2128 tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
d604f1a9
RH		 2129
2130 rbase = TCG_REG_R3;
2131#else /* !CONFIG_SOFTMMU */
b76f21a7 2132 rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
7f25c469 2133 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
dfca1778
RH		 2134 tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
2135 addrlo = TCG_REG_TMP1;
d604f1a9
RH		 2136 }
2137#endif
2138
7f25c469
RH		 2139 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
2140 if (opc & MO_BSWAP) {
2141 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
2142 tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
2143 tcg_out32(s, LWBRX | TAB(datahi, rbase, TCG_REG_R0));
2144 } else if (rbase != 0) {
2145 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
2146 tcg_out32(s, LWZX | TAB(datahi, rbase, addrlo));
2147 tcg_out32(s, LWZX | TAB(datalo, rbase, TCG_REG_R0));
2148 } else if (addrlo == datahi) {
2149 tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
2150 tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
2151 } else {
2152 tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
2153 tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
2154 }
541dd4ce 2155 } else {
2b7ec66f 2156 uint32_t insn = qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)];
4e33fe01 2157 if (!have_isa_2_06 && insn == LDBRX) {
7f25c469
RH		 2158 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
2159 tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
2160 tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0));
2161 tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0);
2162 } else if (insn) {
2163 tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
2164 } else {
2165 insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)];
2166 tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
2167 insn = qemu_exts_opc[s_bits];
2168 tcg_out32(s, insn | RA(datalo) | RS(datalo));
2169 }
810260a8 2170 }
810260a8 2171
d604f1a9 2172#ifdef CONFIG_SOFTMMU
3972ef6f
RH		 2173 add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi,
2174 s->code_ptr, label_ptr);
d604f1a9 2175#endif
810260a8 2176}
2177
7f25c469 2178static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
027ffea9 2179{
7f25c469
RH		 2180 TCGReg datalo, datahi, addrlo, rbase;
2181 TCGReg addrhi __attribute__((unused));
59227d5d 2182 TCGMemOpIdx oi;
14776ab5 2183 MemOp opc, s_bits;
d604f1a9 2184#ifdef CONFIG_SOFTMMU
7f25c469 2185 int mem_index;
d604f1a9
RH		 2186 tcg_insn_unit *label_ptr;
2187#endif
027ffea9 2188
7f25c469
RH		 2189 datalo = *args++;
2190 datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
2191 addrlo = *args++;
2192 addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
59227d5d
RH		 2193 oi = *args++;
2194 opc = get_memop(oi);
7f25c469
RH		 2195 s_bits = opc & MO_SIZE;
2196
d604f1a9 2197#ifdef CONFIG_SOFTMMU
59227d5d 2198 mem_index = get_mmuidx(oi);
68d45bb6 2199 addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false);
027ffea9 2200
d604f1a9
RH		 2201 /* Load a pointer into the current opcode w/conditional branch-link. */
2202 label_ptr = s->code_ptr;
f9c7246f 2203 tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
027ffea9 2204
d604f1a9
RH		 2205 rbase = TCG_REG_R3;
2206#else /* !CONFIG_SOFTMMU */
b76f21a7 2207 rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
7f25c469 2208 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
dfca1778
RH		 2209 tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
2210 addrlo = TCG_REG_TMP1;
d604f1a9
RH		 2211 }
2212#endif
2213
7f25c469
RH		 2214 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
2215 if (opc & MO_BSWAP) {
2216 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
2217 tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
2218 tcg_out32(s, STWBRX | SAB(datahi, rbase, TCG_REG_R0));
2219 } else if (rbase != 0) {
2220 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
2221 tcg_out32(s, STWX | SAB(datahi, rbase, addrlo));
2222 tcg_out32(s, STWX | SAB(datalo, rbase, TCG_REG_R0));
2223 } else {
2224 tcg_out32(s, STW | TAI(datahi, addrlo, 0));
2225 tcg_out32(s, STW | TAI(datalo, addrlo, 4));
2226 }
027ffea9 2227 } else {
2b7ec66f 2228 uint32_t insn = qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)];
4e33fe01 2229 if (!have_isa_2_06 && insn == STDBRX) {
7f25c469 2230 tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
dfca1778 2231 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, addrlo, 4));
7f25c469 2232 tcg_out_shri64(s, TCG_REG_R0, datalo, 32);
dfca1778 2233 tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_TMP1));
7f25c469
RH		 2234 } else {
2235 tcg_out32(s, insn | SAB(datalo, rbase, addrlo));
2236 }
027ffea9 2237 }
d604f1a9
RH		 2238
2239#ifdef CONFIG_SOFTMMU
3972ef6f
RH		 2240 add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi,
2241 s->code_ptr, label_ptr);
d604f1a9 2242#endif
027ffea9
RH		 2243}
2244
53c89efd
RH		 2245static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
2246{
2247 int i;
2248 for (i = 0; i < count; ++i) {
2249 p[i] = NOP;
2250 }
2251}
2252
a921fddc
RH		 2253/* Parameters for function call generation, used in tcg.c. */
2254#define TCG_TARGET_STACK_ALIGN 16
a921fddc
RH		 2255#define TCG_TARGET_EXTEND_ARGS 1
2256
802ca56e
RH		 2257#ifdef _CALL_AIX
2258# define LINK_AREA_SIZE (6 * SZR)
2259# define LR_OFFSET (1 * SZR)
2260# define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR)
1045fc04
PM		 2261#elif defined(TCG_TARGET_CALL_DARWIN)
2262# define LINK_AREA_SIZE (6 * SZR)
2263# define LR_OFFSET (2 * SZR)
ffcfbece
RH		 2264#elif TCG_TARGET_REG_BITS == 64
2265# if defined(_CALL_ELF) && _CALL_ELF == 2
2266# define LINK_AREA_SIZE (4 * SZR)
2267# define LR_OFFSET (1 * SZR)
2268# endif
2269#else /* TCG_TARGET_REG_BITS == 32 */
2270# if defined(_CALL_SYSV)
ffcfbece
RH		 2271# define LINK_AREA_SIZE (2 * SZR)
2272# define LR_OFFSET (1 * SZR)
ffcfbece
RH		 2273# endif
2274#endif
2275#ifndef LR_OFFSET
2276# error "Unhandled abi"
2277#endif
2278#ifndef TCG_TARGET_CALL_STACK_OFFSET
a2a98f80 2279# define TCG_TARGET_CALL_STACK_OFFSET LINK_AREA_SIZE
802ca56e
RH		 2280#endif
2281
2282#define CPU_TEMP_BUF_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
2283#define REG_SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * SZR)
d604f1a9 2284
802ca56e
RH		 2285#define FRAME_SIZE ((TCG_TARGET_CALL_STACK_OFFSET \
2286 + TCG_STATIC_CALL_ARGS_SIZE \
2287 + CPU_TEMP_BUF_SIZE \
2288 + REG_SAVE_SIZE \
2289 + TCG_TARGET_STACK_ALIGN - 1) \
2290 & -TCG_TARGET_STACK_ALIGN)
2291
2292#define REG_SAVE_BOT (FRAME_SIZE - REG_SAVE_SIZE)
d604f1a9
RH		 2293
2294static void tcg_target_qemu_prologue(TCGContext *s)
810260a8 2295{
d604f1a9 2296 int i;
810260a8 2297
802ca56e 2298#ifdef _CALL_AIX
d54401df
RH		 2299 const void **desc = (const void **)s->code_ptr;
2300 desc[0] = tcg_splitwx_to_rx(desc + 2); /* entry point */
2301 desc[1] = 0; /* environment pointer */
2302 s->code_ptr = (void *)(desc + 2); /* skip over descriptor */
d604f1a9
RH		 2303#endif
2304
a84ac4cb
RH		 2305 tcg_set_frame(s, TCG_REG_CALL_STACK, REG_SAVE_BOT - CPU_TEMP_BUF_SIZE,
2306 CPU_TEMP_BUF_SIZE);
2307
d604f1a9
RH		 2308 /* Prologue */
2309 tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR);
ffcfbece
RH		 2310 tcg_out32(s, (SZR == 8 ? STDU : STWU)
2311 | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE));
802ca56e 2312
d604f1a9 2313 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
4c3831a0
RH		 2314 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2315 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
d604f1a9 2316 }
802ca56e 2317 tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
d604f1a9 2318
4cbea598 2319#ifndef CONFIG_SOFTMMU
b76f21a7 2320 if (guest_base) {
5964fca8 2321 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true);
d604f1a9
RH		 2322 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2323 }
2324#endif
2325
2326 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
2327 tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR);
5964fca8
RH		 2328 if (USE_REG_TB) {
2329 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]);
a84ac4cb 2330 }
5964fca8 2331 tcg_out32(s, BCCTR | BO_ALWAYS);
d604f1a9
RH		 2332
2333 /* Epilogue */
c8bc1168 2334 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr);
d604f1a9 2335
802ca56e 2336 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
d604f1a9 2337 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
4c3831a0
RH		 2338 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2339 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
d604f1a9 2340 }
d604f1a9
RH		 2341 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR);
2342 tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE));
2343 tcg_out32(s, BCLR | BO_ALWAYS);
810260a8 2344}
2345
5e8892db
MR		 2346static void tcg_out_op(TCGContext *s, TCGOpcode opc,
2347 const TCGArg args[TCG_MAX_OP_ARGS],
2348 const int const_args[TCG_MAX_OP_ARGS])
810260a8 2349{
ee924fa6 2350 TCGArg a0, a1, a2;
e46b9681 2351
810260a8 2352 switch (opc) {
2353 case INDEX_op_exit_tb:
de3d636d 2354 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]);
d54401df 2355 tcg_out_b(s, 0, tcg_code_gen_epilogue);
810260a8 2356 break;
2357 case INDEX_op_goto_tb:
5964fca8
RH		 2358 if (s->tb_jmp_insn_offset) {
2359 /* Direct jump. */
2360 if (TCG_TARGET_REG_BITS == 64) {
2361 /* Ensure the next insns are 8-byte aligned. */
2362 if ((uintptr_t)s->code_ptr & 7) {
2363 tcg_out32(s, NOP);
2364 }
2365 s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);
2366 tcg_out32(s, ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, 0));
2367 tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, 0));
2368 } else {
2369 s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);
2370 tcg_out32(s, B);
2371 s->tb_jmp_reset_offset[args[0]] = tcg_current_code_size(s);
2372 break;
2373 }
2374 } else {
2375 /* Indirect jump. */
2376 tcg_debug_assert(s->tb_jmp_insn_offset == NULL);
2377 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, 0,
2378 (intptr_t)(s->tb_jmp_insn_offset + args[0]));
2379 }
2380 tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR);
5bfd75a3 2381 tcg_out32(s, BCCTR | BO_ALWAYS);
9f754620 2382 set_jmp_reset_offset(s, args[0]);
5964fca8
RH		 2383 if (USE_REG_TB) {
2384 /* For the unlinked case, need to reset TCG_REG_TB. */
2d6f38eb
RH		 2385 tcg_out_mem_long(s, ADDI, ADD, TCG_REG_TB, TCG_REG_TB,
2386 -tcg_current_code_size(s));
5964fca8 2387 }
810260a8 2388 break;
0c240785
RH		 2389 case INDEX_op_goto_ptr:
2390 tcg_out32(s, MTSPR | RS(args[0]) | CTR);
5964fca8
RH		 2391 if (USE_REG_TB) {
2392 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, args[0]);
2393 }
2394 tcg_out32(s, ADDI | TAI(TCG_REG_R3, 0, 0));
0c240785
RH		 2395 tcg_out32(s, BCCTR | BO_ALWAYS);
2396 break;
810260a8 2397 case INDEX_op_br:
2398 {
bec16311 2399 TCGLabel *l = arg_label(args[0]);
f9c7246f 2400 uint32_t insn = B;
810260a8 2401
2402 if (l->has_value) {
d54401df
RH		 2403 insn |= reloc_pc24_val(tcg_splitwx_to_rx(s->code_ptr),
2404 l->u.value_ptr);
541dd4ce 2405 } else {
bec16311 2406 tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, l, 0);
810260a8 2407 }
f9c7246f 2408 tcg_out32(s, insn);
810260a8 2409 }
2410 break;
810260a8 2411 case INDEX_op_ld8u_i32:
2412 case INDEX_op_ld8u_i64:
b18d5d2b 2413 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
810260a8 2414 break;
2415 case INDEX_op_ld8s_i32:
2416 case INDEX_op_ld8s_i64:
b18d5d2b 2417 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
f4bf14f4 2418 tcg_out_ext8s(s, args[0], args[0]);
810260a8 2419 break;
2420 case INDEX_op_ld16u_i32:
2421 case INDEX_op_ld16u_i64:
b18d5d2b 2422 tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]);
810260a8 2423 break;
2424 case INDEX_op_ld16s_i32:
2425 case INDEX_op_ld16s_i64:
b18d5d2b 2426 tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]);
810260a8 2427 break;
2428 case INDEX_op_ld_i32:
2429 case INDEX_op_ld32u_i64:
b18d5d2b 2430 tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]);
810260a8 2431 break;
2432 case INDEX_op_ld32s_i64:
b18d5d2b 2433 tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]);
810260a8 2434 break;
2435 case INDEX_op_ld_i64:
b18d5d2b 2436 tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]);
810260a8 2437 break;
2438 case INDEX_op_st8_i32:
2439 case INDEX_op_st8_i64:
b18d5d2b 2440 tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]);
810260a8 2441 break;
2442 case INDEX_op_st16_i32:
2443 case INDEX_op_st16_i64:
b18d5d2b 2444 tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]);
810260a8 2445 break;
2446 case INDEX_op_st_i32:
2447 case INDEX_op_st32_i64:
b18d5d2b 2448 tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]);
810260a8 2449 break;
2450 case INDEX_op_st_i64:
b18d5d2b 2451 tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]);
810260a8 2452 break;
2453
2454 case INDEX_op_add_i32:
ee924fa6
RH		 2455 a0 = args[0], a1 = args[1], a2 = args[2];
2456 if (const_args[2]) {
ee924fa6 2457 do_addi_32:
b18d5d2b 2458 tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2);
ee924fa6
RH		 2459 } else {
2460 tcg_out32(s, ADD | TAB(a0, a1, a2));
2461 }
810260a8 2462 break;
2463 case INDEX_op_sub_i32:
ee924fa6 2464 a0 = args[0], a1 = args[1], a2 = args[2];
148bdd23
RH		 2465 if (const_args[1]) {
2466 if (const_args[2]) {
2467 tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2);
2468 } else {
2469 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
2470 }
2471 } else if (const_args[2]) {
ee924fa6
RH		 2472 a2 = -a2;
2473 goto do_addi_32;
2474 } else {
2475 tcg_out32(s, SUBF | TAB(a0, a2, a1));
2476 }
810260a8 2477 break;
2478
2479 case INDEX_op_and_i32:
37251b98 2480 a0 = args[0], a1 = args[1], a2 = args[2];
a9249dff 2481 if (const_args[2]) {
37251b98 2482 tcg_out_andi32(s, a0, a1, a2);
a9249dff 2483 } else {
37251b98 2484 tcg_out32(s, AND | SAB(a1, a0, a2));
a9249dff
RH		 2485 }
2486 break;
2487 case INDEX_op_and_i64:
37251b98 2488 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 2489 if (const_args[2]) {
37251b98 2490 tcg_out_andi64(s, a0, a1, a2);
637af30c 2491 } else {
37251b98 2492 tcg_out32(s, AND | SAB(a1, a0, a2));
810260a8 2493 }
810260a8 2494 break;
fe6f943f 2495 case INDEX_op_or_i64:
810260a8 2496 case INDEX_op_or_i32:
dce74c57 2497 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 2498 if (const_args[2]) {
dce74c57
RH		 2499 tcg_out_ori32(s, a0, a1, a2);
2500 } else {
2501 tcg_out32(s, OR | SAB(a1, a0, a2));
810260a8 2502 }
810260a8 2503 break;
fe6f943f 2504 case INDEX_op_xor_i64:
810260a8 2505 case INDEX_op_xor_i32:
dce74c57 2506 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 2507 if (const_args[2]) {
dce74c57
RH		 2508 tcg_out_xori32(s, a0, a1, a2);
2509 } else {
2510 tcg_out32(s, XOR | SAB(a1, a0, a2));
810260a8 2511 }
810260a8 2512 break;
ce1010d6 2513 case INDEX_op_andc_i32:
37251b98
RH		 2514 a0 = args[0], a1 = args[1], a2 = args[2];
2515 if (const_args[2]) {
2516 tcg_out_andi32(s, a0, a1, ~a2);
2517 } else {
2518 tcg_out32(s, ANDC | SAB(a1, a0, a2));
2519 }
2520 break;
ce1010d6 2521 case INDEX_op_andc_i64:
37251b98
RH		 2522 a0 = args[0], a1 = args[1], a2 = args[2];
2523 if (const_args[2]) {
2524 tcg_out_andi64(s, a0, a1, ~a2);
2525 } else {
2526 tcg_out32(s, ANDC | SAB(a1, a0, a2));
2527 }
ce1010d6
RH		 2528 break;
2529 case INDEX_op_orc_i32:
37251b98
RH		 2530 if (const_args[2]) {
2531 tcg_out_ori32(s, args[0], args[1], ~args[2]);
2532 break;
2533 }
2534 /* FALLTHRU */
ce1010d6
RH		 2535 case INDEX_op_orc_i64:
2536 tcg_out32(s, ORC | SAB(args[1], args[0], args[2]));
2537 break;
2538 case INDEX_op_eqv_i32:
37251b98
RH		 2539 if (const_args[2]) {
2540 tcg_out_xori32(s, args[0], args[1], ~args[2]);
2541 break;
2542 }
2543 /* FALLTHRU */
ce1010d6
RH		 2544 case INDEX_op_eqv_i64:
2545 tcg_out32(s, EQV | SAB(args[1], args[0], args[2]));
2546 break;
2547 case INDEX_op_nand_i32:
2548 case INDEX_op_nand_i64:
2549 tcg_out32(s, NAND | SAB(args[1], args[0], args[2]));
2550 break;
2551 case INDEX_op_nor_i32:
2552 case INDEX_op_nor_i64:
2553 tcg_out32(s, NOR | SAB(args[1], args[0], args[2]));
2554 break;
810260a8 2555
d0b07481
RH		 2556 case INDEX_op_clz_i32:
2557 tcg_out_cntxz(s, TCG_TYPE_I32, CNTLZW, args[0], args[1],
2558 args[2], const_args[2]);
2559 break;
2560 case INDEX_op_ctz_i32:
2561 tcg_out_cntxz(s, TCG_TYPE_I32, CNTTZW, args[0], args[1],
2562 args[2], const_args[2]);
2563 break;
33e75fb9
RH		 2564 case INDEX_op_ctpop_i32:
2565 tcg_out32(s, CNTPOPW | SAB(args[1], args[0], 0));
2566 break;
d0b07481
RH		 2567
2568 case INDEX_op_clz_i64:
2569 tcg_out_cntxz(s, TCG_TYPE_I64, CNTLZD, args[0], args[1],
2570 args[2], const_args[2]);
2571 break;
2572 case INDEX_op_ctz_i64:
2573 tcg_out_cntxz(s, TCG_TYPE_I64, CNTTZD, args[0], args[1],
2574 args[2], const_args[2]);
2575 break;
33e75fb9
RH		 2576 case INDEX_op_ctpop_i64:
2577 tcg_out32(s, CNTPOPD | SAB(args[1], args[0], 0));
2578 break;
d0b07481 2579
810260a8 2580 case INDEX_op_mul_i32:
ef809300 2581 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 2582 if (const_args[2]) {
ef809300
RH		 2583 tcg_out32(s, MULLI | TAI(a0, a1, a2));
2584 } else {
2585 tcg_out32(s, MULLW | TAB(a0, a1, a2));
810260a8 2586 }
810260a8 2587 break;
2588
2589 case INDEX_op_div_i32:
541dd4ce 2590 tcg_out32(s, DIVW | TAB(args[0], args[1], args[2]));
810260a8 2591 break;
2592
2593 case INDEX_op_divu_i32:
541dd4ce 2594 tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2]));
810260a8 2595 break;
2596
810260a8 2597 case INDEX_op_shl_i32:
2598 if (const_args[2]) {
94248cfc
CF		 2599 /* Limit immediate shift count lest we create an illegal insn. */
2600 tcg_out_shli32(s, args[0], args[1], args[2] & 31);
9e555b73 2601 } else {
541dd4ce 2602 tcg_out32(s, SLW | SAB(args[1], args[0], args[2]));
9e555b73 2603 }
810260a8 2604 break;
2605 case INDEX_op_shr_i32:
2606 if (const_args[2]) {
94248cfc
CF		 2607 /* Limit immediate shift count lest we create an illegal insn. */
2608 tcg_out_shri32(s, args[0], args[1], args[2] & 31);
9e555b73 2609 } else {
541dd4ce 2610 tcg_out32(s, SRW | SAB(args[1], args[0], args[2]));
9e555b73 2611 }
810260a8 2612 break;
2613 case INDEX_op_sar_i32:
541dd4ce 2614 if (const_args[2]) {
05dd01fa 2615 tcg_out_sari32(s, args[0], args[1], args[2]);
541dd4ce
RH		 2616 } else {
2617 tcg_out32(s, SRAW | SAB(args[1], args[0], args[2]));
2618 }
810260a8 2619 break;
313d91c7
RH		 2620 case INDEX_op_rotl_i32:
2621 if (const_args[2]) {
2622 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31);
2623 } else {
2624 tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2])
2625 | MB(0) | ME(31));
2626 }
2627 break;
2628 case INDEX_op_rotr_i32:
2629 if (const_args[2]) {
2630 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31);
2631 } else {
8327a470
RH		 2632 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32));
2633 tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0)
313d91c7
RH		 2634 | MB(0) | ME(31));
2635 }
2636 break;
810260a8 2637
2638 case INDEX_op_brcond_i32:
4c314da6 2639 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
bec16311 2640 arg_label(args[3]), TCG_TYPE_I32);
e924bbec 2641 break;
810260a8 2642 case INDEX_op_brcond_i64:
4c314da6 2643 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
bec16311 2644 arg_label(args[3]), TCG_TYPE_I64);
810260a8 2645 break;
abcf61c4
RH		 2646 case INDEX_op_brcond2_i32:
2647 tcg_out_brcond2(s, args, const_args);
2648 break;
810260a8 2649
2650 case INDEX_op_neg_i32:
810260a8 2651 case INDEX_op_neg_i64:
541dd4ce 2652 tcg_out32(s, NEG | RT(args[0]) | RA(args[1]));
810260a8 2653 break;
2654
157f2662 2655 case INDEX_op_not_i32:
2656 case INDEX_op_not_i64:
541dd4ce 2657 tcg_out32(s, NOR | SAB(args[1], args[0], args[1]));
157f2662 2658 break;
2659
810260a8 2660 case INDEX_op_add_i64:
ee924fa6
RH		 2661 a0 = args[0], a1 = args[1], a2 = args[2];
2662 if (const_args[2]) {
ee924fa6 2663 do_addi_64:
b18d5d2b 2664 tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2);
ee924fa6
RH		 2665 } else {
2666 tcg_out32(s, ADD | TAB(a0, a1, a2));
2667 }
810260a8 2668 break;
2669 case INDEX_op_sub_i64:
ee924fa6 2670 a0 = args[0], a1 = args[1], a2 = args[2];
148bdd23
RH		 2671 if (const_args[1]) {
2672 if (const_args[2]) {
2673 tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2);
2674 } else {
2675 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
2676 }
2677 } else if (const_args[2]) {
ee924fa6
RH		 2678 a2 = -a2;
2679 goto do_addi_64;
2680 } else {
2681 tcg_out32(s, SUBF | TAB(a0, a2, a1));
2682 }
810260a8 2683 break;
2684
2685 case INDEX_op_shl_i64:
541dd4ce 2686 if (const_args[2]) {
94248cfc
CF		 2687 /* Limit immediate shift count lest we create an illegal insn. */
2688 tcg_out_shli64(s, args[0], args[1], args[2] & 63);
541dd4ce
RH		 2689 } else {
2690 tcg_out32(s, SLD | SAB(args[1], args[0], args[2]));
2691 }
810260a8 2692 break;
2693 case INDEX_op_shr_i64:
541dd4ce 2694 if (const_args[2]) {
94248cfc
CF		 2695 /* Limit immediate shift count lest we create an illegal insn. */
2696 tcg_out_shri64(s, args[0], args[1], args[2] & 63);
541dd4ce
RH		 2697 } else {
2698 tcg_out32(s, SRD | SAB(args[1], args[0], args[2]));
2699 }
810260a8 2700 break;
2701 case INDEX_op_sar_i64:
fe6f943f 2702 if (const_args[2]) {
05dd01fa 2703 tcg_out_sari64(s, args[0], args[1], args[2]);
541dd4ce
RH		 2704 } else {
2705 tcg_out32(s, SRAD | SAB(args[1], args[0], args[2]));
fe6f943f 2706 }
810260a8 2707 break;
313d91c7
RH		 2708 case INDEX_op_rotl_i64:
2709 if (const_args[2]) {
2710 tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0);
2711 } else {
2712 tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0));
2713 }
2714 break;
2715 case INDEX_op_rotr_i64:
2716 if (const_args[2]) {
2717 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0);
2718 } else {
8327a470
RH		 2719 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64));
2720 tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0));
313d91c7
RH		 2721 }
2722 break;
810260a8 2723
2724 case INDEX_op_mul_i64:
ef809300
RH		 2725 a0 = args[0], a1 = args[1], a2 = args[2];
2726 if (const_args[2]) {
2727 tcg_out32(s, MULLI | TAI(a0, a1, a2));
2728 } else {
2729 tcg_out32(s, MULLD | TAB(a0, a1, a2));
2730 }
810260a8 2731 break;
2732 case INDEX_op_div_i64:
541dd4ce 2733 tcg_out32(s, DIVD | TAB(args[0], args[1], args[2]));
810260a8 2734 break;
2735 case INDEX_op_divu_i64:
541dd4ce 2736 tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2]));
810260a8 2737 break;
810260a8 2738
1768ec06 2739 case INDEX_op_qemu_ld_i32:
7f25c469
RH		 2740 tcg_out_qemu_ld(s, args, false);
2741 break;
1768ec06 2742 case INDEX_op_qemu_ld_i64:
7f25c469 2743 tcg_out_qemu_ld(s, args, true);
810260a8 2744 break;
1768ec06 2745 case INDEX_op_qemu_st_i32:
7f25c469
RH		 2746 tcg_out_qemu_st(s, args, false);
2747 break;
1768ec06 2748 case INDEX_op_qemu_st_i64:
7f25c469 2749 tcg_out_qemu_st(s, args, true);
810260a8 2750 break;
2751
e46b9681 2752 case INDEX_op_ext8s_i32:
2753 case INDEX_op_ext8s_i64:
f4bf14f4
RH		 2754 tcg_out_ext8s(s, args[0], args[1]);
2755 break;
e46b9681 2756 case INDEX_op_ext16s_i32:
2757 case INDEX_op_ext16s_i64:
f4bf14f4
RH		 2758 tcg_out_ext16s(s, args[0], args[1]);
2759 break;
4f2331e5 2760 case INDEX_op_ext_i32_i64:
e46b9681 2761 case INDEX_op_ext32s_i64:
f4bf14f4 2762 tcg_out_ext32s(s, args[0], args[1]);
e46b9681 2763 break;
4f2331e5
AJ		 2764 case INDEX_op_extu_i32_i64:
2765 tcg_out_ext32u(s, args[0], args[1]);
2766 break;
e46b9681 2767
1cd62ae9 2768 case INDEX_op_setcond_i32:
541dd4ce
RH		 2769 tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
2770 const_args[2]);
1cd62ae9 2771 break;
2772 case INDEX_op_setcond_i64:
541dd4ce
RH		 2773 tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2],
2774 const_args[2]);
1cd62ae9 2775 break;
abcf61c4
RH		 2776 case INDEX_op_setcond2_i32:
2777 tcg_out_setcond2(s, args, const_args);
2778 break;
1cd62ae9 2779
5d221582
RH		 2780 case INDEX_op_bswap16_i32:
2781 case INDEX_op_bswap16_i64:
2782 a0 = args[0], a1 = args[1];
2783 /* a1 = abcd */
2784 if (a0 != a1) {
2785 /* a0 = (a1 r<< 24) & 0xff # 000c */
2786 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
2787 /* a0 = (a0 & ~0xff00) | (a1 r<< 8) & 0xff00 # 00dc */
2788 tcg_out_rlw(s, RLWIMI, a0, a1, 8, 16, 23);
2789 } else {
2790 /* r0 = (a1 r<< 8) & 0xff00 # 00d0 */
2791 tcg_out_rlw(s, RLWINM, TCG_REG_R0, a1, 8, 16, 23);
2792 /* a0 = (a1 r<< 24) & 0xff # 000c */
2793 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
2794 /* a0 = a0 | r0 # 00dc */
2795 tcg_out32(s, OR | SAB(TCG_REG_R0, a0, a0));
2796 }
2797 break;
2798
2799 case INDEX_op_bswap32_i32:
2800 case INDEX_op_bswap32_i64:
2801 /* Stolen from gcc's builtin_bswap32 */
2802 a1 = args[1];
2803 a0 = args[0] == a1 ? TCG_REG_R0 : args[0];
2804
2805 /* a1 = args[1] # abcd */
2806 /* a0 = rotate_left (a1, 8) # bcda */
2807 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
2808 /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */
2809 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
2810 /* a0 = (a0 & ~0x0000ff00) | ((a1 r<< 24) & 0x0000ff00) # dcba */
2811 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
2812
2813 if (a0 == TCG_REG_R0) {
de3d636d 2814 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
5d221582
RH		 2815 }
2816 break;
2817
68aebd45 2818 case INDEX_op_bswap64_i64:
8327a470 2819 a0 = args[0], a1 = args[1], a2 = TCG_REG_R0;
68aebd45 2820 if (a0 == a1) {
8327a470 2821 a0 = TCG_REG_R0;
68aebd45
RH		 2822 a2 = a1;
2823 }
2824
2825 /* a1 = # abcd efgh */
2826 /* a0 = rl32(a1, 8) # 0000 fghe */
2827 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
2828 /* a0 = dep(a0, rl32(a1, 24), 0xff000000) # 0000 hghe */
2829 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
2830 /* a0 = dep(a0, rl32(a1, 24), 0x0000ff00) # 0000 hgfe */
2831 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
2832
2833 /* a0 = rl64(a0, 32) # hgfe 0000 */
2834 /* a2 = rl64(a1, 32) # efgh abcd */
2835 tcg_out_rld(s, RLDICL, a0, a0, 32, 0);
2836 tcg_out_rld(s, RLDICL, a2, a1, 32, 0);
2837
2838 /* a0 = dep(a0, rl32(a2, 8), 0xffffffff) # hgfe bcda */
2839 tcg_out_rlw(s, RLWIMI, a0, a2, 8, 0, 31);
2840 /* a0 = dep(a0, rl32(a2, 24), 0xff000000) # hgfe dcda */
2841 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 0, 7);
2842 /* a0 = dep(a0, rl32(a2, 24), 0x0000ff00) # hgfe dcba */
2843 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 16, 23);
2844
2845 if (a0 == 0) {
de3d636d 2846 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
68aebd45
RH		 2847 }
2848 break;
2849
33de9ed2 2850 case INDEX_op_deposit_i32:
39dc85b9
RH		 2851 if (const_args[2]) {
2852 uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3];
2853 tcg_out_andi32(s, args[0], args[0], ~mask);
2854 } else {
2855 tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3],
2856 32 - args[3] - args[4], 31 - args[3]);
2857 }
33de9ed2
RH		 2858 break;
2859 case INDEX_op_deposit_i64:
39dc85b9
RH		 2860 if (const_args[2]) {
2861 uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3];
2862 tcg_out_andi64(s, args[0], args[0], ~mask);
2863 } else {
2864 tcg_out_rld(s, RLDIMI, args[0], args[2], args[3],
2865 64 - args[3] - args[4]);
2866 }
33de9ed2
RH		 2867 break;
2868
c05021c3
RH		 2869 case INDEX_op_extract_i32:
2870 tcg_out_rlw(s, RLWINM, args[0], args[1],
2871 32 - args[2], 32 - args[3], 31);
2872 break;
2873 case INDEX_op_extract_i64:
2874 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 64 - args[3]);
2875 break;
2876
027ffea9
RH		 2877 case INDEX_op_movcond_i32:
2878 tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2],
2879 args[3], args[4], const_args[2]);
2880 break;
2881 case INDEX_op_movcond_i64:
2882 tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2],
2883 args[3], args[4], const_args[2]);
2884 break;
2885
796f1a68 2886#if TCG_TARGET_REG_BITS == 64
6c858762 2887 case INDEX_op_add2_i64:
796f1a68
RH		 2888#else
2889 case INDEX_op_add2_i32:
2890#endif
6c858762
RH		 2891 /* Note that the CA bit is defined based on the word size of the
2892 environment. So in 64-bit mode it's always carry-out of bit 63.
2893 The fallback code using deposit works just as well for 32-bit. */
2894 a0 = args[0], a1 = args[1];
84247357 2895 if (a0 == args[3] || (!const_args[5] && a0 == args[5])) {
6c858762
RH		 2896 a0 = TCG_REG_R0;
2897 }
84247357
AB		 2898 if (const_args[4]) {
2899 tcg_out32(s, ADDIC | TAI(a0, args[2], args[4]));
6c858762 2900 } else {
84247357 2901 tcg_out32(s, ADDC | TAB(a0, args[2], args[4]));
6c858762
RH		 2902 }
2903 if (const_args[5]) {
84247357 2904 tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3]));
6c858762 2905 } else {
84247357 2906 tcg_out32(s, ADDE | TAB(a1, args[3], args[5]));
6c858762
RH		 2907 }
2908 if (a0 != args[0]) {
de3d636d 2909 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
6c858762
RH		 2910 }
2911 break;
2912
796f1a68 2913#if TCG_TARGET_REG_BITS == 64
6c858762 2914 case INDEX_op_sub2_i64:
796f1a68
RH		 2915#else
2916 case INDEX_op_sub2_i32:
2917#endif
6c858762 2918 a0 = args[0], a1 = args[1];
b31284ce 2919 if (a0 == args[5] || (!const_args[3] && a0 == args[3])) {
6c858762
RH		 2920 a0 = TCG_REG_R0;
2921 }
2922 if (const_args[2]) {
b31284ce 2923 tcg_out32(s, SUBFIC | TAI(a0, args[4], args[2]));
6c858762 2924 } else {
b31284ce 2925 tcg_out32(s, SUBFC | TAB(a0, args[4], args[2]));
6c858762 2926 }
b31284ce
RH		 2927 if (const_args[3]) {
2928 tcg_out32(s, (args[3] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5]));
6c858762 2929 } else {
b31284ce 2930 tcg_out32(s, SUBFE | TAB(a1, args[5], args[3]));
6c858762
RH		 2931 }
2932 if (a0 != args[0]) {
de3d636d 2933 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
6c858762
RH		 2934 }
2935 break;
2936
abcf61c4
RH		 2937 case INDEX_op_muluh_i32:
2938 tcg_out32(s, MULHWU | TAB(args[0], args[1], args[2]));
2939 break;
8fa391a0
RH		 2940 case INDEX_op_mulsh_i32:
2941 tcg_out32(s, MULHW | TAB(args[0], args[1], args[2]));
2942 break;
32f5717f
RH		 2943 case INDEX_op_muluh_i64:
2944 tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2]));
2945 break;
2946 case INDEX_op_mulsh_i64:
2947 tcg_out32(s, MULHD | TAB(args[0], args[1], args[2]));
6645c147
RH		 2948 break;
2949
7b4af5ee
PK		 2950 case INDEX_op_mb:
2951 tcg_out_mb(s, args[0]);
2952 break;
2953
96d0ee7f
RH		 2954 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
2955 case INDEX_op_mov_i64:
96d0ee7f 2956 case INDEX_op_call: /* Always emitted via tcg_out_call. */
810260a8 2957 default:
541dd4ce 2958 tcg_abort();
810260a8 2959 }
2960}
2961
4b06c216
RH		 2962int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
2963{
6ef14d7e
RH		 2964 switch (opc) {
2965 case INDEX_op_and_vec:
2966 case INDEX_op_or_vec:
2967 case INDEX_op_xor_vec:
2968 case INDEX_op_andc_vec:
2969 case INDEX_op_not_vec:
2970 return 1;
64ff1c6d
RH		 2971 case INDEX_op_orc_vec:
2972 return have_isa_2_07;
d6750811
RH		 2973 case INDEX_op_add_vec:
2974 case INDEX_op_sub_vec:
e2382972
RH		 2975 case INDEX_op_smax_vec:
2976 case INDEX_op_smin_vec:
2977 case INDEX_op_umax_vec:
2978 case INDEX_op_umin_vec:
64ff1c6d
RH		 2979 case INDEX_op_shlv_vec:
2980 case INDEX_op_shrv_vec:
2981 case INDEX_op_sarv_vec:
ab87a66f 2982 case INDEX_op_rotlv_vec:
64ff1c6d 2983 return vece <= MO_32 || have_isa_2_07;
e9d1a53a
RH		 2984 case INDEX_op_ssadd_vec:
2985 case INDEX_op_sssub_vec:
2986 case INDEX_op_usadd_vec:
2987 case INDEX_op_ussub_vec:
e2382972 2988 return vece <= MO_32;
6ef14d7e 2989 case INDEX_op_cmp_vec:
dabae097
RH		 2990 case INDEX_op_shli_vec:
2991 case INDEX_op_shri_vec:
2992 case INDEX_op_sari_vec:
ab87a66f 2993 case INDEX_op_rotli_vec:
64ff1c6d 2994 return vece <= MO_32 || have_isa_2_07 ? -1 : 0;
d7cd6a2f
RH		 2995 case INDEX_op_neg_vec:
2996 return vece >= MO_32 && have_isa_3_00;
64ff1c6d
RH		 2997 case INDEX_op_mul_vec:
2998 switch (vece) {
2999 case MO_8:
3000 case MO_16:
3001 return -1;
3002 case MO_32:
3003 return have_isa_2_07 ? 1 : -1;
73ebe95e
LP		 3004 case MO_64:
3005 return have_isa_3_10;
64ff1c6d
RH		 3006 }
3007 return 0;
47c906ae
RH		 3008 case INDEX_op_bitsel_vec:
3009 return have_vsx;
ab87a66f
RH		 3010 case INDEX_op_rotrv_vec:
3011 return -1;
6ef14d7e
RH		 3012 default:
3013 return 0;
3014 }
4b06c216
RH		 3015}
3016
3017static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
3018 TCGReg dst, TCGReg src)
3019{
6ef14d7e 3020 tcg_debug_assert(dst >= TCG_REG_V0);
b7ce3cff
RH		 3021
3022 /* Splat from integer reg allowed via constraints for v3.00. */
3023 if (src < TCG_REG_V0) {
3024 tcg_debug_assert(have_isa_3_00);
3025 switch (vece) {
3026 case MO_64:
3027 tcg_out32(s, MTVSRDD | VRT(dst) | RA(src) | RB(src));
3028 return true;
3029 case MO_32:
3030 tcg_out32(s, MTVSRWS | VRT(dst) | RA(src));
3031 return true;
3032 default:
3033 /* Fail, so that we fall back on either dupm or mov+dup. */
3034 return false;
3035 }
3036 }
6ef14d7e
RH		 3037
3038 /*
3039 * Recall we use (or emulate) VSX integer loads, so the integer is
3040 * right justified within the left (zero-index) double-word.
3041 */
3042 switch (vece) {
3043 case MO_8:
3044 tcg_out32(s, VSPLTB | VRT(dst) | VRB(src) | (7 << 16));
3045 break;
3046 case MO_16:
3047 tcg_out32(s, VSPLTH | VRT(dst) | VRB(src) | (3 << 16));
3048 break;
3049 case MO_32:
3050 tcg_out32(s, VSPLTW | VRT(dst) | VRB(src) | (1 << 16));
3051 break;
3052 case MO_64:
47c906ae
RH		 3053 if (have_vsx) {
3054 tcg_out32(s, XXPERMDI | VRT(dst) | VRA(src) | VRB(src));
3055 break;
3056 }
6ef14d7e
RH		 3057 tcg_out_vsldoi(s, TCG_VEC_TMP1, src, src, 8);
3058 tcg_out_vsldoi(s, dst, TCG_VEC_TMP1, src, 8);
3059 break;
3060 default:
3061 g_assert_not_reached();
3062 }
3063 return true;
4b06c216
RH		 3064}
3065
3066static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
3067 TCGReg out, TCGReg base, intptr_t offset)
3068{
6ef14d7e
RH		 3069 int elt;
3070
3071 tcg_debug_assert(out >= TCG_REG_V0);
3072 switch (vece) {
3073 case MO_8:
6e11cde1
RH		 3074 if (have_isa_3_00) {
3075 tcg_out_mem_long(s, LXV, LVX, out, base, offset & -16);
3076 } else {
3077 tcg_out_mem_long(s, 0, LVEBX, out, base, offset);
3078 }
6ef14d7e
RH		 3079 elt = extract32(offset, 0, 4);
3080#ifndef HOST_WORDS_BIGENDIAN
3081 elt ^= 15;
3082#endif
3083 tcg_out32(s, VSPLTB | VRT(out) | VRB(out) | (elt << 16));
3084 break;
3085 case MO_16:
3086 tcg_debug_assert((offset & 1) == 0);
6e11cde1
RH		 3087 if (have_isa_3_00) {
3088 tcg_out_mem_long(s, LXV | 8, LVX, out, base, offset & -16);
3089 } else {
3090 tcg_out_mem_long(s, 0, LVEHX, out, base, offset);
3091 }
6ef14d7e
RH		 3092 elt = extract32(offset, 1, 3);
3093#ifndef HOST_WORDS_BIGENDIAN
3094 elt ^= 7;
3095#endif
3096 tcg_out32(s, VSPLTH | VRT(out) | VRB(out) | (elt << 16));
3097 break;
3098 case MO_32:
6e11cde1
RH		 3099 if (have_isa_3_00) {
3100 tcg_out_mem_long(s, 0, LXVWSX, out, base, offset);
3101 break;
3102 }
6ef14d7e
RH		 3103 tcg_debug_assert((offset & 3) == 0);
3104 tcg_out_mem_long(s, 0, LVEWX, out, base, offset);
3105 elt = extract32(offset, 2, 2);
3106#ifndef HOST_WORDS_BIGENDIAN
3107 elt ^= 3;
3108#endif
3109 tcg_out32(s, VSPLTW | VRT(out) | VRB(out) | (elt << 16));
3110 break;
3111 case MO_64:
47c906ae
RH		 3112 if (have_vsx) {
3113 tcg_out_mem_long(s, 0, LXVDSX, out, base, offset);
3114 break;
3115 }
6ef14d7e
RH		 3116 tcg_debug_assert((offset & 7) == 0);
3117 tcg_out_mem_long(s, 0, LVX, out, base, offset & -16);
3118 tcg_out_vsldoi(s, TCG_VEC_TMP1, out, out, 8);
3119 elt = extract32(offset, 3, 1);
3120#ifndef HOST_WORDS_BIGENDIAN
3121 elt = !elt;
3122#endif
3123 if (elt) {
3124 tcg_out_vsldoi(s, out, out, TCG_VEC_TMP1, 8);
3125 } else {
3126 tcg_out_vsldoi(s, out, TCG_VEC_TMP1, out, 8);
3127 }
3128 break;
3129 default:
3130 g_assert_not_reached();
3131 }
3132 return true;
4b06c216
RH		 3133}
3134
3135static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
3136 unsigned vecl, unsigned vece,
5e8892db
MR		 3137 const TCGArg args[TCG_MAX_OP_ARGS],
3138 const int const_args[TCG_MAX_OP_ARGS])
4b06c216 3139{
6ef14d7e 3140 static const uint32_t
64ff1c6d
RH		 3141 add_op[4] = { VADDUBM, VADDUHM, VADDUWM, VADDUDM },
3142 sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM },
73ebe95e 3143 mul_op[4] = { 0, 0, VMULUWM, VMULLD },
d7cd6a2f 3144 neg_op[4] = { 0, 0, VNEGW, VNEGD },
64ff1c6d 3145 eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD },
d7cd6a2f 3146 ne_op[4] = { VCMPNEB, VCMPNEH, VCMPNEW, 0 },
64ff1c6d
RH		 3147 gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, VCMPGTSD },
3148 gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, VCMPGTUD },
e9d1a53a
RH		 3149 ssadd_op[4] = { VADDSBS, VADDSHS, VADDSWS, 0 },
3150 usadd_op[4] = { VADDUBS, VADDUHS, VADDUWS, 0 },
3151 sssub_op[4] = { VSUBSBS, VSUBSHS, VSUBSWS, 0 },
3152 ussub_op[4] = { VSUBUBS, VSUBUHS, VSUBUWS, 0 },
64ff1c6d
RH		 3153 umin_op[4] = { VMINUB, VMINUH, VMINUW, VMINUD },
3154 smin_op[4] = { VMINSB, VMINSH, VMINSW, VMINSD },
3155 umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, VMAXUD },
3156 smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, VMAXSD },
3157 shlv_op[4] = { VSLB, VSLH, VSLW, VSLD },
3158 shrv_op[4] = { VSRB, VSRH, VSRW, VSRD },
3159 sarv_op[4] = { VSRAB, VSRAH, VSRAW, VSRAD },
d9897efa
RH		 3160 mrgh_op[4] = { VMRGHB, VMRGHH, VMRGHW, 0 },
3161 mrgl_op[4] = { VMRGLB, VMRGLH, VMRGLW, 0 },
64ff1c6d
RH		 3162 muleu_op[4] = { VMULEUB, VMULEUH, VMULEUW, 0 },
3163 mulou_op[4] = { VMULOUB, VMULOUH, VMULOUW, 0 },
d9897efa 3164 pkum_op[4] = { VPKUHUM, VPKUWUM, 0, 0 },
64ff1c6d 3165 rotl_op[4] = { VRLB, VRLH, VRLW, VRLD };
6ef14d7e
RH		 3166
3167 TCGType type = vecl + TCG_TYPE_V64;
3168 TCGArg a0 = args[0], a1 = args[1], a2 = args[2];
3169 uint32_t insn;
3170
3171 switch (opc) {
3172 case INDEX_op_ld_vec:
3173 tcg_out_ld(s, type, a0, a1, a2);
3174 return;
3175 case INDEX_op_st_vec:
3176 tcg_out_st(s, type, a0, a1, a2);
3177 return;
3178 case INDEX_op_dupm_vec:
3179 tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
3180 return;
3181
d6750811
RH		 3182 case INDEX_op_add_vec:
3183 insn = add_op[vece];
3184 break;
3185 case INDEX_op_sub_vec:
3186 insn = sub_op[vece];
3187 break;
d7cd6a2f
RH		 3188 case INDEX_op_neg_vec:
3189 insn = neg_op[vece];
3190 a2 = a1;
3191 a1 = 0;
3192 break;
64ff1c6d 3193 case INDEX_op_mul_vec:
73ebe95e 3194 insn = mul_op[vece];
64ff1c6d 3195 break;
e9d1a53a
RH		 3196 case INDEX_op_ssadd_vec:
3197 insn = ssadd_op[vece];
3198 break;
3199 case INDEX_op_sssub_vec:
3200 insn = sssub_op[vece];
3201 break;
3202 case INDEX_op_usadd_vec:
3203 insn = usadd_op[vece];
3204 break;
3205 case INDEX_op_ussub_vec:
3206 insn = ussub_op[vece];
3207 break;
e2382972
RH		 3208 case INDEX_op_smin_vec:
3209 insn = smin_op[vece];
3210 break;
3211 case INDEX_op_umin_vec:
3212 insn = umin_op[vece];
3213 break;
3214 case INDEX_op_smax_vec:
3215 insn = smax_op[vece];
3216 break;
3217 case INDEX_op_umax_vec:
3218 insn = umax_op[vece];
3219 break;
dabae097
RH		 3220 case INDEX_op_shlv_vec:
3221 insn = shlv_op[vece];
3222 break;
3223 case INDEX_op_shrv_vec:
3224 insn = shrv_op[vece];
3225 break;
3226 case INDEX_op_sarv_vec:
3227 insn = sarv_op[vece];
3228 break;
6ef14d7e
RH		 3229 case INDEX_op_and_vec:
3230 insn = VAND;
3231 break;
3232 case INDEX_op_or_vec:
3233 insn = VOR;
3234 break;
3235 case INDEX_op_xor_vec:
3236 insn = VXOR;
3237 break;
3238 case INDEX_op_andc_vec:
3239 insn = VANDC;
3240 break;
3241 case INDEX_op_not_vec:
3242 insn = VNOR;
3243 a2 = a1;
3244 break;
64ff1c6d
RH		 3245 case INDEX_op_orc_vec:
3246 insn = VORC;
3247 break;
6ef14d7e
RH		 3248
3249 case INDEX_op_cmp_vec:
3250 switch (args[3]) {
3251 case TCG_COND_EQ:
3252 insn = eq_op[vece];
3253 break;
d7cd6a2f
RH		 3254 case TCG_COND_NE:
3255 insn = ne_op[vece];
3256 break;
6ef14d7e
RH		 3257 case TCG_COND_GT:
3258 insn = gts_op[vece];
3259 break;
3260 case TCG_COND_GTU:
3261 insn = gtu_op[vece];
3262 break;
3263 default:
3264 g_assert_not_reached();
3265 }
3266 break;
3267
47c906ae
RH		 3268 case INDEX_op_bitsel_vec:
3269 tcg_out32(s, XXSEL | VRT(a0) | VRC(a1) | VRB(a2) | VRA(args[3]));
3270 return;
3271
597cf978
RH		 3272 case INDEX_op_dup2_vec:
3273 assert(TCG_TARGET_REG_BITS == 32);
3274 /* With inputs a1 = xLxx, a2 = xHxx */
3275 tcg_out32(s, VMRGHW | VRT(a0) | VRA(a2) | VRB(a1)); /* a0 = xxHL */
3276 tcg_out_vsldoi(s, TCG_VEC_TMP1, a0, a0, 8); /* tmp = HLxx */
3277 tcg_out_vsldoi(s, a0, a0, TCG_VEC_TMP1, 8); /* a0 = HLHL */
3278 return;
3279
d9897efa
RH		 3280 case INDEX_op_ppc_mrgh_vec:
3281 insn = mrgh_op[vece];
3282 break;
3283 case INDEX_op_ppc_mrgl_vec:
3284 insn = mrgl_op[vece];
3285 break;
3286 case INDEX_op_ppc_muleu_vec:
3287 insn = muleu_op[vece];
3288 break;
3289 case INDEX_op_ppc_mulou_vec:
3290 insn = mulou_op[vece];
3291 break;
3292 case INDEX_op_ppc_pkum_vec:
3293 insn = pkum_op[vece];
3294 break;
ab87a66f 3295 case INDEX_op_rotlv_vec:
d9897efa
RH		 3296 insn = rotl_op[vece];
3297 break;
3298 case INDEX_op_ppc_msum_vec:
3299 tcg_debug_assert(vece == MO_16);
3300 tcg_out32(s, VMSUMUHM | VRT(a0) | VRA(a1) | VRB(a2) | VRC(args[3]));
3301 return;
3302
6ef14d7e 3303 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
6ef14d7e
RH		 3304 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
3305 default:
3306 g_assert_not_reached();
3307 }
3308
3309 tcg_debug_assert(insn != 0);
3310 tcg_out32(s, insn | VRT(a0) | VRA(a1) | VRB(a2));
3311}
3312
dabae097
RH		 3313static void expand_vec_shi(TCGType type, unsigned vece, TCGv_vec v0,
3314 TCGv_vec v1, TCGArg imm, TCGOpcode opci)
3315{
44aa59a0
RH		 3316 TCGv_vec t1;
3317
3318 if (vece == MO_32) {
3319 /*
3320 * Only 5 bits are significant, and VSPLTISB can represent -16..15.
3321 * So using negative numbers gets us the 4th bit easily.
3322 */
3323 imm = sextract32(imm, 0, 5);
3324 } else {
3325 imm &= (8 << vece) - 1;
3326 }
dabae097 3327
44aa59a0
RH		 3328 /* Splat w/bytes for xxspltib when 2.07 allows MO_64. */
3329 t1 = tcg_constant_vec(type, MO_8, imm);
dabae097
RH		 3330 vec_gen_3(opci, type, vece, tcgv_vec_arg(v0),
3331 tcgv_vec_arg(v1), tcgv_vec_arg(t1));
dabae097
RH		 3332}
3333
6ef14d7e
RH		 3334static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0,
3335 TCGv_vec v1, TCGv_vec v2, TCGCond cond)
3336{
3337 bool need_swap = false, need_inv = false;
3338
64ff1c6d 3339 tcg_debug_assert(vece <= MO_32 || have_isa_2_07);
6ef14d7e
RH		 3340
3341 switch (cond) {
3342 case TCG_COND_EQ:
3343 case TCG_COND_GT:
3344 case TCG_COND_GTU:
3345 break;
3346 case TCG_COND_NE:
d7cd6a2f
RH		 3347 if (have_isa_3_00 && vece <= MO_32) {
3348 break;
3349 }
3350 /* fall through */
6ef14d7e
RH		 3351 case TCG_COND_LE:
3352 case TCG_COND_LEU:
3353 need_inv = true;
3354 break;
3355 case TCG_COND_LT:
3356 case TCG_COND_LTU:
3357 need_swap = true;
3358 break;
3359 case TCG_COND_GE:
3360 case TCG_COND_GEU:
3361 need_swap = need_inv = true;
3362 break;
3363 default:
3364 g_assert_not_reached();
3365 }
3366
3367 if (need_inv) {
3368 cond = tcg_invert_cond(cond);
3369 }
3370 if (need_swap) {
3371 TCGv_vec t1;
3372 t1 = v1, v1 = v2, v2 = t1;
3373 cond = tcg_swap_cond(cond);
3374 }
3375
3376 vec_gen_4(INDEX_op_cmp_vec, type, vece, tcgv_vec_arg(v0),
3377 tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond);
3378
3379 if (need_inv) {
3380 tcg_gen_not_vec(vece, v0, v0);
3381 }
4b06c216
RH		 3382}
3383
d9897efa
RH		 3384static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0,
3385 TCGv_vec v1, TCGv_vec v2)
3386{
3387 TCGv_vec t1 = tcg_temp_new_vec(type);
3388 TCGv_vec t2 = tcg_temp_new_vec(type);
44aa59a0 3389 TCGv_vec c0, c16;
d9897efa
RH		 3390
3391 switch (vece) {
3392 case MO_8:
3393 case MO_16:
3394 vec_gen_3(INDEX_op_ppc_muleu_vec, type, vece, tcgv_vec_arg(t1),
3395 tcgv_vec_arg(v1), tcgv_vec_arg(v2));
3396 vec_gen_3(INDEX_op_ppc_mulou_vec, type, vece, tcgv_vec_arg(t2),
3397 tcgv_vec_arg(v1), tcgv_vec_arg(v2));
3398 vec_gen_3(INDEX_op_ppc_mrgh_vec, type, vece + 1, tcgv_vec_arg(v0),
3399 tcgv_vec_arg(t1), tcgv_vec_arg(t2));
3400 vec_gen_3(INDEX_op_ppc_mrgl_vec, type, vece + 1, tcgv_vec_arg(t1),
3401 tcgv_vec_arg(t1), tcgv_vec_arg(t2));
3402 vec_gen_3(INDEX_op_ppc_pkum_vec, type, vece, tcgv_vec_arg(v0),
3403 tcgv_vec_arg(v0), tcgv_vec_arg(t1));
3404 break;
3405
3406 case MO_32:
64ff1c6d 3407 tcg_debug_assert(!have_isa_2_07);
44aa59a0
RH		 3408 /*
3409 * Only 5 bits are significant, and VSPLTISB can represent -16..15.
3410 * So using -16 is a quick way to represent 16.
3411 */
3412 c16 = tcg_constant_vec(type, MO_8, -16);
3413 c0 = tcg_constant_vec(type, MO_8, 0);
3414
ab87a66f 3415 vec_gen_3(INDEX_op_rotlv_vec, type, MO_32, tcgv_vec_arg(t1),
44aa59a0 3416 tcgv_vec_arg(v2), tcgv_vec_arg(c16));
d9897efa
RH		 3417 vec_gen_3(INDEX_op_ppc_mulou_vec, type, MO_16, tcgv_vec_arg(t2),
3418 tcgv_vec_arg(v1), tcgv_vec_arg(v2));
44aa59a0
RH		 3419 vec_gen_4(INDEX_op_ppc_msum_vec, type, MO_16, tcgv_vec_arg(t1),
3420 tcgv_vec_arg(v1), tcgv_vec_arg(t1), tcgv_vec_arg(c0));
3421 vec_gen_3(INDEX_op_shlv_vec, type, MO_32, tcgv_vec_arg(t1),
3422 tcgv_vec_arg(t1), tcgv_vec_arg(c16));
3423 tcg_gen_add_vec(MO_32, v0, t1, t2);
d9897efa
RH		 3424 break;
3425
3426 default:
3427 g_assert_not_reached();
3428 }
3429 tcg_temp_free_vec(t1);
3430 tcg_temp_free_vec(t2);
3431}
3432
4b06c216
RH		 3433void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
3434 TCGArg a0, ...)
3435{
6ef14d7e 3436 va_list va;
ab87a66f 3437 TCGv_vec v0, v1, v2, t0;
dabae097 3438 TCGArg a2;
6ef14d7e
RH		 3439
3440 va_start(va, a0);
3441 v0 = temp_tcgv_vec(arg_temp(a0));
3442 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
dabae097 3443 a2 = va_arg(va, TCGArg);
6ef14d7e
RH		 3444
3445 switch (opc) {
dabae097
RH		 3446 case INDEX_op_shli_vec:
3447 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shlv_vec);
3448 break;
3449 case INDEX_op_shri_vec:
3450 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shrv_vec);
3451 break;
3452 case INDEX_op_sari_vec:
3453 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_sarv_vec);
3454 break;
ab87a66f
RH		 3455 case INDEX_op_rotli_vec:
3456 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_rotlv_vec);
3457 break;
6ef14d7e 3458 case INDEX_op_cmp_vec:
dabae097 3459 v2 = temp_tcgv_vec(arg_temp(a2));
6ef14d7e
RH		 3460 expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg));
3461 break;
d9897efa
RH		 3462 case INDEX_op_mul_vec:
3463 v2 = temp_tcgv_vec(arg_temp(a2));
3464 expand_vec_mul(type, vece, v0, v1, v2);
3465 break;
ab87a66f
RH		 3466 case INDEX_op_rotlv_vec:
3467 v2 = temp_tcgv_vec(arg_temp(a2));
3468 t0 = tcg_temp_new_vec(type);
3469 tcg_gen_neg_vec(vece, t0, v2);
3470 tcg_gen_rotlv_vec(vece, v0, v1, t0);
3471 tcg_temp_free_vec(t0);
3472 break;
6ef14d7e
RH		 3473 default:
3474 g_assert_not_reached();
3475 }
3476 va_end(va);
4b06c216
RH		 3477}
3478
6893016b
RH		 3479static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
3480{
6cb3658a
RH		 3481 switch (op) {
3482 case INDEX_op_goto_ptr:
6893016b 3483 return C_O0_I1(r);
796f1a68 3484
6cb3658a
RH		 3485 case INDEX_op_ld8u_i32:
3486 case INDEX_op_ld8s_i32:
3487 case INDEX_op_ld16u_i32:
3488 case INDEX_op_ld16s_i32:
3489 case INDEX_op_ld_i32:
6cb3658a
RH		 3490 case INDEX_op_ctpop_i32:
3491 case INDEX_op_neg_i32:
3492 case INDEX_op_not_i32:
3493 case INDEX_op_ext8s_i32:
3494 case INDEX_op_ext16s_i32:
3495 case INDEX_op_bswap16_i32:
3496 case INDEX_op_bswap32_i32:
3497 case INDEX_op_extract_i32:
3498 case INDEX_op_ld8u_i64:
3499 case INDEX_op_ld8s_i64:
3500 case INDEX_op_ld16u_i64:
3501 case INDEX_op_ld16s_i64:
3502 case INDEX_op_ld32u_i64:
3503 case INDEX_op_ld32s_i64:
3504 case INDEX_op_ld_i64:
6cb3658a
RH		 3505 case INDEX_op_ctpop_i64:
3506 case INDEX_op_neg_i64:
3507 case INDEX_op_not_i64:
3508 case INDEX_op_ext8s_i64:
3509 case INDEX_op_ext16s_i64:
3510 case INDEX_op_ext32s_i64:
3511 case INDEX_op_ext_i32_i64:
3512 case INDEX_op_extu_i32_i64:
3513 case INDEX_op_bswap16_i64:
3514 case INDEX_op_bswap32_i64:
3515 case INDEX_op_bswap64_i64:
3516 case INDEX_op_extract_i64:
6893016b
RH		 3517 return C_O1_I1(r, r);
3518
3519 case INDEX_op_st8_i32:
3520 case INDEX_op_st16_i32:
3521 case INDEX_op_st_i32:
3522 case INDEX_op_st8_i64:
3523 case INDEX_op_st16_i64:
3524 case INDEX_op_st32_i64:
3525 case INDEX_op_st_i64:
3526 return C_O0_I2(r, r);
abcf61c4 3527
6cb3658a
RH		 3528 case INDEX_op_add_i32:
3529 case INDEX_op_and_i32:
3530 case INDEX_op_or_i32:
3531 case INDEX_op_xor_i32:
3532 case INDEX_op_andc_i32:
3533 case INDEX_op_orc_i32:
3534 case INDEX_op_eqv_i32:
3535 case INDEX_op_shl_i32:
3536 case INDEX_op_shr_i32:
3537 case INDEX_op_sar_i32:
3538 case INDEX_op_rotl_i32:
3539 case INDEX_op_rotr_i32:
3540 case INDEX_op_setcond_i32:
3541 case INDEX_op_and_i64:
3542 case INDEX_op_andc_i64:
3543 case INDEX_op_shl_i64:
3544 case INDEX_op_shr_i64:
3545 case INDEX_op_sar_i64:
3546 case INDEX_op_rotl_i64:
3547 case INDEX_op_rotr_i64:
3548 case INDEX_op_setcond_i64:
6893016b
RH		 3549 return C_O1_I2(r, r, ri);
3550
6cb3658a
RH		 3551 case INDEX_op_mul_i32:
3552 case INDEX_op_mul_i64:
6893016b
RH		 3553 return C_O1_I2(r, r, rI);
3554
6cb3658a
RH		 3555 case INDEX_op_div_i32:
3556 case INDEX_op_divu_i32:
3557 case INDEX_op_nand_i32:
3558 case INDEX_op_nor_i32:
3559 case INDEX_op_muluh_i32:
3560 case INDEX_op_mulsh_i32:
3561 case INDEX_op_orc_i64:
3562 case INDEX_op_eqv_i64:
3563 case INDEX_op_nand_i64:
3564 case INDEX_op_nor_i64:
3565 case INDEX_op_div_i64:
3566 case INDEX_op_divu_i64:
3567 case INDEX_op_mulsh_i64:
3568 case INDEX_op_muluh_i64:
6893016b
RH		 3569 return C_O1_I2(r, r, r);
3570
6cb3658a 3571 case INDEX_op_sub_i32:
6893016b 3572 return C_O1_I2(r, rI, ri);
6cb3658a 3573 case INDEX_op_add_i64:
6893016b 3574 return C_O1_I2(r, r, rT);
6cb3658a
RH		 3575 case INDEX_op_or_i64:
3576 case INDEX_op_xor_i64:
6893016b 3577 return C_O1_I2(r, r, rU);
6cb3658a 3578 case INDEX_op_sub_i64:
6893016b 3579 return C_O1_I2(r, rI, rT);
6cb3658a
RH		 3580 case INDEX_op_clz_i32:
3581 case INDEX_op_ctz_i32:
3582 case INDEX_op_clz_i64:
3583 case INDEX_op_ctz_i64:
6893016b 3584 return C_O1_I2(r, r, rZW);
796f1a68 3585
6cb3658a
RH		 3586 case INDEX_op_brcond_i32:
3587 case INDEX_op_brcond_i64:
6893016b 3588 return C_O0_I2(r, ri);
6c858762 3589
6cb3658a
RH		 3590 case INDEX_op_movcond_i32:
3591 case INDEX_op_movcond_i64:
6893016b 3592 return C_O1_I4(r, r, ri, rZ, rZ);
6cb3658a
RH		 3593 case INDEX_op_deposit_i32:
3594 case INDEX_op_deposit_i64:
6893016b 3595 return C_O1_I2(r, 0, rZ);
6cb3658a 3596 case INDEX_op_brcond2_i32:
6893016b 3597 return C_O0_I4(r, r, ri, ri);
6cb3658a 3598 case INDEX_op_setcond2_i32:
6893016b 3599 return C_O1_I4(r, r, r, ri, ri);
6cb3658a
RH		 3600 case INDEX_op_add2_i64:
3601 case INDEX_op_add2_i32:
6893016b 3602 return C_O2_I4(r, r, r, r, rI, rZM);
6cb3658a
RH		 3603 case INDEX_op_sub2_i64:
3604 case INDEX_op_sub2_i32:
6893016b 3605 return C_O2_I4(r, r, rI, rZM, r, r);
810260a8 3606
6cb3658a
RH		 3607 case INDEX_op_qemu_ld_i32:
3608 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
6893016b
RH		 3609 ? C_O1_I1(r, L)
3610 : C_O1_I2(r, L, L));
3611
6cb3658a
RH		 3612 case INDEX_op_qemu_st_i32:
3613 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
6893016b
RH		 3614 ? C_O0_I2(S, S)
3615 : C_O0_I3(S, S, S));
3616
6cb3658a 3617 case INDEX_op_qemu_ld_i64:
6893016b
RH		 3618 return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
3619 : TARGET_LONG_BITS == 32 ? C_O2_I1(L, L, L)
3620 : C_O2_I2(L, L, L, L));
3621
6cb3658a 3622 case INDEX_op_qemu_st_i64:
6893016b
RH		 3623 return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(S, S)
3624 : TARGET_LONG_BITS == 32 ? C_O0_I3(S, S, S)
3625 : C_O0_I4(S, S, S, S));
f69d277e 3626
d6750811
RH		 3627 case INDEX_op_add_vec:
3628 case INDEX_op_sub_vec:
d9897efa 3629 case INDEX_op_mul_vec:
6ef14d7e
RH		 3630 case INDEX_op_and_vec:
3631 case INDEX_op_or_vec:
3632 case INDEX_op_xor_vec:
3633 case INDEX_op_andc_vec:
3634 case INDEX_op_orc_vec:
3635 case INDEX_op_cmp_vec:
e9d1a53a
RH		 3636 case INDEX_op_ssadd_vec:
3637 case INDEX_op_sssub_vec:
3638 case INDEX_op_usadd_vec:
3639 case INDEX_op_ussub_vec:
e2382972
RH		 3640 case INDEX_op_smax_vec:
3641 case INDEX_op_smin_vec:
3642 case INDEX_op_umax_vec:
3643 case INDEX_op_umin_vec:
dabae097
RH		 3644 case INDEX_op_shlv_vec:
3645 case INDEX_op_shrv_vec:
3646 case INDEX_op_sarv_vec:
ab87a66f
RH		 3647 case INDEX_op_rotlv_vec:
3648 case INDEX_op_rotrv_vec:
d9897efa
RH		 3649 case INDEX_op_ppc_mrgh_vec:
3650 case INDEX_op_ppc_mrgl_vec:
3651 case INDEX_op_ppc_muleu_vec:
3652 case INDEX_op_ppc_mulou_vec:
3653 case INDEX_op_ppc_pkum_vec:
597cf978 3654 case INDEX_op_dup2_vec:
6893016b
RH		 3655 return C_O1_I2(v, v, v);
3656
6ef14d7e 3657 case INDEX_op_not_vec:
d7cd6a2f 3658 case INDEX_op_neg_vec:
6893016b
RH		 3659 return C_O1_I1(v, v);
3660
b7ce3cff 3661 case INDEX_op_dup_vec:
6893016b
RH		 3662 return have_isa_3_00 ? C_O1_I1(v, vr) : C_O1_I1(v, v);
3663
6ef14d7e 3664 case INDEX_op_ld_vec:
6ef14d7e 3665 case INDEX_op_dupm_vec:
6893016b
RH		 3666 return C_O1_I1(v, r);
3667
3668 case INDEX_op_st_vec:
3669 return C_O0_I2(v, r);
3670
47c906ae 3671 case INDEX_op_bitsel_vec:
d9897efa 3672 case INDEX_op_ppc_msum_vec:
6893016b 3673 return C_O1_I3(v, v, v, v);
6ef14d7e 3674
6cb3658a 3675 default:
6893016b 3676 g_assert_not_reached();
f69d277e 3677 }
f69d277e
RH		 3678}
3679
541dd4ce 3680static void tcg_target_init(TCGContext *s)
810260a8 3681{
cd629de1 3682 unsigned long hwcap = qemu_getauxval(AT_HWCAP);
d0b07481
RH		 3683 unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2);
3684
7d9dae0a 3685 have_isa = tcg_isa_base;
1e6e9aca 3686 if (hwcap & PPC_FEATURE_ARCH_2_06) {
7d9dae0a 3687 have_isa = tcg_isa_2_06;
1e6e9aca 3688 }
64ff1c6d
RH		 3689#ifdef PPC_FEATURE2_ARCH_2_07
3690 if (hwcap2 & PPC_FEATURE2_ARCH_2_07) {
3691 have_isa = tcg_isa_2_07;
3692 }
3693#endif
d0b07481
RH		 3694#ifdef PPC_FEATURE2_ARCH_3_00
3695 if (hwcap2 & PPC_FEATURE2_ARCH_3_00) {
7d9dae0a 3696 have_isa = tcg_isa_3_00;
d0b07481
RH		 3697 }
3698#endif
73ebe95e
LP		 3699#ifdef PPC_FEATURE2_ARCH_3_10
3700 if (hwcap2 & PPC_FEATURE2_ARCH_3_10) {
3701 have_isa = tcg_isa_3_10;
3702 }
3703#endif
1e6e9aca 3704
63922f46
RH		 3705#ifdef PPC_FEATURE2_HAS_ISEL
3706 /* Prefer explicit instruction from the kernel. */
3707 have_isel = (hwcap2 & PPC_FEATURE2_HAS_ISEL) != 0;
3708#else
3709 /* Fall back to knowing Power7 (2.06) has ISEL. */
3710 have_isel = have_isa_2_06;
3711#endif
3712
68f340d4
RH		 3713 if (hwcap & PPC_FEATURE_HAS_ALTIVEC) {
3714 have_altivec = true;
47c906ae
RH		 3715 /* We only care about the portion of VSX that overlaps Altivec. */
3716 if (hwcap & PPC_FEATURE_HAS_VSX) {
3717 have_vsx = true;
3718 }
68f340d4
RH		 3719 }
3720
f46934df
RH		 3721 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
3722 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
4b06c216
RH		 3723 if (have_altivec) {
3724 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
3725 tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull;
3726 }
f46934df
RH		 3727
3728 tcg_target_call_clobber_regs = 0;
3729 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
3730 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2);
3731 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3);
3732 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4);
3733 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5);
3734 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6);
3735 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R7);
3736 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8);
3737 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9);
3738 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10);
3739 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);
3740 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12);
810260a8 3741
42281ec6
RH		 3742 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
3743 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
3744 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2);
3745 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3);
3746 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4);
3747 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5);
3748 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6);
3749 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7);
3750 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V8);
3751 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V9);
3752 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V10);
3753 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V11);
3754 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V12);
3755 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V13);
3756 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V14);
3757 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V15);
3758 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16);
3759 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17);
3760 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18);
3761 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19);
3762
ccb1bb66 3763 s->reserved_regs = 0;
5e1702b0
RH		 3764 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */
3765 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */
dfca1778
RH		 3766#if defined(_CALL_SYSV)
3767 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* toc pointer */
5d7ff5bb 3768#endif
dfca1778 3769#if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS == 64
5e1702b0 3770 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
dfca1778
RH		 3771#endif
3772 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */
42281ec6
RH		 3773 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP1);
3774 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP2);
5964fca8
RH		 3775 if (USE_REG_TB) {
3776 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tb->tc_ptr */
a84ac4cb 3777 }
810260a8 3778}
fa94c3be 3779
ffcfbece 3780#ifdef __ELF__
fa94c3be
RH		 3781typedef struct {
3782 DebugFrameCIE cie;
3783 DebugFrameFDEHeader fde;
3784 uint8_t fde_def_cfa[4];
3785 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2 + 3];
3786} DebugFrame;
3787
3788/* We're expecting a 2 byte uleb128 encoded value. */
3789QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
3790
ffcfbece
RH		 3791#if TCG_TARGET_REG_BITS == 64
3792# define ELF_HOST_MACHINE EM_PPC64
3793#else
3794# define ELF_HOST_MACHINE EM_PPC
3795#endif
fa94c3be
RH		 3796
3797static DebugFrame debug_frame = {
3798 .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
3799 .cie.id = -1,
3800 .cie.version = 1,
3801 .cie.code_align = 1,
802ca56e 3802 .cie.data_align = (-SZR & 0x7f), /* sleb128 -SZR */
fa94c3be
RH		 3803 .cie.return_column = 65,
3804
3805 /* Total FDE size does not include the "len" member. */
3806 .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset),
3807
3808 .fde_def_cfa = {
802ca56e 3809 12, TCG_REG_R1, /* DW_CFA_def_cfa r1, ... */
fa94c3be
RH		 3810 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
3811 (FRAME_SIZE >> 7)
3812 },
3813 .fde_reg_ofs = {
802ca56e
RH		 3814 /* DW_CFA_offset_extended_sf, lr, LR_OFFSET */
3815 0x11, 65, (LR_OFFSET / -SZR) & 0x7f,
fa94c3be
RH		 3816 }
3817};
3818
755bf9e5 3819void tcg_register_jit(const void *buf, size_t buf_size)
fa94c3be
RH		 3820{
3821 uint8_t *p = &debug_frame.fde_reg_ofs[3];
3822 int i;
3823
3824 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i, p += 2) {
3825 p[0] = 0x80 + tcg_target_callee_save_regs[i];
802ca56e 3826 p[1] = (FRAME_SIZE - (REG_SAVE_BOT + i * SZR)) / SZR;
fa94c3be
RH		 3827 }
3828
802ca56e 3829 debug_frame.fde.func_start = (uintptr_t)buf;
fa94c3be
RH		 3830 debug_frame.fde.func_len = buf_size;
3831
3832 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
3833}
ffcfbece 3834#endif /* __ELF__ */
QEMU mirror