]> git.proxmox.com Git - mirror_qemu.git/blame - tcg/ppc/tcg-target.inc.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Update PowerPC AT_HWCAP2 definition
[mirror_qemu.git] / tcg / ppc / tcg-target.inc.c
CommitLineData
810260a8 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
53c89efd 25#include "elf.h"
2b434dd1 26#include "../tcg-pool.inc.c"
53c89efd 27
ffcfbece
RH		 28#if defined _CALL_DARWIN || defined __APPLE__
29#define TCG_TARGET_CALL_DARWIN
30#endif
7f25c469
RH		 31#ifdef _CALL_SYSV
32# define TCG_TARGET_CALL_ALIGN_ARGS 1
33#endif
ffcfbece 34
dfca1778
RH		 35/* For some memory operations, we need a scratch that isn't R0. For the AIX
36 calling convention, we can re-use the TOC register since we'll be reloading
37 it at every call. Otherwise R12 will do nicely as neither a call-saved
38 register nor a parameter register. */
39#ifdef _CALL_AIX
40# define TCG_REG_TMP1 TCG_REG_R2
41#else
42# define TCG_REG_TMP1 TCG_REG_R12
43#endif
44
42281ec6
RH		 45#define TCG_VEC_TMP1 TCG_REG_V0
46#define TCG_VEC_TMP2 TCG_REG_V1
47
5964fca8
RH		 48#define TCG_REG_TB TCG_REG_R31
49#define USE_REG_TB (TCG_TARGET_REG_BITS == 64)
a84ac4cb 50
de3d636d
RH		 51/* Shorthand for size of a pointer. Avoid promotion to unsigned. */
52#define SZP ((int)sizeof(void *))
53
4c3831a0
RH		 54/* Shorthand for size of a register. */
55#define SZR (TCG_TARGET_REG_BITS / 8)
56
3d582c61
RH		 57#define TCG_CT_CONST_S16 0x100
58#define TCG_CT_CONST_U16 0x200
59#define TCG_CT_CONST_S32 0x400
60#define TCG_CT_CONST_U32 0x800
61#define TCG_CT_CONST_ZERO 0x1000
6c858762 62#define TCG_CT_CONST_MONE 0x2000
d0b07481 63#define TCG_CT_CONST_WSZ 0x4000
fe6f943f 64
e083c4a2 65static tcg_insn_unit *tb_ret_addr;
810260a8 66
7d9dae0a 67TCGPowerISA have_isa;
63922f46 68static bool have_isel;
4b06c216 69bool have_altivec;
47c906ae 70bool have_vsx;
49d9870a 71
4cbea598 72#ifndef CONFIG_SOFTMMU
f6548c0a 73#define TCG_GUEST_BASE_REG 30
f6548c0a 74#endif
75
8d8fdbae 76#ifdef CONFIG_DEBUG_TCG
42281ec6
RH		 77static const char tcg_target_reg_names[TCG_TARGET_NB_REGS][4] = {
78 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
79 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
80 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
81 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
82 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
83 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
84 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
85 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
810260a8 86};
d4a9eb1f 87#endif
810260a8 88
89static const int tcg_target_reg_alloc_order[] = {
5e1702b0 90 TCG_REG_R14, /* call saved registers */
810260a8 91 TCG_REG_R15,
92 TCG_REG_R16,
93 TCG_REG_R17,
94 TCG_REG_R18,
95 TCG_REG_R19,
96 TCG_REG_R20,
97 TCG_REG_R21,
98 TCG_REG_R22,
99 TCG_REG_R23,
5e1702b0
RH		 100 TCG_REG_R24,
101 TCG_REG_R25,
102 TCG_REG_R26,
103 TCG_REG_R27,
810260a8 104 TCG_REG_R28,
105 TCG_REG_R29,
106 TCG_REG_R30,
107 TCG_REG_R31,
5e1702b0
RH		 108 TCG_REG_R12, /* call clobbered, non-arguments */
109 TCG_REG_R11,
dfca1778
RH		 110 TCG_REG_R2,
111 TCG_REG_R13,
5e1702b0 112 TCG_REG_R10, /* call clobbered, arguments */
810260a8 113 TCG_REG_R9,
5e1702b0
RH		 114 TCG_REG_R8,
115 TCG_REG_R7,
116 TCG_REG_R6,
117 TCG_REG_R5,
118 TCG_REG_R4,
119 TCG_REG_R3,
42281ec6
RH		 120
121 /* V0 and V1 reserved as temporaries; V20 - V31 are call-saved */
122 TCG_REG_V2, /* call clobbered, vectors */
123 TCG_REG_V3,
124 TCG_REG_V4,
125 TCG_REG_V5,
126 TCG_REG_V6,
127 TCG_REG_V7,
128 TCG_REG_V8,
129 TCG_REG_V9,
130 TCG_REG_V10,
131 TCG_REG_V11,
132 TCG_REG_V12,
133 TCG_REG_V13,
134 TCG_REG_V14,
135 TCG_REG_V15,
136 TCG_REG_V16,
137 TCG_REG_V17,
138 TCG_REG_V18,
139 TCG_REG_V19,
810260a8 140};
141
142static const int tcg_target_call_iarg_regs[] = {
143 TCG_REG_R3,
144 TCG_REG_R4,
145 TCG_REG_R5,
146 TCG_REG_R6,
147 TCG_REG_R7,
148 TCG_REG_R8,
149 TCG_REG_R9,
150 TCG_REG_R10
151};
152
be9c4183 153static const int tcg_target_call_oarg_regs[] = {
dfca1778
RH		 154 TCG_REG_R3,
155 TCG_REG_R4
810260a8 156};
157
158static const int tcg_target_callee_save_regs[] = {
dfca1778 159#ifdef TCG_TARGET_CALL_DARWIN
5d7ff5bb
AF		 160 TCG_REG_R11,
161#endif
810260a8 162 TCG_REG_R14,
163 TCG_REG_R15,
164 TCG_REG_R16,
165 TCG_REG_R17,
166 TCG_REG_R18,
167 TCG_REG_R19,
168 TCG_REG_R20,
169 TCG_REG_R21,
170 TCG_REG_R22,
171 TCG_REG_R23,
095271d4 172 TCG_REG_R24,
173 TCG_REG_R25,
174 TCG_REG_R26,
cea5f9a2 175 TCG_REG_R27, /* currently used for the global env */
810260a8 176 TCG_REG_R28,
177 TCG_REG_R29,
178 TCG_REG_R30,
179 TCG_REG_R31
180};
181
b0940da0
RH		 182static inline bool in_range_b(tcg_target_long target)
183{
184 return target == sextract64(target, 0, 26);
185}
186
e083c4a2 187static uint32_t reloc_pc24_val(tcg_insn_unit *pc, tcg_insn_unit *target)
810260a8 188{
e083c4a2 189 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
eabb7b91 190 tcg_debug_assert(in_range_b(disp));
810260a8 191 return disp & 0x3fffffc;
192}
193
d5132903 194static bool reloc_pc24(tcg_insn_unit *pc, tcg_insn_unit *target)
810260a8 195{
d5132903
RH		 196 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
197 if (in_range_b(disp)) {
198 *pc = (*pc & ~0x3fffffc) | (disp & 0x3fffffc);
199 return true;
200 }
201 return false;
810260a8 202}
203
e083c4a2 204static uint16_t reloc_pc14_val(tcg_insn_unit *pc, tcg_insn_unit *target)
810260a8 205{
e083c4a2 206 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
eabb7b91 207 tcg_debug_assert(disp == (int16_t) disp);
810260a8 208 return disp & 0xfffc;
209}
210
d5132903 211static bool reloc_pc14(tcg_insn_unit *pc, tcg_insn_unit *target)
810260a8 212{
d5132903
RH		 213 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
214 if (disp == (int16_t) disp) {
215 *pc = (*pc & ~0xfffc) | (disp & 0xfffc);
216 return true;
217 }
218 return false;
810260a8 219}
220
810260a8 221/* parse target specific constraints */
069ea736
RH		 222static const char *target_parse_constraint(TCGArgConstraint *ct,
223 const char *ct_str, TCGType type)
810260a8 224{
069ea736 225 switch (*ct_str++) {
810260a8 226 case 'A': case 'B': case 'C': case 'D':
227 ct->ct |= TCG_CT_REG;
541dd4ce 228 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
810260a8 229 break;
230 case 'r':
231 ct->ct |= TCG_CT_REG;
f46934df 232 ct->u.regs = 0xffffffff;
810260a8 233 break;
6ef14d7e
RH		 234 case 'v':
235 ct->ct |= TCG_CT_REG;
236 ct->u.regs = 0xffffffff00000000ull;
237 break;
810260a8 238 case 'L': /* qemu_ld constraint */
239 ct->ct |= TCG_CT_REG;
f46934df 240 ct->u.regs = 0xffffffff;
541dd4ce 241 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
735ee40d 242#ifdef CONFIG_SOFTMMU
541dd4ce
RH		 243 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
244 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
735ee40d 245#endif
810260a8 246 break;
c070355d 247 case 'S': /* qemu_st constraint */
810260a8 248 ct->ct |= TCG_CT_REG;
f46934df 249 ct->u.regs = 0xffffffff;
541dd4ce 250 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
735ee40d 251#ifdef CONFIG_SOFTMMU
541dd4ce
RH		 252 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
253 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
254 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
735ee40d 255#endif
810260a8 256 break;
3d582c61
RH		 257 case 'I':
258 ct->ct |= TCG_CT_CONST_S16;
259 break;
260 case 'J':
261 ct->ct |= TCG_CT_CONST_U16;
262 break;
6c858762
RH		 263 case 'M':
264 ct->ct |= TCG_CT_CONST_MONE;
265 break;
3d582c61
RH		 266 case 'T':
267 ct->ct |= TCG_CT_CONST_S32;
268 break;
269 case 'U':
fe6f943f 270 ct->ct |= TCG_CT_CONST_U32;
271 break;
d0b07481
RH		 272 case 'W':
273 ct->ct |= TCG_CT_CONST_WSZ;
274 break;
3d582c61
RH		 275 case 'Z':
276 ct->ct |= TCG_CT_CONST_ZERO;
277 break;
810260a8 278 default:
069ea736 279 return NULL;
810260a8 280 }
069ea736 281 return ct_str;
810260a8 282}
283
284/* test if a constant matches the constraint */
f6c6afc1 285static int tcg_target_const_match(tcg_target_long val, TCGType type,
541dd4ce 286 const TCGArgConstraint *arg_ct)
810260a8 287{
3d582c61
RH		 288 int ct = arg_ct->ct;
289 if (ct & TCG_CT_CONST) {
290 return 1;
1194dcba
RH		 291 }
292
293 /* The only 32-bit constraint we use aside from
294 TCG_CT_CONST is TCG_CT_CONST_S16. */
295 if (type == TCG_TYPE_I32) {
296 val = (int32_t)val;
297 }
298
299 if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
3d582c61
RH		 300 return 1;
301 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
810260a8 302 return 1;
3d582c61 303 } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
fe6f943f 304 return 1;
3d582c61
RH		 305 } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
306 return 1;
307 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
308 return 1;
6c858762
RH		 309 } else if ((ct & TCG_CT_CONST_MONE) && val == -1) {
310 return 1;
d0b07481
RH		 311 } else if ((ct & TCG_CT_CONST_WSZ)
312 && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
313 return 1;
3d582c61 314 }
810260a8 315 return 0;
316}
317
318#define OPCD(opc) ((opc)<<26)
319#define XO19(opc) (OPCD(19)|((opc)<<1))
8a94cfb0
AB		 320#define MD30(opc) (OPCD(30)|((opc)<<2))
321#define MDS30(opc) (OPCD(30)|((opc)<<1))
810260a8 322#define XO31(opc) (OPCD(31)|((opc)<<1))
323#define XO58(opc) (OPCD(58)|(opc))
324#define XO62(opc) (OPCD(62)|(opc))
1838905e 325#define VX4(opc) (OPCD(4)|(opc))
810260a8 326
327#define B OPCD( 18)
328#define BC OPCD( 16)
329#define LBZ OPCD( 34)
330#define LHZ OPCD( 40)
331#define LHA OPCD( 42)
332#define LWZ OPCD( 32)
644f591a 333#define LWZUX XO31( 55)
810260a8 334#define STB OPCD( 38)
335#define STH OPCD( 44)
336#define STW OPCD( 36)
337
338#define STD XO62( 0)
339#define STDU XO62( 1)
340#define STDX XO31(149)
341
342#define LD XO58( 0)
343#define LDX XO31( 21)
344#define LDU XO58( 1)
644f591a 345#define LDUX XO31( 53)
301f6d90 346#define LWA XO58( 2)
810260a8 347#define LWAX XO31(341)
348
1cd62ae9 349#define ADDIC OPCD( 12)
810260a8 350#define ADDI OPCD( 14)
351#define ADDIS OPCD( 15)
352#define ORI OPCD( 24)
353#define ORIS OPCD( 25)
354#define XORI OPCD( 26)
355#define XORIS OPCD( 27)
356#define ANDI OPCD( 28)
357#define ANDIS OPCD( 29)
358#define MULLI OPCD( 7)
359#define CMPLI OPCD( 10)
360#define CMPI OPCD( 11)
148bdd23 361#define SUBFIC OPCD( 8)
810260a8 362
363#define LWZU OPCD( 33)
364#define STWU OPCD( 37)
365
313d91c7 366#define RLWIMI OPCD( 20)
810260a8 367#define RLWINM OPCD( 21)
313d91c7 368#define RLWNM OPCD( 23)
810260a8 369
8a94cfb0
AB		 370#define RLDICL MD30( 0)
371#define RLDICR MD30( 1)
372#define RLDIMI MD30( 3)
373#define RLDCL MDS30( 8)
810260a8 374
375#define BCLR XO19( 16)
376#define BCCTR XO19(528)
377#define CRAND XO19(257)
378#define CRANDC XO19(129)
379#define CRNAND XO19(225)
380#define CROR XO19(449)
1cd62ae9 381#define CRNOR XO19( 33)
810260a8 382
383#define EXTSB XO31(954)
384#define EXTSH XO31(922)
385#define EXTSW XO31(986)
386#define ADD XO31(266)
387#define ADDE XO31(138)
6c858762
RH		 388#define ADDME XO31(234)
389#define ADDZE XO31(202)
810260a8 390#define ADDC XO31( 10)
391#define AND XO31( 28)
392#define SUBF XO31( 40)
393#define SUBFC XO31( 8)
394#define SUBFE XO31(136)
6c858762
RH		 395#define SUBFME XO31(232)
396#define SUBFZE XO31(200)
810260a8 397#define OR XO31(444)
398#define XOR XO31(316)
399#define MULLW XO31(235)
8fa391a0 400#define MULHW XO31( 75)
810260a8 401#define MULHWU XO31( 11)
402#define DIVW XO31(491)
403#define DIVWU XO31(459)
404#define CMP XO31( 0)
405#define CMPL XO31( 32)
406#define LHBRX XO31(790)
407#define LWBRX XO31(534)
49d9870a 408#define LDBRX XO31(532)
810260a8 409#define STHBRX XO31(918)
410#define STWBRX XO31(662)
49d9870a 411#define STDBRX XO31(660)
810260a8 412#define MFSPR XO31(339)
413#define MTSPR XO31(467)
414#define SRAWI XO31(824)
415#define NEG XO31(104)
1cd62ae9 416#define MFCR XO31( 19)
6995a4a0 417#define MFOCRF (MFCR | (1u << 20))
157f2662 418#define NOR XO31(124)
1cd62ae9 419#define CNTLZW XO31( 26)
420#define CNTLZD XO31( 58)
d0b07481
RH		 421#define CNTTZW XO31(538)
422#define CNTTZD XO31(570)
33e75fb9
RH		 423#define CNTPOPW XO31(378)
424#define CNTPOPD XO31(506)
ce1010d6
RH		 425#define ANDC XO31( 60)
426#define ORC XO31(412)
427#define EQV XO31(284)
428#define NAND XO31(476)
70fac59a 429#define ISEL XO31( 15)
810260a8 430
431#define MULLD XO31(233)
432#define MULHD XO31( 73)
433#define MULHDU XO31( 9)
434#define DIVD XO31(489)
435#define DIVDU XO31(457)
436
437#define LBZX XO31( 87)
4f4a67ae 438#define LHZX XO31(279)
810260a8 439#define LHAX XO31(343)
440#define LWZX XO31( 23)
441#define STBX XO31(215)
442#define STHX XO31(407)
443#define STWX XO31(151)
444
7b4af5ee
PK		 445#define EIEIO XO31(854)
446#define HWSYNC XO31(598)
447#define LWSYNC (HWSYNC | (1u << 21))
448
541dd4ce 449#define SPR(a, b) ((((a)<<5)|(b))<<11)
810260a8 450#define LR SPR(8, 0)
451#define CTR SPR(9, 0)
452
453#define SLW XO31( 24)
454#define SRW XO31(536)
455#define SRAW XO31(792)
456
457#define SLD XO31( 27)
458#define SRD XO31(539)
459#define SRAD XO31(794)
fe6f943f 460#define SRADI XO31(413<<1)
810260a8 461
810260a8 462#define TW XO31( 4)
541dd4ce 463#define TRAP (TW | TO(31))
810260a8 464
a84ac4cb
RH		 465#define NOP ORI /* ori 0,0,0 */
466
6ef14d7e
RH		 467#define LVX XO31(103)
468#define LVEBX XO31(7)
469#define LVEHX XO31(39)
470#define LVEWX XO31(71)
47c906ae
RH		 471#define LXSDX (XO31(588) | 1) /* v2.06, force tx=1 */
472#define LXVDSX (XO31(332) | 1) /* v2.06, force tx=1 */
b2dda640 473#define LXSIWZX (XO31(12) | 1) /* v2.07, force tx=1 */
6e11cde1
RH		 474#define LXV (OPCD(61) | 8 | 1) /* v3.00, force tx=1 */
475#define LXSD (OPCD(57) | 2) /* v3.00 */
476#define LXVWSX (XO31(364) | 1) /* v3.00, force tx=1 */
6ef14d7e
RH		 477
478#define STVX XO31(231)
479#define STVEWX XO31(199)
47c906ae 480#define STXSDX (XO31(716) | 1) /* v2.06, force sx=1 */
b2dda640 481#define STXSIWX (XO31(140) | 1) /* v2.07, force sx=1 */
6e11cde1
RH		 482#define STXV (OPCD(61) | 8 | 5) /* v3.00, force sx=1 */
483#define STXSD (OPCD(61) | 2) /* v3.00 */
6ef14d7e 484
e9d1a53a
RH		 485#define VADDSBS VX4(768)
486#define VADDUBS VX4(512)
d6750811 487#define VADDUBM VX4(0)
e9d1a53a
RH		 488#define VADDSHS VX4(832)
489#define VADDUHS VX4(576)
d6750811 490#define VADDUHM VX4(64)
e9d1a53a
RH		 491#define VADDSWS VX4(896)
492#define VADDUWS VX4(640)
d6750811 493#define VADDUWM VX4(128)
64ff1c6d 494#define VADDUDM VX4(192) /* v2.07 */
d6750811 495
e9d1a53a
RH		 496#define VSUBSBS VX4(1792)
497#define VSUBUBS VX4(1536)
d6750811 498#define VSUBUBM VX4(1024)
e9d1a53a
RH		 499#define VSUBSHS VX4(1856)
500#define VSUBUHS VX4(1600)
d6750811 501#define VSUBUHM VX4(1088)
e9d1a53a
RH		 502#define VSUBSWS VX4(1920)
503#define VSUBUWS VX4(1664)
d6750811 504#define VSUBUWM VX4(1152)
64ff1c6d 505#define VSUBUDM VX4(1216) /* v2.07 */
d6750811 506
d7cd6a2f
RH		 507#define VNEGW (VX4(1538) | (6 << 16)) /* v3.00 */
508#define VNEGD (VX4(1538) | (7 << 16)) /* v3.00 */
509
e2382972
RH		 510#define VMAXSB VX4(258)
511#define VMAXSH VX4(322)
512#define VMAXSW VX4(386)
64ff1c6d 513#define VMAXSD VX4(450) /* v2.07 */
e2382972
RH		 514#define VMAXUB VX4(2)
515#define VMAXUH VX4(66)
516#define VMAXUW VX4(130)
64ff1c6d 517#define VMAXUD VX4(194) /* v2.07 */
e2382972
RH		 518#define VMINSB VX4(770)
519#define VMINSH VX4(834)
520#define VMINSW VX4(898)
64ff1c6d 521#define VMINSD VX4(962) /* v2.07 */
e2382972
RH		 522#define VMINUB VX4(514)
523#define VMINUH VX4(578)
524#define VMINUW VX4(642)
64ff1c6d 525#define VMINUD VX4(706) /* v2.07 */
e2382972 526
6ef14d7e
RH		 527#define VCMPEQUB VX4(6)
528#define VCMPEQUH VX4(70)
529#define VCMPEQUW VX4(134)
64ff1c6d 530#define VCMPEQUD VX4(199) /* v2.07 */
6ef14d7e
RH		 531#define VCMPGTSB VX4(774)
532#define VCMPGTSH VX4(838)
533#define VCMPGTSW VX4(902)
64ff1c6d 534#define VCMPGTSD VX4(967) /* v2.07 */
6ef14d7e
RH		 535#define VCMPGTUB VX4(518)
536#define VCMPGTUH VX4(582)
537#define VCMPGTUW VX4(646)
64ff1c6d 538#define VCMPGTUD VX4(711) /* v2.07 */
d7cd6a2f
RH		 539#define VCMPNEB VX4(7) /* v3.00 */
540#define VCMPNEH VX4(71) /* v3.00 */
541#define VCMPNEW VX4(135) /* v3.00 */
6ef14d7e 542
dabae097
RH		 543#define VSLB VX4(260)
544#define VSLH VX4(324)
545#define VSLW VX4(388)
64ff1c6d 546#define VSLD VX4(1476) /* v2.07 */
dabae097
RH		 547#define VSRB VX4(516)
548#define VSRH VX4(580)
549#define VSRW VX4(644)
64ff1c6d 550#define VSRD VX4(1732) /* v2.07 */
dabae097
RH		 551#define VSRAB VX4(772)
552#define VSRAH VX4(836)
553#define VSRAW VX4(900)
64ff1c6d 554#define VSRAD VX4(964) /* v2.07 */
d9897efa
RH		 555#define VRLB VX4(4)
556#define VRLH VX4(68)
557#define VRLW VX4(132)
64ff1c6d 558#define VRLD VX4(196) /* v2.07 */
d9897efa
RH		 559
560#define VMULEUB VX4(520)
561#define VMULEUH VX4(584)
64ff1c6d 562#define VMULEUW VX4(648) /* v2.07 */
d9897efa
RH		 563#define VMULOUB VX4(8)
564#define VMULOUH VX4(72)
64ff1c6d
RH		 565#define VMULOUW VX4(136) /* v2.07 */
566#define VMULUWM VX4(137) /* v2.07 */
d9897efa
RH		 567#define VMSUMUHM VX4(38)
568
569#define VMRGHB VX4(12)
570#define VMRGHH VX4(76)
571#define VMRGHW VX4(140)
572#define VMRGLB VX4(268)
573#define VMRGLH VX4(332)
574#define VMRGLW VX4(396)
575
576#define VPKUHUM VX4(14)
577#define VPKUWUM VX4(78)
dabae097 578
6ef14d7e
RH		 579#define VAND VX4(1028)
580#define VANDC VX4(1092)
581#define VNOR VX4(1284)
582#define VOR VX4(1156)
583#define VXOR VX4(1220)
64ff1c6d
RH		 584#define VEQV VX4(1668) /* v2.07 */
585#define VNAND VX4(1412) /* v2.07 */
586#define VORC VX4(1348) /* v2.07 */
6ef14d7e
RH		 587
588#define VSPLTB VX4(524)
589#define VSPLTH VX4(588)
590#define VSPLTW VX4(652)
591#define VSPLTISB VX4(780)
592#define VSPLTISH VX4(844)
593#define VSPLTISW VX4(908)
594
595#define VSLDOI VX4(44)
596
47c906ae
RH		 597#define XXPERMDI (OPCD(60) | (10 << 3) | 7) /* v2.06, force ax=bx=tx=1 */
598#define XXSEL (OPCD(60) | (3 << 4) | 0xf) /* v2.06, force ax=bx=cx=tx=1 */
b7ce3cff 599#define XXSPLTIB (OPCD(60) | (360 << 1) | 1) /* v3.00, force tx=1 */
47c906ae 600
7097312d
RH		 601#define MFVSRD (XO31(51) | 1) /* v2.07, force sx=1 */
602#define MFVSRWZ (XO31(115) | 1) /* v2.07, force sx=1 */
603#define MTVSRD (XO31(179) | 1) /* v2.07, force tx=1 */
604#define MTVSRWZ (XO31(243) | 1) /* v2.07, force tx=1 */
b7ce3cff
RH		 605#define MTVSRDD (XO31(435) | 1) /* v3.00, force tx=1 */
606#define MTVSRWS (XO31(403) | 1) /* v3.00, force tx=1 */
7097312d 607
810260a8 608#define RT(r) ((r)<<21)
609#define RS(r) ((r)<<21)
610#define RA(r) ((r)<<16)
611#define RB(r) ((r)<<11)
612#define TO(t) ((t)<<21)
613#define SH(s) ((s)<<11)
614#define MB(b) ((b)<<6)
615#define ME(e) ((e)<<1)
616#define BO(o) ((o)<<21)
617#define MB64(b) ((b)<<5)
6995a4a0 618#define FXM(b) (1 << (19 - (b)))
810260a8 619
b82f769c
RH		 620#define VRT(r) (((r) & 31) << 21)
621#define VRA(r) (((r) & 31) << 16)
622#define VRB(r) (((r) & 31) << 11)
623#define VRC(r) (((r) & 31) << 6)
624
810260a8 625#define LK 1
626
2fd8eddc
RH		 627#define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
628#define SAB(s, a, b) (RS(s) | RA(a) | RB(b))
629#define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff))
630#define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff))
810260a8 631
632#define BF(n) ((n)<<23)
633#define BI(n, c) (((c)+((n)*4))<<16)
634#define BT(n, c) (((c)+((n)*4))<<21)
635#define BA(n, c) (((c)+((n)*4))<<16)
636#define BB(n, c) (((c)+((n)*4))<<11)
70fac59a 637#define BC_(n, c) (((c)+((n)*4))<<6)
810260a8 638
541dd4ce
RH		 639#define BO_COND_TRUE BO(12)
640#define BO_COND_FALSE BO( 4)
641#define BO_ALWAYS BO(20)
810260a8 642
643enum {
644 CR_LT,
645 CR_GT,
646 CR_EQ,
647 CR_SO
648};
649
0aed257f 650static const uint32_t tcg_to_bc[] = {
541dd4ce
RH		 651 [TCG_COND_EQ] = BC | BI(7, CR_EQ) | BO_COND_TRUE,
652 [TCG_COND_NE] = BC | BI(7, CR_EQ) | BO_COND_FALSE,
653 [TCG_COND_LT] = BC | BI(7, CR_LT) | BO_COND_TRUE,
654 [TCG_COND_GE] = BC | BI(7, CR_LT) | BO_COND_FALSE,
655 [TCG_COND_LE] = BC | BI(7, CR_GT) | BO_COND_FALSE,
656 [TCG_COND_GT] = BC | BI(7, CR_GT) | BO_COND_TRUE,
657 [TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE,
658 [TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE,
659 [TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE,
660 [TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE,
810260a8 661};
662
70fac59a
RH		 663/* The low bit here is set if the RA and RB fields must be inverted. */
664static const uint32_t tcg_to_isel[] = {
665 [TCG_COND_EQ] = ISEL | BC_(7, CR_EQ),
666 [TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1,
667 [TCG_COND_LT] = ISEL | BC_(7, CR_LT),
668 [TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1,
669 [TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1,
670 [TCG_COND_GT] = ISEL | BC_(7, CR_GT),
671 [TCG_COND_LTU] = ISEL | BC_(7, CR_LT),
672 [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1,
673 [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1,
674 [TCG_COND_GTU] = ISEL | BC_(7, CR_GT),
675};
676
6ac17786 677static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
030ffe39
RH		 678 intptr_t value, intptr_t addend)
679{
680 tcg_insn_unit *target;
6ef14d7e
RH		 681 int16_t lo;
682 int32_t hi;
030ffe39
RH		 683
684 value += addend;
685 target = (tcg_insn_unit *)value;
686
687 switch (type) {
688 case R_PPC_REL14:
d5132903 689 return reloc_pc14(code_ptr, target);
030ffe39 690 case R_PPC_REL24:
d5132903 691 return reloc_pc24(code_ptr, target);
030ffe39 692 case R_PPC_ADDR16:
a7cdaf71
RH		 693 /*
694 * We are (slightly) abusing this relocation type. In particular,
695 * assert that the low 2 bits are zero, and do not modify them.
696 * That way we can use this with LD et al that have opcode bits
697 * in the low 2 bits of the insn.
698 */
699 if ((value & 3) || value != (int16_t)value) {
700 return false;
030ffe39 701 }
a7cdaf71 702 *code_ptr = (*code_ptr & ~0xfffc) | (value & 0xfffc);
030ffe39 703 break;
6ef14d7e
RH		 704 case R_PPC_ADDR32:
705 /*
706 * We are abusing this relocation type. Again, this points to
707 * a pair of insns, lis + load. This is an absolute address
708 * relocation for PPC32 so the lis cannot be removed.
709 */
710 lo = value;
711 hi = value - lo;
712 if (hi + lo != value) {
713 return false;
714 }
715 code_ptr[0] = deposit32(code_ptr[0], 0, 16, hi >> 16);
716 code_ptr[1] = deposit32(code_ptr[1], 0, 16, lo);
717 break;
030ffe39
RH		 718 default:
719 g_assert_not_reached();
720 }
6ac17786 721 return true;
030ffe39
RH		 722}
723
a84ac4cb
RH		 724static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
725 TCGReg base, tcg_target_long offset);
726
78113e83 727static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
810260a8 728{
6ef14d7e
RH		 729 if (ret == arg) {
730 return true;
731 }
732 switch (type) {
733 case TCG_TYPE_I64:
734 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
735 /* fallthru */
736 case TCG_TYPE_I32:
7097312d
RH		 737 if (ret < TCG_REG_V0) {
738 if (arg < TCG_REG_V0) {
739 tcg_out32(s, OR | SAB(arg, ret, arg));
740 break;
741 } else if (have_isa_2_07) {
742 tcg_out32(s, (type == TCG_TYPE_I32 ? MFVSRWZ : MFVSRD)
743 | VRT(arg) | RA(ret));
744 break;
745 } else {
746 /* Altivec does not support vector->integer moves. */
747 return false;
748 }
749 } else if (arg < TCG_REG_V0) {
750 if (have_isa_2_07) {
751 tcg_out32(s, (type == TCG_TYPE_I32 ? MTVSRWZ : MTVSRD)
752 | VRT(ret) | RA(arg));
753 break;
754 } else {
755 /* Altivec does not support integer->vector moves. */
756 return false;
757 }
6ef14d7e
RH		 758 }
759 /* fallthru */
760 case TCG_TYPE_V64:
761 case TCG_TYPE_V128:
762 tcg_debug_assert(ret >= TCG_REG_V0 && arg >= TCG_REG_V0);
763 tcg_out32(s, VOR | VRT(ret) | VRA(arg) | VRB(arg));
764 break;
765 default:
766 g_assert_not_reached();
f8b84129 767 }
78113e83 768 return true;
810260a8 769}
770
aceac8d6
RH		 771static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs,
772 int sh, int mb)
810260a8 773{
eabb7b91 774 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
541dd4ce
RH		 775 sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1);
776 mb = MB64((mb >> 5) | ((mb << 1) & 0x3f));
777 tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb);
810260a8 778}
779
9e555b73
RH		 780static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs,
781 int sh, int mb, int me)
782{
783 tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me));
784}
785
6e5e0602
RH		 786static inline void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src)
787{
788 tcg_out_rld(s, RLDICL, dst, src, 0, 32);
789}
790
a757e1ee
RH		 791static inline void tcg_out_shli32(TCGContext *s, TCGReg dst, TCGReg src, int c)
792{
793 tcg_out_rlw(s, RLWINM, dst, src, c, 0, 31 - c);
794}
795
0a9564b9
RH		 796static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c)
797{
798 tcg_out_rld(s, RLDICR, dst, src, c, 63 - c);
799}
800
a757e1ee
RH		 801static inline void tcg_out_shri32(TCGContext *s, TCGReg dst, TCGReg src, int c)
802{
803 tcg_out_rlw(s, RLWINM, dst, src, 32 - c, c, 31);
804}
805
5e916c28
RH		 806static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c)
807{
808 tcg_out_rld(s, RLDICL, dst, src, 64 - c, c);
809}
810
77bfc7c0
RH		 811/* Emit a move into ret of arg, if it can be done in one insn. */
812static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg)
813{
814 if (arg == (int16_t)arg) {
815 tcg_out32(s, ADDI | TAI(ret, 0, arg));
816 return true;
817 }
818 if (arg == (int32_t)arg && (arg & 0xffff) == 0) {
819 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
820 return true;
821 }
822 return false;
823}
824
5964fca8
RH		 825static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
826 tcg_target_long arg, bool in_prologue)
810260a8 827{
5964fca8 828 intptr_t tb_diff;
77bfc7c0
RH		 829 tcg_target_long tmp;
830 int shift;
5964fca8
RH		 831
832 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
833
834 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
835 arg = (int32_t)arg;
836 }
837
838 /* Load 16-bit immediates with one insn. */
77bfc7c0 839 if (tcg_out_movi_one(s, ret, arg)) {
5964fca8
RH		 840 return;
841 }
842
843 /* Load addresses within the TB with one insn. */
844 tb_diff = arg - (intptr_t)s->code_gen_ptr;
845 if (!in_prologue && USE_REG_TB && tb_diff == (int16_t)tb_diff) {
846 tcg_out32(s, ADDI | TAI(ret, TCG_REG_TB, tb_diff));
847 return;
848 }
849
77bfc7c0
RH		 850 /* Load 32-bit immediates with two insns. Note that we've already
851 eliminated bare ADDIS, so we know both insns are required. */
5964fca8 852 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
2fd8eddc 853 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
77bfc7c0 854 tcg_out32(s, ORI | SAI(ret, ret, arg));
5964fca8 855 return;
810260a8 856 }
5964fca8 857 if (arg == (uint32_t)arg && !(arg & 0x8000)) {
421233a1
RH		 858 tcg_out32(s, ADDI | TAI(ret, 0, arg));
859 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
5964fca8
RH		 860 return;
861 }
a84ac4cb 862
77bfc7c0
RH		 863 /* Load masked 16-bit value. */
864 if (arg > 0 && (arg & 0x8000)) {
865 tmp = arg | 0x7fff;
866 if ((tmp & (tmp + 1)) == 0) {
867 int mb = clz64(tmp + 1) + 1;
868 tcg_out32(s, ADDI | TAI(ret, 0, arg));
869 tcg_out_rld(s, RLDICL, ret, ret, 0, mb);
870 return;
871 }
872 }
873
874 /* Load common masks with 2 insns. */
875 shift = ctz64(arg);
876 tmp = arg >> shift;
877 if (tmp == (int16_t)tmp) {
878 tcg_out32(s, ADDI | TAI(ret, 0, tmp));
879 tcg_out_shli64(s, ret, ret, shift);
880 return;
881 }
882 shift = clz64(arg);
883 if (tcg_out_movi_one(s, ret, arg << shift)) {
884 tcg_out_shri64(s, ret, ret, shift);
885 return;
886 }
887
5964fca8
RH		 888 /* Load addresses within 2GB of TB with 2 (or rarely 3) insns. */
889 if (!in_prologue && USE_REG_TB && tb_diff == (int32_t)tb_diff) {
890 tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_TB, tb_diff);
891 return;
892 }
a84ac4cb 893
53c89efd
RH		 894 /* Use the constant pool, if possible. */
895 if (!in_prologue && USE_REG_TB) {
896 new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr,
897 -(intptr_t)s->code_gen_ptr);
a7cdaf71 898 tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0));
53c89efd
RH		 899 return;
900 }
901
77bfc7c0
RH		 902 tmp = arg >> 31 >> 1;
903 tcg_out_movi(s, TCG_TYPE_I32, ret, tmp);
904 if (tmp) {
5964fca8 905 tcg_out_shli64(s, ret, ret, 32);
810260a8 906 }
5964fca8
RH		 907 if (arg & 0xffff0000) {
908 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
909 }
910 if (arg & 0xffff) {
911 tcg_out32(s, ORI | SAI(ret, ret, arg));
912 }
913}
914
4b06c216
RH		 915static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg ret,
916 tcg_target_long val)
5964fca8 917{
6ef14d7e
RH		 918 uint32_t load_insn;
919 int rel, low;
920 intptr_t add;
921
922 low = (int8_t)val;
923 if (low >= -16 && low < 16) {
924 if (val == (tcg_target_long)dup_const(MO_8, low)) {
925 tcg_out32(s, VSPLTISB | VRT(ret) | ((val & 31) << 16));
926 return;
927 }
928 if (val == (tcg_target_long)dup_const(MO_16, low)) {
929 tcg_out32(s, VSPLTISH | VRT(ret) | ((val & 31) << 16));
930 return;
931 }
932 if (val == (tcg_target_long)dup_const(MO_32, low)) {
933 tcg_out32(s, VSPLTISW | VRT(ret) | ((val & 31) << 16));
934 return;
935 }
936 }
b7ce3cff
RH		 937 if (have_isa_3_00 && val == (tcg_target_long)dup_const(MO_8, val)) {
938 tcg_out32(s, XXSPLTIB | VRT(ret) | ((val & 0xff) << 11));
939 return;
940 }
6ef14d7e
RH		 941
942 /*
943 * Otherwise we must load the value from the constant pool.
944 */
945 if (USE_REG_TB) {
946 rel = R_PPC_ADDR16;
947 add = -(intptr_t)s->code_gen_ptr;
948 } else {
949 rel = R_PPC_ADDR32;
950 add = 0;
951 }
952
47c906ae
RH		 953 if (have_vsx) {
954 load_insn = type == TCG_TYPE_V64 ? LXSDX : LXVDSX;
955 load_insn |= VRT(ret) | RB(TCG_REG_TMP1);
956 if (TCG_TARGET_REG_BITS == 64) {
957 new_pool_label(s, val, rel, s->code_ptr, add);
958 } else {
959 new_pool_l2(s, rel, s->code_ptr, add, val, val);
960 }
6ef14d7e 961 } else {
47c906ae
RH		 962 load_insn = LVX | VRT(ret) | RB(TCG_REG_TMP1);
963 if (TCG_TARGET_REG_BITS == 64) {
964 new_pool_l2(s, rel, s->code_ptr, add, val, val);
965 } else {
966 new_pool_l4(s, rel, s->code_ptr, add, val, val, val, val);
967 }
6ef14d7e
RH		 968 }
969
970 if (USE_REG_TB) {
971 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, 0, 0));
972 load_insn |= RA(TCG_REG_TB);
973 } else {
974 tcg_out32(s, ADDIS | TAI(TCG_REG_TMP1, 0, 0));
975 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, 0));
976 }
977 tcg_out32(s, load_insn);
4b06c216
RH		 978}
979
980static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
981 tcg_target_long arg)
982{
983 switch (type) {
984 case TCG_TYPE_I32:
985 case TCG_TYPE_I64:
986 tcg_debug_assert(ret < TCG_REG_V0);
987 tcg_out_movi_int(s, type, ret, arg, false);
988 break;
989
990 case TCG_TYPE_V64:
991 case TCG_TYPE_V128:
992 tcg_debug_assert(ret >= TCG_REG_V0);
993 tcg_out_dupi_vec(s, type, ret, arg);
994 break;
995
996 default:
997 g_assert_not_reached();
998 }
810260a8 999}
1000
637af30c 1001static bool mask_operand(uint32_t c, int *mb, int *me)
a9249dff
RH		 1002{
1003 uint32_t lsb, test;
1004
1005 /* Accept a bit pattern like:
1006 0....01....1
1007 1....10....0
1008 0..01..10..0
1009 Keep track of the transitions. */
1010 if (c == 0 || c == -1) {
1011 return false;
1012 }
1013 test = c;
1014 lsb = test & -test;
1015 test += lsb;
1016 if (test & (test - 1)) {
1017 return false;
1018 }
1019
1020 *me = clz32(lsb);
1021 *mb = test ? clz32(test & -test) + 1 : 0;
1022 return true;
1023}
1024
637af30c
RH		 1025static bool mask64_operand(uint64_t c, int *mb, int *me)
1026{
1027 uint64_t lsb;
1028
1029 if (c == 0) {
1030 return false;
1031 }
1032
1033 lsb = c & -c;
1034 /* Accept 1..10..0. */
1035 if (c == -lsb) {
1036 *mb = 0;
1037 *me = clz64(lsb);
1038 return true;
1039 }
1040 /* Accept 0..01..1. */
1041 if (lsb == 1 && (c & (c + 1)) == 0) {
1042 *mb = clz64(c + 1) + 1;
1043 *me = 63;
1044 return true;
1045 }
1046 return false;
1047}
1048
a9249dff
RH		 1049static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
1050{
1051 int mb, me;
1052
1e1df962
RH		 1053 if (mask_operand(c, &mb, &me)) {
1054 tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me);
1055 } else if ((c & 0xffff) == c) {
a9249dff
RH		 1056 tcg_out32(s, ANDI | SAI(src, dst, c));
1057 return;
1058 } else if ((c & 0xffff0000) == c) {
1059 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
1060 return;
a9249dff 1061 } else {
8327a470
RH		 1062 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c);
1063 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
a9249dff
RH		 1064 }
1065}
1066
637af30c
RH		 1067static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c)
1068{
1069 int mb, me;
1070
eabb7b91 1071 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
1e1df962 1072 if (mask64_operand(c, &mb, &me)) {
637af30c
RH		 1073 if (mb == 0) {
1074 tcg_out_rld(s, RLDICR, dst, src, 0, me);
1075 } else {
1076 tcg_out_rld(s, RLDICL, dst, src, 0, mb);
1077 }
1e1df962
RH		 1078 } else if ((c & 0xffff) == c) {
1079 tcg_out32(s, ANDI | SAI(src, dst, c));
1080 return;
1081 } else if ((c & 0xffff0000) == c) {
1082 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
1083 return;
637af30c 1084 } else {
8327a470
RH		 1085 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c);
1086 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
637af30c
RH		 1087 }
1088}
1089
dce74c57
RH		 1090static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c,
1091 int op_lo, int op_hi)
1092{
1093 if (c >> 16) {
1094 tcg_out32(s, op_hi | SAI(src, dst, c >> 16));
1095 src = dst;
1096 }
1097 if (c & 0xffff) {
1098 tcg_out32(s, op_lo | SAI(src, dst, c));
1099 src = dst;
1100 }
1101}
1102
1103static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
1104{
1105 tcg_out_zori32(s, dst, src, c, ORI, ORIS);
1106}
1107
1108static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
1109{
1110 tcg_out_zori32(s, dst, src, c, XORI, XORIS);
1111}
1112
e083c4a2 1113static void tcg_out_b(TCGContext *s, int mask, tcg_insn_unit *target)
5d7ff5bb 1114{
e083c4a2 1115 ptrdiff_t disp = tcg_pcrel_diff(s, target);
b0940da0 1116 if (in_range_b(disp)) {
541dd4ce
RH		 1117 tcg_out32(s, B | (disp & 0x3fffffc) | mask);
1118 } else {
de3d636d 1119 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, (uintptr_t)target);
8327a470 1120 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR);
541dd4ce 1121 tcg_out32(s, BCCTR | BO_ALWAYS | mask);
5d7ff5bb
AF		 1122 }
1123}
1124
b18d5d2b
RH		 1125static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
1126 TCGReg base, tcg_target_long offset)
810260a8 1127{
b18d5d2b 1128 tcg_target_long orig = offset, l0, l1, extra = 0, align = 0;
6e11cde1 1129 bool is_int_store = false;
dfca1778 1130 TCGReg rs = TCG_REG_TMP1;
b18d5d2b 1131
b18d5d2b
RH		 1132 switch (opi) {
1133 case LD: case LWA:
1134 align = 3;
1135 /* FALLTHRU */
1136 default:
6ef14d7e 1137 if (rt > TCG_REG_R0 && rt < TCG_REG_V0) {
b18d5d2b 1138 rs = rt;
de7761a3 1139 break;
b18d5d2b
RH		 1140 }
1141 break;
6e11cde1
RH		 1142 case LXSD:
1143 case STXSD:
1144 align = 3;
1145 break;
1146 case LXV:
1147 case STXV:
1148 align = 15;
1149 break;
b18d5d2b
RH		 1150 case STD:
1151 align = 3;
de7761a3 1152 /* FALLTHRU */
b18d5d2b 1153 case STB: case STH: case STW:
6e11cde1 1154 is_int_store = true;
b18d5d2b 1155 break;
810260a8 1156 }
810260a8 1157
b18d5d2b 1158 /* For unaligned, or very large offsets, use the indexed form. */
6ef14d7e 1159 if (offset & align || offset != (int32_t)offset || opi == 0) {
d4cba13b
RH		 1160 if (rs == base) {
1161 rs = TCG_REG_R0;
1162 }
6e11cde1 1163 tcg_debug_assert(!is_int_store || rs != rt);
de7761a3 1164 tcg_out_movi(s, TCG_TYPE_PTR, rs, orig);
6ef14d7e 1165 tcg_out32(s, opx | TAB(rt & 31, base, rs));
b18d5d2b
RH		 1166 return;
1167 }
1168
1169 l0 = (int16_t)offset;
1170 offset = (offset - l0) >> 16;
1171 l1 = (int16_t)offset;
1172
1173 if (l1 < 0 && orig >= 0) {
1174 extra = 0x4000;
1175 l1 = (int16_t)(offset - 0x4000);
1176 }
1177 if (l1) {
1178 tcg_out32(s, ADDIS | TAI(rs, base, l1));
1179 base = rs;
1180 }
1181 if (extra) {
1182 tcg_out32(s, ADDIS | TAI(rs, base, extra));
1183 base = rs;
1184 }
1185 if (opi != ADDI || base != rt || l0 != 0) {
6ef14d7e 1186 tcg_out32(s, opi | TAI(rt & 31, base, l0));
828808f5 1187 }
1188}
1189
6ef14d7e
RH		 1190static void tcg_out_vsldoi(TCGContext *s, TCGReg ret,
1191 TCGReg va, TCGReg vb, int shb)
d604f1a9 1192{
6ef14d7e
RH		 1193 tcg_out32(s, VSLDOI | VRT(ret) | VRA(va) | VRB(vb) | (shb << 6));
1194}
810260a8 1195
6ef14d7e
RH		 1196static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
1197 TCGReg base, intptr_t offset)
1198{
1199 int shift;
1200
1201 switch (type) {
1202 case TCG_TYPE_I32:
1203 if (ret < TCG_REG_V0) {
1204 tcg_out_mem_long(s, LWZ, LWZX, ret, base, offset);
1205 break;
1206 }
b2dda640
RH		 1207 if (have_isa_2_07 && have_vsx) {
1208 tcg_out_mem_long(s, 0, LXSIWZX, ret, base, offset);
1209 break;
1210 }
6ef14d7e
RH		 1211 tcg_debug_assert((offset & 3) == 0);
1212 tcg_out_mem_long(s, 0, LVEWX, ret, base, offset);
1213 shift = (offset - 4) & 0xc;
1214 if (shift) {
1215 tcg_out_vsldoi(s, ret, ret, ret, shift);
1216 }
1217 break;
1218 case TCG_TYPE_I64:
1219 if (ret < TCG_REG_V0) {
1220 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
1221 tcg_out_mem_long(s, LD, LDX, ret, base, offset);
1222 break;
1223 }
1224 /* fallthru */
1225 case TCG_TYPE_V64:
1226 tcg_debug_assert(ret >= TCG_REG_V0);
47c906ae 1227 if (have_vsx) {
6e11cde1
RH		 1228 tcg_out_mem_long(s, have_isa_3_00 ? LXSD : 0, LXSDX,
1229 ret, base, offset);
47c906ae
RH		 1230 break;
1231 }
6ef14d7e
RH		 1232 tcg_debug_assert((offset & 7) == 0);
1233 tcg_out_mem_long(s, 0, LVX, ret, base, offset & -16);
1234 if (offset & 8) {
1235 tcg_out_vsldoi(s, ret, ret, ret, 8);
1236 }
1237 break;
1238 case TCG_TYPE_V128:
1239 tcg_debug_assert(ret >= TCG_REG_V0);
1240 tcg_debug_assert((offset & 15) == 0);
6e11cde1
RH		 1241 tcg_out_mem_long(s, have_isa_3_00 ? LXV : 0,
1242 LVX, ret, base, offset);
6ef14d7e
RH		 1243 break;
1244 default:
1245 g_assert_not_reached();
d604f1a9 1246 }
d604f1a9 1247}
fedee3e7 1248
6ef14d7e
RH		 1249static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
1250 TCGReg base, intptr_t offset)
810260a8 1251{
6ef14d7e 1252 int shift;
fedee3e7 1253
6ef14d7e
RH		 1254 switch (type) {
1255 case TCG_TYPE_I32:
1256 if (arg < TCG_REG_V0) {
1257 tcg_out_mem_long(s, STW, STWX, arg, base, offset);
1258 break;
1259 }
b2dda640
RH		 1260 if (have_isa_2_07 && have_vsx) {
1261 tcg_out_mem_long(s, 0, STXSIWX, arg, base, offset);
1262 break;
1263 }
1264 assert((offset & 3) == 0);
6ef14d7e
RH		 1265 tcg_debug_assert((offset & 3) == 0);
1266 shift = (offset - 4) & 0xc;
1267 if (shift) {
1268 tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, shift);
1269 arg = TCG_VEC_TMP1;
1270 }
1271 tcg_out_mem_long(s, 0, STVEWX, arg, base, offset);
1272 break;
1273 case TCG_TYPE_I64:
1274 if (arg < TCG_REG_V0) {
1275 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
1276 tcg_out_mem_long(s, STD, STDX, arg, base, offset);
1277 break;
1278 }
1279 /* fallthru */
1280 case TCG_TYPE_V64:
1281 tcg_debug_assert(arg >= TCG_REG_V0);
47c906ae 1282 if (have_vsx) {
6e11cde1
RH		 1283 tcg_out_mem_long(s, have_isa_3_00 ? STXSD : 0,
1284 STXSDX, arg, base, offset);
47c906ae
RH		 1285 break;
1286 }
6ef14d7e
RH		 1287 tcg_debug_assert((offset & 7) == 0);
1288 if (offset & 8) {
1289 tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, 8);
1290 arg = TCG_VEC_TMP1;
1291 }
1292 tcg_out_mem_long(s, 0, STVEWX, arg, base, offset);
1293 tcg_out_mem_long(s, 0, STVEWX, arg, base, offset + 4);
1294 break;
1295 case TCG_TYPE_V128:
1296 tcg_debug_assert(arg >= TCG_REG_V0);
6e11cde1
RH		 1297 tcg_out_mem_long(s, have_isa_3_00 ? STXV : 0,
1298 STVX, arg, base, offset);
6ef14d7e
RH		 1299 break;
1300 default:
1301 g_assert_not_reached();
fedee3e7 1302 }
d604f1a9 1303}
810260a8 1304
59d7c14e
RH		 1305static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
1306 TCGReg base, intptr_t ofs)
1307{
1308 return false;
1309}
1310
d604f1a9
RH		 1311static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
1312 int const_arg2, int cr, TCGType type)
1313{
1314 int imm;
1315 uint32_t op;
810260a8 1316
abcf61c4
RH		 1317 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
1318
d604f1a9
RH		 1319 /* Simplify the comparisons below wrt CMPI. */
1320 if (type == TCG_TYPE_I32) {
1321 arg2 = (int32_t)arg2;
4a40e231 1322 }
fedee3e7 1323
d604f1a9
RH		 1324 switch (cond) {
1325 case TCG_COND_EQ:
1326 case TCG_COND_NE:
1327 if (const_arg2) {
1328 if ((int16_t) arg2 == arg2) {
1329 op = CMPI;
1330 imm = 1;
1331 break;
1332 } else if ((uint16_t) arg2 == arg2) {
1333 op = CMPLI;
1334 imm = 1;
1335 break;
1336 }
1337 }
1338 op = CMPL;
1339 imm = 0;
1340 break;
fedee3e7 1341
d604f1a9
RH		 1342 case TCG_COND_LT:
1343 case TCG_COND_GE:
1344 case TCG_COND_LE:
1345 case TCG_COND_GT:
1346 if (const_arg2) {
1347 if ((int16_t) arg2 == arg2) {
1348 op = CMPI;
1349 imm = 1;
1350 break;
1351 }
1352 }
1353 op = CMP;
1354 imm = 0;
1355 break;
fedee3e7 1356
d604f1a9
RH		 1357 case TCG_COND_LTU:
1358 case TCG_COND_GEU:
1359 case TCG_COND_LEU:
1360 case TCG_COND_GTU:
1361 if (const_arg2) {
1362 if ((uint16_t) arg2 == arg2) {
1363 op = CMPLI;
1364 imm = 1;
1365 break;
1366 }
1367 }
1368 op = CMPL;
1369 imm = 0;
1370 break;
fedee3e7 1371
d604f1a9
RH		 1372 default:
1373 tcg_abort();
fedee3e7 1374 }
d604f1a9 1375 op |= BF(cr) | ((type == TCG_TYPE_I64) << 21);
fedee3e7 1376
d604f1a9
RH		 1377 if (imm) {
1378 tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff));
1379 } else {
1380 if (const_arg2) {
1381 tcg_out_movi(s, type, TCG_REG_R0, arg2);
1382 arg2 = TCG_REG_R0;
1383 }
1384 tcg_out32(s, op | RA(arg1) | RB(arg2));
1385 }
810260a8 1386}
1387
d604f1a9
RH		 1388static void tcg_out_setcond_eq0(TCGContext *s, TCGType type,
1389 TCGReg dst, TCGReg src)
7f12d649 1390{
a757e1ee
RH		 1391 if (type == TCG_TYPE_I32) {
1392 tcg_out32(s, CNTLZW | RS(src) | RA(dst));
1393 tcg_out_shri32(s, dst, dst, 5);
1394 } else {
1395 tcg_out32(s, CNTLZD | RS(src) | RA(dst));
1396 tcg_out_shri64(s, dst, dst, 6);
1397 }
7f12d649
RH		 1398}
1399
d604f1a9 1400static void tcg_out_setcond_ne0(TCGContext *s, TCGReg dst, TCGReg src)
7f12d649 1401{
d604f1a9
RH		 1402 /* X != 0 implies X + -1 generates a carry. Extra addition
1403 trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */
1404 if (dst != src) {
1405 tcg_out32(s, ADDIC | TAI(dst, src, -1));
1406 tcg_out32(s, SUBFE | TAB(dst, dst, src));
7f12d649 1407 } else {
d604f1a9
RH		 1408 tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1));
1409 tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src));
7f12d649 1410 }
d604f1a9 1411}
7f12d649 1412
d604f1a9
RH		 1413static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2,
1414 bool const_arg2)
1415{
1416 if (const_arg2) {
1417 if ((uint32_t)arg2 == arg2) {
1418 tcg_out_xori32(s, TCG_REG_R0, arg1, arg2);
1419 } else {
1420 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2);
1421 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0));
1422 }
1423 } else {
1424 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2));
1425 }
1426 return TCG_REG_R0;
7f12d649
RH		 1427}
1428
d604f1a9
RH		 1429static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond,
1430 TCGArg arg0, TCGArg arg1, TCGArg arg2,
1431 int const_arg2)
7f12d649 1432{
d604f1a9 1433 int crop, sh;
7f12d649 1434
eabb7b91 1435 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
a757e1ee 1436
d604f1a9
RH		 1437 /* Ignore high bits of a potential constant arg2. */
1438 if (type == TCG_TYPE_I32) {
1439 arg2 = (uint32_t)arg2;
1440 }
7f12d649 1441
d604f1a9
RH		 1442 /* Handle common and trivial cases before handling anything else. */
1443 if (arg2 == 0) {
1444 switch (cond) {
1445 case TCG_COND_EQ:
1446 tcg_out_setcond_eq0(s, type, arg0, arg1);
1447 return;
1448 case TCG_COND_NE:
a757e1ee 1449 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
d604f1a9
RH		 1450 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1451 arg1 = TCG_REG_R0;
1452 }
1453 tcg_out_setcond_ne0(s, arg0, arg1);
1454 return;
1455 case TCG_COND_GE:
1456 tcg_out32(s, NOR | SAB(arg1, arg0, arg1));
1457 arg1 = arg0;
1458 /* FALLTHRU */
1459 case TCG_COND_LT:
1460 /* Extract the sign bit. */
a757e1ee
RH		 1461 if (type == TCG_TYPE_I32) {
1462 tcg_out_shri32(s, arg0, arg1, 31);
1463 } else {
1464 tcg_out_shri64(s, arg0, arg1, 63);
1465 }
d604f1a9
RH		 1466 return;
1467 default:
1468 break;
1469 }
1470 }
7f12d649 1471
d604f1a9
RH		 1472 /* If we have ISEL, we can implement everything with 3 or 4 insns.
1473 All other cases below are also at least 3 insns, so speed up the
1474 code generator by not considering them and always using ISEL. */
63922f46 1475 if (have_isel) {
d604f1a9 1476 int isel, tab;
7f12d649 1477
d604f1a9 1478 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
7f12d649 1479
d604f1a9 1480 isel = tcg_to_isel[cond];
7f12d649 1481
d604f1a9
RH		 1482 tcg_out_movi(s, type, arg0, 1);
1483 if (isel & 1) {
1484 /* arg0 = (bc ? 0 : 1) */
1485 tab = TAB(arg0, 0, arg0);
1486 isel &= ~1;
1487 } else {
1488 /* arg0 = (bc ? 1 : 0) */
1489 tcg_out_movi(s, type, TCG_REG_R0, 0);
1490 tab = TAB(arg0, arg0, TCG_REG_R0);
1491 }
1492 tcg_out32(s, isel | tab);
1493 return;
1494 }
49d9870a 1495
d604f1a9
RH		 1496 switch (cond) {
1497 case TCG_COND_EQ:
1498 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1499 tcg_out_setcond_eq0(s, type, arg0, arg1);
1500 return;
810260a8 1501
d604f1a9
RH		 1502 case TCG_COND_NE:
1503 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1504 /* Discard the high bits only once, rather than both inputs. */
a757e1ee 1505 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
d604f1a9
RH		 1506 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1507 arg1 = TCG_REG_R0;
1508 }
1509 tcg_out_setcond_ne0(s, arg0, arg1);
1510 return;
810260a8 1511
d604f1a9
RH		 1512 case TCG_COND_GT:
1513 case TCG_COND_GTU:
1514 sh = 30;
1515 crop = 0;
1516 goto crtest;
810260a8 1517
d604f1a9
RH		 1518 case TCG_COND_LT:
1519 case TCG_COND_LTU:
1520 sh = 29;
1521 crop = 0;
1522 goto crtest;
810260a8 1523
d604f1a9
RH		 1524 case TCG_COND_GE:
1525 case TCG_COND_GEU:
1526 sh = 31;
1527 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_LT) | BB(7, CR_LT);
1528 goto crtest;
810260a8 1529
d604f1a9
RH		 1530 case TCG_COND_LE:
1531 case TCG_COND_LEU:
1532 sh = 31;
1533 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_GT) | BB(7, CR_GT);
1534 crtest:
1535 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1536 if (crop) {
1537 tcg_out32(s, crop);
1538 }
1539 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1540 tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31);
1541 break;
1542
1543 default:
1544 tcg_abort();
1545 }
810260a8 1546}
1547
bec16311 1548static void tcg_out_bc(TCGContext *s, int bc, TCGLabel *l)
810260a8 1549{
d604f1a9 1550 if (l->has_value) {
f9c7246f 1551 bc |= reloc_pc14_val(s->code_ptr, l->u.value_ptr);
49d9870a 1552 } else {
bec16311 1553 tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, l, 0);
810260a8 1554 }
f9c7246f 1555 tcg_out32(s, bc);
810260a8 1556}
1557
d604f1a9
RH		 1558static void tcg_out_brcond(TCGContext *s, TCGCond cond,
1559 TCGArg arg1, TCGArg arg2, int const_arg2,
bec16311 1560 TCGLabel *l, TCGType type)
810260a8 1561{
d604f1a9 1562 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
bec16311 1563 tcg_out_bc(s, tcg_to_bc[cond], l);
d604f1a9 1564}
fa94c3be 1565
d604f1a9
RH		 1566static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond,
1567 TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1,
1568 TCGArg v2, bool const_c2)
1569{
1570 /* If for some reason both inputs are zero, don't produce bad code. */
1571 if (v1 == 0 && v2 == 0) {
1572 tcg_out_movi(s, type, dest, 0);
1573 return;
b9e946c7 1574 }
f6548c0a 1575
d604f1a9 1576 tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type);
a69abbe0 1577
63922f46 1578 if (have_isel) {
d604f1a9 1579 int isel = tcg_to_isel[cond];
810260a8 1580
d604f1a9
RH		 1581 /* Swap the V operands if the operation indicates inversion. */
1582 if (isel & 1) {
1583 int t = v1;
1584 v1 = v2;
1585 v2 = t;
1586 isel &= ~1;
1587 }
1588 /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */
1589 if (v2 == 0) {
1590 tcg_out_movi(s, type, TCG_REG_R0, 0);
1591 }
1592 tcg_out32(s, isel | TAB(dest, v1, v2));
1593 } else {
1594 if (dest == v2) {
1595 cond = tcg_invert_cond(cond);
1596 v2 = v1;
1597 } else if (dest != v1) {
1598 if (v1 == 0) {
1599 tcg_out_movi(s, type, dest, 0);
1600 } else {
1601 tcg_out_mov(s, type, dest, v1);
1602 }
1603 }
1604 /* Branch forward over one insn */
1605 tcg_out32(s, tcg_to_bc[cond] | 8);
1606 if (v2 == 0) {
1607 tcg_out_movi(s, type, dest, 0);
1608 } else {
1609 tcg_out_mov(s, type, dest, v2);
1610 }
29b69198 1611 }
810260a8 1612}
1613
d0b07481
RH		 1614static void tcg_out_cntxz(TCGContext *s, TCGType type, uint32_t opc,
1615 TCGArg a0, TCGArg a1, TCGArg a2, bool const_a2)
1616{
1617 if (const_a2 && a2 == (type == TCG_TYPE_I32 ? 32 : 64)) {
1618 tcg_out32(s, opc | RA(a0) | RS(a1));
1619 } else {
1620 tcg_out_cmp(s, TCG_COND_EQ, a1, 0, 1, 7, type);
1621 /* Note that the only other valid constant for a2 is 0. */
63922f46 1622 if (have_isel) {
d0b07481
RH		 1623 tcg_out32(s, opc | RA(TCG_REG_R0) | RS(a1));
1624 tcg_out32(s, tcg_to_isel[TCG_COND_EQ] | TAB(a0, a2, TCG_REG_R0));
1625 } else if (!const_a2 && a0 == a2) {
1626 tcg_out32(s, tcg_to_bc[TCG_COND_EQ] | 8);
1627 tcg_out32(s, opc | RA(a0) | RS(a1));
1628 } else {
1629 tcg_out32(s, opc | RA(a0) | RS(a1));
1630 tcg_out32(s, tcg_to_bc[TCG_COND_NE] | 8);
1631 if (const_a2) {
1632 tcg_out_movi(s, type, a0, 0);
1633 } else {
1634 tcg_out_mov(s, type, a0, a2);
1635 }
1636 }
1637 }
1638}
1639
abcf61c4
RH		 1640static void tcg_out_cmp2(TCGContext *s, const TCGArg *args,
1641 const int *const_args)
1642{
1643 static const struct { uint8_t bit1, bit2; } bits[] = {
1644 [TCG_COND_LT ] = { CR_LT, CR_LT },
1645 [TCG_COND_LE ] = { CR_LT, CR_GT },
1646 [TCG_COND_GT ] = { CR_GT, CR_GT },
1647 [TCG_COND_GE ] = { CR_GT, CR_LT },
1648 [TCG_COND_LTU] = { CR_LT, CR_LT },
1649 [TCG_COND_LEU] = { CR_LT, CR_GT },
1650 [TCG_COND_GTU] = { CR_GT, CR_GT },
1651 [TCG_COND_GEU] = { CR_GT, CR_LT },
1652 };
1653
1654 TCGCond cond = args[4], cond2;
1655 TCGArg al, ah, bl, bh;
1656 int blconst, bhconst;
1657 int op, bit1, bit2;
1658
1659 al = args[0];
1660 ah = args[1];
1661 bl = args[2];
1662 bh = args[3];
1663 blconst = const_args[2];
1664 bhconst = const_args[3];
1665
1666 switch (cond) {
1667 case TCG_COND_EQ:
1668 op = CRAND;
1669 goto do_equality;
1670 case TCG_COND_NE:
1671 op = CRNAND;
1672 do_equality:
1673 tcg_out_cmp(s, cond, al, bl, blconst, 6, TCG_TYPE_I32);
1674 tcg_out_cmp(s, cond, ah, bh, bhconst, 7, TCG_TYPE_I32);
1675 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
1676 break;
1677
1678 case TCG_COND_LT:
1679 case TCG_COND_LE:
1680 case TCG_COND_GT:
1681 case TCG_COND_GE:
1682 case TCG_COND_LTU:
1683 case TCG_COND_LEU:
1684 case TCG_COND_GTU:
1685 case TCG_COND_GEU:
1686 bit1 = bits[cond].bit1;
1687 bit2 = bits[cond].bit2;
1688 op = (bit1 != bit2 ? CRANDC : CRAND);
1689 cond2 = tcg_unsigned_cond(cond);
1690
1691 tcg_out_cmp(s, cond, ah, bh, bhconst, 6, TCG_TYPE_I32);
1692 tcg_out_cmp(s, cond2, al, bl, blconst, 7, TCG_TYPE_I32);
1693 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2));
1694 tcg_out32(s, CROR | BT(7, CR_EQ) | BA(6, bit1) | BB(7, CR_EQ));
1695 break;
1696
1697 default:
1698 tcg_abort();
1699 }
1700}
1701
1702static void tcg_out_setcond2(TCGContext *s, const TCGArg *args,
1703 const int *const_args)
1704{
1705 tcg_out_cmp2(s, args + 1, const_args + 1);
1706 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1707 tcg_out_rlw(s, RLWINM, args[0], TCG_REG_R0, 31, 31, 31);
1708}
1709
1710static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
1711 const int *const_args)
1712{
1713 tcg_out_cmp2(s, args, const_args);
bec16311 1714 tcg_out_bc(s, BC | BI(7, CR_EQ) | BO_COND_TRUE, arg_label(args[5]));
abcf61c4
RH		 1715}
1716
7b4af5ee
PK		 1717static void tcg_out_mb(TCGContext *s, TCGArg a0)
1718{
1719 uint32_t insn = HWSYNC;
1720 a0 &= TCG_MO_ALL;
1721 if (a0 == TCG_MO_LD_LD) {
1722 insn = LWSYNC;
1723 } else if (a0 == TCG_MO_ST_ST) {
1724 insn = EIEIO;
1725 }
1726 tcg_out32(s, insn);
1727}
1728
a8583393
RH		 1729void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
1730 uintptr_t addr)
810260a8 1731{
5964fca8
RH		 1732 if (TCG_TARGET_REG_BITS == 64) {
1733 tcg_insn_unit i1, i2;
1734 intptr_t tb_diff = addr - tc_ptr;
1735 intptr_t br_diff = addr - (jmp_addr + 4);
1736 uint64_t pair;
1737
1738 /* This does not exercise the range of the branch, but we do
1739 still need to be able to load the new value of TCG_REG_TB.
1740 But this does still happen quite often. */
1741 if (tb_diff == (int16_t)tb_diff) {
1742 i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff);
1743 i2 = B | (br_diff & 0x3fffffc);
1744 } else {
1745 intptr_t lo = (int16_t)tb_diff;
1746 intptr_t hi = (int32_t)(tb_diff - lo);
1747 assert(tb_diff == hi + lo);
1748 i1 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16);
1749 i2 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo);
1750 }
5bfd75a3 1751#ifdef HOST_WORDS_BIGENDIAN
5964fca8 1752 pair = (uint64_t)i1 << 32 | i2;
5bfd75a3 1753#else
5964fca8 1754 pair = (uint64_t)i2 << 32 | i1;
5bfd75a3
RH		 1755#endif
1756
ba026602
PMD		 1757 /* As per the enclosing if, this is ppc64. Avoid the _Static_assert
1758 within atomic_set that would fail to build a ppc32 host. */
1759 atomic_set__nocheck((uint64_t *)jmp_addr, pair);
5964fca8
RH		 1760 flush_icache_range(jmp_addr, jmp_addr + 8);
1761 } else {
1762 intptr_t diff = addr - jmp_addr;
1763 tcg_debug_assert(in_range_b(diff));
1764 atomic_set((uint32_t *)jmp_addr, B | (diff & 0x3fffffc));
1765 flush_icache_range(jmp_addr, jmp_addr + 4);
1766 }
399f1648 1767}
810260a8 1768
d604f1a9 1769static void tcg_out_call(TCGContext *s, tcg_insn_unit *target)
810260a8 1770{
eaf7d1cf 1771#ifdef _CALL_AIX
d604f1a9
RH		 1772 /* Look through the descriptor. If the branch is in range, and we
1773 don't have to spend too much effort on building the toc. */
1774 void *tgt = ((void **)target)[0];
1775 uintptr_t toc = ((uintptr_t *)target)[1];
1776 intptr_t diff = tcg_pcrel_diff(s, tgt);
b18d5d2b 1777
d604f1a9 1778 if (in_range_b(diff) && toc == (uint32_t)toc) {
dfca1778 1779 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, toc);
d604f1a9 1780 tcg_out_b(s, LK, tgt);
541dd4ce 1781 } else {
d604f1a9
RH		 1782 /* Fold the low bits of the constant into the addresses below. */
1783 intptr_t arg = (intptr_t)target;
1784 int ofs = (int16_t)arg;
1785
1786 if (ofs + 8 < 0x8000) {
1787 arg -= ofs;
1788 } else {
1789 ofs = 0;
1790 }
dfca1778
RH		 1791 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, arg);
1792 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_TMP1, ofs);
d604f1a9 1793 tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR);
dfca1778 1794 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_TMP1, ofs + SZP);
d604f1a9 1795 tcg_out32(s, BCCTR | BO_ALWAYS | LK);
541dd4ce 1796 }
77e58d0d
UW		 1797#elif defined(_CALL_ELF) && _CALL_ELF == 2
1798 intptr_t diff;
1799
1800 /* In the ELFv2 ABI, we have to set up r12 to contain the destination
1801 address, which the callee uses to compute its TOC address. */
1802 /* FIXME: when the branch is in range, we could avoid r12 load if we
1803 knew that the destination uses the same TOC, and what its local
1804 entry point offset is. */
1805 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R12, (intptr_t)target);
1806
1807 diff = tcg_pcrel_diff(s, target);
1808 if (in_range_b(diff)) {
1809 tcg_out_b(s, LK, target);
1810 } else {
1811 tcg_out32(s, MTSPR | RS(TCG_REG_R12) | CTR);
1812 tcg_out32(s, BCCTR | BO_ALWAYS | LK);
1813 }
eaf7d1cf
RH		 1814#else
1815 tcg_out_b(s, LK, target);
d604f1a9 1816#endif
810260a8 1817}
1818
d604f1a9
RH		 1819static const uint32_t qemu_ldx_opc[16] = {
1820 [MO_UB] = LBZX,
1821 [MO_UW] = LHZX,
1822 [MO_UL] = LWZX,
1823 [MO_Q] = LDX,
1824 [MO_SW] = LHAX,
1825 [MO_SL] = LWAX,
1826 [MO_BSWAP | MO_UB] = LBZX,
1827 [MO_BSWAP | MO_UW] = LHBRX,
1828 [MO_BSWAP | MO_UL] = LWBRX,
1829 [MO_BSWAP | MO_Q] = LDBRX,
1830};
810260a8 1831
d604f1a9
RH		 1832static const uint32_t qemu_stx_opc[16] = {
1833 [MO_UB] = STBX,
1834 [MO_UW] = STHX,
1835 [MO_UL] = STWX,
1836 [MO_Q] = STDX,
1837 [MO_BSWAP | MO_UB] = STBX,
1838 [MO_BSWAP | MO_UW] = STHBRX,
1839 [MO_BSWAP | MO_UL] = STWBRX,
1840 [MO_BSWAP | MO_Q] = STDBRX,
1841};
991041a4 1842
d604f1a9
RH		 1843static const uint32_t qemu_exts_opc[4] = {
1844 EXTSB, EXTSH, EXTSW, 0
1845};
810260a8 1846
d604f1a9 1847#if defined (CONFIG_SOFTMMU)
2b434dd1 1848#include "../tcg-ldst.inc.c"
659ef5cb 1849
d604f1a9
RH		 1850/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
1851 * int mmu_idx, uintptr_t ra)
1852 */
1853static void * const qemu_ld_helpers[16] = {
1854 [MO_UB] = helper_ret_ldub_mmu,
1855 [MO_LEUW] = helper_le_lduw_mmu,
1856 [MO_LEUL] = helper_le_ldul_mmu,
1857 [MO_LEQ] = helper_le_ldq_mmu,
1858 [MO_BEUW] = helper_be_lduw_mmu,
1859 [MO_BEUL] = helper_be_ldul_mmu,
1860 [MO_BEQ] = helper_be_ldq_mmu,
1861};
810260a8 1862
d604f1a9
RH		 1863/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
1864 * uintxx_t val, int mmu_idx, uintptr_t ra)
1865 */
1866static void * const qemu_st_helpers[16] = {
1867 [MO_UB] = helper_ret_stb_mmu,
1868 [MO_LEUW] = helper_le_stw_mmu,
1869 [MO_LEUL] = helper_le_stl_mmu,
1870 [MO_LEQ] = helper_le_stq_mmu,
1871 [MO_BEUW] = helper_be_stw_mmu,
1872 [MO_BEUL] = helper_be_stl_mmu,
1873 [MO_BEQ] = helper_be_stq_mmu,
1874};
810260a8 1875
269bd5d8
RH		 1876/* We expect to use a 16-bit negative offset from ENV. */
1877QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
1878QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768);
1879
d604f1a9
RH		 1880/* Perform the TLB load and compare. Places the result of the comparison
1881 in CR7, loads the addend of the TLB into R3, and returns the register
1882 containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
1883
14776ab5 1884static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp opc,
7f25c469 1885 TCGReg addrlo, TCGReg addrhi,
d604f1a9
RH		 1886 int mem_index, bool is_read)
1887{
1888 int cmp_off
1889 = (is_read
644f591a
RH		 1890 ? offsetof(CPUTLBEntry, addr_read)
1891 : offsetof(CPUTLBEntry, addr_write));
269bd5d8
RH		 1892 int fast_off = TLB_MASK_TABLE_OFS(mem_index);
1893 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
1894 int table_off = fast_off + offsetof(CPUTLBDescFast, table);
85aa8081
RH		 1895 unsigned s_bits = opc & MO_SIZE;
1896 unsigned a_bits = get_alignment_bits(opc);
d604f1a9 1897
644f591a 1898 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
269bd5d8
RH		 1899 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0, mask_off);
1900 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, TCG_AREG0, table_off);
644f591a
RH		 1901
1902 /* Extract the page index, shifted into place for tlb index. */
1903 if (TCG_TARGET_REG_BITS == 32) {
1904 tcg_out_shri32(s, TCG_REG_TMP1, addrlo,
1905 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
4c314da6 1906 } else {
644f591a
RH		 1907 tcg_out_shri64(s, TCG_REG_TMP1, addrlo,
1908 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
810260a8 1909 }
644f591a 1910 tcg_out32(s, AND | SAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_TMP1));
810260a8 1911
644f591a
RH		 1912 /* Load the TLB comparator. */
1913 if (cmp_off == 0 && TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) {
1914 uint32_t lxu = (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32
1915 ? LWZUX : LDUX);
1916 tcg_out32(s, lxu | TAB(TCG_REG_TMP1, TCG_REG_R3, TCG_REG_R4));
7f25c469 1917 } else {
644f591a
RH		 1918 tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_R4));
1919 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1920 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off + 4);
1921 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off);
1922 } else {
1923 tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off);
1924 }
7f25c469 1925 }
d604f1a9
RH		 1926
1927 /* Load the TLB addend for use on the fast path. Do this asap
1928 to minimize any load use delay. */
644f591a
RH		 1929 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3,
1930 offsetof(CPUTLBEntry, addend));
d604f1a9 1931
68d45bb6 1932 /* Clear the non-page, non-alignment bits from the address */
85aa8081
RH		 1933 if (TCG_TARGET_REG_BITS == 32) {
1934 /* We don't support unaligned accesses on 32-bits.
1935 * Preserve the bottom bits and thus trigger a comparison
1936 * failure on unaligned accesses.
68d45bb6 1937 */
85aa8081 1938 if (a_bits < s_bits) {
1f00b27f
SS		 1939 a_bits = s_bits;
1940 }
7f25c469 1941 tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0,
1f00b27f 1942 (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS);
85aa8081
RH		 1943 } else {
1944 TCGReg t = addrlo;
1945
1946 /* If the access is unaligned, we need to make sure we fail if we
1947 * cross a page boundary. The trick is to add the access size-1
1948 * to the address before masking the low bits. That will make the
1949 * address overflow to the next page if we cross a page boundary,
1950 * which will then force a mismatch of the TLB compare.
1951 */
1952 if (a_bits < s_bits) {
1953 unsigned a_mask = (1 << a_bits) - 1;
1954 unsigned s_mask = (1 << s_bits) - 1;
1955 tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask));
1956 t = TCG_REG_R0;
1957 }
1958
1959 /* Mask the address for the requested alignment. */
1960 if (TARGET_LONG_BITS == 32) {
1961 tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0,
1962 (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS);
644f591a
RH		 1963 /* Zero-extend the address for use in the final address. */
1964 tcg_out_ext32u(s, TCG_REG_R4, addrlo);
1965 addrlo = TCG_REG_R4;
85aa8081
RH		 1966 } else if (a_bits == 0) {
1967 tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS);
1968 } else {
1969 tcg_out_rld(s, RLDICL, TCG_REG_R0, t,
1f00b27f 1970 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - a_bits);
68d45bb6 1971 tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0);
68d45bb6 1972 }
70fac59a 1973 }
d604f1a9 1974
7f25c469 1975 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
dfca1778
RH		 1976 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
1977 0, 7, TCG_TYPE_I32);
7f25c469
RH		 1978 tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32);
1979 tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
1980 } else {
dfca1778
RH		 1981 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
1982 0, 7, TCG_TYPE_TL);
7f25c469 1983 }
d604f1a9 1984
7f25c469 1985 return addrlo;
70fac59a 1986}
1cd62ae9 1987
d604f1a9
RH		 1988/* Record the context of a call to the out of line helper code for the slow
1989 path for a load or store, so that we can later generate the correct
1990 helper code. */
3972ef6f 1991static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
7f25c469
RH		 1992 TCGReg datalo_reg, TCGReg datahi_reg,
1993 TCGReg addrlo_reg, TCGReg addrhi_reg,
3972ef6f 1994 tcg_insn_unit *raddr, tcg_insn_unit *lptr)
70fac59a 1995{
d604f1a9
RH		 1996 TCGLabelQemuLdst *label = new_ldst_label(s);
1997
1998 label->is_ld = is_ld;
3972ef6f 1999 label->oi = oi;
7f25c469
RH		 2000 label->datalo_reg = datalo_reg;
2001 label->datahi_reg = datahi_reg;
2002 label->addrlo_reg = addrlo_reg;
2003 label->addrhi_reg = addrhi_reg;
d604f1a9 2004 label->raddr = raddr;
7f25c469 2005 label->label_ptr[0] = lptr;
70fac59a 2006}
1cd62ae9 2007
aeee05f5 2008static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
70fac59a 2009{
3972ef6f 2010 TCGMemOpIdx oi = lb->oi;
14776ab5 2011 MemOp opc = get_memop(oi);
7f25c469 2012 TCGReg hi, lo, arg = TCG_REG_R3;
70fac59a 2013
aeee05f5
RH		 2014 if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) {
2015 return false;
2016 }
70fac59a 2017
7f25c469 2018 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
1cd62ae9 2019
7f25c469
RH		 2020 lo = lb->addrlo_reg;
2021 hi = lb->addrhi_reg;
2022 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
2023#ifdef TCG_TARGET_CALL_ALIGN_ARGS
2024 arg |= 1;
2025#endif
2026 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
2027 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
2028 } else {
2029 /* If the address needed to be zero-extended, we'll have already
2030 placed it in R4. The only remaining case is 64-bit guest. */
2031 tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
2032 }
752c1fdb 2033
3972ef6f 2034 tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
7f25c469 2035 tcg_out32(s, MFSPR | RT(arg) | LR);
70fac59a 2036
2b7ec66f 2037 tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]);
70fac59a 2038
7f25c469
RH		 2039 lo = lb->datalo_reg;
2040 hi = lb->datahi_reg;
2041 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
2042 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_REG_R4);
2043 tcg_out_mov(s, TCG_TYPE_I32, hi, TCG_REG_R3);
2044 } else if (opc & MO_SIGN) {
d604f1a9 2045 uint32_t insn = qemu_exts_opc[opc & MO_SIZE];
7f25c469 2046 tcg_out32(s, insn | RA(lo) | RS(TCG_REG_R3));
d604f1a9 2047 } else {
7f25c469 2048 tcg_out_mov(s, TCG_TYPE_REG, lo, TCG_REG_R3);
70fac59a
RH		 2049 }
2050
d604f1a9 2051 tcg_out_b(s, 0, lb->raddr);
aeee05f5 2052 return true;
d604f1a9 2053}
70fac59a 2054
aeee05f5 2055static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
d604f1a9 2056{
3972ef6f 2057 TCGMemOpIdx oi = lb->oi;
14776ab5
TN		 2058 MemOp opc = get_memop(oi);
2059 MemOp s_bits = opc & MO_SIZE;
7f25c469 2060 TCGReg hi, lo, arg = TCG_REG_R3;
1cd62ae9 2061
aeee05f5
RH		 2062 if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) {
2063 return false;
2064 }
1cd62ae9 2065
7f25c469
RH		 2066 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
2067
2068 lo = lb->addrlo_reg;
2069 hi = lb->addrhi_reg;
2070 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
2071#ifdef TCG_TARGET_CALL_ALIGN_ARGS
2072 arg |= 1;
2073#endif
2074 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
2075 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
2076 } else {
2077 /* If the address needed to be zero-extended, we'll have already
2078 placed it in R4. The only remaining case is 64-bit guest. */
2079 tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
2080 }
1cd62ae9 2081
7f25c469
RH		 2082 lo = lb->datalo_reg;
2083 hi = lb->datahi_reg;
2084 if (TCG_TARGET_REG_BITS == 32) {
2085 switch (s_bits) {
2086 case MO_64:
2087#ifdef TCG_TARGET_CALL_ALIGN_ARGS
2088 arg |= 1;
2089#endif
2090 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
2091 /* FALLTHRU */
2092 case MO_32:
2093 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
2094 break;
2095 default:
2096 tcg_out_rlw(s, RLWINM, arg++, lo, 0, 32 - (8 << s_bits), 31);
2097 break;
2098 }
2099 } else {
2100 if (s_bits == MO_64) {
2101 tcg_out_mov(s, TCG_TYPE_I64, arg++, lo);
2102 } else {
2103 tcg_out_rld(s, RLDICL, arg++, lo, 0, 64 - (8 << s_bits));
2104 }
2105 }
1cd62ae9 2106
3972ef6f 2107 tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
7f25c469 2108 tcg_out32(s, MFSPR | RT(arg) | LR);
1cd62ae9 2109
2b7ec66f 2110 tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
d604f1a9
RH		 2111
2112 tcg_out_b(s, 0, lb->raddr);
aeee05f5 2113 return true;
1cd62ae9 2114}
d604f1a9 2115#endif /* SOFTMMU */
1cd62ae9 2116
7f25c469 2117static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
810260a8 2118{
7f25c469
RH		 2119 TCGReg datalo, datahi, addrlo, rbase;
2120 TCGReg addrhi __attribute__((unused));
59227d5d 2121 TCGMemOpIdx oi;
14776ab5 2122 MemOp opc, s_bits;
d604f1a9 2123#ifdef CONFIG_SOFTMMU
7f25c469 2124 int mem_index;
d604f1a9
RH		 2125 tcg_insn_unit *label_ptr;
2126#endif
810260a8 2127
7f25c469
RH		 2128 datalo = *args++;
2129 datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
2130 addrlo = *args++;
2131 addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
59227d5d
RH		 2132 oi = *args++;
2133 opc = get_memop(oi);
7f25c469
RH		 2134 s_bits = opc & MO_SIZE;
2135
d604f1a9 2136#ifdef CONFIG_SOFTMMU
59227d5d 2137 mem_index = get_mmuidx(oi);
68d45bb6 2138 addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true);
d604f1a9
RH		 2139
2140 /* Load a pointer into the current opcode w/conditional branch-link. */
2141 label_ptr = s->code_ptr;
f9c7246f 2142 tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
d604f1a9
RH		 2143
2144 rbase = TCG_REG_R3;
2145#else /* !CONFIG_SOFTMMU */
b76f21a7 2146 rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
7f25c469 2147 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
dfca1778
RH		 2148 tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
2149 addrlo = TCG_REG_TMP1;
d604f1a9
RH		 2150 }
2151#endif
2152
7f25c469
RH		 2153 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
2154 if (opc & MO_BSWAP) {
2155 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
2156 tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
2157 tcg_out32(s, LWBRX | TAB(datahi, rbase, TCG_REG_R0));
2158 } else if (rbase != 0) {
2159 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
2160 tcg_out32(s, LWZX | TAB(datahi, rbase, addrlo));
2161 tcg_out32(s, LWZX | TAB(datalo, rbase, TCG_REG_R0));
2162 } else if (addrlo == datahi) {
2163 tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
2164 tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
2165 } else {
2166 tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
2167 tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
2168 }
541dd4ce 2169 } else {
2b7ec66f 2170 uint32_t insn = qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)];
4e33fe01 2171 if (!have_isa_2_06 && insn == LDBRX) {
7f25c469
RH		 2172 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
2173 tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
2174 tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0));
2175 tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0);
2176 } else if (insn) {
2177 tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
2178 } else {
2179 insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)];
2180 tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
2181 insn = qemu_exts_opc[s_bits];
2182 tcg_out32(s, insn | RA(datalo) | RS(datalo));
2183 }
810260a8 2184 }
810260a8 2185
d604f1a9 2186#ifdef CONFIG_SOFTMMU
3972ef6f
RH		 2187 add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi,
2188 s->code_ptr, label_ptr);
d604f1a9 2189#endif
810260a8 2190}
2191
7f25c469 2192static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
027ffea9 2193{
7f25c469
RH		 2194 TCGReg datalo, datahi, addrlo, rbase;
2195 TCGReg addrhi __attribute__((unused));
59227d5d 2196 TCGMemOpIdx oi;
14776ab5 2197 MemOp opc, s_bits;
d604f1a9 2198#ifdef CONFIG_SOFTMMU
7f25c469 2199 int mem_index;
d604f1a9
RH		 2200 tcg_insn_unit *label_ptr;
2201#endif
027ffea9 2202
7f25c469
RH		 2203 datalo = *args++;
2204 datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
2205 addrlo = *args++;
2206 addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
59227d5d
RH		 2207 oi = *args++;
2208 opc = get_memop(oi);
7f25c469
RH		 2209 s_bits = opc & MO_SIZE;
2210
d604f1a9 2211#ifdef CONFIG_SOFTMMU
59227d5d 2212 mem_index = get_mmuidx(oi);
68d45bb6 2213 addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false);
027ffea9 2214
d604f1a9
RH		 2215 /* Load a pointer into the current opcode w/conditional branch-link. */
2216 label_ptr = s->code_ptr;
f9c7246f 2217 tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
027ffea9 2218
d604f1a9
RH		 2219 rbase = TCG_REG_R3;
2220#else /* !CONFIG_SOFTMMU */
b76f21a7 2221 rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
7f25c469 2222 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
dfca1778
RH		 2223 tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
2224 addrlo = TCG_REG_TMP1;
d604f1a9
RH		 2225 }
2226#endif
2227
7f25c469
RH		 2228 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
2229 if (opc & MO_BSWAP) {
2230 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
2231 tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
2232 tcg_out32(s, STWBRX | SAB(datahi, rbase, TCG_REG_R0));
2233 } else if (rbase != 0) {
2234 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
2235 tcg_out32(s, STWX | SAB(datahi, rbase, addrlo));
2236 tcg_out32(s, STWX | SAB(datalo, rbase, TCG_REG_R0));
2237 } else {
2238 tcg_out32(s, STW | TAI(datahi, addrlo, 0));
2239 tcg_out32(s, STW | TAI(datalo, addrlo, 4));
2240 }
027ffea9 2241 } else {
2b7ec66f 2242 uint32_t insn = qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)];
4e33fe01 2243 if (!have_isa_2_06 && insn == STDBRX) {
7f25c469 2244 tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
dfca1778 2245 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, addrlo, 4));
7f25c469 2246 tcg_out_shri64(s, TCG_REG_R0, datalo, 32);
dfca1778 2247 tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_TMP1));
7f25c469
RH		 2248 } else {
2249 tcg_out32(s, insn | SAB(datalo, rbase, addrlo));
2250 }
027ffea9 2251 }
d604f1a9
RH		 2252
2253#ifdef CONFIG_SOFTMMU
3972ef6f
RH		 2254 add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi,
2255 s->code_ptr, label_ptr);
d604f1a9 2256#endif
027ffea9
RH		 2257}
2258
53c89efd
RH		 2259static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
2260{
2261 int i;
2262 for (i = 0; i < count; ++i) {
2263 p[i] = NOP;
2264 }
2265}
2266
a921fddc
RH		 2267/* Parameters for function call generation, used in tcg.c. */
2268#define TCG_TARGET_STACK_ALIGN 16
a921fddc
RH		 2269#define TCG_TARGET_EXTEND_ARGS 1
2270
802ca56e
RH		 2271#ifdef _CALL_AIX
2272# define LINK_AREA_SIZE (6 * SZR)
2273# define LR_OFFSET (1 * SZR)
2274# define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR)
1045fc04
PM		 2275#elif defined(TCG_TARGET_CALL_DARWIN)
2276# define LINK_AREA_SIZE (6 * SZR)
2277# define LR_OFFSET (2 * SZR)
ffcfbece
RH		 2278#elif TCG_TARGET_REG_BITS == 64
2279# if defined(_CALL_ELF) && _CALL_ELF == 2
2280# define LINK_AREA_SIZE (4 * SZR)
2281# define LR_OFFSET (1 * SZR)
2282# endif
2283#else /* TCG_TARGET_REG_BITS == 32 */
2284# if defined(_CALL_SYSV)
ffcfbece
RH		 2285# define LINK_AREA_SIZE (2 * SZR)
2286# define LR_OFFSET (1 * SZR)
ffcfbece
RH		 2287# endif
2288#endif
2289#ifndef LR_OFFSET
2290# error "Unhandled abi"
2291#endif
2292#ifndef TCG_TARGET_CALL_STACK_OFFSET
a2a98f80 2293# define TCG_TARGET_CALL_STACK_OFFSET LINK_AREA_SIZE
802ca56e
RH		 2294#endif
2295
2296#define CPU_TEMP_BUF_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
2297#define REG_SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * SZR)
d604f1a9 2298
802ca56e
RH		 2299#define FRAME_SIZE ((TCG_TARGET_CALL_STACK_OFFSET \
2300 + TCG_STATIC_CALL_ARGS_SIZE \
2301 + CPU_TEMP_BUF_SIZE \
2302 + REG_SAVE_SIZE \
2303 + TCG_TARGET_STACK_ALIGN - 1) \
2304 & -TCG_TARGET_STACK_ALIGN)
2305
2306#define REG_SAVE_BOT (FRAME_SIZE - REG_SAVE_SIZE)
d604f1a9
RH		 2307
2308static void tcg_target_qemu_prologue(TCGContext *s)
810260a8 2309{
d604f1a9 2310 int i;
810260a8 2311
802ca56e 2312#ifdef _CALL_AIX
a84ac4cb
RH		 2313 void **desc = (void **)s->code_ptr;
2314 desc[0] = desc + 2; /* entry point */
2315 desc[1] = 0; /* environment pointer */
2316 s->code_ptr = (void *)(desc + 2); /* skip over descriptor */
d604f1a9
RH		 2317#endif
2318
a84ac4cb
RH		 2319 tcg_set_frame(s, TCG_REG_CALL_STACK, REG_SAVE_BOT - CPU_TEMP_BUF_SIZE,
2320 CPU_TEMP_BUF_SIZE);
2321
d604f1a9
RH		 2322 /* Prologue */
2323 tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR);
ffcfbece
RH		 2324 tcg_out32(s, (SZR == 8 ? STDU : STWU)
2325 | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE));
802ca56e 2326
d604f1a9 2327 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
4c3831a0
RH		 2328 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2329 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
d604f1a9 2330 }
802ca56e 2331 tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
d604f1a9 2332
4cbea598 2333#ifndef CONFIG_SOFTMMU
b76f21a7 2334 if (guest_base) {
5964fca8 2335 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true);
d604f1a9
RH		 2336 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2337 }
2338#endif
2339
2340 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
2341 tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR);
5964fca8
RH		 2342 if (USE_REG_TB) {
2343 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]);
a84ac4cb 2344 }
5964fca8 2345 tcg_out32(s, BCCTR | BO_ALWAYS);
d604f1a9
RH		 2346
2347 /* Epilogue */
5964fca8 2348 s->code_gen_epilogue = tb_ret_addr = s->code_ptr;
d604f1a9 2349
802ca56e 2350 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
d604f1a9 2351 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
4c3831a0
RH		 2352 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2353 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
d604f1a9 2354 }
d604f1a9
RH		 2355 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR);
2356 tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE));
2357 tcg_out32(s, BCLR | BO_ALWAYS);
810260a8 2358}
2359
541dd4ce
RH		 2360static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
2361 const int *const_args)
810260a8 2362{
ee924fa6 2363 TCGArg a0, a1, a2;
e46b9681 2364 int c;
2365
810260a8 2366 switch (opc) {
2367 case INDEX_op_exit_tb:
de3d636d 2368 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]);
e083c4a2 2369 tcg_out_b(s, 0, tb_ret_addr);
810260a8 2370 break;
2371 case INDEX_op_goto_tb:
5964fca8
RH		 2372 if (s->tb_jmp_insn_offset) {
2373 /* Direct jump. */
2374 if (TCG_TARGET_REG_BITS == 64) {
2375 /* Ensure the next insns are 8-byte aligned. */
2376 if ((uintptr_t)s->code_ptr & 7) {
2377 tcg_out32(s, NOP);
2378 }
2379 s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);
2380 tcg_out32(s, ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, 0));
2381 tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, 0));
2382 } else {
2383 s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);
2384 tcg_out32(s, B);
2385 s->tb_jmp_reset_offset[args[0]] = tcg_current_code_size(s);
2386 break;
2387 }
2388 } else {
2389 /* Indirect jump. */
2390 tcg_debug_assert(s->tb_jmp_insn_offset == NULL);
2391 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, 0,
2392 (intptr_t)(s->tb_jmp_insn_offset + args[0]));
2393 }
2394 tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR);
5bfd75a3 2395 tcg_out32(s, BCCTR | BO_ALWAYS);
9f754620 2396 set_jmp_reset_offset(s, args[0]);
5964fca8
RH		 2397 if (USE_REG_TB) {
2398 /* For the unlinked case, need to reset TCG_REG_TB. */
9f754620 2399 c = -tcg_current_code_size(s);
5964fca8
RH		 2400 assert(c == (int16_t)c);
2401 tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, c));
2402 }
810260a8 2403 break;
0c240785
RH		 2404 case INDEX_op_goto_ptr:
2405 tcg_out32(s, MTSPR | RS(args[0]) | CTR);
5964fca8
RH		 2406 if (USE_REG_TB) {
2407 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, args[0]);
2408 }
2409 tcg_out32(s, ADDI | TAI(TCG_REG_R3, 0, 0));
0c240785
RH		 2410 tcg_out32(s, BCCTR | BO_ALWAYS);
2411 break;
810260a8 2412 case INDEX_op_br:
2413 {
bec16311 2414 TCGLabel *l = arg_label(args[0]);
f9c7246f 2415 uint32_t insn = B;
810260a8 2416
2417 if (l->has_value) {
f9c7246f 2418 insn |= reloc_pc24_val(s->code_ptr, l->u.value_ptr);
541dd4ce 2419 } else {
bec16311 2420 tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, l, 0);
810260a8 2421 }
f9c7246f 2422 tcg_out32(s, insn);
810260a8 2423 }
2424 break;
810260a8 2425 case INDEX_op_ld8u_i32:
2426 case INDEX_op_ld8u_i64:
b18d5d2b 2427 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
810260a8 2428 break;
2429 case INDEX_op_ld8s_i32:
2430 case INDEX_op_ld8s_i64:
b18d5d2b 2431 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
541dd4ce 2432 tcg_out32(s, EXTSB | RS(args[0]) | RA(args[0]));
810260a8 2433 break;
2434 case INDEX_op_ld16u_i32:
2435 case INDEX_op_ld16u_i64:
b18d5d2b 2436 tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]);
810260a8 2437 break;
2438 case INDEX_op_ld16s_i32:
2439 case INDEX_op_ld16s_i64:
b18d5d2b 2440 tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]);
810260a8 2441 break;
2442 case INDEX_op_ld_i32:
2443 case INDEX_op_ld32u_i64:
b18d5d2b 2444 tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]);
810260a8 2445 break;
2446 case INDEX_op_ld32s_i64:
b18d5d2b 2447 tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]);
810260a8 2448 break;
2449 case INDEX_op_ld_i64:
b18d5d2b 2450 tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]);
810260a8 2451 break;
2452 case INDEX_op_st8_i32:
2453 case INDEX_op_st8_i64:
b18d5d2b 2454 tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]);
810260a8 2455 break;
2456 case INDEX_op_st16_i32:
2457 case INDEX_op_st16_i64:
b18d5d2b 2458 tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]);
810260a8 2459 break;
2460 case INDEX_op_st_i32:
2461 case INDEX_op_st32_i64:
b18d5d2b 2462 tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]);
810260a8 2463 break;
2464 case INDEX_op_st_i64:
b18d5d2b 2465 tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]);
810260a8 2466 break;
2467
2468 case INDEX_op_add_i32:
ee924fa6
RH		 2469 a0 = args[0], a1 = args[1], a2 = args[2];
2470 if (const_args[2]) {
ee924fa6 2471 do_addi_32:
b18d5d2b 2472 tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2);
ee924fa6
RH		 2473 } else {
2474 tcg_out32(s, ADD | TAB(a0, a1, a2));
2475 }
810260a8 2476 break;
2477 case INDEX_op_sub_i32:
ee924fa6 2478 a0 = args[0], a1 = args[1], a2 = args[2];
148bdd23
RH		 2479 if (const_args[1]) {
2480 if (const_args[2]) {
2481 tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2);
2482 } else {
2483 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
2484 }
2485 } else if (const_args[2]) {
ee924fa6
RH		 2486 a2 = -a2;
2487 goto do_addi_32;
2488 } else {
2489 tcg_out32(s, SUBF | TAB(a0, a2, a1));
2490 }
810260a8 2491 break;
2492
2493 case INDEX_op_and_i32:
37251b98 2494 a0 = args[0], a1 = args[1], a2 = args[2];
a9249dff 2495 if (const_args[2]) {
37251b98 2496 tcg_out_andi32(s, a0, a1, a2);
a9249dff 2497 } else {
37251b98 2498 tcg_out32(s, AND | SAB(a1, a0, a2));
a9249dff
RH		 2499 }
2500 break;
2501 case INDEX_op_and_i64:
37251b98 2502 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 2503 if (const_args[2]) {
37251b98 2504 tcg_out_andi64(s, a0, a1, a2);
637af30c 2505 } else {
37251b98 2506 tcg_out32(s, AND | SAB(a1, a0, a2));
810260a8 2507 }
810260a8 2508 break;
fe6f943f 2509 case INDEX_op_or_i64:
810260a8 2510 case INDEX_op_or_i32:
dce74c57 2511 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 2512 if (const_args[2]) {
dce74c57
RH		 2513 tcg_out_ori32(s, a0, a1, a2);
2514 } else {
2515 tcg_out32(s, OR | SAB(a1, a0, a2));
810260a8 2516 }
810260a8 2517 break;
fe6f943f 2518 case INDEX_op_xor_i64:
810260a8 2519 case INDEX_op_xor_i32:
dce74c57 2520 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 2521 if (const_args[2]) {
dce74c57
RH		 2522 tcg_out_xori32(s, a0, a1, a2);
2523 } else {
2524 tcg_out32(s, XOR | SAB(a1, a0, a2));
810260a8 2525 }
810260a8 2526 break;
ce1010d6 2527 case INDEX_op_andc_i32:
37251b98
RH		 2528 a0 = args[0], a1 = args[1], a2 = args[2];
2529 if (const_args[2]) {
2530 tcg_out_andi32(s, a0, a1, ~a2);
2531 } else {
2532 tcg_out32(s, ANDC | SAB(a1, a0, a2));
2533 }
2534 break;
ce1010d6 2535 case INDEX_op_andc_i64:
37251b98
RH		 2536 a0 = args[0], a1 = args[1], a2 = args[2];
2537 if (const_args[2]) {
2538 tcg_out_andi64(s, a0, a1, ~a2);
2539 } else {
2540 tcg_out32(s, ANDC | SAB(a1, a0, a2));
2541 }
ce1010d6
RH		 2542 break;
2543 case INDEX_op_orc_i32:
37251b98
RH		 2544 if (const_args[2]) {
2545 tcg_out_ori32(s, args[0], args[1], ~args[2]);
2546 break;
2547 }
2548 /* FALLTHRU */
ce1010d6
RH		 2549 case INDEX_op_orc_i64:
2550 tcg_out32(s, ORC | SAB(args[1], args[0], args[2]));
2551 break;
2552 case INDEX_op_eqv_i32:
37251b98
RH		 2553 if (const_args[2]) {
2554 tcg_out_xori32(s, args[0], args[1], ~args[2]);
2555 break;
2556 }
2557 /* FALLTHRU */
ce1010d6
RH		 2558 case INDEX_op_eqv_i64:
2559 tcg_out32(s, EQV | SAB(args[1], args[0], args[2]));
2560 break;
2561 case INDEX_op_nand_i32:
2562 case INDEX_op_nand_i64:
2563 tcg_out32(s, NAND | SAB(args[1], args[0], args[2]));
2564 break;
2565 case INDEX_op_nor_i32:
2566 case INDEX_op_nor_i64:
2567 tcg_out32(s, NOR | SAB(args[1], args[0], args[2]));
2568 break;
810260a8 2569
d0b07481
RH		 2570 case INDEX_op_clz_i32:
2571 tcg_out_cntxz(s, TCG_TYPE_I32, CNTLZW, args[0], args[1],
2572 args[2], const_args[2]);
2573 break;
2574 case INDEX_op_ctz_i32:
2575 tcg_out_cntxz(s, TCG_TYPE_I32, CNTTZW, args[0], args[1],
2576 args[2], const_args[2]);
2577 break;
33e75fb9
RH		 2578 case INDEX_op_ctpop_i32:
2579 tcg_out32(s, CNTPOPW | SAB(args[1], args[0], 0));
2580 break;
d0b07481
RH		 2581
2582 case INDEX_op_clz_i64:
2583 tcg_out_cntxz(s, TCG_TYPE_I64, CNTLZD, args[0], args[1],
2584 args[2], const_args[2]);
2585 break;
2586 case INDEX_op_ctz_i64:
2587 tcg_out_cntxz(s, TCG_TYPE_I64, CNTTZD, args[0], args[1],
2588 args[2], const_args[2]);
2589 break;
33e75fb9
RH		 2590 case INDEX_op_ctpop_i64:
2591 tcg_out32(s, CNTPOPD | SAB(args[1], args[0], 0));
2592 break;
d0b07481 2593
810260a8 2594 case INDEX_op_mul_i32:
ef809300 2595 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 2596 if (const_args[2]) {
ef809300
RH		 2597 tcg_out32(s, MULLI | TAI(a0, a1, a2));
2598 } else {
2599 tcg_out32(s, MULLW | TAB(a0, a1, a2));
810260a8 2600 }
810260a8 2601 break;
2602
2603 case INDEX_op_div_i32:
541dd4ce 2604 tcg_out32(s, DIVW | TAB(args[0], args[1], args[2]));
810260a8 2605 break;
2606
2607 case INDEX_op_divu_i32:
541dd4ce 2608 tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2]));
810260a8 2609 break;
2610
810260a8 2611 case INDEX_op_shl_i32:
2612 if (const_args[2]) {
94248cfc
CF		 2613 /* Limit immediate shift count lest we create an illegal insn. */
2614 tcg_out_shli32(s, args[0], args[1], args[2] & 31);
9e555b73 2615 } else {
541dd4ce 2616 tcg_out32(s, SLW | SAB(args[1], args[0], args[2]));
9e555b73 2617 }
810260a8 2618 break;
2619 case INDEX_op_shr_i32:
2620 if (const_args[2]) {
94248cfc
CF		 2621 /* Limit immediate shift count lest we create an illegal insn. */
2622 tcg_out_shri32(s, args[0], args[1], args[2] & 31);
9e555b73 2623 } else {
541dd4ce 2624 tcg_out32(s, SRW | SAB(args[1], args[0], args[2]));
9e555b73 2625 }
810260a8 2626 break;
2627 case INDEX_op_sar_i32:
541dd4ce 2628 if (const_args[2]) {
94248cfc
CF		 2629 /* Limit immediate shift count lest we create an illegal insn. */
2630 tcg_out32(s, SRAWI | RS(args[1]) | RA(args[0]) | SH(args[2] & 31));
541dd4ce
RH		 2631 } else {
2632 tcg_out32(s, SRAW | SAB(args[1], args[0], args[2]));
2633 }
810260a8 2634 break;
313d91c7
RH		 2635 case INDEX_op_rotl_i32:
2636 if (const_args[2]) {
2637 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31);
2638 } else {
2639 tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2])
2640 | MB(0) | ME(31));
2641 }
2642 break;
2643 case INDEX_op_rotr_i32:
2644 if (const_args[2]) {
2645 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31);
2646 } else {
8327a470
RH		 2647 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32));
2648 tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0)
313d91c7
RH		 2649 | MB(0) | ME(31));
2650 }
2651 break;
810260a8 2652
2653 case INDEX_op_brcond_i32:
4c314da6 2654 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
bec16311 2655 arg_label(args[3]), TCG_TYPE_I32);
e924bbec 2656 break;
810260a8 2657 case INDEX_op_brcond_i64:
4c314da6 2658 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
bec16311 2659 arg_label(args[3]), TCG_TYPE_I64);
810260a8 2660 break;
abcf61c4
RH		 2661 case INDEX_op_brcond2_i32:
2662 tcg_out_brcond2(s, args, const_args);
2663 break;
810260a8 2664
2665 case INDEX_op_neg_i32:
810260a8 2666 case INDEX_op_neg_i64:
541dd4ce 2667 tcg_out32(s, NEG | RT(args[0]) | RA(args[1]));
810260a8 2668 break;
2669
157f2662 2670 case INDEX_op_not_i32:
2671 case INDEX_op_not_i64:
541dd4ce 2672 tcg_out32(s, NOR | SAB(args[1], args[0], args[1]));
157f2662 2673 break;
2674
810260a8 2675 case INDEX_op_add_i64:
ee924fa6
RH		 2676 a0 = args[0], a1 = args[1], a2 = args[2];
2677 if (const_args[2]) {
ee924fa6 2678 do_addi_64:
b18d5d2b 2679 tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2);
ee924fa6
RH		 2680 } else {
2681 tcg_out32(s, ADD | TAB(a0, a1, a2));
2682 }
810260a8 2683 break;
2684 case INDEX_op_sub_i64:
ee924fa6 2685 a0 = args[0], a1 = args[1], a2 = args[2];
148bdd23
RH		 2686 if (const_args[1]) {
2687 if (const_args[2]) {
2688 tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2);
2689 } else {
2690 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
2691 }
2692 } else if (const_args[2]) {
ee924fa6
RH		 2693 a2 = -a2;
2694 goto do_addi_64;
2695 } else {
2696 tcg_out32(s, SUBF | TAB(a0, a2, a1));
2697 }
810260a8 2698 break;
2699
2700 case INDEX_op_shl_i64:
541dd4ce 2701 if (const_args[2]) {
94248cfc
CF		 2702 /* Limit immediate shift count lest we create an illegal insn. */
2703 tcg_out_shli64(s, args[0], args[1], args[2] & 63);
541dd4ce
RH		 2704 } else {
2705 tcg_out32(s, SLD | SAB(args[1], args[0], args[2]));
2706 }
810260a8 2707 break;
2708 case INDEX_op_shr_i64:
541dd4ce 2709 if (const_args[2]) {
94248cfc
CF		 2710 /* Limit immediate shift count lest we create an illegal insn. */
2711 tcg_out_shri64(s, args[0], args[1], args[2] & 63);
541dd4ce
RH		 2712 } else {
2713 tcg_out32(s, SRD | SAB(args[1], args[0], args[2]));
2714 }
810260a8 2715 break;
2716 case INDEX_op_sar_i64:
fe6f943f 2717 if (const_args[2]) {
541dd4ce
RH		 2718 int sh = SH(args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1);
2719 tcg_out32(s, SRADI | RA(args[0]) | RS(args[1]) | sh);
2720 } else {
2721 tcg_out32(s, SRAD | SAB(args[1], args[0], args[2]));
fe6f943f 2722 }
810260a8 2723 break;
313d91c7
RH		 2724 case INDEX_op_rotl_i64:
2725 if (const_args[2]) {
2726 tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0);
2727 } else {
2728 tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0));
2729 }
2730 break;
2731 case INDEX_op_rotr_i64:
2732 if (const_args[2]) {
2733 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0);
2734 } else {
8327a470
RH		 2735 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64));
2736 tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0));
313d91c7
RH		 2737 }
2738 break;
810260a8 2739
2740 case INDEX_op_mul_i64:
ef809300
RH		 2741 a0 = args[0], a1 = args[1], a2 = args[2];
2742 if (const_args[2]) {
2743 tcg_out32(s, MULLI | TAI(a0, a1, a2));
2744 } else {
2745 tcg_out32(s, MULLD | TAB(a0, a1, a2));
2746 }
810260a8 2747 break;
2748 case INDEX_op_div_i64:
541dd4ce 2749 tcg_out32(s, DIVD | TAB(args[0], args[1], args[2]));
810260a8 2750 break;
2751 case INDEX_op_divu_i64:
541dd4ce 2752 tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2]));
810260a8 2753 break;
810260a8 2754
1768ec06 2755 case INDEX_op_qemu_ld_i32:
7f25c469
RH		 2756 tcg_out_qemu_ld(s, args, false);
2757 break;
1768ec06 2758 case INDEX_op_qemu_ld_i64:
7f25c469 2759 tcg_out_qemu_ld(s, args, true);
810260a8 2760 break;
1768ec06 2761 case INDEX_op_qemu_st_i32:
7f25c469
RH		 2762 tcg_out_qemu_st(s, args, false);
2763 break;
1768ec06 2764 case INDEX_op_qemu_st_i64:
7f25c469 2765 tcg_out_qemu_st(s, args, true);
810260a8 2766 break;
2767
e46b9681 2768 case INDEX_op_ext8s_i32:
2769 case INDEX_op_ext8s_i64:
2770 c = EXTSB;
2771 goto gen_ext;
2772 case INDEX_op_ext16s_i32:
2773 case INDEX_op_ext16s_i64:
2774 c = EXTSH;
2775 goto gen_ext;
4f2331e5 2776 case INDEX_op_ext_i32_i64:
e46b9681 2777 case INDEX_op_ext32s_i64:
2778 c = EXTSW;
2779 goto gen_ext;
2780 gen_ext:
541dd4ce 2781 tcg_out32(s, c | RS(args[1]) | RA(args[0]));
e46b9681 2782 break;
4f2331e5
AJ		 2783 case INDEX_op_extu_i32_i64:
2784 tcg_out_ext32u(s, args[0], args[1]);
2785 break;
e46b9681 2786
1cd62ae9 2787 case INDEX_op_setcond_i32:
541dd4ce
RH		 2788 tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
2789 const_args[2]);
1cd62ae9 2790 break;
2791 case INDEX_op_setcond_i64:
541dd4ce
RH		 2792 tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2],
2793 const_args[2]);
1cd62ae9 2794 break;
abcf61c4
RH		 2795 case INDEX_op_setcond2_i32:
2796 tcg_out_setcond2(s, args, const_args);
2797 break;
1cd62ae9 2798
5d221582
RH		 2799 case INDEX_op_bswap16_i32:
2800 case INDEX_op_bswap16_i64:
2801 a0 = args[0], a1 = args[1];
2802 /* a1 = abcd */
2803 if (a0 != a1) {
2804 /* a0 = (a1 r<< 24) & 0xff # 000c */
2805 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
2806 /* a0 = (a0 & ~0xff00) | (a1 r<< 8) & 0xff00 # 00dc */
2807 tcg_out_rlw(s, RLWIMI, a0, a1, 8, 16, 23);
2808 } else {
2809 /* r0 = (a1 r<< 8) & 0xff00 # 00d0 */
2810 tcg_out_rlw(s, RLWINM, TCG_REG_R0, a1, 8, 16, 23);
2811 /* a0 = (a1 r<< 24) & 0xff # 000c */
2812 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
2813 /* a0 = a0 | r0 # 00dc */
2814 tcg_out32(s, OR | SAB(TCG_REG_R0, a0, a0));
2815 }
2816 break;
2817
2818 case INDEX_op_bswap32_i32:
2819 case INDEX_op_bswap32_i64:
2820 /* Stolen from gcc's builtin_bswap32 */
2821 a1 = args[1];
2822 a0 = args[0] == a1 ? TCG_REG_R0 : args[0];
2823
2824 /* a1 = args[1] # abcd */
2825 /* a0 = rotate_left (a1, 8) # bcda */
2826 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
2827 /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */
2828 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
2829 /* a0 = (a0 & ~0x0000ff00) | ((a1 r<< 24) & 0x0000ff00) # dcba */
2830 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
2831
2832 if (a0 == TCG_REG_R0) {
de3d636d 2833 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
5d221582
RH		 2834 }
2835 break;
2836
68aebd45 2837 case INDEX_op_bswap64_i64:
8327a470 2838 a0 = args[0], a1 = args[1], a2 = TCG_REG_R0;
68aebd45 2839 if (a0 == a1) {
8327a470 2840 a0 = TCG_REG_R0;
68aebd45
RH		 2841 a2 = a1;
2842 }
2843
2844 /* a1 = # abcd efgh */
2845 /* a0 = rl32(a1, 8) # 0000 fghe */
2846 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
2847 /* a0 = dep(a0, rl32(a1, 24), 0xff000000) # 0000 hghe */
2848 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
2849 /* a0 = dep(a0, rl32(a1, 24), 0x0000ff00) # 0000 hgfe */
2850 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
2851
2852 /* a0 = rl64(a0, 32) # hgfe 0000 */
2853 /* a2 = rl64(a1, 32) # efgh abcd */
2854 tcg_out_rld(s, RLDICL, a0, a0, 32, 0);
2855 tcg_out_rld(s, RLDICL, a2, a1, 32, 0);
2856
2857 /* a0 = dep(a0, rl32(a2, 8), 0xffffffff) # hgfe bcda */
2858 tcg_out_rlw(s, RLWIMI, a0, a2, 8, 0, 31);
2859 /* a0 = dep(a0, rl32(a2, 24), 0xff000000) # hgfe dcda */
2860 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 0, 7);
2861 /* a0 = dep(a0, rl32(a2, 24), 0x0000ff00) # hgfe dcba */
2862 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 16, 23);
2863
2864 if (a0 == 0) {
de3d636d 2865 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
68aebd45
RH		 2866 }
2867 break;
2868
33de9ed2 2869 case INDEX_op_deposit_i32:
39dc85b9
RH		 2870 if (const_args[2]) {
2871 uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3];
2872 tcg_out_andi32(s, args[0], args[0], ~mask);
2873 } else {
2874 tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3],
2875 32 - args[3] - args[4], 31 - args[3]);
2876 }
33de9ed2
RH		 2877 break;
2878 case INDEX_op_deposit_i64:
39dc85b9
RH		 2879 if (const_args[2]) {
2880 uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3];
2881 tcg_out_andi64(s, args[0], args[0], ~mask);
2882 } else {
2883 tcg_out_rld(s, RLDIMI, args[0], args[2], args[3],
2884 64 - args[3] - args[4]);
2885 }
33de9ed2
RH		 2886 break;
2887
c05021c3
RH		 2888 case INDEX_op_extract_i32:
2889 tcg_out_rlw(s, RLWINM, args[0], args[1],
2890 32 - args[2], 32 - args[3], 31);
2891 break;
2892 case INDEX_op_extract_i64:
2893 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 64 - args[3]);
2894 break;
2895
027ffea9
RH		 2896 case INDEX_op_movcond_i32:
2897 tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2],
2898 args[3], args[4], const_args[2]);
2899 break;
2900 case INDEX_op_movcond_i64:
2901 tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2],
2902 args[3], args[4], const_args[2]);
2903 break;
2904
796f1a68 2905#if TCG_TARGET_REG_BITS == 64
6c858762 2906 case INDEX_op_add2_i64:
796f1a68
RH		 2907#else
2908 case INDEX_op_add2_i32:
2909#endif
6c858762
RH		 2910 /* Note that the CA bit is defined based on the word size of the
2911 environment. So in 64-bit mode it's always carry-out of bit 63.
2912 The fallback code using deposit works just as well for 32-bit. */
2913 a0 = args[0], a1 = args[1];
84247357 2914 if (a0 == args[3] || (!const_args[5] && a0 == args[5])) {
6c858762
RH		 2915 a0 = TCG_REG_R0;
2916 }
84247357
AB		 2917 if (const_args[4]) {
2918 tcg_out32(s, ADDIC | TAI(a0, args[2], args[4]));
6c858762 2919 } else {
84247357 2920 tcg_out32(s, ADDC | TAB(a0, args[2], args[4]));
6c858762
RH		 2921 }
2922 if (const_args[5]) {
84247357 2923 tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3]));
6c858762 2924 } else {
84247357 2925 tcg_out32(s, ADDE | TAB(a1, args[3], args[5]));
6c858762
RH		 2926 }
2927 if (a0 != args[0]) {
de3d636d 2928 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
6c858762
RH		 2929 }
2930 break;
2931
796f1a68 2932#if TCG_TARGET_REG_BITS == 64
6c858762 2933 case INDEX_op_sub2_i64:
796f1a68
RH		 2934#else
2935 case INDEX_op_sub2_i32:
2936#endif
6c858762 2937 a0 = args[0], a1 = args[1];
b31284ce 2938 if (a0 == args[5] || (!const_args[3] && a0 == args[3])) {
6c858762
RH		 2939 a0 = TCG_REG_R0;
2940 }
2941 if (const_args[2]) {
b31284ce 2942 tcg_out32(s, SUBFIC | TAI(a0, args[4], args[2]));
6c858762 2943 } else {
b31284ce 2944 tcg_out32(s, SUBFC | TAB(a0, args[4], args[2]));
6c858762 2945 }
b31284ce
RH		 2946 if (const_args[3]) {
2947 tcg_out32(s, (args[3] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5]));
6c858762 2948 } else {
b31284ce 2949 tcg_out32(s, SUBFE | TAB(a1, args[5], args[3]));
6c858762
RH		 2950 }
2951 if (a0 != args[0]) {
de3d636d 2952 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
6c858762
RH		 2953 }
2954 break;
2955
abcf61c4
RH		 2956 case INDEX_op_muluh_i32:
2957 tcg_out32(s, MULHWU | TAB(args[0], args[1], args[2]));
2958 break;
8fa391a0
RH		 2959 case INDEX_op_mulsh_i32:
2960 tcg_out32(s, MULHW | TAB(args[0], args[1], args[2]));
2961 break;
32f5717f
RH		 2962 case INDEX_op_muluh_i64:
2963 tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2]));
2964 break;
2965 case INDEX_op_mulsh_i64:
2966 tcg_out32(s, MULHD | TAB(args[0], args[1], args[2]));
6645c147
RH		 2967 break;
2968
7b4af5ee
PK		 2969 case INDEX_op_mb:
2970 tcg_out_mb(s, args[0]);
2971 break;
2972
96d0ee7f
RH		 2973 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
2974 case INDEX_op_mov_i64:
2975 case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
2976 case INDEX_op_movi_i64:
2977 case INDEX_op_call: /* Always emitted via tcg_out_call. */
810260a8 2978 default:
541dd4ce 2979 tcg_abort();
810260a8 2980 }
2981}
2982
4b06c216
RH		 2983int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
2984{
6ef14d7e
RH		 2985 switch (opc) {
2986 case INDEX_op_and_vec:
2987 case INDEX_op_or_vec:
2988 case INDEX_op_xor_vec:
2989 case INDEX_op_andc_vec:
2990 case INDEX_op_not_vec:
2991 return 1;
64ff1c6d
RH		 2992 case INDEX_op_orc_vec:
2993 return have_isa_2_07;
d6750811
RH		 2994 case INDEX_op_add_vec:
2995 case INDEX_op_sub_vec:
e2382972
RH		 2996 case INDEX_op_smax_vec:
2997 case INDEX_op_smin_vec:
2998 case INDEX_op_umax_vec:
2999 case INDEX_op_umin_vec:
64ff1c6d
RH		 3000 case INDEX_op_shlv_vec:
3001 case INDEX_op_shrv_vec:
3002 case INDEX_op_sarv_vec:
ab87a66f 3003 case INDEX_op_rotlv_vec:
64ff1c6d 3004 return vece <= MO_32 || have_isa_2_07;
e9d1a53a
RH		 3005 case INDEX_op_ssadd_vec:
3006 case INDEX_op_sssub_vec:
3007 case INDEX_op_usadd_vec:
3008 case INDEX_op_ussub_vec:
e2382972 3009 return vece <= MO_32;
6ef14d7e 3010 case INDEX_op_cmp_vec:
dabae097
RH		 3011 case INDEX_op_shli_vec:
3012 case INDEX_op_shri_vec:
3013 case INDEX_op_sari_vec:
ab87a66f 3014 case INDEX_op_rotli_vec:
64ff1c6d 3015 return vece <= MO_32 || have_isa_2_07 ? -1 : 0;
d7cd6a2f
RH		 3016 case INDEX_op_neg_vec:
3017 return vece >= MO_32 && have_isa_3_00;
64ff1c6d
RH		 3018 case INDEX_op_mul_vec:
3019 switch (vece) {
3020 case MO_8:
3021 case MO_16:
3022 return -1;
3023 case MO_32:
3024 return have_isa_2_07 ? 1 : -1;
3025 }
3026 return 0;
47c906ae
RH		 3027 case INDEX_op_bitsel_vec:
3028 return have_vsx;
ab87a66f
RH		 3029 case INDEX_op_rotrv_vec:
3030 return -1;
6ef14d7e
RH		 3031 default:
3032 return 0;
3033 }
4b06c216
RH		 3034}
3035
3036static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
3037 TCGReg dst, TCGReg src)
3038{
6ef14d7e 3039 tcg_debug_assert(dst >= TCG_REG_V0);
b7ce3cff
RH		 3040
3041 /* Splat from integer reg allowed via constraints for v3.00. */
3042 if (src < TCG_REG_V0) {
3043 tcg_debug_assert(have_isa_3_00);
3044 switch (vece) {
3045 case MO_64:
3046 tcg_out32(s, MTVSRDD | VRT(dst) | RA(src) | RB(src));
3047 return true;
3048 case MO_32:
3049 tcg_out32(s, MTVSRWS | VRT(dst) | RA(src));
3050 return true;
3051 default:
3052 /* Fail, so that we fall back on either dupm or mov+dup. */
3053 return false;
3054 }
3055 }
6ef14d7e
RH		 3056
3057 /*
3058 * Recall we use (or emulate) VSX integer loads, so the integer is
3059 * right justified within the left (zero-index) double-word.
3060 */
3061 switch (vece) {
3062 case MO_8:
3063 tcg_out32(s, VSPLTB | VRT(dst) | VRB(src) | (7 << 16));
3064 break;
3065 case MO_16:
3066 tcg_out32(s, VSPLTH | VRT(dst) | VRB(src) | (3 << 16));
3067 break;
3068 case MO_32:
3069 tcg_out32(s, VSPLTW | VRT(dst) | VRB(src) | (1 << 16));
3070 break;
3071 case MO_64:
47c906ae
RH		 3072 if (have_vsx) {
3073 tcg_out32(s, XXPERMDI | VRT(dst) | VRA(src) | VRB(src));
3074 break;
3075 }
6ef14d7e
RH		 3076 tcg_out_vsldoi(s, TCG_VEC_TMP1, src, src, 8);
3077 tcg_out_vsldoi(s, dst, TCG_VEC_TMP1, src, 8);
3078 break;
3079 default:
3080 g_assert_not_reached();
3081 }
3082 return true;
4b06c216
RH		 3083}
3084
3085static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
3086 TCGReg out, TCGReg base, intptr_t offset)
3087{
6ef14d7e
RH		 3088 int elt;
3089
3090 tcg_debug_assert(out >= TCG_REG_V0);
3091 switch (vece) {
3092 case MO_8:
6e11cde1
RH		 3093 if (have_isa_3_00) {
3094 tcg_out_mem_long(s, LXV, LVX, out, base, offset & -16);
3095 } else {
3096 tcg_out_mem_long(s, 0, LVEBX, out, base, offset);
3097 }
6ef14d7e
RH		 3098 elt = extract32(offset, 0, 4);
3099#ifndef HOST_WORDS_BIGENDIAN
3100 elt ^= 15;
3101#endif
3102 tcg_out32(s, VSPLTB | VRT(out) | VRB(out) | (elt << 16));
3103 break;
3104 case MO_16:
3105 tcg_debug_assert((offset & 1) == 0);
6e11cde1
RH		 3106 if (have_isa_3_00) {
3107 tcg_out_mem_long(s, LXV | 8, LVX, out, base, offset & -16);
3108 } else {
3109 tcg_out_mem_long(s, 0, LVEHX, out, base, offset);
3110 }
6ef14d7e
RH		 3111 elt = extract32(offset, 1, 3);
3112#ifndef HOST_WORDS_BIGENDIAN
3113 elt ^= 7;
3114#endif
3115 tcg_out32(s, VSPLTH | VRT(out) | VRB(out) | (elt << 16));
3116 break;
3117 case MO_32:
6e11cde1
RH		 3118 if (have_isa_3_00) {
3119 tcg_out_mem_long(s, 0, LXVWSX, out, base, offset);
3120 break;
3121 }
6ef14d7e
RH		 3122 tcg_debug_assert((offset & 3) == 0);
3123 tcg_out_mem_long(s, 0, LVEWX, out, base, offset);
3124 elt = extract32(offset, 2, 2);
3125#ifndef HOST_WORDS_BIGENDIAN
3126 elt ^= 3;
3127#endif
3128 tcg_out32(s, VSPLTW | VRT(out) | VRB(out) | (elt << 16));
3129 break;
3130 case MO_64:
47c906ae
RH		 3131 if (have_vsx) {
3132 tcg_out_mem_long(s, 0, LXVDSX, out, base, offset);
3133 break;
3134 }
6ef14d7e
RH		 3135 tcg_debug_assert((offset & 7) == 0);
3136 tcg_out_mem_long(s, 0, LVX, out, base, offset & -16);
3137 tcg_out_vsldoi(s, TCG_VEC_TMP1, out, out, 8);
3138 elt = extract32(offset, 3, 1);
3139#ifndef HOST_WORDS_BIGENDIAN
3140 elt = !elt;
3141#endif
3142 if (elt) {
3143 tcg_out_vsldoi(s, out, out, TCG_VEC_TMP1, 8);
3144 } else {
3145 tcg_out_vsldoi(s, out, TCG_VEC_TMP1, out, 8);
3146 }
3147 break;
3148 default:
3149 g_assert_not_reached();
3150 }
3151 return true;
4b06c216
RH		 3152}
3153
3154static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
3155 unsigned vecl, unsigned vece,
3156 const TCGArg *args, const int *const_args)
3157{
6ef14d7e 3158 static const uint32_t
64ff1c6d
RH		 3159 add_op[4] = { VADDUBM, VADDUHM, VADDUWM, VADDUDM },
3160 sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM },
d7cd6a2f 3161 neg_op[4] = { 0, 0, VNEGW, VNEGD },
64ff1c6d 3162 eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD },
d7cd6a2f 3163 ne_op[4] = { VCMPNEB, VCMPNEH, VCMPNEW, 0 },
64ff1c6d
RH		 3164 gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, VCMPGTSD },
3165 gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, VCMPGTUD },
e9d1a53a
RH		 3166 ssadd_op[4] = { VADDSBS, VADDSHS, VADDSWS, 0 },
3167 usadd_op[4] = { VADDUBS, VADDUHS, VADDUWS, 0 },
3168 sssub_op[4] = { VSUBSBS, VSUBSHS, VSUBSWS, 0 },
3169 ussub_op[4] = { VSUBUBS, VSUBUHS, VSUBUWS, 0 },
64ff1c6d
RH		 3170 umin_op[4] = { VMINUB, VMINUH, VMINUW, VMINUD },
3171 smin_op[4] = { VMINSB, VMINSH, VMINSW, VMINSD },
3172 umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, VMAXUD },
3173 smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, VMAXSD },
3174 shlv_op[4] = { VSLB, VSLH, VSLW, VSLD },
3175 shrv_op[4] = { VSRB, VSRH, VSRW, VSRD },
3176 sarv_op[4] = { VSRAB, VSRAH, VSRAW, VSRAD },
d9897efa
RH		 3177 mrgh_op[4] = { VMRGHB, VMRGHH, VMRGHW, 0 },
3178 mrgl_op[4] = { VMRGLB, VMRGLH, VMRGLW, 0 },
64ff1c6d
RH		 3179 muleu_op[4] = { VMULEUB, VMULEUH, VMULEUW, 0 },
3180 mulou_op[4] = { VMULOUB, VMULOUH, VMULOUW, 0 },
d9897efa 3181 pkum_op[4] = { VPKUHUM, VPKUWUM, 0, 0 },
64ff1c6d 3182 rotl_op[4] = { VRLB, VRLH, VRLW, VRLD };
6ef14d7e
RH		 3183
3184 TCGType type = vecl + TCG_TYPE_V64;
3185 TCGArg a0 = args[0], a1 = args[1], a2 = args[2];
3186 uint32_t insn;
3187
3188 switch (opc) {
3189 case INDEX_op_ld_vec:
3190 tcg_out_ld(s, type, a0, a1, a2);
3191 return;
3192 case INDEX_op_st_vec:
3193 tcg_out_st(s, type, a0, a1, a2);
3194 return;
3195 case INDEX_op_dupm_vec:
3196 tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
3197 return;
3198
d6750811
RH		 3199 case INDEX_op_add_vec:
3200 insn = add_op[vece];
3201 break;
3202 case INDEX_op_sub_vec:
3203 insn = sub_op[vece];
3204 break;
d7cd6a2f
RH		 3205 case INDEX_op_neg_vec:
3206 insn = neg_op[vece];
3207 a2 = a1;
3208 a1 = 0;
3209 break;
64ff1c6d
RH		 3210 case INDEX_op_mul_vec:
3211 tcg_debug_assert(vece == MO_32 && have_isa_2_07);
3212 insn = VMULUWM;
3213 break;
e9d1a53a
RH		 3214 case INDEX_op_ssadd_vec:
3215 insn = ssadd_op[vece];
3216 break;
3217 case INDEX_op_sssub_vec:
3218 insn = sssub_op[vece];
3219 break;
3220 case INDEX_op_usadd_vec:
3221 insn = usadd_op[vece];
3222 break;
3223 case INDEX_op_ussub_vec:
3224 insn = ussub_op[vece];
3225 break;
e2382972
RH		 3226 case INDEX_op_smin_vec:
3227 insn = smin_op[vece];
3228 break;
3229 case INDEX_op_umin_vec:
3230 insn = umin_op[vece];
3231 break;
3232 case INDEX_op_smax_vec:
3233 insn = smax_op[vece];
3234 break;
3235 case INDEX_op_umax_vec:
3236 insn = umax_op[vece];
3237 break;
dabae097
RH		 3238 case INDEX_op_shlv_vec:
3239 insn = shlv_op[vece];
3240 break;
3241 case INDEX_op_shrv_vec:
3242 insn = shrv_op[vece];
3243 break;
3244 case INDEX_op_sarv_vec:
3245 insn = sarv_op[vece];
3246 break;
6ef14d7e
RH		 3247 case INDEX_op_and_vec:
3248 insn = VAND;
3249 break;
3250 case INDEX_op_or_vec:
3251 insn = VOR;
3252 break;
3253 case INDEX_op_xor_vec:
3254 insn = VXOR;
3255 break;
3256 case INDEX_op_andc_vec:
3257 insn = VANDC;
3258 break;
3259 case INDEX_op_not_vec:
3260 insn = VNOR;
3261 a2 = a1;
3262 break;
64ff1c6d
RH		 3263 case INDEX_op_orc_vec:
3264 insn = VORC;
3265 break;
6ef14d7e
RH		 3266
3267 case INDEX_op_cmp_vec:
3268 switch (args[3]) {
3269 case TCG_COND_EQ:
3270 insn = eq_op[vece];
3271 break;
d7cd6a2f
RH		 3272 case TCG_COND_NE:
3273 insn = ne_op[vece];
3274 break;
6ef14d7e
RH		 3275 case TCG_COND_GT:
3276 insn = gts_op[vece];
3277 break;
3278 case TCG_COND_GTU:
3279 insn = gtu_op[vece];
3280 break;
3281 default:
3282 g_assert_not_reached();
3283 }
3284 break;
3285
47c906ae
RH		 3286 case INDEX_op_bitsel_vec:
3287 tcg_out32(s, XXSEL | VRT(a0) | VRC(a1) | VRB(a2) | VRA(args[3]));
3288 return;
3289
597cf978
RH		 3290 case INDEX_op_dup2_vec:
3291 assert(TCG_TARGET_REG_BITS == 32);
3292 /* With inputs a1 = xLxx, a2 = xHxx */
3293 tcg_out32(s, VMRGHW | VRT(a0) | VRA(a2) | VRB(a1)); /* a0 = xxHL */
3294 tcg_out_vsldoi(s, TCG_VEC_TMP1, a0, a0, 8); /* tmp = HLxx */
3295 tcg_out_vsldoi(s, a0, a0, TCG_VEC_TMP1, 8); /* a0 = HLHL */
3296 return;
3297
d9897efa
RH		 3298 case INDEX_op_ppc_mrgh_vec:
3299 insn = mrgh_op[vece];
3300 break;
3301 case INDEX_op_ppc_mrgl_vec:
3302 insn = mrgl_op[vece];
3303 break;
3304 case INDEX_op_ppc_muleu_vec:
3305 insn = muleu_op[vece];
3306 break;
3307 case INDEX_op_ppc_mulou_vec:
3308 insn = mulou_op[vece];
3309 break;
3310 case INDEX_op_ppc_pkum_vec:
3311 insn = pkum_op[vece];
3312 break;
ab87a66f 3313 case INDEX_op_rotlv_vec:
d9897efa
RH		 3314 insn = rotl_op[vece];
3315 break;
3316 case INDEX_op_ppc_msum_vec:
3317 tcg_debug_assert(vece == MO_16);
3318 tcg_out32(s, VMSUMUHM | VRT(a0) | VRA(a1) | VRB(a2) | VRC(args[3]));
3319 return;
3320
6ef14d7e
RH		 3321 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
3322 case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */
3323 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
3324 default:
3325 g_assert_not_reached();
3326 }
3327
3328 tcg_debug_assert(insn != 0);
3329 tcg_out32(s, insn | VRT(a0) | VRA(a1) | VRB(a2));
3330}
3331
dabae097
RH		 3332static void expand_vec_shi(TCGType type, unsigned vece, TCGv_vec v0,
3333 TCGv_vec v1, TCGArg imm, TCGOpcode opci)
3334{
3335 TCGv_vec t1 = tcg_temp_new_vec(type);
3336
3337 /* Splat w/bytes for xxspltib. */
3338 tcg_gen_dupi_vec(MO_8, t1, imm & ((8 << vece) - 1));
3339 vec_gen_3(opci, type, vece, tcgv_vec_arg(v0),
3340 tcgv_vec_arg(v1), tcgv_vec_arg(t1));
3341 tcg_temp_free_vec(t1);
3342}
3343
6ef14d7e
RH		 3344static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0,
3345 TCGv_vec v1, TCGv_vec v2, TCGCond cond)
3346{
3347 bool need_swap = false, need_inv = false;
3348
64ff1c6d 3349 tcg_debug_assert(vece <= MO_32 || have_isa_2_07);
6ef14d7e
RH		 3350
3351 switch (cond) {
3352 case TCG_COND_EQ:
3353 case TCG_COND_GT:
3354 case TCG_COND_GTU:
3355 break;
3356 case TCG_COND_NE:
d7cd6a2f
RH		 3357 if (have_isa_3_00 && vece <= MO_32) {
3358 break;
3359 }
3360 /* fall through */
6ef14d7e
RH		 3361 case TCG_COND_LE:
3362 case TCG_COND_LEU:
3363 need_inv = true;
3364 break;
3365 case TCG_COND_LT:
3366 case TCG_COND_LTU:
3367 need_swap = true;
3368 break;
3369 case TCG_COND_GE:
3370 case TCG_COND_GEU:
3371 need_swap = need_inv = true;
3372 break;
3373 default:
3374 g_assert_not_reached();
3375 }
3376
3377 if (need_inv) {
3378 cond = tcg_invert_cond(cond);
3379 }
3380 if (need_swap) {
3381 TCGv_vec t1;
3382 t1 = v1, v1 = v2, v2 = t1;
3383 cond = tcg_swap_cond(cond);
3384 }
3385
3386 vec_gen_4(INDEX_op_cmp_vec, type, vece, tcgv_vec_arg(v0),
3387 tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond);
3388
3389 if (need_inv) {
3390 tcg_gen_not_vec(vece, v0, v0);
3391 }
4b06c216
RH		 3392}
3393
d9897efa
RH		 3394static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0,
3395 TCGv_vec v1, TCGv_vec v2)
3396{
3397 TCGv_vec t1 = tcg_temp_new_vec(type);
3398 TCGv_vec t2 = tcg_temp_new_vec(type);
3399 TCGv_vec t3, t4;
3400
3401 switch (vece) {
3402 case MO_8:
3403 case MO_16:
3404 vec_gen_3(INDEX_op_ppc_muleu_vec, type, vece, tcgv_vec_arg(t1),
3405 tcgv_vec_arg(v1), tcgv_vec_arg(v2));
3406 vec_gen_3(INDEX_op_ppc_mulou_vec, type, vece, tcgv_vec_arg(t2),
3407 tcgv_vec_arg(v1), tcgv_vec_arg(v2));
3408 vec_gen_3(INDEX_op_ppc_mrgh_vec, type, vece + 1, tcgv_vec_arg(v0),
3409 tcgv_vec_arg(t1), tcgv_vec_arg(t2));
3410 vec_gen_3(INDEX_op_ppc_mrgl_vec, type, vece + 1, tcgv_vec_arg(t1),
3411 tcgv_vec_arg(t1), tcgv_vec_arg(t2));
3412 vec_gen_3(INDEX_op_ppc_pkum_vec, type, vece, tcgv_vec_arg(v0),
3413 tcgv_vec_arg(v0), tcgv_vec_arg(t1));
3414 break;
3415
3416 case MO_32:
64ff1c6d 3417 tcg_debug_assert(!have_isa_2_07);
d9897efa
RH		 3418 t3 = tcg_temp_new_vec(type);
3419 t4 = tcg_temp_new_vec(type);
3420 tcg_gen_dupi_vec(MO_8, t4, -16);
ab87a66f 3421 vec_gen_3(INDEX_op_rotlv_vec, type, MO_32, tcgv_vec_arg(t1),
d9897efa
RH		 3422 tcgv_vec_arg(v2), tcgv_vec_arg(t4));
3423 vec_gen_3(INDEX_op_ppc_mulou_vec, type, MO_16, tcgv_vec_arg(t2),
3424 tcgv_vec_arg(v1), tcgv_vec_arg(v2));
3425 tcg_gen_dupi_vec(MO_8, t3, 0);
3426 vec_gen_4(INDEX_op_ppc_msum_vec, type, MO_16, tcgv_vec_arg(t3),
3427 tcgv_vec_arg(v1), tcgv_vec_arg(t1), tcgv_vec_arg(t3));
3428 vec_gen_3(INDEX_op_shlv_vec, type, MO_32, tcgv_vec_arg(t3),
3429 tcgv_vec_arg(t3), tcgv_vec_arg(t4));
3430 tcg_gen_add_vec(MO_32, v0, t2, t3);
3431 tcg_temp_free_vec(t3);
3432 tcg_temp_free_vec(t4);
3433 break;
3434
3435 default:
3436 g_assert_not_reached();
3437 }
3438 tcg_temp_free_vec(t1);
3439 tcg_temp_free_vec(t2);
3440}
3441
4b06c216
RH		 3442void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
3443 TCGArg a0, ...)
3444{
6ef14d7e 3445 va_list va;
ab87a66f 3446 TCGv_vec v0, v1, v2, t0;
dabae097 3447 TCGArg a2;
6ef14d7e
RH		 3448
3449 va_start(va, a0);
3450 v0 = temp_tcgv_vec(arg_temp(a0));
3451 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
dabae097 3452 a2 = va_arg(va, TCGArg);
6ef14d7e
RH		 3453
3454 switch (opc) {
dabae097
RH		 3455 case INDEX_op_shli_vec:
3456 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shlv_vec);
3457 break;
3458 case INDEX_op_shri_vec:
3459 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shrv_vec);
3460 break;
3461 case INDEX_op_sari_vec:
3462 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_sarv_vec);
3463 break;
ab87a66f
RH		 3464 case INDEX_op_rotli_vec:
3465 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_rotlv_vec);
3466 break;
6ef14d7e 3467 case INDEX_op_cmp_vec:
dabae097 3468 v2 = temp_tcgv_vec(arg_temp(a2));
6ef14d7e
RH		 3469 expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg));
3470 break;
d9897efa
RH		 3471 case INDEX_op_mul_vec:
3472 v2 = temp_tcgv_vec(arg_temp(a2));
3473 expand_vec_mul(type, vece, v0, v1, v2);
3474 break;
ab87a66f
RH		 3475 case INDEX_op_rotlv_vec:
3476 v2 = temp_tcgv_vec(arg_temp(a2));
3477 t0 = tcg_temp_new_vec(type);
3478 tcg_gen_neg_vec(vece, t0, v2);
3479 tcg_gen_rotlv_vec(vece, v0, v1, t0);
3480 tcg_temp_free_vec(t0);
3481 break;
6ef14d7e
RH		 3482 default:
3483 g_assert_not_reached();
3484 }
3485 va_end(va);
4b06c216
RH		 3486}
3487
6cb3658a
RH		 3488static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
3489{
3490 static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
3491 static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
3492 static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
3493 static const TCGTargetOpDef S_S = { .args_ct_str = { "S", "S" } };
3494 static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } };
3495 static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
3496 static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
3497 static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } };
3498 static const TCGTargetOpDef S_S_S = { .args_ct_str = { "S", "S", "S" } };
3499 static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
3500 static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
3501 static const TCGTargetOpDef r_r_rT = { .args_ct_str = { "r", "r", "rT" } };
3502 static const TCGTargetOpDef r_r_rU = { .args_ct_str = { "r", "r", "rU" } };
3503 static const TCGTargetOpDef r_rI_ri
3504 = { .args_ct_str = { "r", "rI", "ri" } };
3505 static const TCGTargetOpDef r_rI_rT
3506 = { .args_ct_str = { "r", "rI", "rT" } };
3507 static const TCGTargetOpDef r_r_rZW
3508 = { .args_ct_str = { "r", "r", "rZW" } };
3509 static const TCGTargetOpDef L_L_L_L
3510 = { .args_ct_str = { "L", "L", "L", "L" } };
3511 static const TCGTargetOpDef S_S_S_S
3512 = { .args_ct_str = { "S", "S", "S", "S" } };
3513 static const TCGTargetOpDef movc
3514 = { .args_ct_str = { "r", "r", "ri", "rZ", "rZ" } };
3515 static const TCGTargetOpDef dep
3516 = { .args_ct_str = { "r", "0", "rZ" } };
3517 static const TCGTargetOpDef br2
3518 = { .args_ct_str = { "r", "r", "ri", "ri" } };
3519 static const TCGTargetOpDef setc2
3520 = { .args_ct_str = { "r", "r", "r", "ri", "ri" } };
3521 static const TCGTargetOpDef add2
3522 = { .args_ct_str = { "r", "r", "r", "r", "rI", "rZM" } };
3523 static const TCGTargetOpDef sub2
3524 = { .args_ct_str = { "r", "r", "rI", "rZM", "r", "r" } };
6ef14d7e 3525 static const TCGTargetOpDef v_r = { .args_ct_str = { "v", "r" } };
b7ce3cff 3526 static const TCGTargetOpDef v_vr = { .args_ct_str = { "v", "vr" } };
6ef14d7e
RH		 3527 static const TCGTargetOpDef v_v = { .args_ct_str = { "v", "v" } };
3528 static const TCGTargetOpDef v_v_v = { .args_ct_str = { "v", "v", "v" } };
d9897efa
RH		 3529 static const TCGTargetOpDef v_v_v_v
3530 = { .args_ct_str = { "v", "v", "v", "v" } };
6cb3658a
RH		 3531
3532 switch (op) {
3533 case INDEX_op_goto_ptr:
3534 return &r;
796f1a68 3535
6cb3658a
RH		 3536 case INDEX_op_ld8u_i32:
3537 case INDEX_op_ld8s_i32:
3538 case INDEX_op_ld16u_i32:
3539 case INDEX_op_ld16s_i32:
3540 case INDEX_op_ld_i32:
3541 case INDEX_op_st8_i32:
3542 case INDEX_op_st16_i32:
3543 case INDEX_op_st_i32:
3544 case INDEX_op_ctpop_i32:
3545 case INDEX_op_neg_i32:
3546 case INDEX_op_not_i32:
3547 case INDEX_op_ext8s_i32:
3548 case INDEX_op_ext16s_i32:
3549 case INDEX_op_bswap16_i32:
3550 case INDEX_op_bswap32_i32:
3551 case INDEX_op_extract_i32:
3552 case INDEX_op_ld8u_i64:
3553 case INDEX_op_ld8s_i64:
3554 case INDEX_op_ld16u_i64:
3555 case INDEX_op_ld16s_i64:
3556 case INDEX_op_ld32u_i64:
3557 case INDEX_op_ld32s_i64:
3558 case INDEX_op_ld_i64:
3559 case INDEX_op_st8_i64:
3560 case INDEX_op_st16_i64:
3561 case INDEX_op_st32_i64:
3562 case INDEX_op_st_i64:
3563 case INDEX_op_ctpop_i64:
3564 case INDEX_op_neg_i64:
3565 case INDEX_op_not_i64:
3566 case INDEX_op_ext8s_i64:
3567 case INDEX_op_ext16s_i64:
3568 case INDEX_op_ext32s_i64:
3569 case INDEX_op_ext_i32_i64:
3570 case INDEX_op_extu_i32_i64:
3571 case INDEX_op_bswap16_i64:
3572 case INDEX_op_bswap32_i64:
3573 case INDEX_op_bswap64_i64:
3574 case INDEX_op_extract_i64:
3575 return &r_r;
abcf61c4 3576
6cb3658a
RH		 3577 case INDEX_op_add_i32:
3578 case INDEX_op_and_i32:
3579 case INDEX_op_or_i32:
3580 case INDEX_op_xor_i32:
3581 case INDEX_op_andc_i32:
3582 case INDEX_op_orc_i32:
3583 case INDEX_op_eqv_i32:
3584 case INDEX_op_shl_i32:
3585 case INDEX_op_shr_i32:
3586 case INDEX_op_sar_i32:
3587 case INDEX_op_rotl_i32:
3588 case INDEX_op_rotr_i32:
3589 case INDEX_op_setcond_i32:
3590 case INDEX_op_and_i64:
3591 case INDEX_op_andc_i64:
3592 case INDEX_op_shl_i64:
3593 case INDEX_op_shr_i64:
3594 case INDEX_op_sar_i64:
3595 case INDEX_op_rotl_i64:
3596 case INDEX_op_rotr_i64:
3597 case INDEX_op_setcond_i64:
3598 return &r_r_ri;
3599 case INDEX_op_mul_i32:
3600 case INDEX_op_mul_i64:
3601 return &r_r_rI;
3602 case INDEX_op_div_i32:
3603 case INDEX_op_divu_i32:
3604 case INDEX_op_nand_i32:
3605 case INDEX_op_nor_i32:
3606 case INDEX_op_muluh_i32:
3607 case INDEX_op_mulsh_i32:
3608 case INDEX_op_orc_i64:
3609 case INDEX_op_eqv_i64:
3610 case INDEX_op_nand_i64:
3611 case INDEX_op_nor_i64:
3612 case INDEX_op_div_i64:
3613 case INDEX_op_divu_i64:
3614 case INDEX_op_mulsh_i64:
3615 case INDEX_op_muluh_i64:
3616 return &r_r_r;
3617 case INDEX_op_sub_i32:
3618 return &r_rI_ri;
3619 case INDEX_op_add_i64:
3620 return &r_r_rT;
3621 case INDEX_op_or_i64:
3622 case INDEX_op_xor_i64:
3623 return &r_r_rU;
3624 case INDEX_op_sub_i64:
3625 return &r_rI_rT;
3626 case INDEX_op_clz_i32:
3627 case INDEX_op_ctz_i32:
3628 case INDEX_op_clz_i64:
3629 case INDEX_op_ctz_i64:
3630 return &r_r_rZW;
796f1a68 3631
6cb3658a
RH		 3632 case INDEX_op_brcond_i32:
3633 case INDEX_op_brcond_i64:
3634 return &r_ri;
6c858762 3635
6cb3658a
RH		 3636 case INDEX_op_movcond_i32:
3637 case INDEX_op_movcond_i64:
3638 return &movc;
3639 case INDEX_op_deposit_i32:
3640 case INDEX_op_deposit_i64:
3641 return &dep;
3642 case INDEX_op_brcond2_i32:
3643 return &br2;
3644 case INDEX_op_setcond2_i32:
3645 return &setc2;
3646 case INDEX_op_add2_i64:
3647 case INDEX_op_add2_i32:
3648 return &add2;
3649 case INDEX_op_sub2_i64:
3650 case INDEX_op_sub2_i32:
3651 return &sub2;
810260a8 3652
6cb3658a
RH		 3653 case INDEX_op_qemu_ld_i32:
3654 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
3655 ? &r_L : &r_L_L);
3656 case INDEX_op_qemu_st_i32:
3657 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
3658 ? &S_S : &S_S_S);
3659 case INDEX_op_qemu_ld_i64:
3660 return (TCG_TARGET_REG_BITS == 64 ? &r_L
3661 : TARGET_LONG_BITS == 32 ? &L_L_L : &L_L_L_L);
3662 case INDEX_op_qemu_st_i64:
3663 return (TCG_TARGET_REG_BITS == 64 ? &S_S
3664 : TARGET_LONG_BITS == 32 ? &S_S_S : &S_S_S_S);
f69d277e 3665
d6750811
RH		 3666 case INDEX_op_add_vec:
3667 case INDEX_op_sub_vec:
d9897efa 3668 case INDEX_op_mul_vec:
6ef14d7e
RH		 3669 case INDEX_op_and_vec:
3670 case INDEX_op_or_vec:
3671 case INDEX_op_xor_vec:
3672 case INDEX_op_andc_vec:
3673 case INDEX_op_orc_vec:
3674 case INDEX_op_cmp_vec:
e9d1a53a
RH		 3675 case INDEX_op_ssadd_vec:
3676 case INDEX_op_sssub_vec:
3677 case INDEX_op_usadd_vec:
3678 case INDEX_op_ussub_vec:
e2382972
RH		 3679 case INDEX_op_smax_vec:
3680 case INDEX_op_smin_vec:
3681 case INDEX_op_umax_vec:
3682 case INDEX_op_umin_vec:
dabae097
RH		 3683 case INDEX_op_shlv_vec:
3684 case INDEX_op_shrv_vec:
3685 case INDEX_op_sarv_vec:
ab87a66f
RH		 3686 case INDEX_op_rotlv_vec:
3687 case INDEX_op_rotrv_vec:
d9897efa
RH		 3688 case INDEX_op_ppc_mrgh_vec:
3689 case INDEX_op_ppc_mrgl_vec:
3690 case INDEX_op_ppc_muleu_vec:
3691 case INDEX_op_ppc_mulou_vec:
3692 case INDEX_op_ppc_pkum_vec:
597cf978 3693 case INDEX_op_dup2_vec:
6ef14d7e
RH		 3694 return &v_v_v;
3695 case INDEX_op_not_vec:
d7cd6a2f 3696 case INDEX_op_neg_vec:
6ef14d7e 3697 return &v_v;
b7ce3cff
RH		 3698 case INDEX_op_dup_vec:
3699 return have_isa_3_00 ? &v_vr : &v_v;
6ef14d7e
RH		 3700 case INDEX_op_ld_vec:
3701 case INDEX_op_st_vec:
3702 case INDEX_op_dupm_vec:
3703 return &v_r;
47c906ae 3704 case INDEX_op_bitsel_vec:
d9897efa
RH		 3705 case INDEX_op_ppc_msum_vec:
3706 return &v_v_v_v;
6ef14d7e 3707
6cb3658a
RH		 3708 default:
3709 return NULL;
f69d277e 3710 }
f69d277e
RH		 3711}
3712
541dd4ce 3713static void tcg_target_init(TCGContext *s)
810260a8 3714{
cd629de1 3715 unsigned long hwcap = qemu_getauxval(AT_HWCAP);
d0b07481
RH		 3716 unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2);
3717
7d9dae0a 3718 have_isa = tcg_isa_base;
1e6e9aca 3719 if (hwcap & PPC_FEATURE_ARCH_2_06) {
7d9dae0a 3720 have_isa = tcg_isa_2_06;
1e6e9aca 3721 }
64ff1c6d
RH		 3722#ifdef PPC_FEATURE2_ARCH_2_07
3723 if (hwcap2 & PPC_FEATURE2_ARCH_2_07) {
3724 have_isa = tcg_isa_2_07;
3725 }
3726#endif
d0b07481
RH		 3727#ifdef PPC_FEATURE2_ARCH_3_00
3728 if (hwcap2 & PPC_FEATURE2_ARCH_3_00) {
7d9dae0a 3729 have_isa = tcg_isa_3_00;
d0b07481
RH		 3730 }
3731#endif
1e6e9aca 3732
63922f46
RH		 3733#ifdef PPC_FEATURE2_HAS_ISEL
3734 /* Prefer explicit instruction from the kernel. */
3735 have_isel = (hwcap2 & PPC_FEATURE2_HAS_ISEL) != 0;
3736#else
3737 /* Fall back to knowing Power7 (2.06) has ISEL. */
3738 have_isel = have_isa_2_06;
3739#endif
3740
68f340d4
RH		 3741 if (hwcap & PPC_FEATURE_HAS_ALTIVEC) {
3742 have_altivec = true;
47c906ae
RH		 3743 /* We only care about the portion of VSX that overlaps Altivec. */
3744 if (hwcap & PPC_FEATURE_HAS_VSX) {
3745 have_vsx = true;
3746 }
68f340d4
RH		 3747 }
3748
f46934df
RH		 3749 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
3750 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
4b06c216
RH		 3751 if (have_altivec) {
3752 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
3753 tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull;
3754 }
f46934df
RH		 3755
3756 tcg_target_call_clobber_regs = 0;
3757 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
3758 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2);
3759 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3);
3760 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4);
3761 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5);
3762 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6);
3763 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R7);
3764 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8);
3765 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9);
3766 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10);
3767 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);
3768 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12);
810260a8 3769
42281ec6
RH		 3770 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
3771 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
3772 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2);
3773 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3);
3774 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4);
3775 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5);
3776 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6);
3777 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7);
3778 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V8);
3779 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V9);
3780 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V10);
3781 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V11);
3782 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V12);
3783 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V13);
3784 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V14);
3785 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V15);
3786 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16);
3787 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17);
3788 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18);
3789 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19);
3790
ccb1bb66 3791 s->reserved_regs = 0;
5e1702b0
RH		 3792 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */
3793 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */
dfca1778
RH		 3794#if defined(_CALL_SYSV)
3795 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* toc pointer */
5d7ff5bb 3796#endif
dfca1778 3797#if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS == 64
5e1702b0 3798 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
dfca1778
RH		 3799#endif
3800 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */
42281ec6
RH		 3801 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP1);
3802 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP2);
5964fca8
RH		 3803 if (USE_REG_TB) {
3804 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tb->tc_ptr */
a84ac4cb 3805 }
810260a8 3806}
fa94c3be 3807
ffcfbece 3808#ifdef __ELF__
fa94c3be
RH		 3809typedef struct {
3810 DebugFrameCIE cie;
3811 DebugFrameFDEHeader fde;
3812 uint8_t fde_def_cfa[4];
3813 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2 + 3];
3814} DebugFrame;
3815
3816/* We're expecting a 2 byte uleb128 encoded value. */
3817QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
3818
ffcfbece
RH		 3819#if TCG_TARGET_REG_BITS == 64
3820# define ELF_HOST_MACHINE EM_PPC64
3821#else
3822# define ELF_HOST_MACHINE EM_PPC
3823#endif
fa94c3be
RH		 3824
3825static DebugFrame debug_frame = {
3826 .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
3827 .cie.id = -1,
3828 .cie.version = 1,
3829 .cie.code_align = 1,
802ca56e 3830 .cie.data_align = (-SZR & 0x7f), /* sleb128 -SZR */
fa94c3be
RH		 3831 .cie.return_column = 65,
3832
3833 /* Total FDE size does not include the "len" member. */
3834 .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset),
3835
3836 .fde_def_cfa = {
802ca56e 3837 12, TCG_REG_R1, /* DW_CFA_def_cfa r1, ... */
fa94c3be
RH		 3838 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
3839 (FRAME_SIZE >> 7)
3840 },
3841 .fde_reg_ofs = {
802ca56e
RH		 3842 /* DW_CFA_offset_extended_sf, lr, LR_OFFSET */
3843 0x11, 65, (LR_OFFSET / -SZR) & 0x7f,
fa94c3be
RH		 3844 }
3845};
3846
3847void tcg_register_jit(void *buf, size_t buf_size)
3848{
3849 uint8_t *p = &debug_frame.fde_reg_ofs[3];
3850 int i;
3851
3852 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i, p += 2) {
3853 p[0] = 0x80 + tcg_target_callee_save_regs[i];
802ca56e 3854 p[1] = (FRAME_SIZE - (REG_SAVE_BOT + i * SZR)) / SZR;
fa94c3be
RH		 3855 }
3856
802ca56e 3857 debug_frame.fde.func_start = (uintptr_t)buf;
fa94c3be
RH		 3858 debug_frame.fde.func_len = buf_size;
3859
3860 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
3861}
ffcfbece 3862#endif /* __ELF__ */
224f9fd4 3863
224f9fd4
RH		 3864void flush_icache_range(uintptr_t start, uintptr_t stop)
3865{
3866 uintptr_t p, start1, stop1;
b255b2c8
EC		 3867 size_t dsize = qemu_dcache_linesize;
3868 size_t isize = qemu_icache_linesize;
224f9fd4
RH		 3869
3870 start1 = start & ~(dsize - 1);
3871 stop1 = (stop + dsize - 1) & ~(dsize - 1);
3872 for (p = start1; p < stop1; p += dsize) {
3873 asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");
3874 }
3875 asm volatile ("sync" : : : "memory");
3876
3877 start &= start & ~(isize - 1);
3878 stop1 = (stop + isize - 1) & ~(isize - 1);
3879 for (p = start1; p < stop1; p += isize) {
3880 asm volatile ("icbi 0,%0" : : "r"(p) : "memory");
3881 }
3882 asm volatile ("sync" : : : "memory");
3883 asm volatile ("isync" : : : "memory");
3884}
QEMU mirror