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c896fe29 FB |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | #include "tcg.h" | |
25 | ||
c896fe29 FB |
26 | int gen_new_label(void); |
27 | ||
a7812ae4 | 28 | static inline void tcg_gen_op1_i32(int opc, TCGv_i32 arg1) |
c896fe29 FB |
29 | { |
30 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
31 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
32 | } | |
33 | ||
34 | static inline void tcg_gen_op1_i64(int opc, TCGv_i64 arg1) | |
35 | { | |
36 | *gen_opc_ptr++ = opc; | |
37 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
c896fe29 FB |
38 | } |
39 | ||
ac56dd48 | 40 | static inline void tcg_gen_op1i(int opc, TCGArg arg1) |
c896fe29 FB |
41 | { |
42 | *gen_opc_ptr++ = opc; | |
43 | *gen_opparam_ptr++ = arg1; | |
c896fe29 FB |
44 | } |
45 | ||
a7812ae4 PB |
46 | static inline void tcg_gen_op2_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2) |
47 | { | |
48 | *gen_opc_ptr++ = opc; | |
49 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
50 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
51 | } | |
52 | ||
53 | static inline void tcg_gen_op2_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2) | |
54 | { | |
55 | *gen_opc_ptr++ = opc; | |
56 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
57 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
58 | } | |
59 | ||
60 | static inline void tcg_gen_op2i_i32(int opc, TCGv_i32 arg1, TCGArg arg2) | |
c896fe29 FB |
61 | { |
62 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
63 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
64 | *gen_opparam_ptr++ = arg2; | |
c896fe29 FB |
65 | } |
66 | ||
a7812ae4 | 67 | static inline void tcg_gen_op2i_i64(int opc, TCGv_i64 arg1, TCGArg arg2) |
c896fe29 FB |
68 | { |
69 | *gen_opc_ptr++ = opc; | |
a7812ae4 | 70 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
c896fe29 | 71 | *gen_opparam_ptr++ = arg2; |
ac56dd48 PB |
72 | } |
73 | ||
bcb0126f PB |
74 | static inline void tcg_gen_op2ii(int opc, TCGArg arg1, TCGArg arg2) |
75 | { | |
76 | *gen_opc_ptr++ = opc; | |
77 | *gen_opparam_ptr++ = arg1; | |
78 | *gen_opparam_ptr++ = arg2; | |
79 | } | |
80 | ||
a7812ae4 PB |
81 | static inline void tcg_gen_op3_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
82 | TCGv_i32 arg3) | |
83 | { | |
84 | *gen_opc_ptr++ = opc; | |
85 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
86 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
87 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
88 | } | |
89 | ||
90 | static inline void tcg_gen_op3_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, | |
91 | TCGv_i64 arg3) | |
92 | { | |
93 | *gen_opc_ptr++ = opc; | |
94 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
95 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
96 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
97 | } | |
98 | ||
99 | static inline void tcg_gen_op3i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, | |
100 | TCGArg arg3) | |
ac56dd48 PB |
101 | { |
102 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
103 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
104 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
105 | *gen_opparam_ptr++ = arg3; | |
ac56dd48 PB |
106 | } |
107 | ||
a7812ae4 PB |
108 | static inline void tcg_gen_op3i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, |
109 | TCGArg arg3) | |
ac56dd48 PB |
110 | { |
111 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
112 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
113 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
c896fe29 | 114 | *gen_opparam_ptr++ = arg3; |
ac56dd48 PB |
115 | } |
116 | ||
a7812ae4 PB |
117 | static inline void tcg_gen_ldst_op_i32(int opc, TCGv_i32 val, TCGv_ptr base, |
118 | TCGArg offset) | |
119 | { | |
120 | *gen_opc_ptr++ = opc; | |
121 | *gen_opparam_ptr++ = GET_TCGV_I32(val); | |
122 | *gen_opparam_ptr++ = GET_TCGV_PTR(base); | |
123 | *gen_opparam_ptr++ = offset; | |
124 | } | |
125 | ||
126 | static inline void tcg_gen_ldst_op_i64(int opc, TCGv_i64 val, TCGv_ptr base, | |
127 | TCGArg offset) | |
128 | { | |
129 | *gen_opc_ptr++ = opc; | |
a810a2de | 130 | *gen_opparam_ptr++ = GET_TCGV_I64(val); |
a7812ae4 PB |
131 | *gen_opparam_ptr++ = GET_TCGV_PTR(base); |
132 | *gen_opparam_ptr++ = offset; | |
133 | } | |
134 | ||
135 | static inline void tcg_gen_qemu_ldst_op_i64_i32(int opc, TCGv_i64 val, TCGv_i32 addr, | |
136 | TCGArg mem_index) | |
137 | { | |
138 | *gen_opc_ptr++ = opc; | |
139 | *gen_opparam_ptr++ = GET_TCGV_I64(val); | |
140 | *gen_opparam_ptr++ = GET_TCGV_I32(addr); | |
141 | *gen_opparam_ptr++ = mem_index; | |
142 | } | |
143 | ||
144 | static inline void tcg_gen_qemu_ldst_op_i64_i64(int opc, TCGv_i64 val, TCGv_i64 addr, | |
145 | TCGArg mem_index) | |
146 | { | |
147 | *gen_opc_ptr++ = opc; | |
148 | *gen_opparam_ptr++ = GET_TCGV_I64(val); | |
149 | *gen_opparam_ptr++ = GET_TCGV_I64(addr); | |
150 | *gen_opparam_ptr++ = mem_index; | |
151 | } | |
152 | ||
153 | static inline void tcg_gen_op4_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, | |
154 | TCGv_i32 arg3, TCGv_i32 arg4) | |
155 | { | |
156 | *gen_opc_ptr++ = opc; | |
157 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
158 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
159 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
160 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
161 | } | |
162 | ||
163 | static inline void tcg_gen_op4_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, | |
a810a2de | 164 | TCGv_i64 arg3, TCGv_i64 arg4) |
a7812ae4 PB |
165 | { |
166 | *gen_opc_ptr++ = opc; | |
167 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
168 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
169 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
170 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
171 | } | |
172 | ||
173 | static inline void tcg_gen_op4i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, | |
174 | TCGv_i32 arg3, TCGArg arg4) | |
175 | { | |
176 | *gen_opc_ptr++ = opc; | |
177 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
178 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
179 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
180 | *gen_opparam_ptr++ = arg4; | |
181 | } | |
182 | ||
183 | static inline void tcg_gen_op4i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, | |
184 | TCGv_i64 arg3, TCGArg arg4) | |
ac56dd48 PB |
185 | { |
186 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
187 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
188 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
189 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
190 | *gen_opparam_ptr++ = arg4; | |
ac56dd48 PB |
191 | } |
192 | ||
a7812ae4 PB |
193 | static inline void tcg_gen_op4ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
194 | TCGArg arg3, TCGArg arg4) | |
ac56dd48 PB |
195 | { |
196 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
197 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
198 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
199 | *gen_opparam_ptr++ = arg3; | |
c896fe29 FB |
200 | *gen_opparam_ptr++ = arg4; |
201 | } | |
202 | ||
a7812ae4 PB |
203 | static inline void tcg_gen_op4ii_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, |
204 | TCGArg arg3, TCGArg arg4) | |
c896fe29 FB |
205 | { |
206 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
207 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
208 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
c896fe29 FB |
209 | *gen_opparam_ptr++ = arg3; |
210 | *gen_opparam_ptr++ = arg4; | |
ac56dd48 PB |
211 | } |
212 | ||
a7812ae4 PB |
213 | static inline void tcg_gen_op5_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
214 | TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5) | |
215 | { | |
216 | *gen_opc_ptr++ = opc; | |
217 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
218 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
219 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
220 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
221 | *gen_opparam_ptr++ = GET_TCGV_I32(arg5); | |
222 | } | |
223 | ||
224 | static inline void tcg_gen_op5_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, | |
225 | TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5) | |
226 | { | |
227 | *gen_opc_ptr++ = opc; | |
228 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
229 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
230 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
231 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
232 | *gen_opparam_ptr++ = GET_TCGV_I64(arg5); | |
233 | } | |
234 | ||
235 | static inline void tcg_gen_op5i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, | |
236 | TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5) | |
ac56dd48 PB |
237 | { |
238 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
239 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
240 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
241 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
242 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
243 | *gen_opparam_ptr++ = arg5; | |
ac56dd48 PB |
244 | } |
245 | ||
a7812ae4 PB |
246 | static inline void tcg_gen_op5i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, |
247 | TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5) | |
ac56dd48 PB |
248 | { |
249 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
250 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
251 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
252 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
253 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
c896fe29 FB |
254 | *gen_opparam_ptr++ = arg5; |
255 | } | |
256 | ||
a7812ae4 PB |
257 | static inline void tcg_gen_op6_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
258 | TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5, | |
259 | TCGv_i32 arg6) | |
260 | { | |
261 | *gen_opc_ptr++ = opc; | |
262 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
263 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
264 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
265 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
266 | *gen_opparam_ptr++ = GET_TCGV_I32(arg5); | |
267 | *gen_opparam_ptr++ = GET_TCGV_I32(arg6); | |
268 | } | |
269 | ||
270 | static inline void tcg_gen_op6_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, | |
271 | TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5, | |
272 | TCGv_i64 arg6) | |
c896fe29 FB |
273 | { |
274 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
275 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
276 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
277 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
278 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
279 | *gen_opparam_ptr++ = GET_TCGV_I64(arg5); | |
280 | *gen_opparam_ptr++ = GET_TCGV_I64(arg6); | |
ac56dd48 PB |
281 | } |
282 | ||
be210acb RH |
283 | static inline void tcg_gen_op6i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
284 | TCGv_i32 arg3, TCGv_i32 arg4, | |
285 | TCGv_i32 arg5, TCGArg arg6) | |
286 | { | |
287 | *gen_opc_ptr++ = opc; | |
288 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
289 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
290 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
291 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
292 | *gen_opparam_ptr++ = GET_TCGV_I32(arg5); | |
293 | *gen_opparam_ptr++ = arg6; | |
294 | } | |
295 | ||
296 | static inline void tcg_gen_op6i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, | |
297 | TCGv_i64 arg3, TCGv_i64 arg4, | |
298 | TCGv_i64 arg5, TCGArg arg6) | |
299 | { | |
300 | *gen_opc_ptr++ = opc; | |
301 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
302 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
303 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
304 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
305 | *gen_opparam_ptr++ = GET_TCGV_I64(arg5); | |
306 | *gen_opparam_ptr++ = arg6; | |
307 | } | |
308 | ||
a7812ae4 PB |
309 | static inline void tcg_gen_op6ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
310 | TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5, | |
311 | TCGArg arg6) | |
ac56dd48 PB |
312 | { |
313 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
314 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
315 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
316 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
317 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
318 | *gen_opparam_ptr++ = arg5; | |
319 | *gen_opparam_ptr++ = arg6; | |
320 | } | |
321 | ||
322 | static inline void tcg_gen_op6ii_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, | |
323 | TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5, | |
324 | TCGArg arg6) | |
325 | { | |
326 | *gen_opc_ptr++ = opc; | |
327 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
328 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
329 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
330 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
c896fe29 FB |
331 | *gen_opparam_ptr++ = arg5; |
332 | *gen_opparam_ptr++ = arg6; | |
333 | } | |
334 | ||
335 | static inline void gen_set_label(int n) | |
336 | { | |
ac56dd48 | 337 | tcg_gen_op1i(INDEX_op_set_label, n); |
c896fe29 FB |
338 | } |
339 | ||
fb50d413 BS |
340 | static inline void tcg_gen_br(int label) |
341 | { | |
342 | tcg_gen_op1i(INDEX_op_br, label); | |
343 | } | |
344 | ||
a7812ae4 | 345 | static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 | 346 | { |
fe75bcf7 | 347 | if (!TCGV_EQUAL_I32(ret, arg)) |
a7812ae4 | 348 | tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg); |
c896fe29 FB |
349 | } |
350 | ||
a7812ae4 | 351 | static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg) |
c896fe29 | 352 | { |
a7812ae4 | 353 | tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg); |
c896fe29 FB |
354 | } |
355 | ||
356 | /* helper calls */ | |
a7812ae4 PB |
357 | static inline void tcg_gen_helperN(void *func, int flags, int sizemask, |
358 | TCGArg ret, int nargs, TCGArg *args) | |
359 | { | |
360 | TCGv_ptr fn; | |
361 | fn = tcg_const_ptr((tcg_target_long)func); | |
362 | tcg_gen_callN(&tcg_ctx, fn, flags, sizemask, ret, | |
363 | nargs, args); | |
364 | tcg_temp_free_ptr(fn); | |
365 | } | |
c896fe29 | 366 | |
31d66551 AJ |
367 | /* FIXME: Should this be pure? */ |
368 | static inline void tcg_gen_helper32(void *func, TCGv_i32 ret, | |
369 | TCGv_i32 a, TCGv_i32 b) | |
370 | { | |
371 | TCGv_ptr fn; | |
372 | TCGArg args[2]; | |
373 | fn = tcg_const_ptr((tcg_target_long)func); | |
374 | args[0] = GET_TCGV_I32(a); | |
375 | args[1] = GET_TCGV_I32(b); | |
376 | tcg_gen_callN(&tcg_ctx, fn, 0, 0, GET_TCGV_I32(ret), 2, args); | |
377 | tcg_temp_free_ptr(fn); | |
378 | } | |
379 | ||
a7812ae4 PB |
380 | /* FIXME: Should this be pure? */ |
381 | static inline void tcg_gen_helper64(void *func, TCGv_i64 ret, | |
382 | TCGv_i64 a, TCGv_i64 b) | |
c896fe29 | 383 | { |
a7812ae4 PB |
384 | TCGv_ptr fn; |
385 | TCGArg args[2]; | |
386 | fn = tcg_const_ptr((tcg_target_long)func); | |
387 | args[0] = GET_TCGV_I64(a); | |
388 | args[1] = GET_TCGV_I64(b); | |
389 | tcg_gen_callN(&tcg_ctx, fn, 0, 7, GET_TCGV_I64(ret), 2, args); | |
390 | tcg_temp_free_ptr(fn); | |
f8422f52 BS |
391 | } |
392 | ||
c896fe29 FB |
393 | /* 32 bit ops */ |
394 | ||
a7812ae4 | 395 | static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 396 | { |
a7812ae4 | 397 | tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset); |
c896fe29 FB |
398 | } |
399 | ||
a7812ae4 | 400 | static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 401 | { |
a7812ae4 | 402 | tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset); |
c896fe29 FB |
403 | } |
404 | ||
a7812ae4 | 405 | static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 406 | { |
a7812ae4 | 407 | tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset); |
c896fe29 FB |
408 | } |
409 | ||
a7812ae4 | 410 | static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 411 | { |
a7812ae4 | 412 | tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset); |
c896fe29 FB |
413 | } |
414 | ||
a7812ae4 | 415 | static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 416 | { |
a7812ae4 | 417 | tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset); |
c896fe29 FB |
418 | } |
419 | ||
a7812ae4 | 420 | static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 421 | { |
a7812ae4 | 422 | tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset); |
c896fe29 FB |
423 | } |
424 | ||
a7812ae4 | 425 | static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 426 | { |
a7812ae4 | 427 | tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset); |
c896fe29 FB |
428 | } |
429 | ||
a7812ae4 | 430 | static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 431 | { |
a7812ae4 | 432 | tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset); |
c896fe29 FB |
433 | } |
434 | ||
a7812ae4 | 435 | static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 436 | { |
a7812ae4 | 437 | tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2); |
c896fe29 FB |
438 | } |
439 | ||
a7812ae4 | 440 | static inline void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 441 | { |
7089442c BS |
442 | /* some cases can be optimized here */ |
443 | if (arg2 == 0) { | |
444 | tcg_gen_mov_i32(ret, arg1); | |
445 | } else { | |
a7812ae4 | 446 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 447 | tcg_gen_add_i32(ret, arg1, t0); |
a7812ae4 | 448 | tcg_temp_free_i32(t0); |
7089442c | 449 | } |
c896fe29 FB |
450 | } |
451 | ||
a7812ae4 | 452 | static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 453 | { |
a7812ae4 | 454 | tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2); |
c896fe29 FB |
455 | } |
456 | ||
a7812ae4 | 457 | static inline void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2) |
0045734a | 458 | { |
a7812ae4 | 459 | TCGv_i32 t0 = tcg_const_i32(arg1); |
0045734a | 460 | tcg_gen_sub_i32(ret, t0, arg2); |
a7812ae4 | 461 | tcg_temp_free_i32(t0); |
0045734a AJ |
462 | } |
463 | ||
a7812ae4 | 464 | static inline void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 465 | { |
7089442c BS |
466 | /* some cases can be optimized here */ |
467 | if (arg2 == 0) { | |
468 | tcg_gen_mov_i32(ret, arg1); | |
469 | } else { | |
a7812ae4 | 470 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 471 | tcg_gen_sub_i32(ret, arg1, t0); |
a7812ae4 | 472 | tcg_temp_free_i32(t0); |
7089442c | 473 | } |
c896fe29 FB |
474 | } |
475 | ||
a7812ae4 | 476 | static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 477 | { |
7fc81051 AJ |
478 | if (TCGV_EQUAL_I32(arg1, arg2)) { |
479 | tcg_gen_mov_i32(ret, arg1); | |
480 | } else { | |
481 | tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2); | |
482 | } | |
c896fe29 FB |
483 | } |
484 | ||
a7812ae4 | 485 | static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 FB |
486 | { |
487 | /* some cases can be optimized here */ | |
488 | if (arg2 == 0) { | |
489 | tcg_gen_movi_i32(ret, 0); | |
490 | } else if (arg2 == 0xffffffff) { | |
491 | tcg_gen_mov_i32(ret, arg1); | |
492 | } else { | |
a7812ae4 | 493 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 494 | tcg_gen_and_i32(ret, arg1, t0); |
a7812ae4 | 495 | tcg_temp_free_i32(t0); |
c896fe29 FB |
496 | } |
497 | } | |
498 | ||
a7812ae4 | 499 | static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 500 | { |
7fc81051 AJ |
501 | if (TCGV_EQUAL_I32(arg1, arg2)) { |
502 | tcg_gen_mov_i32(ret, arg1); | |
503 | } else { | |
504 | tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2); | |
505 | } | |
c896fe29 FB |
506 | } |
507 | ||
a7812ae4 | 508 | static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 FB |
509 | { |
510 | /* some cases can be optimized here */ | |
511 | if (arg2 == 0xffffffff) { | |
7089442c | 512 | tcg_gen_movi_i32(ret, 0xffffffff); |
c896fe29 FB |
513 | } else if (arg2 == 0) { |
514 | tcg_gen_mov_i32(ret, arg1); | |
515 | } else { | |
a7812ae4 | 516 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 517 | tcg_gen_or_i32(ret, arg1, t0); |
a7812ae4 | 518 | tcg_temp_free_i32(t0); |
c896fe29 FB |
519 | } |
520 | } | |
521 | ||
a7812ae4 | 522 | static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 523 | { |
7fc81051 AJ |
524 | if (TCGV_EQUAL_I32(arg1, arg2)) { |
525 | tcg_gen_movi_i32(ret, 0); | |
526 | } else { | |
527 | tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2); | |
528 | } | |
c896fe29 FB |
529 | } |
530 | ||
a7812ae4 | 531 | static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 FB |
532 | { |
533 | /* some cases can be optimized here */ | |
534 | if (arg2 == 0) { | |
535 | tcg_gen_mov_i32(ret, arg1); | |
536 | } else { | |
a7812ae4 | 537 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 538 | tcg_gen_xor_i32(ret, arg1, t0); |
a7812ae4 | 539 | tcg_temp_free_i32(t0); |
c896fe29 FB |
540 | } |
541 | } | |
542 | ||
a7812ae4 | 543 | static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 544 | { |
a7812ae4 | 545 | tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2); |
c896fe29 FB |
546 | } |
547 | ||
a7812ae4 | 548 | static inline void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 549 | { |
34151a20 FB |
550 | if (arg2 == 0) { |
551 | tcg_gen_mov_i32(ret, arg1); | |
552 | } else { | |
a7812ae4 | 553 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 554 | tcg_gen_shl_i32(ret, arg1, t0); |
a7812ae4 | 555 | tcg_temp_free_i32(t0); |
34151a20 | 556 | } |
c896fe29 FB |
557 | } |
558 | ||
a7812ae4 | 559 | static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 560 | { |
a7812ae4 | 561 | tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2); |
c896fe29 FB |
562 | } |
563 | ||
a7812ae4 | 564 | static inline void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 565 | { |
34151a20 FB |
566 | if (arg2 == 0) { |
567 | tcg_gen_mov_i32(ret, arg1); | |
568 | } else { | |
a7812ae4 | 569 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 570 | tcg_gen_shr_i32(ret, arg1, t0); |
a7812ae4 | 571 | tcg_temp_free_i32(t0); |
34151a20 | 572 | } |
c896fe29 FB |
573 | } |
574 | ||
a7812ae4 | 575 | static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 576 | { |
a7812ae4 | 577 | tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2); |
c896fe29 FB |
578 | } |
579 | ||
a7812ae4 | 580 | static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 581 | { |
34151a20 FB |
582 | if (arg2 == 0) { |
583 | tcg_gen_mov_i32(ret, arg1); | |
584 | } else { | |
a7812ae4 | 585 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 586 | tcg_gen_sar_i32(ret, arg1, t0); |
a7812ae4 | 587 | tcg_temp_free_i32(t0); |
34151a20 | 588 | } |
c896fe29 FB |
589 | } |
590 | ||
a7812ae4 | 591 | static inline void tcg_gen_brcond_i32(int cond, TCGv_i32 arg1, TCGv_i32 arg2, |
c896fe29 FB |
592 | int label_index) |
593 | { | |
a7812ae4 | 594 | tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index); |
c896fe29 FB |
595 | } |
596 | ||
a7812ae4 | 597 | static inline void tcg_gen_brcondi_i32(int cond, TCGv_i32 arg1, int32_t arg2, |
cb63669a PB |
598 | int label_index) |
599 | { | |
a7812ae4 | 600 | TCGv_i32 t0 = tcg_const_i32(arg2); |
cb63669a | 601 | tcg_gen_brcond_i32(cond, arg1, t0, label_index); |
a7812ae4 | 602 | tcg_temp_free_i32(t0); |
cb63669a PB |
603 | } |
604 | ||
5105c556 AJ |
605 | static inline void tcg_gen_setcond_i32(int cond, TCGv_i32 ret, |
606 | TCGv_i32 arg1, TCGv_i32 arg2) | |
607 | { | |
608 | tcg_gen_op4i_i32(INDEX_op_setcond_i32, ret, arg1, arg2, cond); | |
609 | } | |
610 | ||
611 | static inline void tcg_gen_setcondi_i32(int cond, TCGv_i32 ret, TCGv_i32 arg1, | |
612 | int32_t arg2) | |
613 | { | |
614 | TCGv_i32 t0 = tcg_const_i32(arg2); | |
615 | tcg_gen_setcond_i32(cond, ret, arg1, t0); | |
616 | tcg_temp_free_i32(t0); | |
617 | } | |
618 | ||
a7812ae4 | 619 | static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 620 | { |
a7812ae4 | 621 | tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2); |
c896fe29 FB |
622 | } |
623 | ||
a7812ae4 | 624 | static inline void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
f730fd27 | 625 | { |
a7812ae4 | 626 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 627 | tcg_gen_mul_i32(ret, arg1, t0); |
a7812ae4 | 628 | tcg_temp_free_i32(t0); |
f730fd27 TS |
629 | } |
630 | ||
c896fe29 | 631 | #ifdef TCG_TARGET_HAS_div_i32 |
a7812ae4 | 632 | static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 633 | { |
a7812ae4 | 634 | tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2); |
c896fe29 FB |
635 | } |
636 | ||
a7812ae4 | 637 | static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 638 | { |
a7812ae4 | 639 | tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2); |
c896fe29 FB |
640 | } |
641 | ||
a7812ae4 | 642 | static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 643 | { |
a7812ae4 | 644 | tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2); |
c896fe29 FB |
645 | } |
646 | ||
a7812ae4 | 647 | static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 648 | { |
a7812ae4 | 649 | tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2); |
c896fe29 | 650 | } |
31d66551 | 651 | #elif defined(TCG_TARGET_HAS_div2_i32) |
a7812ae4 | 652 | static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 653 | { |
a7812ae4 PB |
654 | TCGv_i32 t0; |
655 | t0 = tcg_temp_new_i32(); | |
c896fe29 | 656 | tcg_gen_sari_i32(t0, arg1, 31); |
a7812ae4 PB |
657 | tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2); |
658 | tcg_temp_free_i32(t0); | |
c896fe29 FB |
659 | } |
660 | ||
a7812ae4 | 661 | static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 662 | { |
a7812ae4 PB |
663 | TCGv_i32 t0; |
664 | t0 = tcg_temp_new_i32(); | |
c896fe29 | 665 | tcg_gen_sari_i32(t0, arg1, 31); |
a7812ae4 PB |
666 | tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2); |
667 | tcg_temp_free_i32(t0); | |
c896fe29 FB |
668 | } |
669 | ||
a7812ae4 | 670 | static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 671 | { |
a7812ae4 PB |
672 | TCGv_i32 t0; |
673 | t0 = tcg_temp_new_i32(); | |
c896fe29 | 674 | tcg_gen_movi_i32(t0, 0); |
a7812ae4 PB |
675 | tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2); |
676 | tcg_temp_free_i32(t0); | |
c896fe29 FB |
677 | } |
678 | ||
a7812ae4 | 679 | static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 680 | { |
a7812ae4 PB |
681 | TCGv_i32 t0; |
682 | t0 = tcg_temp_new_i32(); | |
c896fe29 | 683 | tcg_gen_movi_i32(t0, 0); |
a7812ae4 PB |
684 | tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2); |
685 | tcg_temp_free_i32(t0); | |
c896fe29 | 686 | } |
31d66551 AJ |
687 | #else |
688 | static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) | |
689 | { | |
690 | tcg_gen_helper32(tcg_helper_div_i32, ret, arg1, arg2); | |
691 | } | |
692 | ||
693 | static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) | |
694 | { | |
695 | tcg_gen_helper32(tcg_helper_rem_i32, ret, arg1, arg2); | |
696 | } | |
697 | ||
698 | static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) | |
699 | { | |
700 | tcg_gen_helper32(tcg_helper_divu_i32, ret, arg1, arg2); | |
701 | } | |
702 | ||
703 | static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) | |
704 | { | |
705 | tcg_gen_helper32(tcg_helper_remu_i32, ret, arg1, arg2); | |
706 | } | |
c896fe29 FB |
707 | #endif |
708 | ||
709 | #if TCG_TARGET_REG_BITS == 32 | |
710 | ||
a7812ae4 | 711 | static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 712 | { |
fe75bcf7 | 713 | if (!TCGV_EQUAL_I64(ret, arg)) { |
a7812ae4 | 714 | tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
4d07272d BS |
715 | tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
716 | } | |
c896fe29 FB |
717 | } |
718 | ||
a7812ae4 | 719 | static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) |
c896fe29 | 720 | { |
a7812ae4 | 721 | tcg_gen_movi_i32(TCGV_LOW(ret), arg); |
ac56dd48 | 722 | tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32); |
c896fe29 FB |
723 | } |
724 | ||
a7812ae4 PB |
725 | static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
726 | tcg_target_long offset) | |
c896fe29 | 727 | { |
a7812ae4 | 728 | tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset); |
ac56dd48 | 729 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
730 | } |
731 | ||
a7812ae4 PB |
732 | static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
733 | tcg_target_long offset) | |
c896fe29 | 734 | { |
a7812ae4 PB |
735 | tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset); |
736 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31); | |
c896fe29 FB |
737 | } |
738 | ||
a7812ae4 PB |
739 | static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
740 | tcg_target_long offset) | |
c896fe29 | 741 | { |
a747723b | 742 | tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset); |
ac56dd48 | 743 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
744 | } |
745 | ||
a7812ae4 PB |
746 | static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
747 | tcg_target_long offset) | |
c896fe29 | 748 | { |
a7812ae4 PB |
749 | tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset); |
750 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
751 | } |
752 | ||
a7812ae4 PB |
753 | static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
754 | tcg_target_long offset) | |
c896fe29 | 755 | { |
a7812ae4 | 756 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
ac56dd48 | 757 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
758 | } |
759 | ||
a7812ae4 PB |
760 | static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
761 | tcg_target_long offset) | |
c896fe29 | 762 | { |
a7812ae4 PB |
763 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
764 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
765 | } |
766 | ||
a7812ae4 PB |
767 | static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, |
768 | tcg_target_long offset) | |
c896fe29 FB |
769 | { |
770 | /* since arg2 and ret have different types, they cannot be the | |
771 | same temporary */ | |
772 | #ifdef TCG_TARGET_WORDS_BIGENDIAN | |
ac56dd48 | 773 | tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset); |
a7812ae4 | 774 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4); |
c896fe29 | 775 | #else |
a7812ae4 | 776 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
ac56dd48 | 777 | tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4); |
c896fe29 FB |
778 | #endif |
779 | } | |
780 | ||
a7812ae4 PB |
781 | static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
782 | tcg_target_long offset) | |
c896fe29 | 783 | { |
a7812ae4 | 784 | tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset); |
c896fe29 FB |
785 | } |
786 | ||
a7812ae4 PB |
787 | static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
788 | tcg_target_long offset) | |
c896fe29 | 789 | { |
a7812ae4 | 790 | tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset); |
c896fe29 FB |
791 | } |
792 | ||
a7812ae4 PB |
793 | static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
794 | tcg_target_long offset) | |
c896fe29 | 795 | { |
a7812ae4 | 796 | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); |
c896fe29 FB |
797 | } |
798 | ||
a7812ae4 PB |
799 | static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
800 | tcg_target_long offset) | |
c896fe29 FB |
801 | { |
802 | #ifdef TCG_TARGET_WORDS_BIGENDIAN | |
ac56dd48 | 803 | tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset); |
a7812ae4 | 804 | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4); |
c896fe29 | 805 | #else |
a7812ae4 | 806 | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); |
ac56dd48 | 807 | tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4); |
c896fe29 FB |
808 | #endif |
809 | } | |
810 | ||
a7812ae4 | 811 | static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 812 | { |
a7812ae4 PB |
813 | tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret), |
814 | TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), | |
815 | TCGV_HIGH(arg2)); | |
c896fe29 FB |
816 | } |
817 | ||
a7812ae4 | 818 | static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 819 | { |
a7812ae4 PB |
820 | tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret), |
821 | TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), | |
822 | TCGV_HIGH(arg2)); | |
c896fe29 FB |
823 | } |
824 | ||
a7812ae4 | 825 | static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 826 | { |
a7812ae4 | 827 | tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
ac56dd48 | 828 | tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
c896fe29 FB |
829 | } |
830 | ||
a7812ae4 | 831 | static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 832 | { |
e5105083 AJ |
833 | tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
834 | tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); | |
c896fe29 FB |
835 | } |
836 | ||
a7812ae4 | 837 | static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 838 | { |
e5105083 AJ |
839 | tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
840 | tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); | |
c896fe29 FB |
841 | } |
842 | ||
a7812ae4 | 843 | static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 844 | { |
a7812ae4 | 845 | tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
ac56dd48 | 846 | tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); |
c896fe29 FB |
847 | } |
848 | ||
a7812ae4 | 849 | static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 850 | { |
e5105083 AJ |
851 | tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
852 | tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); | |
c896fe29 FB |
853 | } |
854 | ||
a7812ae4 | 855 | static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 856 | { |
a7812ae4 | 857 | tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
ac56dd48 | 858 | tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); |
c896fe29 FB |
859 | } |
860 | ||
861 | /* XXX: use generic code when basic block handling is OK or CPU | |
862 | specific code (x86) */ | |
a7812ae4 | 863 | static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 864 | { |
a7812ae4 | 865 | tcg_gen_helper64(tcg_helper_shl_i64, ret, arg1, arg2); |
c896fe29 FB |
866 | } |
867 | ||
a7812ae4 | 868 | static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 FB |
869 | { |
870 | tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0); | |
871 | } | |
872 | ||
a7812ae4 | 873 | static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 874 | { |
a7812ae4 | 875 | tcg_gen_helper64(tcg_helper_shr_i64, ret, arg1, arg2); |
c896fe29 FB |
876 | } |
877 | ||
a7812ae4 | 878 | static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 FB |
879 | { |
880 | tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0); | |
881 | } | |
882 | ||
a7812ae4 | 883 | static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 884 | { |
a7812ae4 | 885 | tcg_gen_helper64(tcg_helper_sar_i64, ret, arg1, arg2); |
c896fe29 FB |
886 | } |
887 | ||
a7812ae4 | 888 | static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 FB |
889 | { |
890 | tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1); | |
891 | } | |
892 | ||
a7812ae4 | 893 | static inline void tcg_gen_brcond_i64(int cond, TCGv_i64 arg1, TCGv_i64 arg2, |
c896fe29 FB |
894 | int label_index) |
895 | { | |
a7812ae4 PB |
896 | tcg_gen_op6ii_i32(INDEX_op_brcond2_i32, |
897 | TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), | |
898 | TCGV_HIGH(arg2), cond, label_index); | |
c896fe29 FB |
899 | } |
900 | ||
5105c556 AJ |
901 | static inline void tcg_gen_setcond_i64(int cond, TCGv_i64 ret, |
902 | TCGv_i64 arg1, TCGv_i64 arg2) | |
903 | { | |
904 | tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret), | |
905 | TCGV_LOW(arg1), TCGV_HIGH(arg1), | |
906 | TCGV_LOW(arg2), TCGV_HIGH(arg2), cond); | |
907 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); | |
908 | } | |
909 | ||
a7812ae4 | 910 | static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 911 | { |
a7812ae4 PB |
912 | TCGv_i64 t0; |
913 | TCGv_i32 t1; | |
c896fe29 | 914 | |
a7812ae4 PB |
915 | t0 = tcg_temp_new_i64(); |
916 | t1 = tcg_temp_new_i32(); | |
917 | ||
918 | tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0), | |
919 | TCGV_LOW(arg1), TCGV_LOW(arg2)); | |
920 | ||
921 | tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2)); | |
ac56dd48 | 922 | tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
a7812ae4 | 923 | tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2)); |
ac56dd48 | 924 | tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
a7812ae4 | 925 | |
c896fe29 | 926 | tcg_gen_mov_i64(ret, t0); |
a7812ae4 PB |
927 | tcg_temp_free_i64(t0); |
928 | tcg_temp_free_i32(t1); | |
c896fe29 FB |
929 | } |
930 | ||
a7812ae4 | 931 | static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 932 | { |
a7812ae4 | 933 | tcg_gen_helper64(tcg_helper_div_i64, ret, arg1, arg2); |
c896fe29 FB |
934 | } |
935 | ||
a7812ae4 | 936 | static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 937 | { |
a7812ae4 | 938 | tcg_gen_helper64(tcg_helper_rem_i64, ret, arg1, arg2); |
c896fe29 FB |
939 | } |
940 | ||
a7812ae4 | 941 | static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 942 | { |
a7812ae4 | 943 | tcg_gen_helper64(tcg_helper_divu_i64, ret, arg1, arg2); |
c896fe29 FB |
944 | } |
945 | ||
a7812ae4 | 946 | static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 947 | { |
a7812ae4 | 948 | tcg_gen_helper64(tcg_helper_remu_i64, ret, arg1, arg2); |
c896fe29 FB |
949 | } |
950 | ||
951 | #else | |
952 | ||
a7812ae4 | 953 | static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 954 | { |
fe75bcf7 | 955 | if (!TCGV_EQUAL_I64(ret, arg)) |
a7812ae4 | 956 | tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg); |
c896fe29 FB |
957 | } |
958 | ||
a7812ae4 | 959 | static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) |
c896fe29 | 960 | { |
a7812ae4 | 961 | tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg); |
c896fe29 FB |
962 | } |
963 | ||
a7812ae4 | 964 | static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_i64 arg2, |
ac56dd48 | 965 | tcg_target_long offset) |
c896fe29 | 966 | { |
a7812ae4 | 967 | tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset); |
c896fe29 FB |
968 | } |
969 | ||
a7812ae4 | 970 | static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_i64 arg2, |
ac56dd48 | 971 | tcg_target_long offset) |
c896fe29 | 972 | { |
a7812ae4 | 973 | tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset); |
c896fe29 FB |
974 | } |
975 | ||
a7812ae4 | 976 | static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_i64 arg2, |
ac56dd48 | 977 | tcg_target_long offset) |
c896fe29 | 978 | { |
a7812ae4 | 979 | tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset); |
c896fe29 FB |
980 | } |
981 | ||
a7812ae4 | 982 | static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_i64 arg2, |
ac56dd48 | 983 | tcg_target_long offset) |
c896fe29 | 984 | { |
a7812ae4 | 985 | tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset); |
c896fe29 FB |
986 | } |
987 | ||
a7812ae4 | 988 | static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_i64 arg2, |
ac56dd48 | 989 | tcg_target_long offset) |
c896fe29 | 990 | { |
a7812ae4 | 991 | tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset); |
c896fe29 FB |
992 | } |
993 | ||
a7812ae4 | 994 | static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_i64 arg2, |
ac56dd48 | 995 | tcg_target_long offset) |
c896fe29 | 996 | { |
a7812ae4 | 997 | tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset); |
c896fe29 FB |
998 | } |
999 | ||
a7812ae4 | 1000 | static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_i64 arg2, tcg_target_long offset) |
c896fe29 | 1001 | { |
a7812ae4 | 1002 | tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset); |
c896fe29 FB |
1003 | } |
1004 | ||
a7812ae4 | 1005 | static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_i64 arg2, |
ac56dd48 | 1006 | tcg_target_long offset) |
c896fe29 | 1007 | { |
a7812ae4 | 1008 | tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset); |
c896fe29 FB |
1009 | } |
1010 | ||
a7812ae4 | 1011 | static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_i64 arg2, |
ac56dd48 | 1012 | tcg_target_long offset) |
c896fe29 | 1013 | { |
a7812ae4 | 1014 | tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset); |
c896fe29 FB |
1015 | } |
1016 | ||
a7812ae4 | 1017 | static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_i64 arg2, |
ac56dd48 | 1018 | tcg_target_long offset) |
c896fe29 | 1019 | { |
a7812ae4 | 1020 | tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset); |
c896fe29 FB |
1021 | } |
1022 | ||
a7812ae4 | 1023 | static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_i64 arg2, tcg_target_long offset) |
c896fe29 | 1024 | { |
a7812ae4 | 1025 | tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset); |
c896fe29 FB |
1026 | } |
1027 | ||
a7812ae4 | 1028 | static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1029 | { |
a7812ae4 | 1030 | tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2); |
c896fe29 FB |
1031 | } |
1032 | ||
a7812ae4 | 1033 | static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1034 | { |
a7812ae4 | 1035 | tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2); |
c896fe29 FB |
1036 | } |
1037 | ||
a7812ae4 | 1038 | static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1039 | { |
7fc81051 AJ |
1040 | if (TCGV_EQUAL_I64(arg1, arg2)) { |
1041 | tcg_gen_mov_i64(ret, arg1); | |
1042 | } else { | |
1043 | tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2); | |
1044 | } | |
c896fe29 FB |
1045 | } |
1046 | ||
a7812ae4 | 1047 | static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1048 | { |
a7812ae4 | 1049 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 1050 | tcg_gen_and_i64(ret, arg1, t0); |
a7812ae4 | 1051 | tcg_temp_free_i64(t0); |
c896fe29 FB |
1052 | } |
1053 | ||
a7812ae4 | 1054 | static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1055 | { |
7fc81051 AJ |
1056 | if (TCGV_EQUAL_I64(arg1, arg2)) { |
1057 | tcg_gen_mov_i64(ret, arg1); | |
1058 | } else { | |
1059 | tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2); | |
1060 | } | |
c896fe29 FB |
1061 | } |
1062 | ||
a7812ae4 | 1063 | static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1064 | { |
a7812ae4 | 1065 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 1066 | tcg_gen_or_i64(ret, arg1, t0); |
a7812ae4 | 1067 | tcg_temp_free_i64(t0); |
c896fe29 FB |
1068 | } |
1069 | ||
a7812ae4 | 1070 | static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1071 | { |
7fc81051 AJ |
1072 | if (TCGV_EQUAL_I64(arg1, arg2)) { |
1073 | tcg_gen_movi_i64(ret, 0); | |
1074 | } else { | |
1075 | tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2); | |
1076 | } | |
c896fe29 FB |
1077 | } |
1078 | ||
a7812ae4 | 1079 | static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1080 | { |
a7812ae4 | 1081 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 1082 | tcg_gen_xor_i64(ret, arg1, t0); |
a7812ae4 | 1083 | tcg_temp_free_i64(t0); |
c896fe29 FB |
1084 | } |
1085 | ||
a7812ae4 | 1086 | static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1087 | { |
a7812ae4 | 1088 | tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2); |
c896fe29 FB |
1089 | } |
1090 | ||
a7812ae4 | 1091 | static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1092 | { |
34151a20 FB |
1093 | if (arg2 == 0) { |
1094 | tcg_gen_mov_i64(ret, arg1); | |
1095 | } else { | |
a7812ae4 | 1096 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 1097 | tcg_gen_shl_i64(ret, arg1, t0); |
a7812ae4 | 1098 | tcg_temp_free_i64(t0); |
34151a20 | 1099 | } |
c896fe29 FB |
1100 | } |
1101 | ||
a7812ae4 | 1102 | static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1103 | { |
a7812ae4 | 1104 | tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2); |
c896fe29 FB |
1105 | } |
1106 | ||
a7812ae4 | 1107 | static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1108 | { |
34151a20 FB |
1109 | if (arg2 == 0) { |
1110 | tcg_gen_mov_i64(ret, arg1); | |
1111 | } else { | |
a7812ae4 | 1112 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 1113 | tcg_gen_shr_i64(ret, arg1, t0); |
a7812ae4 | 1114 | tcg_temp_free_i64(t0); |
34151a20 | 1115 | } |
c896fe29 FB |
1116 | } |
1117 | ||
a7812ae4 | 1118 | static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1119 | { |
a7812ae4 | 1120 | tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2); |
c896fe29 FB |
1121 | } |
1122 | ||
a7812ae4 | 1123 | static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1124 | { |
34151a20 FB |
1125 | if (arg2 == 0) { |
1126 | tcg_gen_mov_i64(ret, arg1); | |
1127 | } else { | |
a7812ae4 | 1128 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 1129 | tcg_gen_sar_i64(ret, arg1, t0); |
a7812ae4 | 1130 | tcg_temp_free_i64(t0); |
34151a20 | 1131 | } |
c896fe29 FB |
1132 | } |
1133 | ||
a7812ae4 | 1134 | static inline void tcg_gen_brcond_i64(int cond, TCGv_i64 arg1, TCGv_i64 arg2, |
c896fe29 FB |
1135 | int label_index) |
1136 | { | |
a7812ae4 | 1137 | tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index); |
c896fe29 FB |
1138 | } |
1139 | ||
5105c556 AJ |
1140 | static inline void tcg_gen_setcond_i64(int cond, TCGv_i64 ret, |
1141 | TCGv_i64 arg1, TCGv_i64 arg2) | |
1142 | { | |
1143 | tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond); | |
1144 | } | |
1145 | ||
a7812ae4 | 1146 | static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1147 | { |
a7812ae4 | 1148 | tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2); |
c896fe29 FB |
1149 | } |
1150 | ||
1151 | #ifdef TCG_TARGET_HAS_div_i64 | |
a7812ae4 | 1152 | static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1153 | { |
a7812ae4 | 1154 | tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2); |
c896fe29 FB |
1155 | } |
1156 | ||
a7812ae4 | 1157 | static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1158 | { |
a7812ae4 | 1159 | tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2); |
c896fe29 FB |
1160 | } |
1161 | ||
a7812ae4 | 1162 | static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1163 | { |
a7812ae4 | 1164 | tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2); |
c896fe29 FB |
1165 | } |
1166 | ||
a7812ae4 | 1167 | static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1168 | { |
a7812ae4 | 1169 | tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2); |
c896fe29 | 1170 | } |
31d66551 | 1171 | #elif defined(TCG_TARGET_HAS_div2_i64) |
a7812ae4 | 1172 | static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1173 | { |
a7812ae4 PB |
1174 | TCGv_i64 t0; |
1175 | t0 = tcg_temp_new_i64(); | |
c896fe29 | 1176 | tcg_gen_sari_i64(t0, arg1, 63); |
a7812ae4 PB |
1177 | tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2); |
1178 | tcg_temp_free_i64(t0); | |
c896fe29 FB |
1179 | } |
1180 | ||
a7812ae4 | 1181 | static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1182 | { |
a7812ae4 PB |
1183 | TCGv_i64 t0; |
1184 | t0 = tcg_temp_new_i64(); | |
c896fe29 | 1185 | tcg_gen_sari_i64(t0, arg1, 63); |
a7812ae4 PB |
1186 | tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2); |
1187 | tcg_temp_free_i64(t0); | |
c896fe29 FB |
1188 | } |
1189 | ||
a7812ae4 | 1190 | static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1191 | { |
a7812ae4 PB |
1192 | TCGv_i64 t0; |
1193 | t0 = tcg_temp_new_i64(); | |
c896fe29 | 1194 | tcg_gen_movi_i64(t0, 0); |
a7812ae4 PB |
1195 | tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2); |
1196 | tcg_temp_free_i64(t0); | |
c896fe29 FB |
1197 | } |
1198 | ||
a7812ae4 | 1199 | static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1200 | { |
a7812ae4 PB |
1201 | TCGv_i64 t0; |
1202 | t0 = tcg_temp_new_i64(); | |
c896fe29 | 1203 | tcg_gen_movi_i64(t0, 0); |
a7812ae4 PB |
1204 | tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2); |
1205 | tcg_temp_free_i64(t0); | |
c896fe29 | 1206 | } |
31d66551 AJ |
1207 | #else |
1208 | static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) | |
1209 | { | |
1210 | tcg_gen_helper64(tcg_helper_div_i64, ret, arg1, arg2); | |
1211 | } | |
1212 | ||
1213 | static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) | |
1214 | { | |
1215 | tcg_gen_helper64(tcg_helper_rem_i64, ret, arg1, arg2); | |
1216 | } | |
1217 | ||
1218 | static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) | |
1219 | { | |
1220 | tcg_gen_helper64(tcg_helper_divu_i64, ret, arg1, arg2); | |
1221 | } | |
1222 | ||
1223 | static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) | |
1224 | { | |
1225 | tcg_gen_helper64(tcg_helper_remu_i64, ret, arg1, arg2); | |
1226 | } | |
c896fe29 FB |
1227 | #endif |
1228 | ||
1229 | #endif | |
1230 | ||
a7812ae4 | 1231 | static inline void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
6359706f AJ |
1232 | { |
1233 | /* some cases can be optimized here */ | |
1234 | if (arg2 == 0) { | |
1235 | tcg_gen_mov_i64(ret, arg1); | |
1236 | } else { | |
a7812ae4 | 1237 | TCGv_i64 t0 = tcg_const_i64(arg2); |
6359706f | 1238 | tcg_gen_add_i64(ret, arg1, t0); |
a7812ae4 | 1239 | tcg_temp_free_i64(t0); |
6359706f AJ |
1240 | } |
1241 | } | |
1242 | ||
a7812ae4 | 1243 | static inline void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2) |
0045734a | 1244 | { |
a7812ae4 | 1245 | TCGv_i64 t0 = tcg_const_i64(arg1); |
0045734a | 1246 | tcg_gen_sub_i64(ret, t0, arg2); |
a7812ae4 | 1247 | tcg_temp_free_i64(t0); |
0045734a AJ |
1248 | } |
1249 | ||
a7812ae4 | 1250 | static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
6359706f AJ |
1251 | { |
1252 | /* some cases can be optimized here */ | |
1253 | if (arg2 == 0) { | |
1254 | tcg_gen_mov_i64(ret, arg1); | |
1255 | } else { | |
a7812ae4 | 1256 | TCGv_i64 t0 = tcg_const_i64(arg2); |
6359706f | 1257 | tcg_gen_sub_i64(ret, arg1, t0); |
a7812ae4 | 1258 | tcg_temp_free_i64(t0); |
6359706f AJ |
1259 | } |
1260 | } | |
a7812ae4 | 1261 | static inline void tcg_gen_brcondi_i64(int cond, TCGv_i64 arg1, int64_t arg2, |
f02bb954 AJ |
1262 | int label_index) |
1263 | { | |
a7812ae4 | 1264 | TCGv_i64 t0 = tcg_const_i64(arg2); |
f02bb954 | 1265 | tcg_gen_brcond_i64(cond, arg1, t0, label_index); |
a7812ae4 | 1266 | tcg_temp_free_i64(t0); |
f02bb954 AJ |
1267 | } |
1268 | ||
5105c556 AJ |
1269 | static inline void tcg_gen_setcondi_i64(int cond, TCGv_i64 ret, TCGv_i64 arg1, |
1270 | int64_t arg2) | |
1271 | { | |
1272 | TCGv_i64 t0 = tcg_const_i64(arg2); | |
1273 | tcg_gen_setcond_i64(cond, ret, arg1, t0); | |
1274 | tcg_temp_free_i64(t0); | |
1275 | } | |
1276 | ||
a7812ae4 | 1277 | static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
f02bb954 | 1278 | { |
a7812ae4 | 1279 | TCGv_i64 t0 = tcg_const_i64(arg2); |
f02bb954 | 1280 | tcg_gen_mul_i64(ret, arg1, t0); |
a7812ae4 | 1281 | tcg_temp_free_i64(t0); |
f02bb954 AJ |
1282 | } |
1283 | ||
6359706f | 1284 | |
c896fe29 FB |
1285 | /***************************************/ |
1286 | /* optional operations */ | |
1287 | ||
a7812ae4 | 1288 | static inline void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 FB |
1289 | { |
1290 | #ifdef TCG_TARGET_HAS_ext8s_i32 | |
a7812ae4 | 1291 | tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg); |
c896fe29 FB |
1292 | #else |
1293 | tcg_gen_shli_i32(ret, arg, 24); | |
5ff9d6a4 | 1294 | tcg_gen_sari_i32(ret, ret, 24); |
c896fe29 FB |
1295 | #endif |
1296 | } | |
1297 | ||
a7812ae4 | 1298 | static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 FB |
1299 | { |
1300 | #ifdef TCG_TARGET_HAS_ext16s_i32 | |
a7812ae4 | 1301 | tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg); |
c896fe29 FB |
1302 | #else |
1303 | tcg_gen_shli_i32(ret, arg, 16); | |
5ff9d6a4 | 1304 | tcg_gen_sari_i32(ret, ret, 16); |
c896fe29 FB |
1305 | #endif |
1306 | } | |
1307 | ||
a7812ae4 | 1308 | static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg) |
86831435 | 1309 | { |
cfc86988 AJ |
1310 | #ifdef TCG_TARGET_HAS_ext8u_i32 |
1311 | tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg); | |
1312 | #else | |
86831435 | 1313 | tcg_gen_andi_i32(ret, arg, 0xffu); |
cfc86988 | 1314 | #endif |
86831435 PB |
1315 | } |
1316 | ||
a7812ae4 | 1317 | static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg) |
86831435 | 1318 | { |
cfc86988 AJ |
1319 | #ifdef TCG_TARGET_HAS_ext16u_i32 |
1320 | tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg); | |
1321 | #else | |
86831435 | 1322 | tcg_gen_andi_i32(ret, arg, 0xffffu); |
cfc86988 | 1323 | #endif |
86831435 PB |
1324 | } |
1325 | ||
c896fe29 | 1326 | /* Note: we assume the two high bytes are set to zero */ |
a7812ae4 | 1327 | static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 FB |
1328 | { |
1329 | #ifdef TCG_TARGET_HAS_bswap16_i32 | |
a7812ae4 | 1330 | tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg); |
c896fe29 | 1331 | #else |
dfa1a3f1 | 1332 | TCGv_i32 t0 = tcg_temp_new_i32(); |
c896fe29 | 1333 | |
dfa1a3f1 AJ |
1334 | tcg_gen_ext8u_i32(t0, arg); |
1335 | tcg_gen_shli_i32(t0, t0, 8); | |
1336 | tcg_gen_shri_i32(ret, arg, 8); | |
1337 | tcg_gen_or_i32(ret, ret, t0); | |
a7812ae4 | 1338 | tcg_temp_free_i32(t0); |
c896fe29 FB |
1339 | #endif |
1340 | } | |
1341 | ||
66896cb8 | 1342 | static inline void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 | 1343 | { |
66896cb8 AJ |
1344 | #ifdef TCG_TARGET_HAS_bswap32_i32 |
1345 | tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg); | |
c896fe29 | 1346 | #else |
a7812ae4 PB |
1347 | TCGv_i32 t0, t1; |
1348 | t0 = tcg_temp_new_i32(); | |
1349 | t1 = tcg_temp_new_i32(); | |
c896fe29 FB |
1350 | |
1351 | tcg_gen_shli_i32(t0, arg, 24); | |
1352 | ||
1353 | tcg_gen_andi_i32(t1, arg, 0x0000ff00); | |
1354 | tcg_gen_shli_i32(t1, t1, 8); | |
1355 | tcg_gen_or_i32(t0, t0, t1); | |
1356 | ||
1357 | tcg_gen_shri_i32(t1, arg, 8); | |
1358 | tcg_gen_andi_i32(t1, t1, 0x0000ff00); | |
1359 | tcg_gen_or_i32(t0, t0, t1); | |
1360 | ||
1361 | tcg_gen_shri_i32(t1, arg, 24); | |
1362 | tcg_gen_or_i32(ret, t0, t1); | |
a7812ae4 PB |
1363 | tcg_temp_free_i32(t0); |
1364 | tcg_temp_free_i32(t1); | |
c896fe29 FB |
1365 | #endif |
1366 | } | |
1367 | ||
1368 | #if TCG_TARGET_REG_BITS == 32 | |
a7812ae4 | 1369 | static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1370 | { |
a7812ae4 PB |
1371 | tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1372 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
1373 | } |
1374 | ||
a7812ae4 | 1375 | static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1376 | { |
a7812ae4 PB |
1377 | tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1378 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
1379 | } |
1380 | ||
a7812ae4 | 1381 | static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1382 | { |
a7812ae4 PB |
1383 | tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1384 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
1385 | } |
1386 | ||
a7812ae4 | 1387 | static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1388 | { |
a7812ae4 | 1389 | tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
86831435 PB |
1390 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
1391 | } | |
1392 | ||
a7812ae4 | 1393 | static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1394 | { |
a7812ae4 | 1395 | tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
86831435 PB |
1396 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
1397 | } | |
1398 | ||
a7812ae4 | 1399 | static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1400 | { |
a7812ae4 | 1401 | tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
86831435 PB |
1402 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
1403 | } | |
1404 | ||
a7812ae4 | 1405 | static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg) |
c896fe29 | 1406 | { |
a7812ae4 | 1407 | tcg_gen_mov_i32(ret, TCGV_LOW(arg)); |
c896fe29 FB |
1408 | } |
1409 | ||
a7812ae4 | 1410 | static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
c896fe29 | 1411 | { |
a7812ae4 | 1412 | tcg_gen_mov_i32(TCGV_LOW(ret), arg); |
ac56dd48 | 1413 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
1414 | } |
1415 | ||
a7812ae4 | 1416 | static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
c896fe29 | 1417 | { |
a7812ae4 PB |
1418 | tcg_gen_mov_i32(TCGV_LOW(ret), arg); |
1419 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
1420 | } |
1421 | ||
9a5c57fd AJ |
1422 | /* Note: we assume the six high bytes are set to zero */ |
1423 | static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg) | |
1424 | { | |
1425 | tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); | |
1426 | tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg)); | |
1427 | } | |
1428 | ||
1429 | /* Note: we assume the four high bytes are set to zero */ | |
1430 | static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) | |
1431 | { | |
1432 | tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); | |
1433 | tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg)); | |
1434 | } | |
1435 | ||
66896cb8 | 1436 | static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1437 | { |
a7812ae4 PB |
1438 | TCGv_i32 t0, t1; |
1439 | t0 = tcg_temp_new_i32(); | |
1440 | t1 = tcg_temp_new_i32(); | |
c896fe29 | 1441 | |
66896cb8 AJ |
1442 | tcg_gen_bswap32_i32(t0, TCGV_LOW(arg)); |
1443 | tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg)); | |
a7812ae4 | 1444 | tcg_gen_mov_i32(TCGV_LOW(ret), t1); |
ac56dd48 | 1445 | tcg_gen_mov_i32(TCGV_HIGH(ret), t0); |
a7812ae4 PB |
1446 | tcg_temp_free_i32(t0); |
1447 | tcg_temp_free_i32(t1); | |
c896fe29 FB |
1448 | } |
1449 | #else | |
1450 | ||
a7812ae4 | 1451 | static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 FB |
1452 | { |
1453 | #ifdef TCG_TARGET_HAS_ext8s_i64 | |
a7812ae4 | 1454 | tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg); |
c896fe29 FB |
1455 | #else |
1456 | tcg_gen_shli_i64(ret, arg, 56); | |
5ff9d6a4 | 1457 | tcg_gen_sari_i64(ret, ret, 56); |
c896fe29 FB |
1458 | #endif |
1459 | } | |
1460 | ||
a7812ae4 | 1461 | static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 FB |
1462 | { |
1463 | #ifdef TCG_TARGET_HAS_ext16s_i64 | |
a7812ae4 | 1464 | tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg); |
c896fe29 FB |
1465 | #else |
1466 | tcg_gen_shli_i64(ret, arg, 48); | |
5ff9d6a4 | 1467 | tcg_gen_sari_i64(ret, ret, 48); |
c896fe29 FB |
1468 | #endif |
1469 | } | |
1470 | ||
a7812ae4 | 1471 | static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 FB |
1472 | { |
1473 | #ifdef TCG_TARGET_HAS_ext32s_i64 | |
a7812ae4 | 1474 | tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg); |
c896fe29 FB |
1475 | #else |
1476 | tcg_gen_shli_i64(ret, arg, 32); | |
5ff9d6a4 | 1477 | tcg_gen_sari_i64(ret, ret, 32); |
c896fe29 FB |
1478 | #endif |
1479 | } | |
1480 | ||
a7812ae4 | 1481 | static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1482 | { |
cfc86988 AJ |
1483 | #ifdef TCG_TARGET_HAS_ext8u_i64 |
1484 | tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg); | |
1485 | #else | |
86831435 | 1486 | tcg_gen_andi_i64(ret, arg, 0xffu); |
cfc86988 | 1487 | #endif |
86831435 PB |
1488 | } |
1489 | ||
a7812ae4 | 1490 | static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1491 | { |
cfc86988 AJ |
1492 | #ifdef TCG_TARGET_HAS_ext16u_i64 |
1493 | tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg); | |
1494 | #else | |
86831435 | 1495 | tcg_gen_andi_i64(ret, arg, 0xffffu); |
cfc86988 | 1496 | #endif |
86831435 PB |
1497 | } |
1498 | ||
a7812ae4 | 1499 | static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1500 | { |
cfc86988 AJ |
1501 | #ifdef TCG_TARGET_HAS_ext32u_i64 |
1502 | tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg); | |
1503 | #else | |
86831435 | 1504 | tcg_gen_andi_i64(ret, arg, 0xffffffffu); |
cfc86988 | 1505 | #endif |
86831435 PB |
1506 | } |
1507 | ||
c896fe29 | 1508 | /* Note: we assume the target supports move between 32 and 64 bit |
ac56dd48 | 1509 | registers. This will probably break MIPS64 targets. */ |
a7812ae4 | 1510 | static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg) |
c896fe29 | 1511 | { |
a7812ae4 | 1512 | tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg))); |
c896fe29 FB |
1513 | } |
1514 | ||
1515 | /* Note: we assume the target supports move between 32 and 64 bit | |
1516 | registers */ | |
a7812ae4 | 1517 | static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
c896fe29 | 1518 | { |
cfc86988 | 1519 | tcg_gen_ext32u_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg))); |
c896fe29 FB |
1520 | } |
1521 | ||
1522 | /* Note: we assume the target supports move between 32 and 64 bit | |
1523 | registers */ | |
a7812ae4 | 1524 | static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
c896fe29 | 1525 | { |
a7812ae4 | 1526 | tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg))); |
c896fe29 FB |
1527 | } |
1528 | ||
9a5c57fd AJ |
1529 | /* Note: we assume the six high bytes are set to zero */ |
1530 | static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg) | |
1531 | { | |
1532 | #ifdef TCG_TARGET_HAS_bswap16_i64 | |
1533 | tcg_gen_op2_i64(INDEX_op_bswap16_i64, ret, arg); | |
1534 | #else | |
1535 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
1536 | ||
1537 | tcg_gen_ext8u_i64(t0, arg); | |
1538 | tcg_gen_shli_i64(t0, t0, 8); | |
1539 | tcg_gen_shri_i64(ret, arg, 8); | |
1540 | tcg_gen_or_i64(ret, ret, t0); | |
1541 | tcg_temp_free_i64(t0); | |
1542 | #endif | |
1543 | } | |
1544 | ||
1545 | /* Note: we assume the four high bytes are set to zero */ | |
1546 | static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) | |
1547 | { | |
1548 | #ifdef TCG_TARGET_HAS_bswap32_i64 | |
1549 | tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg); | |
1550 | #else | |
1551 | TCGv_i64 t0, t1; | |
1552 | t0 = tcg_temp_new_i64(); | |
1553 | t1 = tcg_temp_new_i64(); | |
1554 | ||
1555 | tcg_gen_shli_i64(t0, arg, 24); | |
1556 | tcg_gen_ext32u_i64(t0, t0); | |
1557 | ||
1558 | tcg_gen_andi_i64(t1, arg, 0x0000ff00); | |
1559 | tcg_gen_shli_i64(t1, t1, 8); | |
1560 | tcg_gen_or_i64(t0, t0, t1); | |
1561 | ||
1562 | tcg_gen_shri_i64(t1, arg, 8); | |
1563 | tcg_gen_andi_i64(t1, t1, 0x0000ff00); | |
1564 | tcg_gen_or_i64(t0, t0, t1); | |
1565 | ||
1566 | tcg_gen_shri_i64(t1, arg, 24); | |
1567 | tcg_gen_or_i64(ret, t0, t1); | |
1568 | tcg_temp_free_i64(t0); | |
1569 | tcg_temp_free_i64(t1); | |
1570 | #endif | |
1571 | } | |
1572 | ||
66896cb8 | 1573 | static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1574 | { |
66896cb8 AJ |
1575 | #ifdef TCG_TARGET_HAS_bswap64_i64 |
1576 | tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg); | |
c896fe29 | 1577 | #else |
b348113d SW |
1578 | TCGv_i64 t0 = tcg_temp_new_i64(); |
1579 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
c896fe29 FB |
1580 | |
1581 | tcg_gen_shli_i64(t0, arg, 56); | |
1582 | ||
1583 | tcg_gen_andi_i64(t1, arg, 0x0000ff00); | |
1584 | tcg_gen_shli_i64(t1, t1, 40); | |
1585 | tcg_gen_or_i64(t0, t0, t1); | |
1586 | ||
1587 | tcg_gen_andi_i64(t1, arg, 0x00ff0000); | |
1588 | tcg_gen_shli_i64(t1, t1, 24); | |
1589 | tcg_gen_or_i64(t0, t0, t1); | |
1590 | ||
1591 | tcg_gen_andi_i64(t1, arg, 0xff000000); | |
1592 | tcg_gen_shli_i64(t1, t1, 8); | |
1593 | tcg_gen_or_i64(t0, t0, t1); | |
1594 | ||
1595 | tcg_gen_shri_i64(t1, arg, 8); | |
1596 | tcg_gen_andi_i64(t1, t1, 0xff000000); | |
1597 | tcg_gen_or_i64(t0, t0, t1); | |
1598 | ||
1599 | tcg_gen_shri_i64(t1, arg, 24); | |
1600 | tcg_gen_andi_i64(t1, t1, 0x00ff0000); | |
1601 | tcg_gen_or_i64(t0, t0, t1); | |
1602 | ||
1603 | tcg_gen_shri_i64(t1, arg, 40); | |
1604 | tcg_gen_andi_i64(t1, t1, 0x0000ff00); | |
1605 | tcg_gen_or_i64(t0, t0, t1); | |
1606 | ||
1607 | tcg_gen_shri_i64(t1, arg, 56); | |
1608 | tcg_gen_or_i64(ret, t0, t1); | |
b348113d SW |
1609 | tcg_temp_free_i64(t0); |
1610 | tcg_temp_free_i64(t1); | |
c896fe29 FB |
1611 | #endif |
1612 | } | |
1613 | ||
1614 | #endif | |
1615 | ||
a7812ae4 | 1616 | static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg) |
390efc54 PB |
1617 | { |
1618 | #ifdef TCG_TARGET_HAS_neg_i32 | |
a7812ae4 | 1619 | tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg); |
390efc54 | 1620 | #else |
a7812ae4 | 1621 | TCGv_i32 t0 = tcg_const_i32(0); |
e8996ee0 | 1622 | tcg_gen_sub_i32(ret, t0, arg); |
a7812ae4 | 1623 | tcg_temp_free_i32(t0); |
390efc54 PB |
1624 | #endif |
1625 | } | |
1626 | ||
a7812ae4 | 1627 | static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg) |
390efc54 PB |
1628 | { |
1629 | #ifdef TCG_TARGET_HAS_neg_i64 | |
a7812ae4 | 1630 | tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg); |
390efc54 | 1631 | #else |
a7812ae4 | 1632 | TCGv_i64 t0 = tcg_const_i64(0); |
e8996ee0 | 1633 | tcg_gen_sub_i64(ret, t0, arg); |
a7812ae4 | 1634 | tcg_temp_free_i64(t0); |
390efc54 PB |
1635 | #endif |
1636 | } | |
1637 | ||
a7812ae4 | 1638 | static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) |
0b6ce4cf | 1639 | { |
d2604285 AJ |
1640 | #ifdef TCG_TARGET_HAS_not_i32 |
1641 | tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg); | |
1642 | #else | |
e8996ee0 | 1643 | tcg_gen_xori_i32(ret, arg, -1); |
d2604285 | 1644 | #endif |
0b6ce4cf FB |
1645 | } |
1646 | ||
a7812ae4 | 1647 | static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg) |
0b6ce4cf | 1648 | { |
d2604285 | 1649 | #ifdef TCG_TARGET_HAS_not_i64 |
43e860ef | 1650 | tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg); |
d2604285 | 1651 | #else |
e8996ee0 | 1652 | tcg_gen_xori_i64(ret, arg, -1); |
d2604285 | 1653 | #endif |
0b6ce4cf | 1654 | } |
5ff9d6a4 | 1655 | |
a7812ae4 | 1656 | static inline void tcg_gen_discard_i32(TCGv_i32 arg) |
5ff9d6a4 | 1657 | { |
a7812ae4 | 1658 | tcg_gen_op1_i32(INDEX_op_discard, arg); |
5ff9d6a4 FB |
1659 | } |
1660 | ||
1661 | #if TCG_TARGET_REG_BITS == 32 | |
a7812ae4 | 1662 | static inline void tcg_gen_discard_i64(TCGv_i64 arg) |
5ff9d6a4 | 1663 | { |
a7812ae4 | 1664 | tcg_gen_discard_i32(TCGV_LOW(arg)); |
5ff9d6a4 FB |
1665 | tcg_gen_discard_i32(TCGV_HIGH(arg)); |
1666 | } | |
1667 | #else | |
a7812ae4 | 1668 | static inline void tcg_gen_discard_i64(TCGv_i64 arg) |
5ff9d6a4 | 1669 | { |
a7812ae4 | 1670 | tcg_gen_op1_i64(INDEX_op_discard, arg); |
5ff9d6a4 FB |
1671 | } |
1672 | #endif | |
1673 | ||
a7812ae4 | 1674 | static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high) |
36aa55dc PB |
1675 | { |
1676 | #if TCG_TARGET_REG_BITS == 32 | |
a7812ae4 | 1677 | tcg_gen_mov_i32(TCGV_LOW(dest), low); |
36aa55dc PB |
1678 | tcg_gen_mov_i32(TCGV_HIGH(dest), high); |
1679 | #else | |
a7812ae4 | 1680 | TCGv_i64 tmp = tcg_temp_new_i64(); |
36aa55dc PB |
1681 | /* This extension is only needed for type correctness. |
1682 | We may be able to do better given target specific information. */ | |
1683 | tcg_gen_extu_i32_i64(tmp, high); | |
1684 | tcg_gen_shli_i64(tmp, tmp, 32); | |
1685 | tcg_gen_extu_i32_i64(dest, low); | |
1686 | tcg_gen_or_i64(dest, dest, tmp); | |
a7812ae4 | 1687 | tcg_temp_free_i64(tmp); |
36aa55dc PB |
1688 | #endif |
1689 | } | |
1690 | ||
a7812ae4 | 1691 | static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 high) |
945ca823 BS |
1692 | { |
1693 | #if TCG_TARGET_REG_BITS == 32 | |
a7812ae4 | 1694 | tcg_gen_concat_i32_i64(dest, TCGV_LOW(low), TCGV_LOW(high)); |
945ca823 | 1695 | #else |
a7812ae4 | 1696 | TCGv_i64 tmp = tcg_temp_new_i64(); |
88422e2e | 1697 | tcg_gen_ext32u_i64(dest, low); |
945ca823 | 1698 | tcg_gen_shli_i64(tmp, high, 32); |
88422e2e | 1699 | tcg_gen_or_i64(dest, dest, tmp); |
a7812ae4 | 1700 | tcg_temp_free_i64(tmp); |
945ca823 BS |
1701 | #endif |
1702 | } | |
1703 | ||
a7812ae4 | 1704 | static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
f24cb33e | 1705 | { |
241cbed4 RH |
1706 | #ifdef TCG_TARGET_HAS_andc_i32 |
1707 | tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2); | |
1708 | #else | |
a7812ae4 PB |
1709 | TCGv_i32 t0; |
1710 | t0 = tcg_temp_new_i32(); | |
f24cb33e AJ |
1711 | tcg_gen_not_i32(t0, arg2); |
1712 | tcg_gen_and_i32(ret, arg1, t0); | |
a7812ae4 | 1713 | tcg_temp_free_i32(t0); |
241cbed4 | 1714 | #endif |
f24cb33e AJ |
1715 | } |
1716 | ||
a7812ae4 | 1717 | static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
f24cb33e | 1718 | { |
241cbed4 RH |
1719 | #ifdef TCG_TARGET_HAS_andc_i64 |
1720 | tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2); | |
1721 | #elif defined(TCG_TARGET_HAS_andc_i32) && TCG_TARGET_REG_BITS == 32 | |
1722 | tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); | |
1723 | tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); | |
1724 | #else | |
a7812ae4 PB |
1725 | TCGv_i64 t0; |
1726 | t0 = tcg_temp_new_i64(); | |
f24cb33e AJ |
1727 | tcg_gen_not_i64(t0, arg2); |
1728 | tcg_gen_and_i64(ret, arg1, t0); | |
a7812ae4 | 1729 | tcg_temp_free_i64(t0); |
241cbed4 | 1730 | #endif |
f24cb33e AJ |
1731 | } |
1732 | ||
a7812ae4 | 1733 | static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
f24cb33e | 1734 | { |
7fc81051 AJ |
1735 | tcg_gen_xor_i32(ret, arg1, arg2); |
1736 | tcg_gen_not_i32(ret, ret); | |
f24cb33e AJ |
1737 | } |
1738 | ||
a7812ae4 | 1739 | static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
f24cb33e | 1740 | { |
7fc81051 AJ |
1741 | tcg_gen_xor_i64(ret, arg1, arg2); |
1742 | tcg_gen_not_i64(ret, ret); | |
f24cb33e AJ |
1743 | } |
1744 | ||
a7812ae4 | 1745 | static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
f24cb33e | 1746 | { |
7fc81051 AJ |
1747 | tcg_gen_and_i32(ret, arg1, arg2); |
1748 | tcg_gen_not_i32(ret, ret); | |
f24cb33e AJ |
1749 | } |
1750 | ||
a7812ae4 | 1751 | static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
f24cb33e | 1752 | { |
7fc81051 AJ |
1753 | tcg_gen_and_i64(ret, arg1, arg2); |
1754 | tcg_gen_not_i64(ret, ret); | |
f24cb33e AJ |
1755 | } |
1756 | ||
a7812ae4 | 1757 | static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
f24cb33e | 1758 | { |
7fc81051 AJ |
1759 | tcg_gen_or_i32(ret, arg1, arg2); |
1760 | tcg_gen_not_i32(ret, ret); | |
f24cb33e AJ |
1761 | } |
1762 | ||
a7812ae4 | 1763 | static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
f24cb33e | 1764 | { |
7fc81051 AJ |
1765 | tcg_gen_or_i64(ret, arg1, arg2); |
1766 | tcg_gen_not_i64(ret, ret); | |
f24cb33e AJ |
1767 | } |
1768 | ||
a7812ae4 | 1769 | static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
f24cb33e | 1770 | { |
791d1262 RH |
1771 | #ifdef TCG_TARGET_HAS_orc_i32 |
1772 | tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2); | |
1773 | #else | |
a7812ae4 PB |
1774 | TCGv_i32 t0; |
1775 | t0 = tcg_temp_new_i32(); | |
f24cb33e AJ |
1776 | tcg_gen_not_i32(t0, arg2); |
1777 | tcg_gen_or_i32(ret, arg1, t0); | |
a7812ae4 | 1778 | tcg_temp_free_i32(t0); |
791d1262 | 1779 | #endif |
f24cb33e AJ |
1780 | } |
1781 | ||
a7812ae4 | 1782 | static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
f24cb33e | 1783 | { |
791d1262 RH |
1784 | #ifdef TCG_TARGET_HAS_orc_i64 |
1785 | tcg_gen_op3_i64(INDEX_op_orc_i64, ret, arg1, arg2); | |
1786 | #elif defined(TCG_TARGET_HAS_orc_i32) && TCG_TARGET_REG_BITS == 32 | |
1787 | tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); | |
1788 | tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); | |
1789 | #else | |
a7812ae4 PB |
1790 | TCGv_i64 t0; |
1791 | t0 = tcg_temp_new_i64(); | |
f24cb33e AJ |
1792 | tcg_gen_not_i64(t0, arg2); |
1793 | tcg_gen_or_i64(ret, arg1, t0); | |
a7812ae4 | 1794 | tcg_temp_free_i64(t0); |
791d1262 | 1795 | #endif |
f24cb33e AJ |
1796 | } |
1797 | ||
a7812ae4 | 1798 | static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
15824571 | 1799 | { |
d42f183c AJ |
1800 | #ifdef TCG_TARGET_HAS_rot_i32 |
1801 | tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2); | |
1802 | #else | |
a7812ae4 | 1803 | TCGv_i32 t0, t1; |
15824571 | 1804 | |
a7812ae4 PB |
1805 | t0 = tcg_temp_new_i32(); |
1806 | t1 = tcg_temp_new_i32(); | |
15824571 AJ |
1807 | tcg_gen_shl_i32(t0, arg1, arg2); |
1808 | tcg_gen_subfi_i32(t1, 32, arg2); | |
1809 | tcg_gen_shr_i32(t1, arg1, t1); | |
1810 | tcg_gen_or_i32(ret, t0, t1); | |
a7812ae4 PB |
1811 | tcg_temp_free_i32(t0); |
1812 | tcg_temp_free_i32(t1); | |
d42f183c | 1813 | #endif |
15824571 AJ |
1814 | } |
1815 | ||
a7812ae4 | 1816 | static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
15824571 | 1817 | { |
d42f183c AJ |
1818 | #ifdef TCG_TARGET_HAS_rot_i64 |
1819 | tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2); | |
1820 | #else | |
a7812ae4 | 1821 | TCGv_i64 t0, t1; |
15824571 | 1822 | |
a7812ae4 PB |
1823 | t0 = tcg_temp_new_i64(); |
1824 | t1 = tcg_temp_new_i64(); | |
15824571 AJ |
1825 | tcg_gen_shl_i64(t0, arg1, arg2); |
1826 | tcg_gen_subfi_i64(t1, 64, arg2); | |
1827 | tcg_gen_shr_i64(t1, arg1, t1); | |
1828 | tcg_gen_or_i64(ret, t0, t1); | |
a7812ae4 PB |
1829 | tcg_temp_free_i64(t0); |
1830 | tcg_temp_free_i64(t1); | |
d42f183c | 1831 | #endif |
15824571 AJ |
1832 | } |
1833 | ||
a7812ae4 | 1834 | static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
15824571 AJ |
1835 | { |
1836 | /* some cases can be optimized here */ | |
1837 | if (arg2 == 0) { | |
1838 | tcg_gen_mov_i32(ret, arg1); | |
1839 | } else { | |
d42f183c AJ |
1840 | #ifdef TCG_TARGET_HAS_rot_i32 |
1841 | TCGv_i32 t0 = tcg_const_i32(arg2); | |
1842 | tcg_gen_rotl_i32(ret, arg1, t0); | |
1843 | tcg_temp_free_i32(t0); | |
1844 | #else | |
a7812ae4 PB |
1845 | TCGv_i32 t0, t1; |
1846 | t0 = tcg_temp_new_i32(); | |
1847 | t1 = tcg_temp_new_i32(); | |
15824571 AJ |
1848 | tcg_gen_shli_i32(t0, arg1, arg2); |
1849 | tcg_gen_shri_i32(t1, arg1, 32 - arg2); | |
1850 | tcg_gen_or_i32(ret, t0, t1); | |
a7812ae4 PB |
1851 | tcg_temp_free_i32(t0); |
1852 | tcg_temp_free_i32(t1); | |
d42f183c | 1853 | #endif |
15824571 AJ |
1854 | } |
1855 | } | |
1856 | ||
a7812ae4 | 1857 | static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
15824571 AJ |
1858 | { |
1859 | /* some cases can be optimized here */ | |
1860 | if (arg2 == 0) { | |
1861 | tcg_gen_mov_i64(ret, arg1); | |
1862 | } else { | |
d42f183c AJ |
1863 | #ifdef TCG_TARGET_HAS_rot_i64 |
1864 | TCGv_i64 t0 = tcg_const_i64(arg2); | |
1865 | tcg_gen_rotl_i64(ret, arg1, t0); | |
1866 | tcg_temp_free_i64(t0); | |
1867 | #else | |
a7812ae4 PB |
1868 | TCGv_i64 t0, t1; |
1869 | t0 = tcg_temp_new_i64(); | |
1870 | t1 = tcg_temp_new_i64(); | |
15824571 AJ |
1871 | tcg_gen_shli_i64(t0, arg1, arg2); |
1872 | tcg_gen_shri_i64(t1, arg1, 64 - arg2); | |
1873 | tcg_gen_or_i64(ret, t0, t1); | |
a7812ae4 PB |
1874 | tcg_temp_free_i64(t0); |
1875 | tcg_temp_free_i64(t1); | |
d42f183c | 1876 | #endif |
15824571 AJ |
1877 | } |
1878 | } | |
1879 | ||
a7812ae4 | 1880 | static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
15824571 | 1881 | { |
d42f183c AJ |
1882 | #ifdef TCG_TARGET_HAS_rot_i32 |
1883 | tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2); | |
1884 | #else | |
a7812ae4 | 1885 | TCGv_i32 t0, t1; |
15824571 | 1886 | |
a7812ae4 PB |
1887 | t0 = tcg_temp_new_i32(); |
1888 | t1 = tcg_temp_new_i32(); | |
15824571 AJ |
1889 | tcg_gen_shr_i32(t0, arg1, arg2); |
1890 | tcg_gen_subfi_i32(t1, 32, arg2); | |
1891 | tcg_gen_shl_i32(t1, arg1, t1); | |
1892 | tcg_gen_or_i32(ret, t0, t1); | |
a7812ae4 PB |
1893 | tcg_temp_free_i32(t0); |
1894 | tcg_temp_free_i32(t1); | |
d42f183c | 1895 | #endif |
15824571 AJ |
1896 | } |
1897 | ||
a7812ae4 | 1898 | static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
15824571 | 1899 | { |
d42f183c AJ |
1900 | #ifdef TCG_TARGET_HAS_rot_i64 |
1901 | tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2); | |
1902 | #else | |
a7812ae4 | 1903 | TCGv_i64 t0, t1; |
15824571 | 1904 | |
a7812ae4 PB |
1905 | t0 = tcg_temp_new_i64(); |
1906 | t1 = tcg_temp_new_i64(); | |
d9885a0b | 1907 | tcg_gen_shr_i64(t0, arg1, arg2); |
15824571 AJ |
1908 | tcg_gen_subfi_i64(t1, 64, arg2); |
1909 | tcg_gen_shl_i64(t1, arg1, t1); | |
1910 | tcg_gen_or_i64(ret, t0, t1); | |
a7812ae4 PB |
1911 | tcg_temp_free_i64(t0); |
1912 | tcg_temp_free_i64(t1); | |
d42f183c | 1913 | #endif |
15824571 AJ |
1914 | } |
1915 | ||
a7812ae4 | 1916 | static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
15824571 AJ |
1917 | { |
1918 | /* some cases can be optimized here */ | |
1919 | if (arg2 == 0) { | |
1920 | tcg_gen_mov_i32(ret, arg1); | |
1921 | } else { | |
1922 | tcg_gen_rotli_i32(ret, arg1, 32 - arg2); | |
1923 | } | |
1924 | } | |
1925 | ||
a7812ae4 | 1926 | static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
15824571 AJ |
1927 | { |
1928 | /* some cases can be optimized here */ | |
1929 | if (arg2 == 0) { | |
de3526b2 | 1930 | tcg_gen_mov_i64(ret, arg1); |
15824571 AJ |
1931 | } else { |
1932 | tcg_gen_rotli_i64(ret, arg1, 64 - arg2); | |
1933 | } | |
1934 | } | |
1935 | ||
c896fe29 FB |
1936 | /***************************************/ |
1937 | /* QEMU specific operations. Their type depend on the QEMU CPU | |
1938 | type. */ | |
1939 | #ifndef TARGET_LONG_BITS | |
1940 | #error must include QEMU headers | |
1941 | #endif | |
1942 | ||
a7812ae4 PB |
1943 | #if TARGET_LONG_BITS == 32 |
1944 | #define TCGv TCGv_i32 | |
1945 | #define tcg_temp_new() tcg_temp_new_i32() | |
1946 | #define tcg_global_reg_new tcg_global_reg_new_i32 | |
1947 | #define tcg_global_mem_new tcg_global_mem_new_i32 | |
df9247b2 | 1948 | #define tcg_temp_local_new() tcg_temp_local_new_i32() |
a7812ae4 PB |
1949 | #define tcg_temp_free tcg_temp_free_i32 |
1950 | #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32 | |
1951 | #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32 | |
1952 | #define TCGV_UNUSED(x) TCGV_UNUSED_I32(x) | |
fe75bcf7 | 1953 | #define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b) |
a7812ae4 PB |
1954 | #else |
1955 | #define TCGv TCGv_i64 | |
1956 | #define tcg_temp_new() tcg_temp_new_i64() | |
1957 | #define tcg_global_reg_new tcg_global_reg_new_i64 | |
1958 | #define tcg_global_mem_new tcg_global_mem_new_i64 | |
df9247b2 | 1959 | #define tcg_temp_local_new() tcg_temp_local_new_i64() |
a7812ae4 PB |
1960 | #define tcg_temp_free tcg_temp_free_i64 |
1961 | #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64 | |
1962 | #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64 | |
1963 | #define TCGV_UNUSED(x) TCGV_UNUSED_I64(x) | |
fe75bcf7 | 1964 | #define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b) |
a7812ae4 PB |
1965 | #endif |
1966 | ||
7e4597d7 FB |
1967 | /* debug info: write the PC of the corresponding QEMU CPU instruction */ |
1968 | static inline void tcg_gen_debug_insn_start(uint64_t pc) | |
1969 | { | |
1970 | /* XXX: must really use a 32 bit size for TCGArg in all cases */ | |
1971 | #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS | |
bcb0126f PB |
1972 | tcg_gen_op2ii(INDEX_op_debug_insn_start, |
1973 | (uint32_t)(pc), (uint32_t)(pc >> 32)); | |
7e4597d7 FB |
1974 | #else |
1975 | tcg_gen_op1i(INDEX_op_debug_insn_start, pc); | |
1976 | #endif | |
1977 | } | |
1978 | ||
c896fe29 FB |
1979 | static inline void tcg_gen_exit_tb(tcg_target_long val) |
1980 | { | |
ac56dd48 | 1981 | tcg_gen_op1i(INDEX_op_exit_tb, val); |
c896fe29 FB |
1982 | } |
1983 | ||
1984 | static inline void tcg_gen_goto_tb(int idx) | |
1985 | { | |
ac56dd48 | 1986 | tcg_gen_op1i(INDEX_op_goto_tb, idx); |
c896fe29 FB |
1987 | } |
1988 | ||
1989 | #if TCG_TARGET_REG_BITS == 32 | |
ac56dd48 | 1990 | static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
1991 | { |
1992 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 1993 | tcg_gen_op3i_i32(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
c896fe29 | 1994 | #else |
a7812ae4 PB |
1995 | tcg_gen_op4i_i32(INDEX_op_qemu_ld8u, TCGV_LOW(ret), TCGV_LOW(addr), |
1996 | TCGV_HIGH(addr), mem_index); | |
ac56dd48 | 1997 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
1998 | #endif |
1999 | } | |
2000 | ||
ac56dd48 | 2001 | static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
2002 | { |
2003 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2004 | tcg_gen_op3i_i32(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
c896fe29 | 2005 | #else |
a7812ae4 PB |
2006 | tcg_gen_op4i_i32(INDEX_op_qemu_ld8s, TCGV_LOW(ret), TCGV_LOW(addr), |
2007 | TCGV_HIGH(addr), mem_index); | |
2008 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
2009 | #endif |
2010 | } | |
2011 | ||
ac56dd48 | 2012 | static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
2013 | { |
2014 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2015 | tcg_gen_op3i_i32(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
c896fe29 | 2016 | #else |
a7812ae4 PB |
2017 | tcg_gen_op4i_i32(INDEX_op_qemu_ld16u, TCGV_LOW(ret), TCGV_LOW(addr), |
2018 | TCGV_HIGH(addr), mem_index); | |
ac56dd48 | 2019 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
2020 | #endif |
2021 | } | |
2022 | ||
ac56dd48 | 2023 | static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
2024 | { |
2025 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2026 | tcg_gen_op3i_i32(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
c896fe29 | 2027 | #else |
a7812ae4 PB |
2028 | tcg_gen_op4i_i32(INDEX_op_qemu_ld16s, TCGV_LOW(ret), TCGV_LOW(addr), |
2029 | TCGV_HIGH(addr), mem_index); | |
2030 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
2031 | #endif |
2032 | } | |
2033 | ||
ac56dd48 | 2034 | static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
2035 | { |
2036 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2037 | tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
c896fe29 | 2038 | #else |
a7812ae4 PB |
2039 | tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr), |
2040 | TCGV_HIGH(addr), mem_index); | |
ac56dd48 | 2041 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
2042 | #endif |
2043 | } | |
2044 | ||
ac56dd48 | 2045 | static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
2046 | { |
2047 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2048 | tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
c896fe29 | 2049 | #else |
a7812ae4 PB |
2050 | tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr), |
2051 | TCGV_HIGH(addr), mem_index); | |
2052 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
2053 | #endif |
2054 | } | |
2055 | ||
a7812ae4 | 2056 | static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) |
c896fe29 FB |
2057 | { |
2058 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2059 | tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index); |
c896fe29 | 2060 | #else |
a7812ae4 PB |
2061 | tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), |
2062 | TCGV_LOW(addr), TCGV_HIGH(addr), mem_index); | |
c896fe29 FB |
2063 | #endif |
2064 | } | |
2065 | ||
ac56dd48 | 2066 | static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
c896fe29 FB |
2067 | { |
2068 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2069 | tcg_gen_op3i_i32(INDEX_op_qemu_st8, arg, addr, mem_index); |
c896fe29 | 2070 | #else |
a7812ae4 PB |
2071 | tcg_gen_op4i_i32(INDEX_op_qemu_st8, TCGV_LOW(arg), TCGV_LOW(addr), |
2072 | TCGV_HIGH(addr), mem_index); | |
c896fe29 FB |
2073 | #endif |
2074 | } | |
2075 | ||
ac56dd48 | 2076 | static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
c896fe29 FB |
2077 | { |
2078 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2079 | tcg_gen_op3i_i32(INDEX_op_qemu_st16, arg, addr, mem_index); |
c896fe29 | 2080 | #else |
a7812ae4 PB |
2081 | tcg_gen_op4i_i32(INDEX_op_qemu_st16, TCGV_LOW(arg), TCGV_LOW(addr), |
2082 | TCGV_HIGH(addr), mem_index); | |
c896fe29 FB |
2083 | #endif |
2084 | } | |
2085 | ||
ac56dd48 | 2086 | static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
c896fe29 FB |
2087 | { |
2088 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2089 | tcg_gen_op3i_i32(INDEX_op_qemu_st32, arg, addr, mem_index); |
c896fe29 | 2090 | #else |
a7812ae4 PB |
2091 | tcg_gen_op4i_i32(INDEX_op_qemu_st32, TCGV_LOW(arg), TCGV_LOW(addr), |
2092 | TCGV_HIGH(addr), mem_index); | |
c896fe29 FB |
2093 | #endif |
2094 | } | |
2095 | ||
a7812ae4 | 2096 | static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) |
c896fe29 FB |
2097 | { |
2098 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 PB |
2099 | tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr, |
2100 | mem_index); | |
c896fe29 | 2101 | #else |
a7812ae4 PB |
2102 | tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), |
2103 | TCGV_LOW(addr), TCGV_HIGH(addr), mem_index); | |
c896fe29 FB |
2104 | #endif |
2105 | } | |
2106 | ||
56b8f567 | 2107 | #define tcg_gen_ld_ptr tcg_gen_ld_i32 |
a768e4b2 | 2108 | #define tcg_gen_discard_ptr tcg_gen_discard_i32 |
f8422f52 | 2109 | |
c896fe29 FB |
2110 | #else /* TCG_TARGET_REG_BITS == 32 */ |
2111 | ||
ac56dd48 | 2112 | static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 2113 | { |
a7812ae4 | 2114 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
c896fe29 FB |
2115 | } |
2116 | ||
ac56dd48 | 2117 | static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 2118 | { |
a7812ae4 | 2119 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
c896fe29 FB |
2120 | } |
2121 | ||
ac56dd48 | 2122 | static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 2123 | { |
a7812ae4 | 2124 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
c896fe29 FB |
2125 | } |
2126 | ||
ac56dd48 | 2127 | static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 2128 | { |
a7812ae4 | 2129 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
c896fe29 FB |
2130 | } |
2131 | ||
ac56dd48 | 2132 | static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 2133 | { |
a7812ae4 | 2134 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
c896fe29 FB |
2135 | } |
2136 | ||
ac56dd48 | 2137 | static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 2138 | { |
a7812ae4 | 2139 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32s, ret, addr, mem_index); |
c896fe29 FB |
2140 | } |
2141 | ||
a7812ae4 | 2142 | static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) |
c896fe29 | 2143 | { |
a7812ae4 | 2144 | tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_ld64, ret, addr, mem_index); |
c896fe29 FB |
2145 | } |
2146 | ||
ac56dd48 | 2147 | static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
c896fe29 | 2148 | { |
a7812ae4 | 2149 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_st8, arg, addr, mem_index); |
c896fe29 FB |
2150 | } |
2151 | ||
ac56dd48 | 2152 | static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
c896fe29 | 2153 | { |
a7812ae4 | 2154 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_st16, arg, addr, mem_index); |
c896fe29 FB |
2155 | } |
2156 | ||
ac56dd48 | 2157 | static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
c896fe29 | 2158 | { |
a7812ae4 | 2159 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_st32, arg, addr, mem_index); |
c896fe29 FB |
2160 | } |
2161 | ||
a7812ae4 | 2162 | static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) |
c896fe29 | 2163 | { |
a7812ae4 | 2164 | tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_st64, arg, addr, mem_index); |
c896fe29 FB |
2165 | } |
2166 | ||
56b8f567 | 2167 | #define tcg_gen_ld_ptr tcg_gen_ld_i64 |
a768e4b2 | 2168 | #define tcg_gen_discard_ptr tcg_gen_discard_i64 |
f8422f52 | 2169 | |
c896fe29 | 2170 | #endif /* TCG_TARGET_REG_BITS != 32 */ |
f8422f52 BS |
2171 | |
2172 | #if TARGET_LONG_BITS == 64 | |
2173 | #define TCG_TYPE_TL TCG_TYPE_I64 | |
2174 | #define tcg_gen_movi_tl tcg_gen_movi_i64 | |
2175 | #define tcg_gen_mov_tl tcg_gen_mov_i64 | |
2176 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i64 | |
2177 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i64 | |
2178 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i64 | |
2179 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i64 | |
2180 | #define tcg_gen_ld32u_tl tcg_gen_ld32u_i64 | |
2181 | #define tcg_gen_ld32s_tl tcg_gen_ld32s_i64 | |
2182 | #define tcg_gen_ld_tl tcg_gen_ld_i64 | |
2183 | #define tcg_gen_st8_tl tcg_gen_st8_i64 | |
2184 | #define tcg_gen_st16_tl tcg_gen_st16_i64 | |
2185 | #define tcg_gen_st32_tl tcg_gen_st32_i64 | |
2186 | #define tcg_gen_st_tl tcg_gen_st_i64 | |
2187 | #define tcg_gen_add_tl tcg_gen_add_i64 | |
2188 | #define tcg_gen_addi_tl tcg_gen_addi_i64 | |
2189 | #define tcg_gen_sub_tl tcg_gen_sub_i64 | |
390efc54 | 2190 | #define tcg_gen_neg_tl tcg_gen_neg_i64 |
10460c8a | 2191 | #define tcg_gen_subfi_tl tcg_gen_subfi_i64 |
f8422f52 BS |
2192 | #define tcg_gen_subi_tl tcg_gen_subi_i64 |
2193 | #define tcg_gen_and_tl tcg_gen_and_i64 | |
2194 | #define tcg_gen_andi_tl tcg_gen_andi_i64 | |
2195 | #define tcg_gen_or_tl tcg_gen_or_i64 | |
2196 | #define tcg_gen_ori_tl tcg_gen_ori_i64 | |
2197 | #define tcg_gen_xor_tl tcg_gen_xor_i64 | |
2198 | #define tcg_gen_xori_tl tcg_gen_xori_i64 | |
0b6ce4cf | 2199 | #define tcg_gen_not_tl tcg_gen_not_i64 |
f8422f52 BS |
2200 | #define tcg_gen_shl_tl tcg_gen_shl_i64 |
2201 | #define tcg_gen_shli_tl tcg_gen_shli_i64 | |
2202 | #define tcg_gen_shr_tl tcg_gen_shr_i64 | |
2203 | #define tcg_gen_shri_tl tcg_gen_shri_i64 | |
2204 | #define tcg_gen_sar_tl tcg_gen_sar_i64 | |
2205 | #define tcg_gen_sari_tl tcg_gen_sari_i64 | |
0cf767d6 | 2206 | #define tcg_gen_brcond_tl tcg_gen_brcond_i64 |
cb63669a | 2207 | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64 |
be210acb | 2208 | #define tcg_gen_setcond_tl tcg_gen_setcond_i64 |
add1e7ea | 2209 | #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64 |
f730fd27 TS |
2210 | #define tcg_gen_mul_tl tcg_gen_mul_i64 |
2211 | #define tcg_gen_muli_tl tcg_gen_muli_i64 | |
ab36421e AJ |
2212 | #define tcg_gen_div_tl tcg_gen_div_i64 |
2213 | #define tcg_gen_rem_tl tcg_gen_rem_i64 | |
864951af AJ |
2214 | #define tcg_gen_divu_tl tcg_gen_divu_i64 |
2215 | #define tcg_gen_remu_tl tcg_gen_remu_i64 | |
a768e4b2 | 2216 | #define tcg_gen_discard_tl tcg_gen_discard_i64 |
e429073d BS |
2217 | #define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32 |
2218 | #define tcg_gen_trunc_i64_tl tcg_gen_mov_i64 | |
2219 | #define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64 | |
2220 | #define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64 | |
2221 | #define tcg_gen_extu_tl_i64 tcg_gen_mov_i64 | |
2222 | #define tcg_gen_ext_tl_i64 tcg_gen_mov_i64 | |
0b6ce4cf FB |
2223 | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i64 |
2224 | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i64 | |
2225 | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i64 | |
2226 | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i64 | |
2227 | #define tcg_gen_ext32u_tl tcg_gen_ext32u_i64 | |
2228 | #define tcg_gen_ext32s_tl tcg_gen_ext32s_i64 | |
911d79ba AJ |
2229 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i64 |
2230 | #define tcg_gen_bswap32_tl tcg_gen_bswap32_i64 | |
2231 | #define tcg_gen_bswap64_tl tcg_gen_bswap64_i64 | |
945ca823 | 2232 | #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64 |
f24cb33e AJ |
2233 | #define tcg_gen_andc_tl tcg_gen_andc_i64 |
2234 | #define tcg_gen_eqv_tl tcg_gen_eqv_i64 | |
2235 | #define tcg_gen_nand_tl tcg_gen_nand_i64 | |
2236 | #define tcg_gen_nor_tl tcg_gen_nor_i64 | |
2237 | #define tcg_gen_orc_tl tcg_gen_orc_i64 | |
15824571 AJ |
2238 | #define tcg_gen_rotl_tl tcg_gen_rotl_i64 |
2239 | #define tcg_gen_rotli_tl tcg_gen_rotli_i64 | |
2240 | #define tcg_gen_rotr_tl tcg_gen_rotr_i64 | |
2241 | #define tcg_gen_rotri_tl tcg_gen_rotri_i64 | |
a98824ac | 2242 | #define tcg_const_tl tcg_const_i64 |
bdffd4a9 | 2243 | #define tcg_const_local_tl tcg_const_local_i64 |
f8422f52 BS |
2244 | #else |
2245 | #define TCG_TYPE_TL TCG_TYPE_I32 | |
2246 | #define tcg_gen_movi_tl tcg_gen_movi_i32 | |
2247 | #define tcg_gen_mov_tl tcg_gen_mov_i32 | |
2248 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i32 | |
2249 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i32 | |
2250 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i32 | |
2251 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i32 | |
2252 | #define tcg_gen_ld32u_tl tcg_gen_ld_i32 | |
2253 | #define tcg_gen_ld32s_tl tcg_gen_ld_i32 | |
2254 | #define tcg_gen_ld_tl tcg_gen_ld_i32 | |
2255 | #define tcg_gen_st8_tl tcg_gen_st8_i32 | |
2256 | #define tcg_gen_st16_tl tcg_gen_st16_i32 | |
2257 | #define tcg_gen_st32_tl tcg_gen_st_i32 | |
2258 | #define tcg_gen_st_tl tcg_gen_st_i32 | |
2259 | #define tcg_gen_add_tl tcg_gen_add_i32 | |
2260 | #define tcg_gen_addi_tl tcg_gen_addi_i32 | |
2261 | #define tcg_gen_sub_tl tcg_gen_sub_i32 | |
390efc54 | 2262 | #define tcg_gen_neg_tl tcg_gen_neg_i32 |
0045734a | 2263 | #define tcg_gen_subfi_tl tcg_gen_subfi_i32 |
f8422f52 BS |
2264 | #define tcg_gen_subi_tl tcg_gen_subi_i32 |
2265 | #define tcg_gen_and_tl tcg_gen_and_i32 | |
2266 | #define tcg_gen_andi_tl tcg_gen_andi_i32 | |
2267 | #define tcg_gen_or_tl tcg_gen_or_i32 | |
2268 | #define tcg_gen_ori_tl tcg_gen_ori_i32 | |
2269 | #define tcg_gen_xor_tl tcg_gen_xor_i32 | |
2270 | #define tcg_gen_xori_tl tcg_gen_xori_i32 | |
0b6ce4cf | 2271 | #define tcg_gen_not_tl tcg_gen_not_i32 |
f8422f52 BS |
2272 | #define tcg_gen_shl_tl tcg_gen_shl_i32 |
2273 | #define tcg_gen_shli_tl tcg_gen_shli_i32 | |
2274 | #define tcg_gen_shr_tl tcg_gen_shr_i32 | |
2275 | #define tcg_gen_shri_tl tcg_gen_shri_i32 | |
2276 | #define tcg_gen_sar_tl tcg_gen_sar_i32 | |
2277 | #define tcg_gen_sari_tl tcg_gen_sari_i32 | |
0cf767d6 | 2278 | #define tcg_gen_brcond_tl tcg_gen_brcond_i32 |
cb63669a | 2279 | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32 |
be210acb | 2280 | #define tcg_gen_setcond_tl tcg_gen_setcond_i32 |
add1e7ea | 2281 | #define tcg_gen_setcondi_tl tcg_gen_setcondi_i32 |
f730fd27 TS |
2282 | #define tcg_gen_mul_tl tcg_gen_mul_i32 |
2283 | #define tcg_gen_muli_tl tcg_gen_muli_i32 | |
ab36421e AJ |
2284 | #define tcg_gen_div_tl tcg_gen_div_i32 |
2285 | #define tcg_gen_rem_tl tcg_gen_rem_i32 | |
864951af AJ |
2286 | #define tcg_gen_divu_tl tcg_gen_divu_i32 |
2287 | #define tcg_gen_remu_tl tcg_gen_remu_i32 | |
a768e4b2 | 2288 | #define tcg_gen_discard_tl tcg_gen_discard_i32 |
e429073d BS |
2289 | #define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32 |
2290 | #define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32 | |
2291 | #define tcg_gen_extu_i32_tl tcg_gen_mov_i32 | |
2292 | #define tcg_gen_ext_i32_tl tcg_gen_mov_i32 | |
2293 | #define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64 | |
2294 | #define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64 | |
0b6ce4cf FB |
2295 | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i32 |
2296 | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i32 | |
2297 | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i32 | |
2298 | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i32 | |
2299 | #define tcg_gen_ext32u_tl tcg_gen_mov_i32 | |
2300 | #define tcg_gen_ext32s_tl tcg_gen_mov_i32 | |
911d79ba AJ |
2301 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i32 |
2302 | #define tcg_gen_bswap32_tl tcg_gen_bswap32_i32 | |
945ca823 | 2303 | #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64 |
f24cb33e AJ |
2304 | #define tcg_gen_andc_tl tcg_gen_andc_i32 |
2305 | #define tcg_gen_eqv_tl tcg_gen_eqv_i32 | |
2306 | #define tcg_gen_nand_tl tcg_gen_nand_i32 | |
2307 | #define tcg_gen_nor_tl tcg_gen_nor_i32 | |
2308 | #define tcg_gen_orc_tl tcg_gen_orc_i32 | |
15824571 AJ |
2309 | #define tcg_gen_rotl_tl tcg_gen_rotl_i32 |
2310 | #define tcg_gen_rotli_tl tcg_gen_rotli_i32 | |
2311 | #define tcg_gen_rotr_tl tcg_gen_rotr_i32 | |
2312 | #define tcg_gen_rotri_tl tcg_gen_rotri_i32 | |
a98824ac | 2313 | #define tcg_const_tl tcg_const_i32 |
bdffd4a9 | 2314 | #define tcg_const_local_tl tcg_const_local_i32 |
f8422f52 | 2315 | #endif |
6ddbc6e4 PB |
2316 | |
2317 | #if TCG_TARGET_REG_BITS == 32 | |
48d38ca5 | 2318 | #define tcg_gen_add_ptr tcg_gen_add_i32 |
6ddbc6e4 | 2319 | #define tcg_gen_addi_ptr tcg_gen_addi_i32 |
48d38ca5 | 2320 | #define tcg_gen_ext_i32_ptr tcg_gen_mov_i32 |
6ddbc6e4 | 2321 | #else /* TCG_TARGET_REG_BITS == 32 */ |
48d38ca5 | 2322 | #define tcg_gen_add_ptr tcg_gen_add_i64 |
6ddbc6e4 | 2323 | #define tcg_gen_addi_ptr tcg_gen_addi_i64 |
48d38ca5 | 2324 | #define tcg_gen_ext_i32_ptr tcg_gen_ext_i32_i64 |
6ddbc6e4 | 2325 | #endif /* TCG_TARGET_REG_BITS != 32 */ |