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c896fe29
FB
1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
c896fe29
FB
25/* define it to use liveness analysis (better code) */
26#define USE_LIVENESS_ANALYSIS
8f2e8c07 27#define USE_TCG_OPTIMIZATIONS
c896fe29 28
cca82982
AJ
29#include "config.h"
30
813da627
RH
31/* Define to jump the ELF file used to communicate with GDB. */
32#undef DEBUG_JIT
33
a6c6f76c 34#if !defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG)
cca82982
AJ
35/* define it to suppress various consistency checks (faster) */
36#define NDEBUG
37#endif
38
ca10f867 39#include "qemu-common.h"
1de7afc9
PB
40#include "qemu/host-utils.h"
41#include "qemu/timer.h"
c896fe29 42
c5d3c498 43/* Note: the long term plan is to reduce the dependencies on the QEMU
c896fe29
FB
44 CPU definitions. Currently they are used for qemu_ld/st
45 instructions */
46#define NO_CPU_IO_DEFS
47#include "cpu.h"
c896fe29
FB
48
49#include "tcg-op.h"
813da627 50
edee2579 51#if UINTPTR_MAX == UINT32_MAX
813da627 52# define ELF_CLASS ELFCLASS32
edee2579
RH
53#else
54# define ELF_CLASS ELFCLASS64
813da627
RH
55#endif
56#ifdef HOST_WORDS_BIGENDIAN
57# define ELF_DATA ELFDATA2MSB
58#else
59# define ELF_DATA ELFDATA2LSB
60#endif
61
c896fe29
FB
62#include "elf.h"
63
c0ad3001 64/* Forward declarations for functions declared in tcg-target.c and used here. */
e4d58b41
RH
65static void tcg_target_init(TCGContext *s);
66static void tcg_target_qemu_prologue(TCGContext *s);
1813e175 67static void patch_reloc(tcg_insn_unit *code_ptr, int type,
2ba7fae2 68 intptr_t value, intptr_t addend);
c896fe29 69
497a22eb
RH
70/* The CIE and FDE header definitions will be common to all hosts. */
71typedef struct {
72 uint32_t len __attribute__((aligned((sizeof(void *)))));
73 uint32_t id;
74 uint8_t version;
75 char augmentation[1];
76 uint8_t code_align;
77 uint8_t data_align;
78 uint8_t return_column;
79} DebugFrameCIE;
80
81typedef struct QEMU_PACKED {
82 uint32_t len __attribute__((aligned((sizeof(void *)))));
83 uint32_t cie_offset;
edee2579
RH
84 uintptr_t func_start;
85 uintptr_t func_len;
497a22eb
RH
86} DebugFrameFDEHeader;
87
2c90784a
RH
88typedef struct QEMU_PACKED {
89 DebugFrameCIE cie;
90 DebugFrameFDEHeader fde;
91} DebugFrameHeader;
92
813da627 93static void tcg_register_jit_int(void *buf, size_t size,
2c90784a
RH
94 const void *debug_frame,
95 size_t debug_frame_size)
813da627
RH
96 __attribute__((unused));
97
c0ad3001
SW
98/* Forward declarations for functions declared and used in tcg-target.c. */
99static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str);
2a534aff 100static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
a05b5b9b 101 intptr_t arg2);
2a534aff 102static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg);
c0ad3001 103static void tcg_out_movi(TCGContext *s, TCGType type,
2a534aff 104 TCGReg ret, tcg_target_long arg);
c0ad3001
SW
105static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
106 const int *const_args);
2a534aff 107static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
a05b5b9b 108 intptr_t arg2);
cf066674 109static void tcg_out_call(TCGContext *s, tcg_insn_unit *target);
f6c6afc1 110static int tcg_target_const_match(tcg_target_long val, TCGType type,
c0ad3001 111 const TCGArgConstraint *arg_ct);
9ecefc84
RH
112static void tcg_out_tb_init(TCGContext *s);
113static void tcg_out_tb_finalize(TCGContext *s);
114
c0ad3001 115
8399ad59 116TCGOpDef tcg_op_defs[] = {
0e2029a0 117#define DEF(s, oargs, iargs, cargs, flags) { #s, oargs, iargs, cargs, iargs + oargs + cargs, flags },
c896fe29
FB
118#include "tcg-opc.h"
119#undef DEF
c896fe29 120};
2a24374a 121const size_t tcg_op_defs_max = ARRAY_SIZE(tcg_op_defs);
c896fe29 122
b1d8e52e
BS
123static TCGRegSet tcg_target_available_regs[2];
124static TCGRegSet tcg_target_call_clobber_regs;
c896fe29 125
1813e175 126#if TCG_TARGET_INSN_UNIT_SIZE == 1
4196dca6 127static __attribute__((unused)) inline void tcg_out8(TCGContext *s, uint8_t v)
c896fe29
FB
128{
129 *s->code_ptr++ = v;
130}
131
4196dca6
PM
132static __attribute__((unused)) inline void tcg_patch8(tcg_insn_unit *p,
133 uint8_t v)
5c53bb81 134{
1813e175 135 *p = v;
5c53bb81 136}
1813e175 137#endif
5c53bb81 138
1813e175 139#if TCG_TARGET_INSN_UNIT_SIZE <= 2
4196dca6 140static __attribute__((unused)) inline void tcg_out16(TCGContext *s, uint16_t v)
c896fe29 141{
1813e175
RH
142 if (TCG_TARGET_INSN_UNIT_SIZE == 2) {
143 *s->code_ptr++ = v;
144 } else {
145 tcg_insn_unit *p = s->code_ptr;
146 memcpy(p, &v, sizeof(v));
147 s->code_ptr = p + (2 / TCG_TARGET_INSN_UNIT_SIZE);
148 }
c896fe29
FB
149}
150
4196dca6
PM
151static __attribute__((unused)) inline void tcg_patch16(tcg_insn_unit *p,
152 uint16_t v)
5c53bb81 153{
1813e175
RH
154 if (TCG_TARGET_INSN_UNIT_SIZE == 2) {
155 *p = v;
156 } else {
157 memcpy(p, &v, sizeof(v));
158 }
5c53bb81 159}
1813e175 160#endif
5c53bb81 161
1813e175 162#if TCG_TARGET_INSN_UNIT_SIZE <= 4
4196dca6 163static __attribute__((unused)) inline void tcg_out32(TCGContext *s, uint32_t v)
c896fe29 164{
1813e175
RH
165 if (TCG_TARGET_INSN_UNIT_SIZE == 4) {
166 *s->code_ptr++ = v;
167 } else {
168 tcg_insn_unit *p = s->code_ptr;
169 memcpy(p, &v, sizeof(v));
170 s->code_ptr = p + (4 / TCG_TARGET_INSN_UNIT_SIZE);
171 }
c896fe29
FB
172}
173
4196dca6
PM
174static __attribute__((unused)) inline void tcg_patch32(tcg_insn_unit *p,
175 uint32_t v)
5c53bb81 176{
1813e175
RH
177 if (TCG_TARGET_INSN_UNIT_SIZE == 4) {
178 *p = v;
179 } else {
180 memcpy(p, &v, sizeof(v));
181 }
5c53bb81 182}
1813e175 183#endif
5c53bb81 184
1813e175 185#if TCG_TARGET_INSN_UNIT_SIZE <= 8
4196dca6 186static __attribute__((unused)) inline void tcg_out64(TCGContext *s, uint64_t v)
ac26eb69 187{
1813e175
RH
188 if (TCG_TARGET_INSN_UNIT_SIZE == 8) {
189 *s->code_ptr++ = v;
190 } else {
191 tcg_insn_unit *p = s->code_ptr;
192 memcpy(p, &v, sizeof(v));
193 s->code_ptr = p + (8 / TCG_TARGET_INSN_UNIT_SIZE);
194 }
ac26eb69
RH
195}
196
4196dca6
PM
197static __attribute__((unused)) inline void tcg_patch64(tcg_insn_unit *p,
198 uint64_t v)
5c53bb81 199{
1813e175
RH
200 if (TCG_TARGET_INSN_UNIT_SIZE == 8) {
201 *p = v;
202 } else {
203 memcpy(p, &v, sizeof(v));
204 }
5c53bb81 205}
1813e175 206#endif
5c53bb81 207
c896fe29
FB
208/* label relocation processing */
209
1813e175 210static void tcg_out_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type,
bec16311 211 TCGLabel *l, intptr_t addend)
c896fe29 212{
c896fe29
FB
213 TCGRelocation *r;
214
c896fe29 215 if (l->has_value) {
623e265c
PB
216 /* FIXME: This may break relocations on RISC targets that
217 modify instruction fields in place. The caller may not have
218 written the initial value. */
f54b3f92 219 patch_reloc(code_ptr, type, l->u.value, addend);
c896fe29
FB
220 } else {
221 /* add a new relocation entry */
222 r = tcg_malloc(sizeof(TCGRelocation));
223 r->type = type;
224 r->ptr = code_ptr;
225 r->addend = addend;
226 r->next = l->u.first_reloc;
227 l->u.first_reloc = r;
228 }
229}
230
bec16311 231static void tcg_out_label(TCGContext *s, TCGLabel *l, tcg_insn_unit *ptr)
c896fe29 232{
2ba7fae2 233 intptr_t value = (intptr_t)ptr;
1813e175 234 TCGRelocation *r;
c896fe29 235
1813e175
RH
236 assert(!l->has_value);
237
238 for (r = l->u.first_reloc; r != NULL; r = r->next) {
f54b3f92 239 patch_reloc(r->ptr, r->type, value, r->addend);
c896fe29 240 }
1813e175 241
c896fe29 242 l->has_value = 1;
1813e175 243 l->u.value_ptr = ptr;
c896fe29
FB
244}
245
42a268c2 246TCGLabel *gen_new_label(void)
c896fe29
FB
247{
248 TCGContext *s = &tcg_ctx;
51e3972c 249 TCGLabel *l = tcg_malloc(sizeof(TCGLabel));
c896fe29 250
51e3972c
RH
251 *l = (TCGLabel){
252 .id = s->nb_labels++
253 };
42a268c2
RH
254
255 return l;
c896fe29
FB
256}
257
258#include "tcg-target.c"
259
c896fe29
FB
260/* pool based memory allocation */
261void *tcg_malloc_internal(TCGContext *s, int size)
262{
263 TCGPool *p;
264 int pool_size;
265
266 if (size > TCG_POOL_CHUNK_SIZE) {
267 /* big malloc: insert a new pool (XXX: could optimize) */
7267c094 268 p = g_malloc(sizeof(TCGPool) + size);
c896fe29 269 p->size = size;
4055299e
KB
270 p->next = s->pool_first_large;
271 s->pool_first_large = p;
272 return p->data;
c896fe29
FB
273 } else {
274 p = s->pool_current;
275 if (!p) {
276 p = s->pool_first;
277 if (!p)
278 goto new_pool;
279 } else {
280 if (!p->next) {
281 new_pool:
282 pool_size = TCG_POOL_CHUNK_SIZE;
7267c094 283 p = g_malloc(sizeof(TCGPool) + pool_size);
c896fe29
FB
284 p->size = pool_size;
285 p->next = NULL;
286 if (s->pool_current)
287 s->pool_current->next = p;
288 else
289 s->pool_first = p;
290 } else {
291 p = p->next;
292 }
293 }
294 }
295 s->pool_current = p;
296 s->pool_cur = p->data + size;
297 s->pool_end = p->data + p->size;
298 return p->data;
299}
300
301void tcg_pool_reset(TCGContext *s)
302{
4055299e
KB
303 TCGPool *p, *t;
304 for (p = s->pool_first_large; p; p = t) {
305 t = p->next;
306 g_free(p);
307 }
308 s->pool_first_large = NULL;
c896fe29
FB
309 s->pool_cur = s->pool_end = NULL;
310 s->pool_current = NULL;
311}
312
100b5e01
RH
313typedef struct TCGHelperInfo {
314 void *func;
315 const char *name;
afb49896
RH
316 unsigned flags;
317 unsigned sizemask;
100b5e01
RH
318} TCGHelperInfo;
319
2ef6175a
RH
320#include "exec/helper-proto.h"
321
100b5e01 322static const TCGHelperInfo all_helpers[] = {
2ef6175a 323#include "exec/helper-tcg.h"
100b5e01
RH
324};
325
c896fe29
FB
326void tcg_context_init(TCGContext *s)
327{
100b5e01 328 int op, total_args, n, i;
c896fe29
FB
329 TCGOpDef *def;
330 TCGArgConstraint *args_ct;
331 int *sorted_args;
84fd9dd3 332 GHashTable *helper_table;
c896fe29
FB
333
334 memset(s, 0, sizeof(*s));
c896fe29
FB
335 s->nb_globals = 0;
336
337 /* Count total number of arguments and allocate the corresponding
338 space */
339 total_args = 0;
340 for(op = 0; op < NB_OPS; op++) {
341 def = &tcg_op_defs[op];
342 n = def->nb_iargs + def->nb_oargs;
343 total_args += n;
344 }
345
7267c094
AL
346 args_ct = g_malloc(sizeof(TCGArgConstraint) * total_args);
347 sorted_args = g_malloc(sizeof(int) * total_args);
c896fe29
FB
348
349 for(op = 0; op < NB_OPS; op++) {
350 def = &tcg_op_defs[op];
351 def->args_ct = args_ct;
352 def->sorted_args = sorted_args;
353 n = def->nb_iargs + def->nb_oargs;
354 sorted_args += n;
355 args_ct += n;
356 }
5cd8f621
RH
357
358 /* Register helpers. */
84fd9dd3
RH
359 /* Use g_direct_hash/equal for direct pointer comparisons on func. */
360 s->helpers = helper_table = g_hash_table_new(NULL, NULL);
361
100b5e01 362 for (i = 0; i < ARRAY_SIZE(all_helpers); ++i) {
84fd9dd3 363 g_hash_table_insert(helper_table, (gpointer)all_helpers[i].func,
72866e82 364 (gpointer)&all_helpers[i]);
100b5e01 365 }
5cd8f621 366
c896fe29 367 tcg_target_init(s);
9002ec79 368}
b03cce8e 369
9002ec79
RH
370void tcg_prologue_init(TCGContext *s)
371{
b03cce8e 372 /* init global prologue and epilogue */
0b0d3320 373 s->code_buf = s->code_gen_prologue;
b03cce8e
FB
374 s->code_ptr = s->code_buf;
375 tcg_target_qemu_prologue(s);
b93949ef 376 flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr);
d6b64b2b
RH
377
378#ifdef DEBUG_DISAS
379 if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) {
1813e175 380 size_t size = tcg_current_code_size(s);
d6b64b2b
RH
381 qemu_log("PROLOGUE: [size=%zu]\n", size);
382 log_disas(s->code_buf, size);
383 qemu_log("\n");
384 qemu_log_flush();
385 }
386#endif
c896fe29
FB
387}
388
e2c6d1b4 389void tcg_set_frame(TCGContext *s, int reg, intptr_t start, intptr_t size)
c896fe29
FB
390{
391 s->frame_start = start;
392 s->frame_end = start + size;
393 s->frame_reg = reg;
394}
395
c896fe29
FB
396void tcg_func_start(TCGContext *s)
397{
398 tcg_pool_reset(s);
399 s->nb_temps = s->nb_globals;
0ec9eabc
RH
400
401 /* No temps have been previously allocated for size or locality. */
402 memset(s->free_temps, 0, sizeof(s->free_temps));
403
c896fe29
FB
404 s->nb_labels = 0;
405 s->current_frame_offset = s->frame_start;
406
0a209d4b
RH
407#ifdef CONFIG_DEBUG_TCG
408 s->goto_tb_issue_mask = 0;
409#endif
410
c45cb8bb
RH
411 s->gen_first_op_idx = 0;
412 s->gen_last_op_idx = -1;
413 s->gen_next_op_idx = 0;
414 s->gen_next_parm_idx = 0;
b76f0d8c 415
9ecefc84 416 s->be = tcg_malloc(sizeof(TCGBackendData));
c896fe29
FB
417}
418
419static inline void tcg_temp_alloc(TCGContext *s, int n)
420{
421 if (n > TCG_MAX_TEMPS)
422 tcg_abort();
423}
424
a7812ae4
PB
425static inline int tcg_global_reg_new_internal(TCGType type, int reg,
426 const char *name)
c896fe29
FB
427{
428 TCGContext *s = &tcg_ctx;
429 TCGTemp *ts;
430 int idx;
431
432#if TCG_TARGET_REG_BITS == 32
433 if (type != TCG_TYPE_I32)
434 tcg_abort();
435#endif
436 if (tcg_regset_test_reg(s->reserved_regs, reg))
437 tcg_abort();
438 idx = s->nb_globals;
439 tcg_temp_alloc(s, s->nb_globals + 1);
440 ts = &s->temps[s->nb_globals];
441 ts->base_type = type;
442 ts->type = type;
443 ts->fixed_reg = 1;
444 ts->reg = reg;
c896fe29
FB
445 ts->name = name;
446 s->nb_globals++;
447 tcg_regset_set_reg(s->reserved_regs, reg);
a7812ae4
PB
448 return idx;
449}
450
451TCGv_i32 tcg_global_reg_new_i32(int reg, const char *name)
452{
453 int idx;
454
455 idx = tcg_global_reg_new_internal(TCG_TYPE_I32, reg, name);
456 return MAKE_TCGV_I32(idx);
457}
458
459TCGv_i64 tcg_global_reg_new_i64(int reg, const char *name)
460{
461 int idx;
462
463 idx = tcg_global_reg_new_internal(TCG_TYPE_I64, reg, name);
464 return MAKE_TCGV_I64(idx);
c896fe29
FB
465}
466
a7812ae4 467static inline int tcg_global_mem_new_internal(TCGType type, int reg,
2f2f244d 468 intptr_t offset,
a7812ae4 469 const char *name)
c896fe29
FB
470{
471 TCGContext *s = &tcg_ctx;
472 TCGTemp *ts;
473 int idx;
474
475 idx = s->nb_globals;
476#if TCG_TARGET_REG_BITS == 32
477 if (type == TCG_TYPE_I64) {
478 char buf[64];
c588979b 479 tcg_temp_alloc(s, s->nb_globals + 2);
c896fe29
FB
480 ts = &s->temps[s->nb_globals];
481 ts->base_type = type;
482 ts->type = TCG_TYPE_I32;
483 ts->fixed_reg = 0;
484 ts->mem_allocated = 1;
485 ts->mem_reg = reg;
02eb19d0 486#ifdef HOST_WORDS_BIGENDIAN
c896fe29
FB
487 ts->mem_offset = offset + 4;
488#else
489 ts->mem_offset = offset;
490#endif
c896fe29
FB
491 pstrcpy(buf, sizeof(buf), name);
492 pstrcat(buf, sizeof(buf), "_0");
493 ts->name = strdup(buf);
494 ts++;
495
496 ts->base_type = type;
497 ts->type = TCG_TYPE_I32;
498 ts->fixed_reg = 0;
499 ts->mem_allocated = 1;
500 ts->mem_reg = reg;
02eb19d0 501#ifdef HOST_WORDS_BIGENDIAN
c896fe29
FB
502 ts->mem_offset = offset;
503#else
504 ts->mem_offset = offset + 4;
505#endif
c896fe29
FB
506 pstrcpy(buf, sizeof(buf), name);
507 pstrcat(buf, sizeof(buf), "_1");
508 ts->name = strdup(buf);
509
510 s->nb_globals += 2;
511 } else
512#endif
513 {
514 tcg_temp_alloc(s, s->nb_globals + 1);
515 ts = &s->temps[s->nb_globals];
516 ts->base_type = type;
517 ts->type = type;
518 ts->fixed_reg = 0;
519 ts->mem_allocated = 1;
520 ts->mem_reg = reg;
521 ts->mem_offset = offset;
c896fe29
FB
522 ts->name = name;
523 s->nb_globals++;
524 }
a7812ae4
PB
525 return idx;
526}
527
2f2f244d 528TCGv_i32 tcg_global_mem_new_i32(int reg, intptr_t offset, const char *name)
a7812ae4 529{
2f2f244d 530 int idx = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name);
a7812ae4
PB
531 return MAKE_TCGV_I32(idx);
532}
533
2f2f244d 534TCGv_i64 tcg_global_mem_new_i64(int reg, intptr_t offset, const char *name)
a7812ae4 535{
2f2f244d 536 int idx = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name);
a7812ae4 537 return MAKE_TCGV_I64(idx);
c896fe29
FB
538}
539
a7812ae4 540static inline int tcg_temp_new_internal(TCGType type, int temp_local)
c896fe29
FB
541{
542 TCGContext *s = &tcg_ctx;
543 TCGTemp *ts;
641d5fbe 544 int idx, k;
c896fe29 545
0ec9eabc
RH
546 k = type + (temp_local ? TCG_TYPE_COUNT : 0);
547 idx = find_first_bit(s->free_temps[k].l, TCG_MAX_TEMPS);
548 if (idx < TCG_MAX_TEMPS) {
549 /* There is already an available temp with the right type. */
550 clear_bit(idx, s->free_temps[k].l);
551
e8996ee0 552 ts = &s->temps[idx];
e8996ee0 553 ts->temp_allocated = 1;
0ec9eabc 554 assert(ts->base_type == type);
641d5fbe 555 assert(ts->temp_local == temp_local);
e8996ee0
FB
556 } else {
557 idx = s->nb_temps;
c896fe29 558#if TCG_TARGET_REG_BITS == 32
e8996ee0 559 if (type == TCG_TYPE_I64) {
8df1ca4b 560 tcg_temp_alloc(s, s->nb_temps + 2);
e8996ee0
FB
561 ts = &s->temps[s->nb_temps];
562 ts->base_type = type;
563 ts->type = TCG_TYPE_I32;
564 ts->temp_allocated = 1;
641d5fbe 565 ts->temp_local = temp_local;
e8996ee0
FB
566 ts->name = NULL;
567 ts++;
f6aa2f7d 568 ts->base_type = type;
e8996ee0
FB
569 ts->type = TCG_TYPE_I32;
570 ts->temp_allocated = 1;
641d5fbe 571 ts->temp_local = temp_local;
e8996ee0
FB
572 ts->name = NULL;
573 s->nb_temps += 2;
574 } else
c896fe29 575#endif
e8996ee0
FB
576 {
577 tcg_temp_alloc(s, s->nb_temps + 1);
578 ts = &s->temps[s->nb_temps];
579 ts->base_type = type;
580 ts->type = type;
581 ts->temp_allocated = 1;
641d5fbe 582 ts->temp_local = temp_local;
e8996ee0
FB
583 ts->name = NULL;
584 s->nb_temps++;
585 }
c896fe29 586 }
27bfd83c
PM
587
588#if defined(CONFIG_DEBUG_TCG)
589 s->temps_in_use++;
590#endif
a7812ae4 591 return idx;
c896fe29
FB
592}
593
a7812ae4
PB
594TCGv_i32 tcg_temp_new_internal_i32(int temp_local)
595{
596 int idx;
597
598 idx = tcg_temp_new_internal(TCG_TYPE_I32, temp_local);
599 return MAKE_TCGV_I32(idx);
600}
601
602TCGv_i64 tcg_temp_new_internal_i64(int temp_local)
603{
604 int idx;
605
606 idx = tcg_temp_new_internal(TCG_TYPE_I64, temp_local);
607 return MAKE_TCGV_I64(idx);
608}
609
0ec9eabc 610static void tcg_temp_free_internal(int idx)
c896fe29
FB
611{
612 TCGContext *s = &tcg_ctx;
613 TCGTemp *ts;
641d5fbe 614 int k;
c896fe29 615
27bfd83c
PM
616#if defined(CONFIG_DEBUG_TCG)
617 s->temps_in_use--;
618 if (s->temps_in_use < 0) {
619 fprintf(stderr, "More temporaries freed than allocated!\n");
620 }
621#endif
622
e8996ee0 623 assert(idx >= s->nb_globals && idx < s->nb_temps);
c896fe29 624 ts = &s->temps[idx];
e8996ee0
FB
625 assert(ts->temp_allocated != 0);
626 ts->temp_allocated = 0;
0ec9eabc 627
18d13fa2 628 k = ts->base_type + (ts->temp_local ? TCG_TYPE_COUNT : 0);
0ec9eabc 629 set_bit(idx, s->free_temps[k].l);
c896fe29
FB
630}
631
a7812ae4
PB
632void tcg_temp_free_i32(TCGv_i32 arg)
633{
634 tcg_temp_free_internal(GET_TCGV_I32(arg));
635}
636
637void tcg_temp_free_i64(TCGv_i64 arg)
638{
639 tcg_temp_free_internal(GET_TCGV_I64(arg));
640}
e8996ee0 641
a7812ae4 642TCGv_i32 tcg_const_i32(int32_t val)
c896fe29 643{
a7812ae4
PB
644 TCGv_i32 t0;
645 t0 = tcg_temp_new_i32();
e8996ee0
FB
646 tcg_gen_movi_i32(t0, val);
647 return t0;
648}
c896fe29 649
a7812ae4 650TCGv_i64 tcg_const_i64(int64_t val)
e8996ee0 651{
a7812ae4
PB
652 TCGv_i64 t0;
653 t0 = tcg_temp_new_i64();
e8996ee0
FB
654 tcg_gen_movi_i64(t0, val);
655 return t0;
c896fe29
FB
656}
657
a7812ae4 658TCGv_i32 tcg_const_local_i32(int32_t val)
bdffd4a9 659{
a7812ae4
PB
660 TCGv_i32 t0;
661 t0 = tcg_temp_local_new_i32();
bdffd4a9
AJ
662 tcg_gen_movi_i32(t0, val);
663 return t0;
664}
665
a7812ae4 666TCGv_i64 tcg_const_local_i64(int64_t val)
bdffd4a9 667{
a7812ae4
PB
668 TCGv_i64 t0;
669 t0 = tcg_temp_local_new_i64();
bdffd4a9
AJ
670 tcg_gen_movi_i64(t0, val);
671 return t0;
672}
673
27bfd83c
PM
674#if defined(CONFIG_DEBUG_TCG)
675void tcg_clear_temp_count(void)
676{
677 TCGContext *s = &tcg_ctx;
678 s->temps_in_use = 0;
679}
680
681int tcg_check_temp_count(void)
682{
683 TCGContext *s = &tcg_ctx;
684 if (s->temps_in_use) {
685 /* Clear the count so that we don't give another
686 * warning immediately next time around.
687 */
688 s->temps_in_use = 0;
689 return 1;
690 }
691 return 0;
692}
693#endif
694
39cf05d3
FB
695/* Note: we convert the 64 bit args to 32 bit and do some alignment
696 and endian swap. Maybe it would be better to do the alignment
697 and endian swap in tcg_reg_alloc_call(). */
bbb8a1b4
RH
698void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret,
699 int nargs, TCGArg *args)
c896fe29 700{
c45cb8bb 701 int i, real_args, nb_rets, pi, pi_first;
bbb8a1b4 702 unsigned sizemask, flags;
afb49896
RH
703 TCGHelperInfo *info;
704
705 info = g_hash_table_lookup(s->helpers, (gpointer)func);
bbb8a1b4
RH
706 flags = info->flags;
707 sizemask = info->sizemask;
2bece2c8 708
34b1a49c
RH
709#if defined(__sparc__) && !defined(__arch64__) \
710 && !defined(CONFIG_TCG_INTERPRETER)
711 /* We have 64-bit values in one register, but need to pass as two
712 separate parameters. Split them. */
713 int orig_sizemask = sizemask;
714 int orig_nargs = nargs;
715 TCGv_i64 retl, reth;
716
717 TCGV_UNUSED_I64(retl);
718 TCGV_UNUSED_I64(reth);
719 if (sizemask != 0) {
720 TCGArg *split_args = __builtin_alloca(sizeof(TCGArg) * nargs * 2);
721 for (i = real_args = 0; i < nargs; ++i) {
722 int is_64bit = sizemask & (1 << (i+1)*2);
723 if (is_64bit) {
724 TCGv_i64 orig = MAKE_TCGV_I64(args[i]);
725 TCGv_i32 h = tcg_temp_new_i32();
726 TCGv_i32 l = tcg_temp_new_i32();
727 tcg_gen_extr_i64_i32(l, h, orig);
728 split_args[real_args++] = GET_TCGV_I32(h);
729 split_args[real_args++] = GET_TCGV_I32(l);
730 } else {
731 split_args[real_args++] = args[i];
732 }
733 }
734 nargs = real_args;
735 args = split_args;
736 sizemask = 0;
737 }
738#elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64
2bece2c8
RH
739 for (i = 0; i < nargs; ++i) {
740 int is_64bit = sizemask & (1 << (i+1)*2);
741 int is_signed = sizemask & (2 << (i+1)*2);
742 if (!is_64bit) {
743 TCGv_i64 temp = tcg_temp_new_i64();
744 TCGv_i64 orig = MAKE_TCGV_I64(args[i]);
745 if (is_signed) {
746 tcg_gen_ext32s_i64(temp, orig);
747 } else {
748 tcg_gen_ext32u_i64(temp, orig);
749 }
750 args[i] = GET_TCGV_I64(temp);
751 }
752 }
753#endif /* TCG_TARGET_EXTEND_ARGS */
754
c45cb8bb 755 pi_first = pi = s->gen_next_parm_idx;
a7812ae4 756 if (ret != TCG_CALL_DUMMY_ARG) {
34b1a49c
RH
757#if defined(__sparc__) && !defined(__arch64__) \
758 && !defined(CONFIG_TCG_INTERPRETER)
759 if (orig_sizemask & 1) {
760 /* The 32-bit ABI is going to return the 64-bit value in
761 the %o0/%o1 register pair. Prepare for this by using
762 two return temporaries, and reassemble below. */
763 retl = tcg_temp_new_i64();
764 reth = tcg_temp_new_i64();
c45cb8bb
RH
765 s->gen_opparam_buf[pi++] = GET_TCGV_I64(reth);
766 s->gen_opparam_buf[pi++] = GET_TCGV_I64(retl);
34b1a49c
RH
767 nb_rets = 2;
768 } else {
c45cb8bb 769 s->gen_opparam_buf[pi++] = ret;
34b1a49c
RH
770 nb_rets = 1;
771 }
772#else
773 if (TCG_TARGET_REG_BITS < 64 && (sizemask & 1)) {
02eb19d0 774#ifdef HOST_WORDS_BIGENDIAN
c45cb8bb
RH
775 s->gen_opparam_buf[pi++] = ret + 1;
776 s->gen_opparam_buf[pi++] = ret;
39cf05d3 777#else
c45cb8bb
RH
778 s->gen_opparam_buf[pi++] = ret;
779 s->gen_opparam_buf[pi++] = ret + 1;
39cf05d3 780#endif
a7812ae4 781 nb_rets = 2;
34b1a49c 782 } else {
c45cb8bb 783 s->gen_opparam_buf[pi++] = ret;
a7812ae4 784 nb_rets = 1;
c896fe29 785 }
34b1a49c 786#endif
a7812ae4
PB
787 } else {
788 nb_rets = 0;
c896fe29 789 }
a7812ae4
PB
790 real_args = 0;
791 for (i = 0; i < nargs; i++) {
2bece2c8 792 int is_64bit = sizemask & (1 << (i+1)*2);
bbb8a1b4 793 if (TCG_TARGET_REG_BITS < 64 && is_64bit) {
39cf05d3
FB
794#ifdef TCG_TARGET_CALL_ALIGN_ARGS
795 /* some targets want aligned 64 bit args */
ebd486d5 796 if (real_args & 1) {
c45cb8bb 797 s->gen_opparam_buf[pi++] = TCG_CALL_DUMMY_ARG;
ebd486d5 798 real_args++;
39cf05d3
FB
799 }
800#endif
3f90f252
RH
801 /* If stack grows up, then we will be placing successive
802 arguments at lower addresses, which means we need to
803 reverse the order compared to how we would normally
804 treat either big or little-endian. For those arguments
805 that will wind up in registers, this still works for
806 HPPA (the only current STACK_GROWSUP target) since the
807 argument registers are *also* allocated in decreasing
808 order. If another such target is added, this logic may
809 have to get more complicated to differentiate between
810 stack arguments and register arguments. */
02eb19d0 811#if defined(HOST_WORDS_BIGENDIAN) != defined(TCG_TARGET_STACK_GROWSUP)
c45cb8bb
RH
812 s->gen_opparam_buf[pi++] = args[i] + 1;
813 s->gen_opparam_buf[pi++] = args[i];
c896fe29 814#else
c45cb8bb
RH
815 s->gen_opparam_buf[pi++] = args[i];
816 s->gen_opparam_buf[pi++] = args[i] + 1;
c896fe29 817#endif
a7812ae4 818 real_args += 2;
2bece2c8 819 continue;
c896fe29 820 }
2bece2c8 821
c45cb8bb 822 s->gen_opparam_buf[pi++] = args[i];
2bece2c8 823 real_args++;
c896fe29 824 }
c45cb8bb
RH
825 s->gen_opparam_buf[pi++] = (uintptr_t)func;
826 s->gen_opparam_buf[pi++] = flags;
a7812ae4 827
c45cb8bb
RH
828 i = s->gen_next_op_idx;
829 tcg_debug_assert(i < OPC_BUF_SIZE);
830 tcg_debug_assert(pi <= OPPARAM_BUF_SIZE);
a7812ae4 831
c45cb8bb
RH
832 /* Set links for sequential allocation during translation. */
833 s->gen_op_buf[i] = (TCGOp){
834 .opc = INDEX_op_call,
835 .callo = nb_rets,
836 .calli = real_args,
837 .args = pi_first,
838 .prev = i - 1,
839 .next = i + 1
840 };
841
842 /* Make sure the calli field didn't overflow. */
843 tcg_debug_assert(s->gen_op_buf[i].calli == real_args);
844
845 s->gen_last_op_idx = i;
846 s->gen_next_op_idx = i + 1;
847 s->gen_next_parm_idx = pi;
2bece2c8 848
34b1a49c
RH
849#if defined(__sparc__) && !defined(__arch64__) \
850 && !defined(CONFIG_TCG_INTERPRETER)
851 /* Free all of the parts we allocated above. */
852 for (i = real_args = 0; i < orig_nargs; ++i) {
853 int is_64bit = orig_sizemask & (1 << (i+1)*2);
854 if (is_64bit) {
855 TCGv_i32 h = MAKE_TCGV_I32(args[real_args++]);
856 TCGv_i32 l = MAKE_TCGV_I32(args[real_args++]);
857 tcg_temp_free_i32(h);
858 tcg_temp_free_i32(l);
859 } else {
860 real_args++;
861 }
862 }
863 if (orig_sizemask & 1) {
864 /* The 32-bit ABI returned two 32-bit pieces. Re-assemble them.
865 Note that describing these as TCGv_i64 eliminates an unnecessary
866 zero-extension that tcg_gen_concat_i32_i64 would create. */
867 tcg_gen_concat32_i64(MAKE_TCGV_I64(ret), retl, reth);
868 tcg_temp_free_i64(retl);
869 tcg_temp_free_i64(reth);
870 }
871#elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64
2bece2c8
RH
872 for (i = 0; i < nargs; ++i) {
873 int is_64bit = sizemask & (1 << (i+1)*2);
874 if (!is_64bit) {
875 TCGv_i64 temp = MAKE_TCGV_I64(args[i]);
876 tcg_temp_free_i64(temp);
877 }
878 }
879#endif /* TCG_TARGET_EXTEND_ARGS */
c896fe29 880}
c896fe29 881
8fcd3692 882static void tcg_reg_alloc_start(TCGContext *s)
c896fe29
FB
883{
884 int i;
885 TCGTemp *ts;
886 for(i = 0; i < s->nb_globals; i++) {
887 ts = &s->temps[i];
888 if (ts->fixed_reg) {
889 ts->val_type = TEMP_VAL_REG;
890 } else {
891 ts->val_type = TEMP_VAL_MEM;
892 }
893 }
e8996ee0
FB
894 for(i = s->nb_globals; i < s->nb_temps; i++) {
895 ts = &s->temps[i];
7dfd8c6a
AJ
896 if (ts->temp_local) {
897 ts->val_type = TEMP_VAL_MEM;
898 } else {
899 ts->val_type = TEMP_VAL_DEAD;
900 }
e8996ee0
FB
901 ts->mem_allocated = 0;
902 ts->fixed_reg = 0;
903 }
c896fe29
FB
904 for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
905 s->reg_to_temp[i] = -1;
906 }
907}
908
ac56dd48
PB
909static char *tcg_get_arg_str_idx(TCGContext *s, char *buf, int buf_size,
910 int idx)
c896fe29
FB
911{
912 TCGTemp *ts;
ac56dd48 913
7f6f0ae5 914 assert(idx >= 0 && idx < s->nb_temps);
ac56dd48
PB
915 ts = &s->temps[idx];
916 if (idx < s->nb_globals) {
917 pstrcpy(buf, buf_size, ts->name);
c896fe29 918 } else {
641d5fbe
FB
919 if (ts->temp_local)
920 snprintf(buf, buf_size, "loc%d", idx - s->nb_globals);
921 else
922 snprintf(buf, buf_size, "tmp%d", idx - s->nb_globals);
c896fe29
FB
923 }
924 return buf;
925}
926
a7812ae4
PB
927char *tcg_get_arg_str_i32(TCGContext *s, char *buf, int buf_size, TCGv_i32 arg)
928{
929 return tcg_get_arg_str_idx(s, buf, buf_size, GET_TCGV_I32(arg));
930}
931
932char *tcg_get_arg_str_i64(TCGContext *s, char *buf, int buf_size, TCGv_i64 arg)
ac56dd48 933{
a810a2de 934 return tcg_get_arg_str_idx(s, buf, buf_size, GET_TCGV_I64(arg));
ac56dd48
PB
935}
936
6e085f72
RH
937/* Find helper name. */
938static inline const char *tcg_find_helper(TCGContext *s, uintptr_t val)
4dc81f28 939{
6e085f72
RH
940 const char *ret = NULL;
941 if (s->helpers) {
72866e82
RH
942 TCGHelperInfo *info = g_hash_table_lookup(s->helpers, (gpointer)val);
943 if (info) {
944 ret = info->name;
945 }
4dc81f28 946 }
6e085f72 947 return ret;
4dc81f28
FB
948}
949
f48f3ede
BS
950static const char * const cond_name[] =
951{
0aed257f
RH
952 [TCG_COND_NEVER] = "never",
953 [TCG_COND_ALWAYS] = "always",
f48f3ede
BS
954 [TCG_COND_EQ] = "eq",
955 [TCG_COND_NE] = "ne",
956 [TCG_COND_LT] = "lt",
957 [TCG_COND_GE] = "ge",
958 [TCG_COND_LE] = "le",
959 [TCG_COND_GT] = "gt",
960 [TCG_COND_LTU] = "ltu",
961 [TCG_COND_GEU] = "geu",
962 [TCG_COND_LEU] = "leu",
963 [TCG_COND_GTU] = "gtu"
964};
965
f713d6ad
RH
966static const char * const ldst_name[] =
967{
968 [MO_UB] = "ub",
969 [MO_SB] = "sb",
970 [MO_LEUW] = "leuw",
971 [MO_LESW] = "lesw",
972 [MO_LEUL] = "leul",
973 [MO_LESL] = "lesl",
974 [MO_LEQ] = "leq",
975 [MO_BEUW] = "beuw",
976 [MO_BESW] = "besw",
977 [MO_BEUL] = "beul",
978 [MO_BESL] = "besl",
979 [MO_BEQ] = "beq",
980};
981
eeacee4d 982void tcg_dump_ops(TCGContext *s)
c896fe29 983{
c896fe29 984 char buf[128];
c45cb8bb
RH
985 TCGOp *op;
986 int oi;
987
988 for (oi = s->gen_first_op_idx; oi >= 0; oi = op->next) {
989 int i, k, nb_oargs, nb_iargs, nb_cargs;
990 const TCGOpDef *def;
991 const TCGArg *args;
992 TCGOpcode c;
c896fe29 993
c45cb8bb
RH
994 op = &s->gen_op_buf[oi];
995 c = op->opc;
c896fe29 996 def = &tcg_op_defs[c];
c45cb8bb
RH
997 args = &s->gen_opparam_buf[op->args];
998
7e4597d7
FB
999 if (c == INDEX_op_debug_insn_start) {
1000 uint64_t pc;
1001#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
1002 pc = ((uint64_t)args[1] << 32) | args[0];
1003#else
1004 pc = args[0];
1005#endif
c45cb8bb 1006 if (oi != s->gen_first_op_idx) {
eeacee4d
BS
1007 qemu_log("\n");
1008 }
1009 qemu_log(" ---- 0x%" PRIx64, pc);
7e4597d7 1010 } else if (c == INDEX_op_call) {
c896fe29 1011 /* variable number of arguments */
c45cb8bb
RH
1012 nb_oargs = op->callo;
1013 nb_iargs = op->calli;
c896fe29 1014 nb_cargs = def->nb_cargs;
c896fe29 1015
cf066674
RH
1016 /* function name, flags, out args */
1017 qemu_log(" %s %s,$0x%" TCG_PRIlx ",$%d", def->name,
1018 tcg_find_helper(s, args[nb_oargs + nb_iargs]),
1019 args[nb_oargs + nb_iargs + 1], nb_oargs);
1020 for (i = 0; i < nb_oargs; i++) {
1021 qemu_log(",%s", tcg_get_arg_str_idx(s, buf, sizeof(buf),
eeacee4d 1022 args[i]));
b03cce8e 1023 }
cf066674
RH
1024 for (i = 0; i < nb_iargs; i++) {
1025 TCGArg arg = args[nb_oargs + i];
1026 const char *t = "<dummy>";
1027 if (arg != TCG_CALL_DUMMY_ARG) {
1028 t = tcg_get_arg_str_idx(s, buf, sizeof(buf), arg);
eeacee4d 1029 }
cf066674 1030 qemu_log(",%s", t);
e8996ee0 1031 }
b03cce8e 1032 } else {
eeacee4d 1033 qemu_log(" %s ", def->name);
c45cb8bb
RH
1034
1035 nb_oargs = def->nb_oargs;
1036 nb_iargs = def->nb_iargs;
1037 nb_cargs = def->nb_cargs;
1038
b03cce8e 1039 k = 0;
c45cb8bb 1040 for (i = 0; i < nb_oargs; i++) {
eeacee4d
BS
1041 if (k != 0) {
1042 qemu_log(",");
1043 }
1044 qemu_log("%s", tcg_get_arg_str_idx(s, buf, sizeof(buf),
1045 args[k++]));
b03cce8e 1046 }
c45cb8bb 1047 for (i = 0; i < nb_iargs; i++) {
eeacee4d
BS
1048 if (k != 0) {
1049 qemu_log(",");
1050 }
1051 qemu_log("%s", tcg_get_arg_str_idx(s, buf, sizeof(buf),
1052 args[k++]));
b03cce8e 1053 }
be210acb
RH
1054 switch (c) {
1055 case INDEX_op_brcond_i32:
be210acb 1056 case INDEX_op_setcond_i32:
ffc5ea09 1057 case INDEX_op_movcond_i32:
ffc5ea09 1058 case INDEX_op_brcond2_i32:
be210acb 1059 case INDEX_op_setcond2_i32:
ffc5ea09 1060 case INDEX_op_brcond_i64:
be210acb 1061 case INDEX_op_setcond_i64:
ffc5ea09 1062 case INDEX_op_movcond_i64:
eeacee4d
BS
1063 if (args[k] < ARRAY_SIZE(cond_name) && cond_name[args[k]]) {
1064 qemu_log(",%s", cond_name[args[k++]]);
1065 } else {
1066 qemu_log(",$0x%" TCG_PRIlx, args[k++]);
1067 }
f48f3ede 1068 i = 1;
be210acb 1069 break;
f713d6ad
RH
1070 case INDEX_op_qemu_ld_i32:
1071 case INDEX_op_qemu_st_i32:
1072 case INDEX_op_qemu_ld_i64:
1073 case INDEX_op_qemu_st_i64:
59227d5d
RH
1074 {
1075 TCGMemOpIdx oi = args[k++];
1076 TCGMemOp op = get_memop(oi);
1077 unsigned ix = get_mmuidx(oi);
1078
59c4b7e8 1079 if (op & ~(MO_AMASK | MO_BSWAP | MO_SSIZE)) {
59227d5d 1080 qemu_log(",$0x%x,%u", op, ix);
59c4b7e8
RH
1081 } else {
1082 const char *s_al = "", *s_op;
1083 if (op & MO_AMASK) {
1084 if ((op & MO_AMASK) == MO_ALIGN) {
1085 s_al = "al+";
1086 } else {
1087 s_al = "un+";
1088 }
1089 }
1090 s_op = ldst_name[op & (MO_BSWAP | MO_SSIZE)];
1091 qemu_log(",%s%s,%u", s_al, s_op, ix);
59227d5d
RH
1092 }
1093 i = 1;
f713d6ad 1094 }
f713d6ad 1095 break;
be210acb 1096 default:
f48f3ede 1097 i = 0;
be210acb
RH
1098 break;
1099 }
51e3972c
RH
1100 switch (c) {
1101 case INDEX_op_set_label:
1102 case INDEX_op_br:
1103 case INDEX_op_brcond_i32:
1104 case INDEX_op_brcond_i64:
1105 case INDEX_op_brcond2_i32:
1106 qemu_log("%s$L%d", k ? "," : "", arg_label(args[k])->id);
1107 i++, k++;
1108 break;
1109 default:
1110 break;
1111 }
1112 for (; i < nb_cargs; i++, k++) {
1113 qemu_log("%s$0x%" TCG_PRIlx, k ? "," : "", args[k]);
b03cce8e 1114 }
c896fe29 1115 }
eeacee4d 1116 qemu_log("\n");
c896fe29
FB
1117 }
1118}
1119
1120/* we give more priority to constraints with less registers */
1121static int get_constraint_priority(const TCGOpDef *def, int k)
1122{
1123 const TCGArgConstraint *arg_ct;
1124
1125 int i, n;
1126 arg_ct = &def->args_ct[k];
1127 if (arg_ct->ct & TCG_CT_ALIAS) {
1128 /* an alias is equivalent to a single register */
1129 n = 1;
1130 } else {
1131 if (!(arg_ct->ct & TCG_CT_REG))
1132 return 0;
1133 n = 0;
1134 for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
1135 if (tcg_regset_test_reg(arg_ct->u.regs, i))
1136 n++;
1137 }
1138 }
1139 return TCG_TARGET_NB_REGS - n + 1;
1140}
1141
1142/* sort from highest priority to lowest */
1143static void sort_constraints(TCGOpDef *def, int start, int n)
1144{
1145 int i, j, p1, p2, tmp;
1146
1147 for(i = 0; i < n; i++)
1148 def->sorted_args[start + i] = start + i;
1149 if (n <= 1)
1150 return;
1151 for(i = 0; i < n - 1; i++) {
1152 for(j = i + 1; j < n; j++) {
1153 p1 = get_constraint_priority(def, def->sorted_args[start + i]);
1154 p2 = get_constraint_priority(def, def->sorted_args[start + j]);
1155 if (p1 < p2) {
1156 tmp = def->sorted_args[start + i];
1157 def->sorted_args[start + i] = def->sorted_args[start + j];
1158 def->sorted_args[start + j] = tmp;
1159 }
1160 }
1161 }
1162}
1163
1164void tcg_add_target_add_op_defs(const TCGTargetOpDef *tdefs)
1165{
a9751609 1166 TCGOpcode op;
c896fe29
FB
1167 TCGOpDef *def;
1168 const char *ct_str;
1169 int i, nb_args;
1170
1171 for(;;) {
a9751609 1172 if (tdefs->op == (TCGOpcode)-1)
c896fe29
FB
1173 break;
1174 op = tdefs->op;
c3b08d0e 1175 assert((unsigned)op < NB_OPS);
c896fe29 1176 def = &tcg_op_defs[op];
c68aaa18
SW
1177#if defined(CONFIG_DEBUG_TCG)
1178 /* Duplicate entry in op definitions? */
1179 assert(!def->used);
1180 def->used = 1;
1181#endif
c896fe29
FB
1182 nb_args = def->nb_iargs + def->nb_oargs;
1183 for(i = 0; i < nb_args; i++) {
1184 ct_str = tdefs->args_ct_str[i];
c68aaa18
SW
1185 /* Incomplete TCGTargetOpDef entry? */
1186 assert(ct_str != NULL);
c896fe29
FB
1187 tcg_regset_clear(def->args_ct[i].u.regs);
1188 def->args_ct[i].ct = 0;
1189 if (ct_str[0] >= '0' && ct_str[0] <= '9') {
1190 int oarg;
1191 oarg = ct_str[0] - '0';
1192 assert(oarg < def->nb_oargs);
1193 assert(def->args_ct[oarg].ct & TCG_CT_REG);
1194 /* TCG_CT_ALIAS is for the output arguments. The input
5ff9d6a4 1195 argument is tagged with TCG_CT_IALIAS. */
c896fe29 1196 def->args_ct[i] = def->args_ct[oarg];
5ff9d6a4
FB
1197 def->args_ct[oarg].ct = TCG_CT_ALIAS;
1198 def->args_ct[oarg].alias_index = i;
c896fe29 1199 def->args_ct[i].ct |= TCG_CT_IALIAS;
5ff9d6a4 1200 def->args_ct[i].alias_index = oarg;
c896fe29
FB
1201 } else {
1202 for(;;) {
1203 if (*ct_str == '\0')
1204 break;
1205 switch(*ct_str) {
1206 case 'i':
1207 def->args_ct[i].ct |= TCG_CT_CONST;
1208 ct_str++;
1209 break;
1210 default:
1211 if (target_parse_constraint(&def->args_ct[i], &ct_str) < 0) {
1212 fprintf(stderr, "Invalid constraint '%s' for arg %d of operation '%s'\n",
1213 ct_str, i, def->name);
1214 exit(1);
1215 }
1216 }
1217 }
1218 }
1219 }
1220
c68aaa18
SW
1221 /* TCGTargetOpDef entry with too much information? */
1222 assert(i == TCG_MAX_OP_ARGS || tdefs->args_ct_str[i] == NULL);
1223
c896fe29
FB
1224 /* sort the constraints (XXX: this is just an heuristic) */
1225 sort_constraints(def, 0, def->nb_oargs);
1226 sort_constraints(def, def->nb_oargs, def->nb_iargs);
1227
1228#if 0
1229 {
1230 int i;
1231
1232 printf("%s: sorted=", def->name);
1233 for(i = 0; i < def->nb_oargs + def->nb_iargs; i++)
1234 printf(" %d", def->sorted_args[i]);
1235 printf("\n");
1236 }
1237#endif
1238 tdefs++;
1239 }
1240
c68aaa18 1241#if defined(CONFIG_DEBUG_TCG)
a9751609 1242 i = 0;
c68aaa18 1243 for (op = 0; op < ARRAY_SIZE(tcg_op_defs); op++) {
f412c762 1244 const TCGOpDef *def = &tcg_op_defs[op];
c1a61f6c 1245 if (def->flags & TCG_OPF_NOT_PRESENT) {
c68aaa18 1246 /* Wrong entry in op definitions? */
f412c762
RH
1247 if (def->used) {
1248 fprintf(stderr, "Invalid op definition for %s\n", def->name);
a9751609
RH
1249 i = 1;
1250 }
c68aaa18
SW
1251 } else {
1252 /* Missing entry in op definitions? */
f412c762
RH
1253 if (!def->used) {
1254 fprintf(stderr, "Missing op definition for %s\n", def->name);
a9751609
RH
1255 i = 1;
1256 }
c68aaa18
SW
1257 }
1258 }
a9751609
RH
1259 if (i == 1) {
1260 tcg_abort();
1261 }
c68aaa18 1262#endif
c896fe29
FB
1263}
1264
0c627cdc
RH
1265void tcg_op_remove(TCGContext *s, TCGOp *op)
1266{
1267 int next = op->next;
1268 int prev = op->prev;
1269
1270 if (next >= 0) {
1271 s->gen_op_buf[next].prev = prev;
1272 } else {
1273 s->gen_last_op_idx = prev;
1274 }
1275 if (prev >= 0) {
1276 s->gen_op_buf[prev].next = next;
1277 } else {
1278 s->gen_first_op_idx = next;
1279 }
1280
15fc7daa 1281 memset(op, -1, sizeof(*op));
0c627cdc
RH
1282
1283#ifdef CONFIG_PROFILER
1284 s->del_op_count++;
1285#endif
1286}
1287
c896fe29 1288#ifdef USE_LIVENESS_ANALYSIS
9c43b68d
AJ
1289/* liveness analysis: end of function: all temps are dead, and globals
1290 should be in memory. */
1291static inline void tcg_la_func_end(TCGContext *s, uint8_t *dead_temps,
1292 uint8_t *mem_temps)
c896fe29 1293{
9c43b68d
AJ
1294 memset(dead_temps, 1, s->nb_temps);
1295 memset(mem_temps, 1, s->nb_globals);
1296 memset(mem_temps + s->nb_globals, 0, s->nb_temps - s->nb_globals);
c896fe29
FB
1297}
1298
9c43b68d
AJ
1299/* liveness analysis: end of basic block: all temps are dead, globals
1300 and local temps should be in memory. */
1301static inline void tcg_la_bb_end(TCGContext *s, uint8_t *dead_temps,
1302 uint8_t *mem_temps)
641d5fbe
FB
1303{
1304 int i;
641d5fbe 1305
9c43b68d
AJ
1306 memset(dead_temps, 1, s->nb_temps);
1307 memset(mem_temps, 1, s->nb_globals);
641d5fbe 1308 for(i = s->nb_globals; i < s->nb_temps; i++) {
9c43b68d 1309 mem_temps[i] = s->temps[i].temp_local;
641d5fbe
FB
1310 }
1311}
1312
866cb6cb 1313/* Liveness analysis : update the opc_dead_args array to tell if a
c896fe29
FB
1314 given input arguments is dead. Instructions updating dead
1315 temporaries are removed. */
8fcd3692 1316static void tcg_liveness_analysis(TCGContext *s)
c896fe29 1317{
9c43b68d 1318 uint8_t *dead_temps, *mem_temps;
c45cb8bb 1319 int oi, oi_prev, nb_ops;
c896fe29 1320
c45cb8bb 1321 nb_ops = s->gen_next_op_idx;
866cb6cb 1322 s->op_dead_args = tcg_malloc(nb_ops * sizeof(uint16_t));
ec7a869d 1323 s->op_sync_args = tcg_malloc(nb_ops * sizeof(uint8_t));
c896fe29
FB
1324
1325 dead_temps = tcg_malloc(s->nb_temps);
9c43b68d
AJ
1326 mem_temps = tcg_malloc(s->nb_temps);
1327 tcg_la_func_end(s, dead_temps, mem_temps);
c896fe29 1328
c45cb8bb
RH
1329 for (oi = s->gen_last_op_idx; oi >= 0; oi = oi_prev) {
1330 int i, nb_iargs, nb_oargs;
1331 TCGOpcode opc_new, opc_new2;
1332 bool have_opc_new2;
1333 uint16_t dead_args;
1334 uint8_t sync_args;
1335 TCGArg arg;
1336
1337 TCGOp * const op = &s->gen_op_buf[oi];
1338 TCGArg * const args = &s->gen_opparam_buf[op->args];
1339 TCGOpcode opc = op->opc;
1340 const TCGOpDef *def = &tcg_op_defs[opc];
1341
1342 oi_prev = op->prev;
1343
1344 switch (opc) {
c896fe29 1345 case INDEX_op_call:
c6e113f5
FB
1346 {
1347 int call_flags;
c896fe29 1348
c45cb8bb
RH
1349 nb_oargs = op->callo;
1350 nb_iargs = op->calli;
cf066674 1351 call_flags = args[nb_oargs + nb_iargs + 1];
c6e113f5 1352
c45cb8bb 1353 /* pure functions can be removed if their result is unused */
78505279 1354 if (call_flags & TCG_CALL_NO_SIDE_EFFECTS) {
cf066674 1355 for (i = 0; i < nb_oargs; i++) {
c6e113f5 1356 arg = args[i];
9c43b68d 1357 if (!dead_temps[arg] || mem_temps[arg]) {
c6e113f5 1358 goto do_not_remove_call;
9c43b68d 1359 }
c6e113f5 1360 }
c45cb8bb 1361 goto do_remove;
c6e113f5
FB
1362 } else {
1363 do_not_remove_call:
c896fe29 1364
c6e113f5 1365 /* output args are dead */
6b64b624 1366 dead_args = 0;
ec7a869d 1367 sync_args = 0;
cf066674 1368 for (i = 0; i < nb_oargs; i++) {
c6e113f5 1369 arg = args[i];
6b64b624
AJ
1370 if (dead_temps[arg]) {
1371 dead_args |= (1 << i);
1372 }
9c43b68d
AJ
1373 if (mem_temps[arg]) {
1374 sync_args |= (1 << i);
1375 }
c6e113f5 1376 dead_temps[arg] = 1;
9c43b68d 1377 mem_temps[arg] = 0;
c6e113f5 1378 }
78505279
AJ
1379
1380 if (!(call_flags & TCG_CALL_NO_READ_GLOBALS)) {
1381 /* globals should be synced to memory */
1382 memset(mem_temps, 1, s->nb_globals);
1383 }
1384 if (!(call_flags & (TCG_CALL_NO_WRITE_GLOBALS |
1385 TCG_CALL_NO_READ_GLOBALS))) {
9c43b68d
AJ
1386 /* globals should go back to memory */
1387 memset(dead_temps, 1, s->nb_globals);
b9c18f56
AJ
1388 }
1389
c19f47bf 1390 /* record arguments that die in this helper */
cf066674 1391 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
866cb6cb 1392 arg = args[i];
39cf05d3
FB
1393 if (arg != TCG_CALL_DUMMY_ARG) {
1394 if (dead_temps[arg]) {
866cb6cb 1395 dead_args |= (1 << i);
39cf05d3 1396 }
c6e113f5 1397 }
c6e113f5 1398 }
c19f47bf
AJ
1399 /* input arguments are live for preceeding opcodes */
1400 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
1401 arg = args[i];
1402 dead_temps[arg] = 0;
1403 }
c45cb8bb
RH
1404 s->op_dead_args[oi] = dead_args;
1405 s->op_sync_args[oi] = sync_args;
c896fe29 1406 }
c896fe29 1407 }
c896fe29 1408 break;
7e4597d7 1409 case INDEX_op_debug_insn_start:
c896fe29 1410 break;
5ff9d6a4 1411 case INDEX_op_discard:
5ff9d6a4
FB
1412 /* mark the temporary as dead */
1413 dead_temps[args[0]] = 1;
9c43b68d 1414 mem_temps[args[0]] = 0;
5ff9d6a4 1415 break;
1305c451
RH
1416
1417 case INDEX_op_add2_i32:
c45cb8bb 1418 opc_new = INDEX_op_add_i32;
f1fae40c 1419 goto do_addsub2;
1305c451 1420 case INDEX_op_sub2_i32:
c45cb8bb 1421 opc_new = INDEX_op_sub_i32;
f1fae40c
RH
1422 goto do_addsub2;
1423 case INDEX_op_add2_i64:
c45cb8bb 1424 opc_new = INDEX_op_add_i64;
f1fae40c
RH
1425 goto do_addsub2;
1426 case INDEX_op_sub2_i64:
c45cb8bb 1427 opc_new = INDEX_op_sub_i64;
f1fae40c 1428 do_addsub2:
1305c451
RH
1429 nb_iargs = 4;
1430 nb_oargs = 2;
1431 /* Test if the high part of the operation is dead, but not
1432 the low part. The result can be optimized to a simple
1433 add or sub. This happens often for x86_64 guest when the
1434 cpu mode is set to 32 bit. */
3c5645fa
KB
1435 if (dead_temps[args[1]] && !mem_temps[args[1]]) {
1436 if (dead_temps[args[0]] && !mem_temps[args[0]]) {
1305c451
RH
1437 goto do_remove;
1438 }
c45cb8bb
RH
1439 /* Replace the opcode and adjust the args in place,
1440 leaving 3 unused args at the end. */
1441 op->opc = opc = opc_new;
1305c451
RH
1442 args[1] = args[2];
1443 args[2] = args[4];
1305c451
RH
1444 /* Fall through and mark the single-word operation live. */
1445 nb_iargs = 2;
1446 nb_oargs = 1;
1447 }
1448 goto do_not_remove;
1449
1414968a 1450 case INDEX_op_mulu2_i32:
c45cb8bb
RH
1451 opc_new = INDEX_op_mul_i32;
1452 opc_new2 = INDEX_op_muluh_i32;
1453 have_opc_new2 = TCG_TARGET_HAS_muluh_i32;
03271524 1454 goto do_mul2;
f1fae40c 1455 case INDEX_op_muls2_i32:
c45cb8bb
RH
1456 opc_new = INDEX_op_mul_i32;
1457 opc_new2 = INDEX_op_mulsh_i32;
1458 have_opc_new2 = TCG_TARGET_HAS_mulsh_i32;
f1fae40c
RH
1459 goto do_mul2;
1460 case INDEX_op_mulu2_i64:
c45cb8bb
RH
1461 opc_new = INDEX_op_mul_i64;
1462 opc_new2 = INDEX_op_muluh_i64;
1463 have_opc_new2 = TCG_TARGET_HAS_muluh_i64;
03271524 1464 goto do_mul2;
f1fae40c 1465 case INDEX_op_muls2_i64:
c45cb8bb
RH
1466 opc_new = INDEX_op_mul_i64;
1467 opc_new2 = INDEX_op_mulsh_i64;
1468 have_opc_new2 = TCG_TARGET_HAS_mulsh_i64;
03271524 1469 goto do_mul2;
f1fae40c 1470 do_mul2:
1414968a
RH
1471 nb_iargs = 2;
1472 nb_oargs = 2;
3c5645fa
KB
1473 if (dead_temps[args[1]] && !mem_temps[args[1]]) {
1474 if (dead_temps[args[0]] && !mem_temps[args[0]]) {
03271524 1475 /* Both parts of the operation are dead. */
1414968a
RH
1476 goto do_remove;
1477 }
03271524 1478 /* The high part of the operation is dead; generate the low. */
c45cb8bb 1479 op->opc = opc = opc_new;
1414968a
RH
1480 args[1] = args[2];
1481 args[2] = args[3];
c45cb8bb 1482 } else if (have_opc_new2 && dead_temps[args[0]]
03271524 1483 && !mem_temps[args[0]]) {
c45cb8bb
RH
1484 /* The low part of the operation is dead; generate the high. */
1485 op->opc = opc = opc_new2;
03271524
RH
1486 args[0] = args[1];
1487 args[1] = args[2];
1488 args[2] = args[3];
1489 } else {
1490 goto do_not_remove;
1414968a 1491 }
03271524
RH
1492 /* Mark the single-word operation live. */
1493 nb_oargs = 1;
1414968a
RH
1494 goto do_not_remove;
1495
c896fe29 1496 default:
1305c451 1497 /* XXX: optimize by hardcoding common cases (e.g. triadic ops) */
49516bc0
AJ
1498 nb_iargs = def->nb_iargs;
1499 nb_oargs = def->nb_oargs;
c896fe29 1500
49516bc0
AJ
1501 /* Test if the operation can be removed because all
1502 its outputs are dead. We assume that nb_oargs == 0
1503 implies side effects */
1504 if (!(def->flags & TCG_OPF_SIDE_EFFECTS) && nb_oargs != 0) {
c45cb8bb 1505 for (i = 0; i < nb_oargs; i++) {
49516bc0 1506 arg = args[i];
9c43b68d 1507 if (!dead_temps[arg] || mem_temps[arg]) {
49516bc0 1508 goto do_not_remove;
9c43b68d 1509 }
49516bc0 1510 }
1305c451 1511 do_remove:
0c627cdc 1512 tcg_op_remove(s, op);
49516bc0
AJ
1513 } else {
1514 do_not_remove:
49516bc0 1515 /* output args are dead */
6b64b624 1516 dead_args = 0;
ec7a869d 1517 sync_args = 0;
c45cb8bb 1518 for (i = 0; i < nb_oargs; i++) {
49516bc0 1519 arg = args[i];
6b64b624
AJ
1520 if (dead_temps[arg]) {
1521 dead_args |= (1 << i);
1522 }
9c43b68d
AJ
1523 if (mem_temps[arg]) {
1524 sync_args |= (1 << i);
1525 }
49516bc0 1526 dead_temps[arg] = 1;
9c43b68d 1527 mem_temps[arg] = 0;
49516bc0
AJ
1528 }
1529
1530 /* if end of basic block, update */
1531 if (def->flags & TCG_OPF_BB_END) {
9c43b68d 1532 tcg_la_bb_end(s, dead_temps, mem_temps);
3d5c5f87
AJ
1533 } else if (def->flags & TCG_OPF_SIDE_EFFECTS) {
1534 /* globals should be synced to memory */
9c43b68d 1535 memset(mem_temps, 1, s->nb_globals);
49516bc0
AJ
1536 }
1537
c19f47bf 1538 /* record arguments that die in this opcode */
c45cb8bb 1539 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
866cb6cb 1540 arg = args[i];
49516bc0 1541 if (dead_temps[arg]) {
866cb6cb 1542 dead_args |= (1 << i);
c896fe29 1543 }
c19f47bf
AJ
1544 }
1545 /* input arguments are live for preceeding opcodes */
1546 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
1547 arg = args[i];
49516bc0 1548 dead_temps[arg] = 0;
c896fe29 1549 }
c45cb8bb
RH
1550 s->op_dead_args[oi] = dead_args;
1551 s->op_sync_args[oi] = sync_args;
c896fe29
FB
1552 }
1553 break;
1554 }
1ff0a2c5 1555 }
c896fe29
FB
1556}
1557#else
1558/* dummy liveness analysis */
655feed5 1559static void tcg_liveness_analysis(TCGContext *s)
c896fe29
FB
1560{
1561 int nb_ops;
92414b31 1562 nb_ops = s->gen_opc_ptr - s->gen_opc_buf;
c896fe29 1563
866cb6cb
AJ
1564 s->op_dead_args = tcg_malloc(nb_ops * sizeof(uint16_t));
1565 memset(s->op_dead_args, 0, nb_ops * sizeof(uint16_t));
ec7a869d
AJ
1566 s->op_sync_args = tcg_malloc(nb_ops * sizeof(uint8_t));
1567 memset(s->op_sync_args, 0, nb_ops * sizeof(uint8_t));
c896fe29
FB
1568}
1569#endif
1570
1571#ifndef NDEBUG
1572static void dump_regs(TCGContext *s)
1573{
1574 TCGTemp *ts;
1575 int i;
1576 char buf[64];
1577
1578 for(i = 0; i < s->nb_temps; i++) {
1579 ts = &s->temps[i];
ac56dd48 1580 printf(" %10s: ", tcg_get_arg_str_idx(s, buf, sizeof(buf), i));
c896fe29
FB
1581 switch(ts->val_type) {
1582 case TEMP_VAL_REG:
1583 printf("%s", tcg_target_reg_names[ts->reg]);
1584 break;
1585 case TEMP_VAL_MEM:
1586 printf("%d(%s)", (int)ts->mem_offset, tcg_target_reg_names[ts->mem_reg]);
1587 break;
1588 case TEMP_VAL_CONST:
1589 printf("$0x%" TCG_PRIlx, ts->val);
1590 break;
1591 case TEMP_VAL_DEAD:
1592 printf("D");
1593 break;
1594 default:
1595 printf("???");
1596 break;
1597 }
1598 printf("\n");
1599 }
1600
1601 for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
1602 if (s->reg_to_temp[i] >= 0) {
1603 printf("%s: %s\n",
1604 tcg_target_reg_names[i],
ac56dd48 1605 tcg_get_arg_str_idx(s, buf, sizeof(buf), s->reg_to_temp[i]));
c896fe29
FB
1606 }
1607 }
1608}
1609
1610static void check_regs(TCGContext *s)
1611{
1612 int reg, k;
1613 TCGTemp *ts;
1614 char buf[64];
1615
1616 for(reg = 0; reg < TCG_TARGET_NB_REGS; reg++) {
1617 k = s->reg_to_temp[reg];
1618 if (k >= 0) {
1619 ts = &s->temps[k];
1620 if (ts->val_type != TEMP_VAL_REG ||
1621 ts->reg != reg) {
1622 printf("Inconsistency for register %s:\n",
1623 tcg_target_reg_names[reg]);
b03cce8e 1624 goto fail;
c896fe29
FB
1625 }
1626 }
1627 }
1628 for(k = 0; k < s->nb_temps; k++) {
1629 ts = &s->temps[k];
1630 if (ts->val_type == TEMP_VAL_REG &&
1631 !ts->fixed_reg &&
1632 s->reg_to_temp[ts->reg] != k) {
1633 printf("Inconsistency for temp %s:\n",
ac56dd48 1634 tcg_get_arg_str_idx(s, buf, sizeof(buf), k));
b03cce8e 1635 fail:
c896fe29
FB
1636 printf("reg state:\n");
1637 dump_regs(s);
1638 tcg_abort();
1639 }
1640 }
1641}
1642#endif
1643
1644static void temp_allocate_frame(TCGContext *s, int temp)
1645{
1646 TCGTemp *ts;
1647 ts = &s->temps[temp];
9b9c37c3
RH
1648#if !(defined(__sparc__) && TCG_TARGET_REG_BITS == 64)
1649 /* Sparc64 stack is accessed with offset of 2047 */
b591dc59
BS
1650 s->current_frame_offset = (s->current_frame_offset +
1651 (tcg_target_long)sizeof(tcg_target_long) - 1) &
1652 ~(sizeof(tcg_target_long) - 1);
f44c9960 1653#endif
b591dc59
BS
1654 if (s->current_frame_offset + (tcg_target_long)sizeof(tcg_target_long) >
1655 s->frame_end) {
5ff9d6a4 1656 tcg_abort();
b591dc59 1657 }
c896fe29
FB
1658 ts->mem_offset = s->current_frame_offset;
1659 ts->mem_reg = s->frame_reg;
1660 ts->mem_allocated = 1;
e2c6d1b4 1661 s->current_frame_offset += sizeof(tcg_target_long);
c896fe29
FB
1662}
1663
7f6ceedf
AJ
1664/* sync register 'reg' by saving it to the corresponding temporary */
1665static inline void tcg_reg_sync(TCGContext *s, int reg)
1666{
1667 TCGTemp *ts;
1668 int temp;
1669
1670 temp = s->reg_to_temp[reg];
1671 ts = &s->temps[temp];
1672 assert(ts->val_type == TEMP_VAL_REG);
1673 if (!ts->mem_coherent && !ts->fixed_reg) {
1674 if (!ts->mem_allocated) {
1675 temp_allocate_frame(s, temp);
1676 }
1677 tcg_out_st(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
1678 }
1679 ts->mem_coherent = 1;
1680}
1681
c896fe29
FB
1682/* free register 'reg' by spilling the corresponding temporary if necessary */
1683static void tcg_reg_free(TCGContext *s, int reg)
1684{
c896fe29
FB
1685 int temp;
1686
1687 temp = s->reg_to_temp[reg];
1688 if (temp != -1) {
7f6ceedf
AJ
1689 tcg_reg_sync(s, reg);
1690 s->temps[temp].val_type = TEMP_VAL_MEM;
c896fe29
FB
1691 s->reg_to_temp[reg] = -1;
1692 }
1693}
1694
1695/* Allocate a register belonging to reg1 & ~reg2 */
1696static int tcg_reg_alloc(TCGContext *s, TCGRegSet reg1, TCGRegSet reg2)
1697{
1698 int i, reg;
1699 TCGRegSet reg_ct;
1700
1701 tcg_regset_andnot(reg_ct, reg1, reg2);
1702
1703 /* first try free registers */
0954d0d9 1704 for(i = 0; i < ARRAY_SIZE(tcg_target_reg_alloc_order); i++) {
c896fe29
FB
1705 reg = tcg_target_reg_alloc_order[i];
1706 if (tcg_regset_test_reg(reg_ct, reg) && s->reg_to_temp[reg] == -1)
1707 return reg;
1708 }
1709
1710 /* XXX: do better spill choice */
0954d0d9 1711 for(i = 0; i < ARRAY_SIZE(tcg_target_reg_alloc_order); i++) {
c896fe29
FB
1712 reg = tcg_target_reg_alloc_order[i];
1713 if (tcg_regset_test_reg(reg_ct, reg)) {
1714 tcg_reg_free(s, reg);
1715 return reg;
1716 }
1717 }
1718
1719 tcg_abort();
1720}
1721
639368dd
AJ
1722/* mark a temporary as dead. */
1723static inline void temp_dead(TCGContext *s, int temp)
1724{
1725 TCGTemp *ts;
1726
1727 ts = &s->temps[temp];
1728 if (!ts->fixed_reg) {
1729 if (ts->val_type == TEMP_VAL_REG) {
1730 s->reg_to_temp[ts->reg] = -1;
1731 }
e5138db5 1732 if (temp < s->nb_globals || ts->temp_local) {
639368dd
AJ
1733 ts->val_type = TEMP_VAL_MEM;
1734 } else {
1735 ts->val_type = TEMP_VAL_DEAD;
1736 }
1737 }
1738}
1739
1ad80729 1740/* sync a temporary to memory. 'allocated_regs' is used in case a
641d5fbe 1741 temporary registers needs to be allocated to store a constant. */
1ad80729 1742static inline void temp_sync(TCGContext *s, int temp, TCGRegSet allocated_regs)
641d5fbe
FB
1743{
1744 TCGTemp *ts;
641d5fbe
FB
1745
1746 ts = &s->temps[temp];
1747 if (!ts->fixed_reg) {
1748 switch(ts->val_type) {
1ad80729
AJ
1749 case TEMP_VAL_CONST:
1750 ts->reg = tcg_reg_alloc(s, tcg_target_available_regs[ts->type],
1751 allocated_regs);
1752 ts->val_type = TEMP_VAL_REG;
1753 s->reg_to_temp[ts->reg] = temp;
1754 ts->mem_coherent = 0;
1755 tcg_out_movi(s, ts->type, ts->reg, ts->val);
1756 /* fallthrough*/
641d5fbe 1757 case TEMP_VAL_REG:
1ad80729 1758 tcg_reg_sync(s, ts->reg);
641d5fbe
FB
1759 break;
1760 case TEMP_VAL_DEAD:
641d5fbe
FB
1761 case TEMP_VAL_MEM:
1762 break;
1763 default:
1764 tcg_abort();
1765 }
1766 }
1767}
1768
1ad80729
AJ
1769/* save a temporary to memory. 'allocated_regs' is used in case a
1770 temporary registers needs to be allocated to store a constant. */
1771static inline void temp_save(TCGContext *s, int temp, TCGRegSet allocated_regs)
1772{
2c0366f0
AJ
1773#ifdef USE_LIVENESS_ANALYSIS
1774 /* The liveness analysis already ensures that globals are back
1775 in memory. Keep an assert for safety. */
1776 assert(s->temps[temp].val_type == TEMP_VAL_MEM || s->temps[temp].fixed_reg);
1777#else
1ad80729
AJ
1778 temp_sync(s, temp, allocated_regs);
1779 temp_dead(s, temp);
2c0366f0 1780#endif
1ad80729
AJ
1781}
1782
9814dd27 1783/* save globals to their canonical location and assume they can be
e8996ee0
FB
1784 modified be the following code. 'allocated_regs' is used in case a
1785 temporary registers needs to be allocated to store a constant. */
1786static void save_globals(TCGContext *s, TCGRegSet allocated_regs)
c896fe29 1787{
641d5fbe 1788 int i;
c896fe29
FB
1789
1790 for(i = 0; i < s->nb_globals; i++) {
641d5fbe 1791 temp_save(s, i, allocated_regs);
c896fe29 1792 }
e5097dc8
FB
1793}
1794
3d5c5f87
AJ
1795/* sync globals to their canonical location and assume they can be
1796 read by the following code. 'allocated_regs' is used in case a
1797 temporary registers needs to be allocated to store a constant. */
1798static void sync_globals(TCGContext *s, TCGRegSet allocated_regs)
1799{
1800 int i;
1801
1802 for (i = 0; i < s->nb_globals; i++) {
1803#ifdef USE_LIVENESS_ANALYSIS
1804 assert(s->temps[i].val_type != TEMP_VAL_REG || s->temps[i].fixed_reg ||
1805 s->temps[i].mem_coherent);
1806#else
1807 temp_sync(s, i, allocated_regs);
1808#endif
1809 }
1810}
1811
e5097dc8 1812/* at the end of a basic block, we assume all temporaries are dead and
e8996ee0
FB
1813 all globals are stored at their canonical location. */
1814static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs)
e5097dc8
FB
1815{
1816 TCGTemp *ts;
1817 int i;
1818
c896fe29
FB
1819 for(i = s->nb_globals; i < s->nb_temps; i++) {
1820 ts = &s->temps[i];
641d5fbe
FB
1821 if (ts->temp_local) {
1822 temp_save(s, i, allocated_regs);
1823 } else {
2c0366f0
AJ
1824#ifdef USE_LIVENESS_ANALYSIS
1825 /* The liveness analysis already ensures that temps are dead.
1826 Keep an assert for safety. */
1827 assert(ts->val_type == TEMP_VAL_DEAD);
1828#else
639368dd 1829 temp_dead(s, i);
2c0366f0 1830#endif
c896fe29
FB
1831 }
1832 }
e8996ee0
FB
1833
1834 save_globals(s, allocated_regs);
c896fe29
FB
1835}
1836
866cb6cb 1837#define IS_DEAD_ARG(n) ((dead_args >> (n)) & 1)
ec7a869d 1838#define NEED_SYNC_ARG(n) ((sync_args >> (n)) & 1)
c896fe29 1839
ec7a869d
AJ
1840static void tcg_reg_alloc_movi(TCGContext *s, const TCGArg *args,
1841 uint16_t dead_args, uint8_t sync_args)
e8996ee0
FB
1842{
1843 TCGTemp *ots;
1844 tcg_target_ulong val;
1845
1846 ots = &s->temps[args[0]];
1847 val = args[1];
1848
1849 if (ots->fixed_reg) {
1850 /* for fixed registers, we do not do any constant
1851 propagation */
1852 tcg_out_movi(s, ots->type, ots->reg, val);
1853 } else {
1235fc06 1854 /* The movi is not explicitly generated here */
e8996ee0
FB
1855 if (ots->val_type == TEMP_VAL_REG)
1856 s->reg_to_temp[ots->reg] = -1;
1857 ots->val_type = TEMP_VAL_CONST;
1858 ots->val = val;
1859 }
ec7a869d
AJ
1860 if (NEED_SYNC_ARG(0)) {
1861 temp_sync(s, args[0], s->reserved_regs);
1862 }
4c4e1ab2
AJ
1863 if (IS_DEAD_ARG(0)) {
1864 temp_dead(s, args[0]);
1865 }
e8996ee0
FB
1866}
1867
c896fe29 1868static void tcg_reg_alloc_mov(TCGContext *s, const TCGOpDef *def,
ec7a869d
AJ
1869 const TCGArg *args, uint16_t dead_args,
1870 uint8_t sync_args)
c896fe29 1871{
c29c1d7e 1872 TCGRegSet allocated_regs;
c896fe29 1873 TCGTemp *ts, *ots;
450445d5 1874 TCGType otype, itype;
c896fe29 1875
c29c1d7e 1876 tcg_regset_set(allocated_regs, s->reserved_regs);
c896fe29
FB
1877 ots = &s->temps[args[0]];
1878 ts = &s->temps[args[1]];
450445d5
RH
1879
1880 /* Note that otype != itype for no-op truncation. */
1881 otype = ots->type;
1882 itype = ts->type;
c29c1d7e
AJ
1883
1884 /* If the source value is not in a register, and we're going to be
1885 forced to have it in a register in order to perform the copy,
1886 then copy the SOURCE value into its own register first. That way
1887 we don't have to reload SOURCE the next time it is used. */
1888 if (((NEED_SYNC_ARG(0) || ots->fixed_reg) && ts->val_type != TEMP_VAL_REG)
1889 || ts->val_type == TEMP_VAL_MEM) {
450445d5 1890 ts->reg = tcg_reg_alloc(s, tcg_target_available_regs[itype],
af3cbfbe 1891 allocated_regs);
c29c1d7e 1892 if (ts->val_type == TEMP_VAL_MEM) {
450445d5 1893 tcg_out_ld(s, itype, ts->reg, ts->mem_reg, ts->mem_offset);
c29c1d7e
AJ
1894 ts->mem_coherent = 1;
1895 } else if (ts->val_type == TEMP_VAL_CONST) {
450445d5 1896 tcg_out_movi(s, itype, ts->reg, ts->val);
c29c1d7e
AJ
1897 }
1898 s->reg_to_temp[ts->reg] = args[1];
1899 ts->val_type = TEMP_VAL_REG;
1900 }
c896fe29 1901
c29c1d7e
AJ
1902 if (IS_DEAD_ARG(0) && !ots->fixed_reg) {
1903 /* mov to a non-saved dead register makes no sense (even with
1904 liveness analysis disabled). */
1905 assert(NEED_SYNC_ARG(0));
1906 /* The code above should have moved the temp to a register. */
1907 assert(ts->val_type == TEMP_VAL_REG);
1908 if (!ots->mem_allocated) {
1909 temp_allocate_frame(s, args[0]);
1910 }
450445d5 1911 tcg_out_st(s, otype, ts->reg, ots->mem_reg, ots->mem_offset);
c29c1d7e
AJ
1912 if (IS_DEAD_ARG(1)) {
1913 temp_dead(s, args[1]);
1914 }
1915 temp_dead(s, args[0]);
1916 } else if (ts->val_type == TEMP_VAL_CONST) {
1917 /* propagate constant */
1918 if (ots->val_type == TEMP_VAL_REG) {
1919 s->reg_to_temp[ots->reg] = -1;
1920 }
1921 ots->val_type = TEMP_VAL_CONST;
1922 ots->val = ts->val;
1923 } else {
1924 /* The code in the first if block should have moved the
1925 temp to a register. */
1926 assert(ts->val_type == TEMP_VAL_REG);
866cb6cb 1927 if (IS_DEAD_ARG(1) && !ts->fixed_reg && !ots->fixed_reg) {
c896fe29 1928 /* the mov can be suppressed */
c29c1d7e 1929 if (ots->val_type == TEMP_VAL_REG) {
c896fe29 1930 s->reg_to_temp[ots->reg] = -1;
c29c1d7e
AJ
1931 }
1932 ots->reg = ts->reg;
639368dd 1933 temp_dead(s, args[1]);
c896fe29 1934 } else {
c29c1d7e
AJ
1935 if (ots->val_type != TEMP_VAL_REG) {
1936 /* When allocating a new register, make sure to not spill the
1937 input one. */
1938 tcg_regset_set_reg(allocated_regs, ts->reg);
450445d5 1939 ots->reg = tcg_reg_alloc(s, tcg_target_available_regs[otype],
af3cbfbe 1940 allocated_regs);
c896fe29 1941 }
450445d5 1942 tcg_out_mov(s, otype, ots->reg, ts->reg);
c896fe29 1943 }
c29c1d7e
AJ
1944 ots->val_type = TEMP_VAL_REG;
1945 ots->mem_coherent = 0;
1946 s->reg_to_temp[ots->reg] = args[0];
1947 if (NEED_SYNC_ARG(0)) {
1948 tcg_reg_sync(s, ots->reg);
c896fe29 1949 }
ec7a869d 1950 }
c896fe29
FB
1951}
1952
1953static void tcg_reg_alloc_op(TCGContext *s,
a9751609 1954 const TCGOpDef *def, TCGOpcode opc,
ec7a869d
AJ
1955 const TCGArg *args, uint16_t dead_args,
1956 uint8_t sync_args)
c896fe29
FB
1957{
1958 TCGRegSet allocated_regs;
1959 int i, k, nb_iargs, nb_oargs, reg;
1960 TCGArg arg;
1961 const TCGArgConstraint *arg_ct;
1962 TCGTemp *ts;
1963 TCGArg new_args[TCG_MAX_OP_ARGS];
1964 int const_args[TCG_MAX_OP_ARGS];
1965
1966 nb_oargs = def->nb_oargs;
1967 nb_iargs = def->nb_iargs;
1968
1969 /* copy constants */
1970 memcpy(new_args + nb_oargs + nb_iargs,
1971 args + nb_oargs + nb_iargs,
1972 sizeof(TCGArg) * def->nb_cargs);
1973
1974 /* satisfy input constraints */
1975 tcg_regset_set(allocated_regs, s->reserved_regs);
1976 for(k = 0; k < nb_iargs; k++) {
1977 i = def->sorted_args[nb_oargs + k];
1978 arg = args[i];
1979 arg_ct = &def->args_ct[i];
1980 ts = &s->temps[arg];
1981 if (ts->val_type == TEMP_VAL_MEM) {
1982 reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
e4d5434c 1983 tcg_out_ld(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
c896fe29
FB
1984 ts->val_type = TEMP_VAL_REG;
1985 ts->reg = reg;
1986 ts->mem_coherent = 1;
1987 s->reg_to_temp[reg] = arg;
1988 } else if (ts->val_type == TEMP_VAL_CONST) {
f6c6afc1 1989 if (tcg_target_const_match(ts->val, ts->type, arg_ct)) {
c896fe29
FB
1990 /* constant is OK for instruction */
1991 const_args[i] = 1;
1992 new_args[i] = ts->val;
1993 goto iarg_end;
1994 } else {
e8996ee0 1995 /* need to move to a register */
c896fe29
FB
1996 reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
1997 tcg_out_movi(s, ts->type, reg, ts->val);
e8996ee0
FB
1998 ts->val_type = TEMP_VAL_REG;
1999 ts->reg = reg;
2000 ts->mem_coherent = 0;
2001 s->reg_to_temp[reg] = arg;
c896fe29
FB
2002 }
2003 }
2004 assert(ts->val_type == TEMP_VAL_REG);
5ff9d6a4
FB
2005 if (arg_ct->ct & TCG_CT_IALIAS) {
2006 if (ts->fixed_reg) {
2007 /* if fixed register, we must allocate a new register
2008 if the alias is not the same register */
2009 if (arg != args[arg_ct->alias_index])
2010 goto allocate_in_reg;
2011 } else {
2012 /* if the input is aliased to an output and if it is
2013 not dead after the instruction, we must allocate
2014 a new register and move it */
866cb6cb 2015 if (!IS_DEAD_ARG(i)) {
5ff9d6a4 2016 goto allocate_in_reg;
866cb6cb 2017 }
7e1df267
AJ
2018 /* check if the current register has already been allocated
2019 for another input aliased to an output */
2020 int k2, i2;
2021 for (k2 = 0 ; k2 < k ; k2++) {
2022 i2 = def->sorted_args[nb_oargs + k2];
2023 if ((def->args_ct[i2].ct & TCG_CT_IALIAS) &&
2024 (new_args[i2] == ts->reg)) {
2025 goto allocate_in_reg;
2026 }
2027 }
5ff9d6a4 2028 }
c896fe29
FB
2029 }
2030 reg = ts->reg;
2031 if (tcg_regset_test_reg(arg_ct->u.regs, reg)) {
2032 /* nothing to do : the constraint is satisfied */
2033 } else {
2034 allocate_in_reg:
2035 /* allocate a new register matching the constraint
2036 and move the temporary register into it */
2037 reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
3b6dac34 2038 tcg_out_mov(s, ts->type, reg, ts->reg);
c896fe29 2039 }
c896fe29
FB
2040 new_args[i] = reg;
2041 const_args[i] = 0;
2042 tcg_regset_set_reg(allocated_regs, reg);
2043 iarg_end: ;
2044 }
2045
a52ad07e
AJ
2046 /* mark dead temporaries and free the associated registers */
2047 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
2048 if (IS_DEAD_ARG(i)) {
2049 temp_dead(s, args[i]);
2050 }
2051 }
2052
e8996ee0
FB
2053 if (def->flags & TCG_OPF_BB_END) {
2054 tcg_reg_alloc_bb_end(s, allocated_regs);
2055 } else {
e8996ee0
FB
2056 if (def->flags & TCG_OPF_CALL_CLOBBER) {
2057 /* XXX: permit generic clobber register list ? */
2058 for(reg = 0; reg < TCG_TARGET_NB_REGS; reg++) {
2059 if (tcg_regset_test_reg(tcg_target_call_clobber_regs, reg)) {
2060 tcg_reg_free(s, reg);
2061 }
c896fe29 2062 }
3d5c5f87
AJ
2063 }
2064 if (def->flags & TCG_OPF_SIDE_EFFECTS) {
2065 /* sync globals if the op has side effects and might trigger
2066 an exception. */
2067 sync_globals(s, allocated_regs);
c896fe29 2068 }
e8996ee0
FB
2069
2070 /* satisfy the output constraints */
2071 tcg_regset_set(allocated_regs, s->reserved_regs);
2072 for(k = 0; k < nb_oargs; k++) {
2073 i = def->sorted_args[k];
2074 arg = args[i];
2075 arg_ct = &def->args_ct[i];
2076 ts = &s->temps[arg];
2077 if (arg_ct->ct & TCG_CT_ALIAS) {
2078 reg = new_args[arg_ct->alias_index];
2079 } else {
2080 /* if fixed register, we try to use it */
2081 reg = ts->reg;
2082 if (ts->fixed_reg &&
2083 tcg_regset_test_reg(arg_ct->u.regs, reg)) {
2084 goto oarg_end;
2085 }
2086 reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
c896fe29 2087 }
e8996ee0
FB
2088 tcg_regset_set_reg(allocated_regs, reg);
2089 /* if a fixed register is used, then a move will be done afterwards */
2090 if (!ts->fixed_reg) {
ec7a869d
AJ
2091 if (ts->val_type == TEMP_VAL_REG) {
2092 s->reg_to_temp[ts->reg] = -1;
2093 }
2094 ts->val_type = TEMP_VAL_REG;
2095 ts->reg = reg;
2096 /* temp value is modified, so the value kept in memory is
2097 potentially not the same */
2098 ts->mem_coherent = 0;
2099 s->reg_to_temp[reg] = arg;
e8996ee0
FB
2100 }
2101 oarg_end:
2102 new_args[i] = reg;
c896fe29 2103 }
c896fe29
FB
2104 }
2105
c896fe29
FB
2106 /* emit instruction */
2107 tcg_out_op(s, opc, new_args, const_args);
2108
2109 /* move the outputs in the correct register if needed */
2110 for(i = 0; i < nb_oargs; i++) {
2111 ts = &s->temps[args[i]];
2112 reg = new_args[i];
2113 if (ts->fixed_reg && ts->reg != reg) {
3b6dac34 2114 tcg_out_mov(s, ts->type, ts->reg, reg);
c896fe29 2115 }
ec7a869d
AJ
2116 if (NEED_SYNC_ARG(i)) {
2117 tcg_reg_sync(s, reg);
2118 }
2119 if (IS_DEAD_ARG(i)) {
2120 temp_dead(s, args[i]);
2121 }
c896fe29
FB
2122 }
2123}
2124
b03cce8e
FB
2125#ifdef TCG_TARGET_STACK_GROWSUP
2126#define STACK_DIR(x) (-(x))
2127#else
2128#define STACK_DIR(x) (x)
2129#endif
2130
c45cb8bb
RH
2131static void tcg_reg_alloc_call(TCGContext *s, int nb_oargs, int nb_iargs,
2132 const TCGArg * const args, uint16_t dead_args,
2133 uint8_t sync_args)
c896fe29 2134{
c45cb8bb 2135 int flags, nb_regs, i, reg;
cf066674 2136 TCGArg arg;
c896fe29 2137 TCGTemp *ts;
d3452f1f
RH
2138 intptr_t stack_offset;
2139 size_t call_stack_size;
cf066674
RH
2140 tcg_insn_unit *func_addr;
2141 int allocate_args;
c896fe29 2142 TCGRegSet allocated_regs;
c896fe29 2143
cf066674
RH
2144 func_addr = (tcg_insn_unit *)(intptr_t)args[nb_oargs + nb_iargs];
2145 flags = args[nb_oargs + nb_iargs + 1];
c896fe29 2146
6e17d0c5 2147 nb_regs = ARRAY_SIZE(tcg_target_call_iarg_regs);
c45cb8bb
RH
2148 if (nb_regs > nb_iargs) {
2149 nb_regs = nb_iargs;
cf066674 2150 }
c896fe29
FB
2151
2152 /* assign stack slots first */
c45cb8bb 2153 call_stack_size = (nb_iargs - nb_regs) * sizeof(tcg_target_long);
c896fe29
FB
2154 call_stack_size = (call_stack_size + TCG_TARGET_STACK_ALIGN - 1) &
2155 ~(TCG_TARGET_STACK_ALIGN - 1);
b03cce8e
FB
2156 allocate_args = (call_stack_size > TCG_STATIC_CALL_ARGS_SIZE);
2157 if (allocate_args) {
345649c0
BS
2158 /* XXX: if more than TCG_STATIC_CALL_ARGS_SIZE is needed,
2159 preallocate call stack */
2160 tcg_abort();
b03cce8e 2161 }
39cf05d3
FB
2162
2163 stack_offset = TCG_TARGET_CALL_STACK_OFFSET;
c45cb8bb 2164 for(i = nb_regs; i < nb_iargs; i++) {
c896fe29 2165 arg = args[nb_oargs + i];
39cf05d3
FB
2166#ifdef TCG_TARGET_STACK_GROWSUP
2167 stack_offset -= sizeof(tcg_target_long);
2168#endif
2169 if (arg != TCG_CALL_DUMMY_ARG) {
2170 ts = &s->temps[arg];
2171 if (ts->val_type == TEMP_VAL_REG) {
2172 tcg_out_st(s, ts->type, ts->reg, TCG_REG_CALL_STACK, stack_offset);
2173 } else if (ts->val_type == TEMP_VAL_MEM) {
2174 reg = tcg_reg_alloc(s, tcg_target_available_regs[ts->type],
2175 s->reserved_regs);
2176 /* XXX: not correct if reading values from the stack */
2177 tcg_out_ld(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
2178 tcg_out_st(s, ts->type, reg, TCG_REG_CALL_STACK, stack_offset);
2179 } else if (ts->val_type == TEMP_VAL_CONST) {
2180 reg = tcg_reg_alloc(s, tcg_target_available_regs[ts->type],
2181 s->reserved_regs);
2182 /* XXX: sign extend may be needed on some targets */
2183 tcg_out_movi(s, ts->type, reg, ts->val);
2184 tcg_out_st(s, ts->type, reg, TCG_REG_CALL_STACK, stack_offset);
2185 } else {
2186 tcg_abort();
2187 }
c896fe29 2188 }
39cf05d3
FB
2189#ifndef TCG_TARGET_STACK_GROWSUP
2190 stack_offset += sizeof(tcg_target_long);
2191#endif
c896fe29
FB
2192 }
2193
2194 /* assign input registers */
2195 tcg_regset_set(allocated_regs, s->reserved_regs);
2196 for(i = 0; i < nb_regs; i++) {
2197 arg = args[nb_oargs + i];
39cf05d3
FB
2198 if (arg != TCG_CALL_DUMMY_ARG) {
2199 ts = &s->temps[arg];
2200 reg = tcg_target_call_iarg_regs[i];
2201 tcg_reg_free(s, reg);
2202 if (ts->val_type == TEMP_VAL_REG) {
2203 if (ts->reg != reg) {
3b6dac34 2204 tcg_out_mov(s, ts->type, reg, ts->reg);
39cf05d3
FB
2205 }
2206 } else if (ts->val_type == TEMP_VAL_MEM) {
2207 tcg_out_ld(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
2208 } else if (ts->val_type == TEMP_VAL_CONST) {
2209 /* XXX: sign extend ? */
2210 tcg_out_movi(s, ts->type, reg, ts->val);
2211 } else {
2212 tcg_abort();
c896fe29 2213 }
39cf05d3 2214 tcg_regset_set_reg(allocated_regs, reg);
c896fe29 2215 }
c896fe29
FB
2216 }
2217
c896fe29 2218 /* mark dead temporaries and free the associated registers */
866cb6cb 2219 for(i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
866cb6cb 2220 if (IS_DEAD_ARG(i)) {
639368dd 2221 temp_dead(s, args[i]);
c896fe29
FB
2222 }
2223 }
2224
2225 /* clobber call registers */
2226 for(reg = 0; reg < TCG_TARGET_NB_REGS; reg++) {
2227 if (tcg_regset_test_reg(tcg_target_call_clobber_regs, reg)) {
2228 tcg_reg_free(s, reg);
2229 }
2230 }
78505279
AJ
2231
2232 /* Save globals if they might be written by the helper, sync them if
2233 they might be read. */
2234 if (flags & TCG_CALL_NO_READ_GLOBALS) {
2235 /* Nothing to do */
2236 } else if (flags & TCG_CALL_NO_WRITE_GLOBALS) {
2237 sync_globals(s, allocated_regs);
2238 } else {
b9c18f56
AJ
2239 save_globals(s, allocated_regs);
2240 }
c896fe29 2241
cf066674 2242 tcg_out_call(s, func_addr);
c896fe29
FB
2243
2244 /* assign output registers and emit moves if needed */
2245 for(i = 0; i < nb_oargs; i++) {
2246 arg = args[i];
2247 ts = &s->temps[arg];
2248 reg = tcg_target_call_oarg_regs[i];
e8996ee0 2249 assert(s->reg_to_temp[reg] == -1);
34b1a49c 2250
c896fe29
FB
2251 if (ts->fixed_reg) {
2252 if (ts->reg != reg) {
3b6dac34 2253 tcg_out_mov(s, ts->type, ts->reg, reg);
c896fe29
FB
2254 }
2255 } else {
ec7a869d
AJ
2256 if (ts->val_type == TEMP_VAL_REG) {
2257 s->reg_to_temp[ts->reg] = -1;
2258 }
2259 ts->val_type = TEMP_VAL_REG;
2260 ts->reg = reg;
2261 ts->mem_coherent = 0;
2262 s->reg_to_temp[reg] = arg;
2263 if (NEED_SYNC_ARG(i)) {
2264 tcg_reg_sync(s, reg);
2265 }
8c11ad25 2266 if (IS_DEAD_ARG(i)) {
639368dd 2267 temp_dead(s, args[i]);
8c11ad25 2268 }
c896fe29
FB
2269 }
2270 }
c896fe29
FB
2271}
2272
2273#ifdef CONFIG_PROFILER
2274
54604f74 2275static int64_t tcg_table_op_count[NB_OPS];
c896fe29 2276
246ae24d 2277void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf)
c896fe29
FB
2278{
2279 int i;
d70724ce 2280
15fc7daa 2281 for (i = 0; i < NB_OPS; i++) {
246ae24d
MF
2282 cpu_fprintf(f, "%s %" PRId64 "\n", tcg_op_defs[i].name,
2283 tcg_table_op_count[i]);
c896fe29 2284 }
c896fe29 2285}
246ae24d
MF
2286#else
2287void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf)
2288{
2289 cpu_fprintf(f, "[TCG profiler not compiled]\n");
2290}
c896fe29
FB
2291#endif
2292
2293
1813e175
RH
2294static inline int tcg_gen_code_common(TCGContext *s,
2295 tcg_insn_unit *gen_code_buf,
2ba1eeb6 2296 long search_pc)
c896fe29 2297{
c45cb8bb 2298 int oi, oi_next;
c896fe29
FB
2299
2300#ifdef DEBUG_DISAS
8fec2b8c 2301 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
93fcfe39 2302 qemu_log("OP:\n");
eeacee4d 2303 tcg_dump_ops(s);
93fcfe39 2304 qemu_log("\n");
c896fe29
FB
2305 }
2306#endif
2307
c5cc28ff
AJ
2308#ifdef CONFIG_PROFILER
2309 s->opt_time -= profile_getclock();
2310#endif
2311
8f2e8c07 2312#ifdef USE_TCG_OPTIMIZATIONS
c45cb8bb 2313 tcg_optimize(s);
8f2e8c07
KB
2314#endif
2315
a23a9ec6 2316#ifdef CONFIG_PROFILER
c5cc28ff 2317 s->opt_time += profile_getclock();
a23a9ec6
FB
2318 s->la_time -= profile_getclock();
2319#endif
c5cc28ff 2320
c896fe29 2321 tcg_liveness_analysis(s);
c5cc28ff 2322
a23a9ec6
FB
2323#ifdef CONFIG_PROFILER
2324 s->la_time += profile_getclock();
2325#endif
c896fe29
FB
2326
2327#ifdef DEBUG_DISAS
8fec2b8c 2328 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT))) {
c5cc28ff 2329 qemu_log("OP after optimization and liveness analysis:\n");
eeacee4d 2330 tcg_dump_ops(s);
93fcfe39 2331 qemu_log("\n");
c896fe29
FB
2332 }
2333#endif
2334
2335 tcg_reg_alloc_start(s);
2336
2337 s->code_buf = gen_code_buf;
2338 s->code_ptr = gen_code_buf;
2339
9ecefc84
RH
2340 tcg_out_tb_init(s);
2341
c45cb8bb
RH
2342 for (oi = s->gen_first_op_idx; oi >= 0; oi = oi_next) {
2343 TCGOp * const op = &s->gen_op_buf[oi];
2344 TCGArg * const args = &s->gen_opparam_buf[op->args];
2345 TCGOpcode opc = op->opc;
2346 const TCGOpDef *def = &tcg_op_defs[opc];
2347 uint16_t dead_args = s->op_dead_args[oi];
2348 uint8_t sync_args = s->op_sync_args[oi];
b3db8758 2349
c45cb8bb 2350 oi_next = op->next;
c896fe29 2351#ifdef CONFIG_PROFILER
54604f74 2352 tcg_table_op_count[opc]++;
c896fe29 2353#endif
c45cb8bb
RH
2354
2355 switch (opc) {
c896fe29 2356 case INDEX_op_mov_i32:
c896fe29 2357 case INDEX_op_mov_i64:
c45cb8bb 2358 tcg_reg_alloc_mov(s, def, args, dead_args, sync_args);
c896fe29 2359 break;
e8996ee0 2360 case INDEX_op_movi_i32:
e8996ee0 2361 case INDEX_op_movi_i64:
c45cb8bb 2362 tcg_reg_alloc_movi(s, args, dead_args, sync_args);
e8996ee0 2363 break;
7e4597d7 2364 case INDEX_op_debug_insn_start:
c896fe29 2365 break;
5ff9d6a4 2366 case INDEX_op_discard:
639368dd 2367 temp_dead(s, args[0]);
5ff9d6a4 2368 break;
c896fe29 2369 case INDEX_op_set_label:
e8996ee0 2370 tcg_reg_alloc_bb_end(s, s->reserved_regs);
bec16311 2371 tcg_out_label(s, arg_label(args[0]), s->code_ptr);
c896fe29
FB
2372 break;
2373 case INDEX_op_call:
c45cb8bb
RH
2374 tcg_reg_alloc_call(s, op->callo, op->calli, args,
2375 dead_args, sync_args);
2376 break;
c896fe29 2377 default:
25c4d9cc
RH
2378 /* Sanity check that we've not introduced any unhandled opcodes. */
2379 if (def->flags & TCG_OPF_NOT_PRESENT) {
2380 tcg_abort();
2381 }
c896fe29
FB
2382 /* Note: in order to speed up the code, it would be much
2383 faster to have specialized register allocator functions for
2384 some common argument patterns */
c45cb8bb 2385 tcg_reg_alloc_op(s, def, opc, args, dead_args, sync_args);
c896fe29
FB
2386 break;
2387 }
1813e175 2388 if (search_pc >= 0 && search_pc < tcg_current_code_size(s)) {
c45cb8bb 2389 return oi;
c896fe29 2390 }
c896fe29
FB
2391#ifndef NDEBUG
2392 check_regs(s);
2393#endif
2394 }
c45cb8bb 2395
b76f0d8c
YL
2396 /* Generate TB finalization at the end of block */
2397 tcg_out_tb_finalize(s);
c896fe29
FB
2398 return -1;
2399}
2400
1813e175 2401int tcg_gen_code(TCGContext *s, tcg_insn_unit *gen_code_buf)
c896fe29
FB
2402{
2403#ifdef CONFIG_PROFILER
2404 {
c896fe29 2405 int n;
c45cb8bb
RH
2406
2407 n = s->gen_last_op_idx + 1;
a23a9ec6 2408 s->op_count += n;
c45cb8bb 2409 if (n > s->op_count_max) {
a23a9ec6 2410 s->op_count_max = n;
c45cb8bb 2411 }
a23a9ec6 2412
c45cb8bb
RH
2413 n = s->nb_temps;
2414 s->temp_count += n;
2415 if (n > s->temp_count_max) {
2416 s->temp_count_max = n;
2417 }
c896fe29
FB
2418 }
2419#endif
2420
2ba1eeb6 2421 tcg_gen_code_common(s, gen_code_buf, -1);
c896fe29
FB
2422
2423 /* flush instruction cache */
1813e175 2424 flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr);
2aeabc08 2425
1813e175 2426 return tcg_current_code_size(s);
c896fe29
FB
2427}
2428
2ba1eeb6 2429/* Return the index of the micro operation such as the pc after is <
623e265c
PB
2430 offset bytes from the start of the TB. The contents of gen_code_buf must
2431 not be changed, though writing the same values is ok.
2432 Return -1 if not found. */
1813e175
RH
2433int tcg_gen_code_search_pc(TCGContext *s, tcg_insn_unit *gen_code_buf,
2434 long offset)
c896fe29 2435{
623e265c 2436 return tcg_gen_code_common(s, gen_code_buf, offset);
c896fe29 2437}
a23a9ec6
FB
2438
2439#ifdef CONFIG_PROFILER
405cf9ff 2440void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf)
a23a9ec6
FB
2441{
2442 TCGContext *s = &tcg_ctx;
2443 int64_t tot;
2444
2445 tot = s->interm_time + s->code_time;
2446 cpu_fprintf(f, "JIT cycles %" PRId64 " (%0.3f s at 2.4 GHz)\n",
2447 tot, tot / 2.4e9);
2448 cpu_fprintf(f, "translated TBs %" PRId64 " (aborted=%" PRId64 " %0.1f%%)\n",
2449 s->tb_count,
2450 s->tb_count1 - s->tb_count,
2451 s->tb_count1 ? (double)(s->tb_count1 - s->tb_count) / s->tb_count1 * 100.0 : 0);
2452 cpu_fprintf(f, "avg ops/TB %0.1f max=%d\n",
2453 s->tb_count ? (double)s->op_count / s->tb_count : 0, s->op_count_max);
a23a9ec6
FB
2454 cpu_fprintf(f, "deleted ops/TB %0.2f\n",
2455 s->tb_count ?
2456 (double)s->del_op_count / s->tb_count : 0);
2457 cpu_fprintf(f, "avg temps/TB %0.2f max=%d\n",
2458 s->tb_count ?
2459 (double)s->temp_count / s->tb_count : 0,
2460 s->temp_count_max);
2461
2462 cpu_fprintf(f, "cycles/op %0.1f\n",
2463 s->op_count ? (double)tot / s->op_count : 0);
2464 cpu_fprintf(f, "cycles/in byte %0.1f\n",
2465 s->code_in_len ? (double)tot / s->code_in_len : 0);
2466 cpu_fprintf(f, "cycles/out byte %0.1f\n",
2467 s->code_out_len ? (double)tot / s->code_out_len : 0);
2468 if (tot == 0)
2469 tot = 1;
2470 cpu_fprintf(f, " gen_interm time %0.1f%%\n",
2471 (double)s->interm_time / tot * 100.0);
2472 cpu_fprintf(f, " gen_code time %0.1f%%\n",
2473 (double)s->code_time / tot * 100.0);
c5cc28ff
AJ
2474 cpu_fprintf(f, "optim./code time %0.1f%%\n",
2475 (double)s->opt_time / (s->code_time ? s->code_time : 1)
2476 * 100.0);
a23a9ec6
FB
2477 cpu_fprintf(f, "liveness/code time %0.1f%%\n",
2478 (double)s->la_time / (s->code_time ? s->code_time : 1) * 100.0);
2479 cpu_fprintf(f, "cpu_restore count %" PRId64 "\n",
2480 s->restore_count);
2481 cpu_fprintf(f, " avg cycles %0.1f\n",
2482 s->restore_count ? (double)s->restore_time / s->restore_count : 0);
a23a9ec6
FB
2483}
2484#else
405cf9ff 2485void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf)
a23a9ec6 2486{
24bf7b3a 2487 cpu_fprintf(f, "[TCG profiler not compiled]\n");
a23a9ec6
FB
2488}
2489#endif
813da627
RH
2490
2491#ifdef ELF_HOST_MACHINE
5872bbf2
RH
2492/* In order to use this feature, the backend needs to do three things:
2493
2494 (1) Define ELF_HOST_MACHINE to indicate both what value to
2495 put into the ELF image and to indicate support for the feature.
2496
2497 (2) Define tcg_register_jit. This should create a buffer containing
2498 the contents of a .debug_frame section that describes the post-
2499 prologue unwind info for the tcg machine.
2500
2501 (3) Call tcg_register_jit_int, with the constructed .debug_frame.
2502*/
813da627
RH
2503
2504/* Begin GDB interface. THE FOLLOWING MUST MATCH GDB DOCS. */
2505typedef enum {
2506 JIT_NOACTION = 0,
2507 JIT_REGISTER_FN,
2508 JIT_UNREGISTER_FN
2509} jit_actions_t;
2510
2511struct jit_code_entry {
2512 struct jit_code_entry *next_entry;
2513 struct jit_code_entry *prev_entry;
2514 const void *symfile_addr;
2515 uint64_t symfile_size;
2516};
2517
2518struct jit_descriptor {
2519 uint32_t version;
2520 uint32_t action_flag;
2521 struct jit_code_entry *relevant_entry;
2522 struct jit_code_entry *first_entry;
2523};
2524
2525void __jit_debug_register_code(void) __attribute__((noinline));
2526void __jit_debug_register_code(void)
2527{
2528 asm("");
2529}
2530
2531/* Must statically initialize the version, because GDB may check
2532 the version before we can set it. */
2533struct jit_descriptor __jit_debug_descriptor = { 1, 0, 0, 0 };
2534
2535/* End GDB interface. */
2536
2537static int find_string(const char *strtab, const char *str)
2538{
2539 const char *p = strtab + 1;
2540
2541 while (1) {
2542 if (strcmp(p, str) == 0) {
2543 return p - strtab;
2544 }
2545 p += strlen(p) + 1;
2546 }
2547}
2548
5872bbf2 2549static void tcg_register_jit_int(void *buf_ptr, size_t buf_size,
2c90784a
RH
2550 const void *debug_frame,
2551 size_t debug_frame_size)
813da627 2552{
5872bbf2
RH
2553 struct __attribute__((packed)) DebugInfo {
2554 uint32_t len;
2555 uint16_t version;
2556 uint32_t abbrev;
2557 uint8_t ptr_size;
2558 uint8_t cu_die;
2559 uint16_t cu_lang;
2560 uintptr_t cu_low_pc;
2561 uintptr_t cu_high_pc;
2562 uint8_t fn_die;
2563 char fn_name[16];
2564 uintptr_t fn_low_pc;
2565 uintptr_t fn_high_pc;
2566 uint8_t cu_eoc;
2567 };
813da627
RH
2568
2569 struct ElfImage {
2570 ElfW(Ehdr) ehdr;
2571 ElfW(Phdr) phdr;
5872bbf2
RH
2572 ElfW(Shdr) shdr[7];
2573 ElfW(Sym) sym[2];
2574 struct DebugInfo di;
2575 uint8_t da[24];
2576 char str[80];
2577 };
2578
2579 struct ElfImage *img;
2580
2581 static const struct ElfImage img_template = {
2582 .ehdr = {
2583 .e_ident[EI_MAG0] = ELFMAG0,
2584 .e_ident[EI_MAG1] = ELFMAG1,
2585 .e_ident[EI_MAG2] = ELFMAG2,
2586 .e_ident[EI_MAG3] = ELFMAG3,
2587 .e_ident[EI_CLASS] = ELF_CLASS,
2588 .e_ident[EI_DATA] = ELF_DATA,
2589 .e_ident[EI_VERSION] = EV_CURRENT,
2590 .e_type = ET_EXEC,
2591 .e_machine = ELF_HOST_MACHINE,
2592 .e_version = EV_CURRENT,
2593 .e_phoff = offsetof(struct ElfImage, phdr),
2594 .e_shoff = offsetof(struct ElfImage, shdr),
2595 .e_ehsize = sizeof(ElfW(Shdr)),
2596 .e_phentsize = sizeof(ElfW(Phdr)),
2597 .e_phnum = 1,
2598 .e_shentsize = sizeof(ElfW(Shdr)),
2599 .e_shnum = ARRAY_SIZE(img->shdr),
2600 .e_shstrndx = ARRAY_SIZE(img->shdr) - 1,
abbb3eae
RH
2601#ifdef ELF_HOST_FLAGS
2602 .e_flags = ELF_HOST_FLAGS,
2603#endif
2604#ifdef ELF_OSABI
2605 .e_ident[EI_OSABI] = ELF_OSABI,
2606#endif
5872bbf2
RH
2607 },
2608 .phdr = {
2609 .p_type = PT_LOAD,
2610 .p_flags = PF_X,
2611 },
2612 .shdr = {
2613 [0] = { .sh_type = SHT_NULL },
2614 /* Trick: The contents of code_gen_buffer are not present in
2615 this fake ELF file; that got allocated elsewhere. Therefore
2616 we mark .text as SHT_NOBITS (similar to .bss) so that readers
2617 will not look for contents. We can record any address. */
2618 [1] = { /* .text */
2619 .sh_type = SHT_NOBITS,
2620 .sh_flags = SHF_EXECINSTR | SHF_ALLOC,
2621 },
2622 [2] = { /* .debug_info */
2623 .sh_type = SHT_PROGBITS,
2624 .sh_offset = offsetof(struct ElfImage, di),
2625 .sh_size = sizeof(struct DebugInfo),
2626 },
2627 [3] = { /* .debug_abbrev */
2628 .sh_type = SHT_PROGBITS,
2629 .sh_offset = offsetof(struct ElfImage, da),
2630 .sh_size = sizeof(img->da),
2631 },
2632 [4] = { /* .debug_frame */
2633 .sh_type = SHT_PROGBITS,
2634 .sh_offset = sizeof(struct ElfImage),
2635 },
2636 [5] = { /* .symtab */
2637 .sh_type = SHT_SYMTAB,
2638 .sh_offset = offsetof(struct ElfImage, sym),
2639 .sh_size = sizeof(img->sym),
2640 .sh_info = 1,
2641 .sh_link = ARRAY_SIZE(img->shdr) - 1,
2642 .sh_entsize = sizeof(ElfW(Sym)),
2643 },
2644 [6] = { /* .strtab */
2645 .sh_type = SHT_STRTAB,
2646 .sh_offset = offsetof(struct ElfImage, str),
2647 .sh_size = sizeof(img->str),
2648 }
2649 },
2650 .sym = {
2651 [1] = { /* code_gen_buffer */
2652 .st_info = ELF_ST_INFO(STB_GLOBAL, STT_FUNC),
2653 .st_shndx = 1,
2654 }
2655 },
2656 .di = {
2657 .len = sizeof(struct DebugInfo) - 4,
2658 .version = 2,
2659 .ptr_size = sizeof(void *),
2660 .cu_die = 1,
2661 .cu_lang = 0x8001, /* DW_LANG_Mips_Assembler */
2662 .fn_die = 2,
2663 .fn_name = "code_gen_buffer"
2664 },
2665 .da = {
2666 1, /* abbrev number (the cu) */
2667 0x11, 1, /* DW_TAG_compile_unit, has children */
2668 0x13, 0x5, /* DW_AT_language, DW_FORM_data2 */
2669 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */
2670 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */
2671 0, 0, /* end of abbrev */
2672 2, /* abbrev number (the fn) */
2673 0x2e, 0, /* DW_TAG_subprogram, no children */
2674 0x3, 0x8, /* DW_AT_name, DW_FORM_string */
2675 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */
2676 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */
2677 0, 0, /* end of abbrev */
2678 0 /* no more abbrev */
2679 },
2680 .str = "\0" ".text\0" ".debug_info\0" ".debug_abbrev\0"
2681 ".debug_frame\0" ".symtab\0" ".strtab\0" "code_gen_buffer",
813da627
RH
2682 };
2683
2684 /* We only need a single jit entry; statically allocate it. */
2685 static struct jit_code_entry one_entry;
2686
5872bbf2 2687 uintptr_t buf = (uintptr_t)buf_ptr;
813da627 2688 size_t img_size = sizeof(struct ElfImage) + debug_frame_size;
2c90784a 2689 DebugFrameHeader *dfh;
813da627 2690
5872bbf2
RH
2691 img = g_malloc(img_size);
2692 *img = img_template;
813da627 2693
5872bbf2
RH
2694 img->phdr.p_vaddr = buf;
2695 img->phdr.p_paddr = buf;
2696 img->phdr.p_memsz = buf_size;
813da627 2697
813da627 2698 img->shdr[1].sh_name = find_string(img->str, ".text");
5872bbf2 2699 img->shdr[1].sh_addr = buf;
813da627
RH
2700 img->shdr[1].sh_size = buf_size;
2701
5872bbf2
RH
2702 img->shdr[2].sh_name = find_string(img->str, ".debug_info");
2703 img->shdr[3].sh_name = find_string(img->str, ".debug_abbrev");
2704
2705 img->shdr[4].sh_name = find_string(img->str, ".debug_frame");
2706 img->shdr[4].sh_size = debug_frame_size;
2707
2708 img->shdr[5].sh_name = find_string(img->str, ".symtab");
2709 img->shdr[6].sh_name = find_string(img->str, ".strtab");
2710
2711 img->sym[1].st_name = find_string(img->str, "code_gen_buffer");
2712 img->sym[1].st_value = buf;
2713 img->sym[1].st_size = buf_size;
813da627 2714
5872bbf2 2715 img->di.cu_low_pc = buf;
45aba097 2716 img->di.cu_high_pc = buf + buf_size;
5872bbf2 2717 img->di.fn_low_pc = buf;
45aba097 2718 img->di.fn_high_pc = buf + buf_size;
813da627 2719
2c90784a
RH
2720 dfh = (DebugFrameHeader *)(img + 1);
2721 memcpy(dfh, debug_frame, debug_frame_size);
2722 dfh->fde.func_start = buf;
2723 dfh->fde.func_len = buf_size;
2724
813da627
RH
2725#ifdef DEBUG_JIT
2726 /* Enable this block to be able to debug the ELF image file creation.
2727 One can use readelf, objdump, or other inspection utilities. */
2728 {
2729 FILE *f = fopen("/tmp/qemu.jit", "w+b");
2730 if (f) {
5872bbf2 2731 if (fwrite(img, img_size, 1, f) != img_size) {
813da627
RH
2732 /* Avoid stupid unused return value warning for fwrite. */
2733 }
2734 fclose(f);
2735 }
2736 }
2737#endif
2738
2739 one_entry.symfile_addr = img;
2740 one_entry.symfile_size = img_size;
2741
2742 __jit_debug_descriptor.action_flag = JIT_REGISTER_FN;
2743 __jit_debug_descriptor.relevant_entry = &one_entry;
2744 __jit_debug_descriptor.first_entry = &one_entry;
2745 __jit_debug_register_code();
2746}
2747#else
5872bbf2
RH
2748/* No support for the feature. Provide the entry point expected by exec.c,
2749 and implement the internal function we declared earlier. */
813da627
RH
2750
2751static void tcg_register_jit_int(void *buf, size_t size,
2c90784a
RH
2752 const void *debug_frame,
2753 size_t debug_frame_size)
813da627
RH
2754{
2755}
2756
2757void tcg_register_jit(void *buf, size_t buf_size)
2758{
2759}
2760#endif /* ELF_HOST_MACHINE */