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9a75b0a0 JS |
1 | /* |
2 | * libqos AHCI functions | |
3 | * | |
4 | * Copyright (c) 2014 John Snow <jsnow@redhat.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
53239262 | 25 | #include "qemu/osdep.h" |
9a75b0a0 JS |
26 | |
27 | #include "libqtest.h" | |
28 | #include "libqos/ahci.h" | |
29 | #include "libqos/pci-pc.h" | |
30 | ||
31 | #include "qemu-common.h" | |
32 | #include "qemu/host-utils.h" | |
33 | ||
34 | #include "hw/pci/pci_ids.h" | |
35 | #include "hw/pci/pci_regs.h" | |
36 | ||
716b6407 JS |
37 | typedef struct AHCICommandProp { |
38 | uint8_t cmd; /* Command Code */ | |
39 | bool data; /* Data transfer command? */ | |
40 | bool pio; | |
41 | bool dma; | |
42 | bool lba28; | |
43 | bool lba48; | |
44 | bool read; | |
45 | bool write; | |
46 | bool atapi; | |
47 | bool ncq; | |
48 | uint64_t size; /* Static transfer size, for commands like IDENTIFY. */ | |
49 | uint32_t interrupts; /* Expected interrupts for this command. */ | |
50 | } AHCICommandProp; | |
51 | ||
52 | AHCICommandProp ahci_command_properties[] = { | |
26ad0045 JS |
53 | { .cmd = CMD_READ_PIO, .data = true, .pio = true, |
54 | .lba28 = true, .read = true }, | |
55 | { .cmd = CMD_WRITE_PIO, .data = true, .pio = true, | |
56 | .lba28 = true, .write = true }, | |
57 | { .cmd = CMD_READ_PIO_EXT, .data = true, .pio = true, | |
58 | .lba48 = true, .read = true }, | |
59 | { .cmd = CMD_WRITE_PIO_EXT, .data = true, .pio = true, | |
60 | .lba48 = true, .write = true }, | |
61 | { .cmd = CMD_READ_DMA, .data = true, .dma = true, | |
62 | .lba28 = true, .read = true }, | |
63 | { .cmd = CMD_WRITE_DMA, .data = true, .dma = true, | |
64 | .lba28 = true, .write = true }, | |
65 | { .cmd = CMD_READ_DMA_EXT, .data = true, .dma = true, | |
66 | .lba48 = true, .read = true }, | |
67 | { .cmd = CMD_WRITE_DMA_EXT, .data = true, .dma = true, | |
68 | .lba48 = true, .write = true }, | |
69 | { .cmd = CMD_IDENTIFY, .data = true, .pio = true, | |
70 | .size = 512, .read = true }, | |
71 | { .cmd = READ_FPDMA_QUEUED, .data = true, .dma = true, | |
72 | .lba48 = true, .read = true, .ncq = true }, | |
73 | { .cmd = WRITE_FPDMA_QUEUED, .data = true, .dma = true, | |
74 | .lba48 = true, .write = true, .ncq = true }, | |
75 | { .cmd = CMD_READ_MAX, .lba28 = true }, | |
76 | { .cmd = CMD_READ_MAX_EXT, .lba48 = true }, | |
54d268b2 JS |
77 | { .cmd = CMD_FLUSH_CACHE, .data = false }, |
78 | { .cmd = CMD_PACKET, .data = true, .size = 16, | |
b88641e2 | 79 | .atapi = true, .pio = true }, |
54d268b2 JS |
80 | { .cmd = CMD_PACKET_ID, .data = true, .pio = true, |
81 | .size = 512, .read = true } | |
716b6407 JS |
82 | }; |
83 | ||
40d29928 JS |
84 | struct AHCICommand { |
85 | /* Test Management Data */ | |
86 | uint8_t name; | |
87 | uint8_t port; | |
88 | uint8_t slot; | |
f697b0ed | 89 | uint8_t errors; |
40d29928 JS |
90 | uint32_t interrupts; |
91 | uint64_t xbytes; | |
92 | uint32_t prd_size; | |
93 | uint64_t buffer; | |
94 | AHCICommandProp *props; | |
95 | /* Data to be transferred to the guest */ | |
96 | AHCICommandHeader header; | |
97 | RegH2DFIS fis; | |
54d268b2 | 98 | unsigned char *atapi_cmd; |
40d29928 JS |
99 | }; |
100 | ||
9a75b0a0 JS |
101 | /** |
102 | * Allocate space in the guest using information in the AHCIQState object. | |
103 | */ | |
104 | uint64_t ahci_alloc(AHCIQState *ahci, size_t bytes) | |
105 | { | |
106 | g_assert(ahci); | |
107 | g_assert(ahci->parent); | |
108 | return qmalloc(ahci->parent, bytes); | |
109 | } | |
110 | ||
111 | void ahci_free(AHCIQState *ahci, uint64_t addr) | |
112 | { | |
113 | g_assert(ahci); | |
114 | g_assert(ahci->parent); | |
115 | qfree(ahci->parent, addr); | |
116 | } | |
117 | ||
d0b282a5 JS |
118 | bool is_atapi(AHCIQState *ahci, uint8_t port) |
119 | { | |
120 | return ahci_px_rreg(ahci, port, AHCI_PX_SIG) == AHCI_SIGNATURE_CDROM; | |
121 | } | |
122 | ||
9a75b0a0 JS |
123 | /** |
124 | * Locate, verify, and return a handle to the AHCI device. | |
125 | */ | |
126 | QPCIDevice *get_ahci_device(uint32_t *fingerprint) | |
127 | { | |
128 | QPCIDevice *ahci; | |
129 | uint32_t ahci_fingerprint; | |
130 | QPCIBus *pcibus; | |
131 | ||
2ecd7e2f | 132 | pcibus = qpci_init_pc(NULL); |
9a75b0a0 JS |
133 | |
134 | /* Find the AHCI PCI device and verify it's the right one. */ | |
135 | ahci = qpci_device_find(pcibus, QPCI_DEVFN(0x1F, 0x02)); | |
136 | g_assert(ahci != NULL); | |
137 | ||
138 | ahci_fingerprint = qpci_config_readl(ahci, PCI_VENDOR_ID); | |
139 | ||
140 | switch (ahci_fingerprint) { | |
141 | case AHCI_INTEL_ICH9: | |
142 | break; | |
143 | default: | |
144 | /* Unknown device. */ | |
145 | g_assert_not_reached(); | |
146 | } | |
147 | ||
148 | if (fingerprint) { | |
149 | *fingerprint = ahci_fingerprint; | |
150 | } | |
151 | return ahci; | |
152 | } | |
153 | ||
154 | void free_ahci_device(QPCIDevice *dev) | |
155 | { | |
156 | QPCIBus *pcibus = dev ? dev->bus : NULL; | |
157 | ||
158 | /* libqos doesn't have a function for this, so free it manually */ | |
159 | g_free(dev); | |
160 | qpci_free_pc(pcibus); | |
161 | } | |
162 | ||
259342d3 JS |
163 | /* Free all memory in-use by the AHCI device. */ |
164 | void ahci_clean_mem(AHCIQState *ahci) | |
165 | { | |
166 | uint8_t port, slot; | |
167 | ||
168 | for (port = 0; port < 32; ++port) { | |
169 | if (ahci->port[port].fb) { | |
170 | ahci_free(ahci, ahci->port[port].fb); | |
95ea6636 | 171 | ahci->port[port].fb = 0; |
259342d3 JS |
172 | } |
173 | if (ahci->port[port].clb) { | |
174 | for (slot = 0; slot < 32; slot++) { | |
175 | ahci_destroy_command(ahci, port, slot); | |
176 | } | |
177 | ahci_free(ahci, ahci->port[port].clb); | |
95ea6636 | 178 | ahci->port[port].clb = 0; |
259342d3 JS |
179 | } |
180 | } | |
181 | } | |
182 | ||
9a75b0a0 JS |
183 | /*** Logical Device Initialization ***/ |
184 | ||
185 | /** | |
186 | * Start the PCI device and sanity-check default operation. | |
187 | */ | |
188 | void ahci_pci_enable(AHCIQState *ahci) | |
189 | { | |
190 | uint8_t reg; | |
191 | ||
192 | start_ahci_device(ahci); | |
193 | ||
194 | switch (ahci->fingerprint) { | |
195 | case AHCI_INTEL_ICH9: | |
196 | /* ICH9 has a register at PCI 0x92 that | |
197 | * acts as a master port enabler mask. */ | |
198 | reg = qpci_config_readb(ahci->dev, 0x92); | |
199 | reg |= 0x3F; | |
200 | qpci_config_writeb(ahci->dev, 0x92, reg); | |
201 | /* 0...0111111b -- bit significant, ports 0-5 enabled. */ | |
202 | ASSERT_BIT_SET(qpci_config_readb(ahci->dev, 0x92), 0x3F); | |
203 | break; | |
204 | } | |
205 | ||
206 | } | |
207 | ||
208 | /** | |
209 | * Map BAR5/ABAR, and engage the PCI device. | |
210 | */ | |
211 | void start_ahci_device(AHCIQState *ahci) | |
212 | { | |
213 | /* Map AHCI's ABAR (BAR5) */ | |
b4ba67d9 | 214 | ahci->hba_bar = qpci_iomap(ahci->dev, 5, &ahci->barsize); |
9a75b0a0 JS |
215 | |
216 | /* turns on pci.cmd.iose, pci.cmd.mse and pci.cmd.bme */ | |
217 | qpci_device_enable(ahci->dev); | |
218 | } | |
219 | ||
220 | /** | |
221 | * Test and initialize the AHCI's HBA memory areas. | |
222 | * Initialize and start any ports with devices attached. | |
223 | * Bring the HBA into the idle state. | |
224 | */ | |
225 | void ahci_hba_enable(AHCIQState *ahci) | |
226 | { | |
227 | /* Bits of interest in this section: | |
228 | * GHC.AE Global Host Control / AHCI Enable | |
229 | * PxCMD.ST Port Command: Start | |
230 | * PxCMD.SUD "Spin Up Device" | |
231 | * PxCMD.POD "Power On Device" | |
232 | * PxCMD.FRE "FIS Receive Enable" | |
233 | * PxCMD.FR "FIS Receive Running" | |
234 | * PxCMD.CR "Command List Running" | |
235 | */ | |
236 | uint32_t reg, ports_impl; | |
237 | uint16_t i; | |
238 | uint8_t num_cmd_slots; | |
239 | ||
240 | g_assert(ahci != NULL); | |
241 | ||
242 | /* Set GHC.AE to 1 */ | |
243 | ahci_set(ahci, AHCI_GHC, AHCI_GHC_AE); | |
244 | reg = ahci_rreg(ahci, AHCI_GHC); | |
245 | ASSERT_BIT_SET(reg, AHCI_GHC_AE); | |
246 | ||
247 | /* Cache CAP and CAP2. */ | |
248 | ahci->cap = ahci_rreg(ahci, AHCI_CAP); | |
249 | ahci->cap2 = ahci_rreg(ahci, AHCI_CAP2); | |
250 | ||
251 | /* Read CAP.NCS, how many command slots do we have? */ | |
252 | num_cmd_slots = ((ahci->cap & AHCI_CAP_NCS) >> ctzl(AHCI_CAP_NCS)) + 1; | |
253 | g_test_message("Number of Command Slots: %u", num_cmd_slots); | |
254 | ||
255 | /* Determine which ports are implemented. */ | |
256 | ports_impl = ahci_rreg(ahci, AHCI_PI); | |
257 | ||
258 | for (i = 0; ports_impl; ports_impl >>= 1, ++i) { | |
259 | if (!(ports_impl & 0x01)) { | |
260 | continue; | |
261 | } | |
262 | ||
263 | g_test_message("Initializing port %u", i); | |
264 | ||
265 | reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD); | |
266 | if (BITCLR(reg, AHCI_PX_CMD_ST | AHCI_PX_CMD_CR | | |
267 | AHCI_PX_CMD_FRE | AHCI_PX_CMD_FR)) { | |
268 | g_test_message("port is idle"); | |
269 | } else { | |
270 | g_test_message("port needs to be idled"); | |
271 | ahci_px_clr(ahci, i, AHCI_PX_CMD, | |
272 | (AHCI_PX_CMD_ST | AHCI_PX_CMD_FRE)); | |
273 | /* The port has 500ms to disengage. */ | |
274 | usleep(500000); | |
275 | reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD); | |
276 | ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR); | |
277 | ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR); | |
278 | g_test_message("port is now idle"); | |
279 | /* The spec does allow for possibly needing a PORT RESET | |
280 | * or HBA reset if we fail to idle the port. */ | |
281 | } | |
282 | ||
283 | /* Allocate Memory for the Command List Buffer & FIS Buffer */ | |
284 | /* PxCLB space ... 0x20 per command, as in 4.2.2 p 36 */ | |
285 | ahci->port[i].clb = ahci_alloc(ahci, num_cmd_slots * 0x20); | |
95ea6636 | 286 | qmemset(ahci->port[i].clb, 0x00, num_cmd_slots * 0x20); |
9a75b0a0 JS |
287 | g_test_message("CLB: 0x%08" PRIx64, ahci->port[i].clb); |
288 | ahci_px_wreg(ahci, i, AHCI_PX_CLB, ahci->port[i].clb); | |
289 | g_assert_cmphex(ahci->port[i].clb, ==, | |
290 | ahci_px_rreg(ahci, i, AHCI_PX_CLB)); | |
291 | ||
292 | /* PxFB space ... 0x100, as in 4.2.1 p 35 */ | |
293 | ahci->port[i].fb = ahci_alloc(ahci, 0x100); | |
294 | qmemset(ahci->port[i].fb, 0x00, 0x100); | |
295 | g_test_message("FB: 0x%08" PRIx64, ahci->port[i].fb); | |
296 | ahci_px_wreg(ahci, i, AHCI_PX_FB, ahci->port[i].fb); | |
297 | g_assert_cmphex(ahci->port[i].fb, ==, | |
298 | ahci_px_rreg(ahci, i, AHCI_PX_FB)); | |
299 | ||
300 | /* Clear PxSERR, PxIS, then IS.IPS[x] by writing '1's. */ | |
301 | ahci_px_wreg(ahci, i, AHCI_PX_SERR, 0xFFFFFFFF); | |
302 | ahci_px_wreg(ahci, i, AHCI_PX_IS, 0xFFFFFFFF); | |
303 | ahci_wreg(ahci, AHCI_IS, (1 << i)); | |
304 | ||
305 | /* Verify Interrupts Cleared */ | |
306 | reg = ahci_px_rreg(ahci, i, AHCI_PX_SERR); | |
307 | g_assert_cmphex(reg, ==, 0); | |
308 | ||
309 | reg = ahci_px_rreg(ahci, i, AHCI_PX_IS); | |
310 | g_assert_cmphex(reg, ==, 0); | |
311 | ||
312 | reg = ahci_rreg(ahci, AHCI_IS); | |
313 | ASSERT_BIT_CLEAR(reg, (1 << i)); | |
314 | ||
315 | /* Enable All Interrupts: */ | |
316 | ahci_px_wreg(ahci, i, AHCI_PX_IE, 0xFFFFFFFF); | |
317 | reg = ahci_px_rreg(ahci, i, AHCI_PX_IE); | |
318 | g_assert_cmphex(reg, ==, ~((uint32_t)AHCI_PX_IE_RESERVED)); | |
319 | ||
320 | /* Enable the FIS Receive Engine. */ | |
321 | ahci_px_set(ahci, i, AHCI_PX_CMD, AHCI_PX_CMD_FRE); | |
322 | reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD); | |
323 | ASSERT_BIT_SET(reg, AHCI_PX_CMD_FR); | |
324 | ||
325 | /* AHCI 1.3 spec: if !STS.BSY, !STS.DRQ and PxSSTS.DET indicates | |
326 | * physical presence, a device is present and may be started. However, | |
327 | * PxSERR.DIAG.X /may/ need to be cleared a priori. */ | |
328 | reg = ahci_px_rreg(ahci, i, AHCI_PX_SERR); | |
329 | if (BITSET(reg, AHCI_PX_SERR_DIAG_X)) { | |
330 | ahci_px_set(ahci, i, AHCI_PX_SERR, AHCI_PX_SERR_DIAG_X); | |
331 | } | |
332 | ||
333 | reg = ahci_px_rreg(ahci, i, AHCI_PX_TFD); | |
334 | if (BITCLR(reg, AHCI_PX_TFD_STS_BSY | AHCI_PX_TFD_STS_DRQ)) { | |
335 | reg = ahci_px_rreg(ahci, i, AHCI_PX_SSTS); | |
336 | if ((reg & AHCI_PX_SSTS_DET) == SSTS_DET_ESTABLISHED) { | |
337 | /* Device Found: set PxCMD.ST := 1 */ | |
338 | ahci_px_set(ahci, i, AHCI_PX_CMD, AHCI_PX_CMD_ST); | |
339 | ASSERT_BIT_SET(ahci_px_rreg(ahci, i, AHCI_PX_CMD), | |
340 | AHCI_PX_CMD_CR); | |
341 | g_test_message("Started Device %u", i); | |
342 | } else if ((reg & AHCI_PX_SSTS_DET)) { | |
343 | /* Device present, but in some unknown state. */ | |
344 | g_assert_not_reached(); | |
345 | } | |
346 | } | |
347 | } | |
348 | ||
349 | /* Enable GHC.IE */ | |
350 | ahci_set(ahci, AHCI_GHC, AHCI_GHC_IE); | |
351 | reg = ahci_rreg(ahci, AHCI_GHC); | |
352 | ASSERT_BIT_SET(reg, AHCI_GHC_IE); | |
353 | ||
e7c8526b | 354 | ahci->enabled = true; |
9a75b0a0 JS |
355 | /* TODO: The device should now be idling and waiting for commands. |
356 | * In the future, a small test-case to inspect the Register D2H FIS | |
357 | * and clear the initial interrupts might be good. */ | |
358 | } | |
e77448a3 JS |
359 | |
360 | /** | |
361 | * Pick the first implemented and running port | |
362 | */ | |
363 | unsigned ahci_port_select(AHCIQState *ahci) | |
364 | { | |
365 | uint32_t ports, reg; | |
366 | unsigned i; | |
367 | ||
368 | ports = ahci_rreg(ahci, AHCI_PI); | |
369 | for (i = 0; i < 32; ports >>= 1, ++i) { | |
370 | if (ports == 0) { | |
371 | i = 32; | |
372 | } | |
373 | ||
374 | if (!(ports & 0x01)) { | |
375 | continue; | |
376 | } | |
377 | ||
378 | reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD); | |
379 | if (BITSET(reg, AHCI_PX_CMD_ST)) { | |
380 | break; | |
381 | } | |
382 | } | |
383 | g_assert(i < 32); | |
384 | return i; | |
385 | } | |
e83fd96b JS |
386 | |
387 | /** | |
388 | * Clear a port's interrupts and status information prior to a test. | |
389 | */ | |
390 | void ahci_port_clear(AHCIQState *ahci, uint8_t port) | |
391 | { | |
392 | uint32_t reg; | |
393 | ||
394 | /* Clear out this port's interrupts (ignore the init register d2h fis) */ | |
395 | reg = ahci_px_rreg(ahci, port, AHCI_PX_IS); | |
396 | ahci_px_wreg(ahci, port, AHCI_PX_IS, reg); | |
397 | g_assert_cmphex(ahci_px_rreg(ahci, port, AHCI_PX_IS), ==, 0); | |
398 | ||
631b22ea | 399 | /* Wipe the FIS-Receive Buffer */ |
e83fd96b JS |
400 | qmemset(ahci->port[port].fb, 0x00, 0x100); |
401 | } | |
6cae27a6 | 402 | |
85c34e93 JS |
403 | /** |
404 | * Check a port for errors. | |
405 | */ | |
f697b0ed JS |
406 | void ahci_port_check_error(AHCIQState *ahci, uint8_t port, |
407 | uint32_t imask, uint8_t emask) | |
85c34e93 JS |
408 | { |
409 | uint32_t reg; | |
410 | ||
411 | /* The upper 9 bits of the IS register all indicate errors. */ | |
412 | reg = ahci_px_rreg(ahci, port, AHCI_PX_IS); | |
f697b0ed | 413 | reg &= ~imask; |
85c34e93 JS |
414 | reg >>= 23; |
415 | g_assert_cmphex(reg, ==, 0); | |
416 | ||
417 | /* The Sata Error Register should be empty. */ | |
418 | reg = ahci_px_rreg(ahci, port, AHCI_PX_SERR); | |
419 | g_assert_cmphex(reg, ==, 0); | |
420 | ||
421 | /* The TFD also has two error sections. */ | |
422 | reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD); | |
f697b0ed JS |
423 | if (!emask) { |
424 | ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_ERR); | |
425 | } else { | |
426 | ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_ERR); | |
427 | } | |
428 | ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR & (~emask << 8)); | |
429 | ASSERT_BIT_SET(reg, AHCI_PX_TFD_ERR & (emask << 8)); | |
85c34e93 JS |
430 | } |
431 | ||
5bf99aa1 JS |
432 | void ahci_port_check_interrupts(AHCIQState *ahci, uint8_t port, |
433 | uint32_t intr_mask) | |
434 | { | |
435 | uint32_t reg; | |
436 | ||
437 | /* Check for expected interrupts */ | |
438 | reg = ahci_px_rreg(ahci, port, AHCI_PX_IS); | |
439 | ASSERT_BIT_SET(reg, intr_mask); | |
440 | ||
441 | /* Clear expected interrupts and assert all interrupts now cleared. */ | |
442 | ahci_px_wreg(ahci, port, AHCI_PX_IS, intr_mask); | |
443 | g_assert_cmphex(ahci_px_rreg(ahci, port, AHCI_PX_IS), ==, 0); | |
444 | } | |
445 | ||
89a46723 JS |
446 | void ahci_port_check_nonbusy(AHCIQState *ahci, uint8_t port, uint8_t slot) |
447 | { | |
448 | uint32_t reg; | |
449 | ||
450 | /* Assert that the command slot is no longer busy (NCQ) */ | |
451 | reg = ahci_px_rreg(ahci, port, AHCI_PX_SACT); | |
452 | ASSERT_BIT_CLEAR(reg, (1 << slot)); | |
453 | ||
454 | /* Non-NCQ */ | |
455 | reg = ahci_px_rreg(ahci, port, AHCI_PX_CI); | |
456 | ASSERT_BIT_CLEAR(reg, (1 << slot)); | |
457 | ||
458 | /* And assert that we are generally not busy. */ | |
459 | reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD); | |
460 | ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_BSY); | |
461 | ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_DRQ); | |
462 | } | |
463 | ||
d1ef8838 JS |
464 | void ahci_port_check_d2h_sanity(AHCIQState *ahci, uint8_t port, uint8_t slot) |
465 | { | |
466 | RegD2HFIS *d2h = g_malloc0(0x20); | |
467 | uint32_t reg; | |
468 | ||
469 | memread(ahci->port[port].fb + 0x40, d2h, 0x20); | |
470 | g_assert_cmphex(d2h->fis_type, ==, 0x34); | |
471 | ||
472 | reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD); | |
473 | g_assert_cmphex((reg & AHCI_PX_TFD_ERR) >> 8, ==, d2h->error); | |
474 | g_assert_cmphex((reg & AHCI_PX_TFD_STS), ==, d2h->status); | |
475 | ||
476 | g_free(d2h); | |
477 | } | |
478 | ||
479 | void ahci_port_check_pio_sanity(AHCIQState *ahci, uint8_t port, | |
480 | uint8_t slot, size_t buffsize) | |
481 | { | |
482 | PIOSetupFIS *pio = g_malloc0(0x20); | |
483 | ||
631b22ea | 484 | /* We cannot check the Status or E_Status registers, because |
d1ef8838 JS |
485 | * the status may have again changed between the PIO Setup FIS |
486 | * and the conclusion of the command with the D2H Register FIS. */ | |
487 | memread(ahci->port[port].fb + 0x20, pio, 0x20); | |
488 | g_assert_cmphex(pio->fis_type, ==, 0x5f); | |
489 | ||
490 | /* BUG: PIO Setup FIS as utilized by QEMU tries to fit the entire | |
491 | * transfer size in a uint16_t field. The maximum transfer size can | |
492 | * eclipse this; the field is meant to convey the size of data per | |
493 | * each Data FIS, not the entire operation as a whole. For now, | |
494 | * we will sanity check the broken case where applicable. */ | |
495 | if (buffsize <= UINT16_MAX) { | |
496 | g_assert_cmphex(le16_to_cpu(pio->tx_count), ==, buffsize); | |
497 | } | |
498 | ||
499 | g_free(pio); | |
500 | } | |
501 | ||
40d29928 | 502 | void ahci_port_check_cmd_sanity(AHCIQState *ahci, AHCICommand *cmd) |
d1ef8838 | 503 | { |
40d29928 | 504 | AHCICommandHeader cmdh; |
d1ef8838 | 505 | |
40d29928 JS |
506 | ahci_get_command_header(ahci, cmd->port, cmd->slot, &cmdh); |
507 | /* Physical Region Descriptor Byte Count is not required to work for NCQ. */ | |
508 | if (!cmd->props->ncq) { | |
509 | g_assert_cmphex(cmd->xbytes, ==, cmdh.prdbc); | |
510 | } | |
d1ef8838 JS |
511 | } |
512 | ||
6cae27a6 JS |
513 | /* Get the command in #slot of port #port. */ |
514 | void ahci_get_command_header(AHCIQState *ahci, uint8_t port, | |
515 | uint8_t slot, AHCICommandHeader *cmd) | |
516 | { | |
517 | uint64_t ba = ahci->port[port].clb; | |
518 | ba += slot * sizeof(AHCICommandHeader); | |
519 | memread(ba, cmd, sizeof(AHCICommandHeader)); | |
520 | ||
521 | cmd->flags = le16_to_cpu(cmd->flags); | |
522 | cmd->prdtl = le16_to_cpu(cmd->prdtl); | |
523 | cmd->prdbc = le32_to_cpu(cmd->prdbc); | |
524 | cmd->ctba = le64_to_cpu(cmd->ctba); | |
525 | } | |
526 | ||
527 | /* Set the command in #slot of port #port. */ | |
528 | void ahci_set_command_header(AHCIQState *ahci, uint8_t port, | |
529 | uint8_t slot, AHCICommandHeader *cmd) | |
530 | { | |
4a42f6d4 | 531 | AHCICommandHeader tmp = { .flags = 0 }; |
6cae27a6 JS |
532 | uint64_t ba = ahci->port[port].clb; |
533 | ba += slot * sizeof(AHCICommandHeader); | |
534 | ||
535 | tmp.flags = cpu_to_le16(cmd->flags); | |
536 | tmp.prdtl = cpu_to_le16(cmd->prdtl); | |
537 | tmp.prdbc = cpu_to_le32(cmd->prdbc); | |
538 | tmp.ctba = cpu_to_le64(cmd->ctba); | |
539 | ||
540 | memwrite(ba, &tmp, sizeof(AHCICommandHeader)); | |
541 | } | |
542 | ||
543 | void ahci_destroy_command(AHCIQState *ahci, uint8_t port, uint8_t slot) | |
544 | { | |
545 | AHCICommandHeader cmd; | |
546 | ||
547 | /* Obtain the Nth Command Header */ | |
548 | ahci_get_command_header(ahci, port, slot, &cmd); | |
549 | if (cmd.ctba == 0) { | |
550 | /* No address in it, so just return -- it's empty. */ | |
551 | goto tidy; | |
552 | } | |
553 | ||
554 | /* Free the Table */ | |
555 | ahci_free(ahci, cmd.ctba); | |
556 | ||
557 | tidy: | |
558 | /* NULL the header. */ | |
559 | memset(&cmd, 0x00, sizeof(cmd)); | |
560 | ahci_set_command_header(ahci, port, slot, &cmd); | |
561 | ahci->port[port].ctba[slot] = 0; | |
562 | ahci->port[port].prdtl[slot] = 0; | |
563 | } | |
564 | ||
9ab9993f | 565 | void ahci_write_fis(AHCIQState *ahci, AHCICommand *cmd) |
52515766 | 566 | { |
9ab9993f JS |
567 | RegH2DFIS tmp = cmd->fis; |
568 | uint64_t addr = cmd->header.ctba; | |
52515766 | 569 | |
9ab9993f JS |
570 | /* NCQ commands use exclusively 8 bit fields and needs no adjustment. |
571 | * Only the count field needs to be adjusted for non-NCQ commands. | |
572 | * The auxiliary FIS fields are defined per-command and are not currently | |
573 | * implemented in libqos/ahci.o, but may or may not need to be flipped. */ | |
574 | if (!cmd->props->ncq) { | |
575 | tmp.count = cpu_to_le16(tmp.count); | |
576 | } | |
52515766 JS |
577 | |
578 | memwrite(addr, &tmp, sizeof(tmp)); | |
579 | } | |
580 | ||
6cae27a6 JS |
581 | unsigned ahci_pick_cmd(AHCIQState *ahci, uint8_t port) |
582 | { | |
583 | unsigned i; | |
584 | unsigned j; | |
585 | uint32_t reg; | |
586 | ||
587 | reg = ahci_px_rreg(ahci, port, AHCI_PX_CI); | |
588 | ||
589 | /* Pick the least recently used command slot that's available */ | |
590 | for (i = 0; i < 32; ++i) { | |
591 | j = ((ahci->port[port].next + i) % 32); | |
592 | if (reg & (1 << j)) { | |
593 | continue; | |
594 | } | |
95ea6636 | 595 | ahci_destroy_command(ahci, port, j); |
6cae27a6 JS |
596 | ahci->port[port].next = (j + 1) % 32; |
597 | return j; | |
598 | } | |
599 | ||
600 | g_test_message("All command slots were busy."); | |
601 | g_assert_not_reached(); | |
602 | } | |
64a5a272 JS |
603 | |
604 | inline unsigned size_to_prdtl(unsigned bytes, unsigned bytes_per_prd) | |
605 | { | |
606 | /* Each PRD can describe up to 4MiB */ | |
607 | g_assert_cmphex(bytes_per_prd, <=, 4096 * 1024); | |
608 | g_assert_cmphex(bytes_per_prd & 0x01, ==, 0x00); | |
609 | return (bytes + bytes_per_prd - 1) / bytes_per_prd; | |
610 | } | |
611 | ||
9350df7c JS |
612 | const AHCIOpts default_opts = { .size = 0 }; |
613 | ||
614 | /** | |
615 | * ahci_exec: execute a given command on a specific | |
616 | * AHCI port. | |
617 | * | |
618 | * @ahci: The device to send the command to | |
619 | * @port: The port number of the SATA device we wish | |
620 | * to have execute this command | |
621 | * @op: The S/ATA command to execute, or if opts.atapi | |
622 | * is true, the SCSI command code. | |
623 | * @opts: Optional arguments to modify execution behavior. | |
624 | */ | |
625 | void ahci_exec(AHCIQState *ahci, uint8_t port, | |
626 | uint8_t op, const AHCIOpts *opts_in) | |
627 | { | |
628 | AHCICommand *cmd; | |
629 | int rc; | |
630 | AHCIOpts *opts; | |
631 | ||
632 | opts = g_memdup((opts_in == NULL ? &default_opts : opts_in), | |
633 | sizeof(AHCIOpts)); | |
634 | ||
635 | /* No guest buffer provided, create one. */ | |
636 | if (opts->size && !opts->buffer) { | |
637 | opts->buffer = ahci_alloc(ahci, opts->size); | |
638 | g_assert(opts->buffer); | |
639 | qmemset(opts->buffer, 0x00, opts->size); | |
640 | } | |
641 | ||
642 | /* Command creation */ | |
643 | if (opts->atapi) { | |
ebde93bf JS |
644 | uint16_t bcl = opts->set_bcl ? opts->bcl : ATAPI_SECTOR_SIZE; |
645 | cmd = ahci_atapi_command_create(op, bcl); | |
9350df7c JS |
646 | if (opts->atapi_dma) { |
647 | ahci_command_enable_atapi_dma(cmd); | |
648 | } | |
649 | } else { | |
650 | cmd = ahci_command_create(op); | |
651 | } | |
652 | ahci_command_adjust(cmd, opts->lba, opts->buffer, | |
653 | opts->size, opts->prd_size); | |
654 | ||
655 | if (opts->pre_cb) { | |
656 | rc = opts->pre_cb(ahci, cmd, opts); | |
657 | g_assert_cmpint(rc, ==, 0); | |
658 | } | |
659 | ||
660 | /* Write command to memory and issue it */ | |
661 | ahci_command_commit(ahci, cmd, port); | |
662 | ahci_command_issue_async(ahci, cmd); | |
663 | if (opts->error) { | |
664 | qmp_eventwait("STOP"); | |
665 | } | |
666 | if (opts->mid_cb) { | |
667 | rc = opts->mid_cb(ahci, cmd, opts); | |
668 | g_assert_cmpint(rc, ==, 0); | |
669 | } | |
670 | if (opts->error) { | |
671 | qmp_async("{'execute':'cont' }"); | |
672 | qmp_eventwait("RESUME"); | |
673 | } | |
674 | ||
675 | /* Wait for command to complete and verify sanity */ | |
676 | ahci_command_wait(ahci, cmd); | |
677 | ahci_command_verify(ahci, cmd); | |
678 | if (opts->post_cb) { | |
679 | rc = opts->post_cb(ahci, cmd, opts); | |
680 | g_assert_cmpint(rc, ==, 0); | |
681 | } | |
682 | ahci_command_free(cmd); | |
683 | if (opts->buffer != opts_in->buffer) { | |
684 | ahci_free(ahci, opts->buffer); | |
685 | } | |
686 | g_free(opts); | |
687 | } | |
688 | ||
008b6e12 JS |
689 | /* Issue a command, expecting it to fail and STOP the VM */ |
690 | AHCICommand *ahci_guest_io_halt(AHCIQState *ahci, uint8_t port, | |
691 | uint8_t ide_cmd, uint64_t buffer, | |
692 | size_t bufsize, uint64_t sector) | |
693 | { | |
694 | AHCICommand *cmd; | |
695 | ||
696 | cmd = ahci_command_create(ide_cmd); | |
697 | ahci_command_adjust(cmd, sector, buffer, bufsize, 0); | |
698 | ahci_command_commit(ahci, cmd, port); | |
699 | ahci_command_issue_async(ahci, cmd); | |
700 | qmp_eventwait("STOP"); | |
701 | ||
702 | return cmd; | |
703 | } | |
704 | ||
705 | /* Resume a previously failed command and verify/finalize */ | |
706 | void ahci_guest_io_resume(AHCIQState *ahci, AHCICommand *cmd) | |
707 | { | |
708 | /* Complete the command */ | |
709 | qmp_async("{'execute':'cont' }"); | |
710 | qmp_eventwait("RESUME"); | |
711 | ahci_command_wait(ahci, cmd); | |
712 | ahci_command_verify(ahci, cmd); | |
713 | ahci_command_free(cmd); | |
714 | } | |
715 | ||
11322195 JS |
716 | /* Given a guest buffer address, perform an IO operation */ |
717 | void ahci_guest_io(AHCIQState *ahci, uint8_t port, uint8_t ide_cmd, | |
727be1a7 | 718 | uint64_t buffer, size_t bufsize, uint64_t sector) |
11322195 JS |
719 | { |
720 | AHCICommand *cmd; | |
11322195 JS |
721 | cmd = ahci_command_create(ide_cmd); |
722 | ahci_command_set_buffer(cmd, buffer); | |
723 | ahci_command_set_size(cmd, bufsize); | |
727be1a7 JS |
724 | if (sector) { |
725 | ahci_command_set_offset(cmd, sector); | |
726 | } | |
11322195 JS |
727 | ahci_command_commit(ahci, cmd, port); |
728 | ahci_command_issue(ahci, cmd); | |
729 | ahci_command_verify(ahci, cmd); | |
730 | ahci_command_free(cmd); | |
731 | } | |
732 | ||
64a5a272 JS |
733 | static AHCICommandProp *ahci_command_find(uint8_t command_name) |
734 | { | |
735 | int i; | |
736 | ||
737 | for (i = 0; i < ARRAY_SIZE(ahci_command_properties); i++) { | |
738 | if (ahci_command_properties[i].cmd == command_name) { | |
739 | return &ahci_command_properties[i]; | |
740 | } | |
741 | } | |
742 | ||
743 | return NULL; | |
744 | } | |
745 | ||
ae029620 JS |
746 | /* Given a HOST buffer, create a buffer address and perform an IO operation. */ |
747 | void ahci_io(AHCIQState *ahci, uint8_t port, uint8_t ide_cmd, | |
727be1a7 | 748 | void *buffer, size_t bufsize, uint64_t sector) |
ae029620 JS |
749 | { |
750 | uint64_t ptr; | |
751 | AHCICommandProp *props; | |
752 | ||
753 | props = ahci_command_find(ide_cmd); | |
754 | g_assert(props); | |
755 | ptr = ahci_alloc(ahci, bufsize); | |
b1b66c3b | 756 | g_assert(!bufsize || ptr); |
88e21f94 | 757 | qmemset(ptr, 0x00, bufsize); |
ae029620 | 758 | |
b1b66c3b | 759 | if (bufsize && props->write) { |
91d0374a | 760 | bufwrite(ptr, buffer, bufsize); |
ae029620 JS |
761 | } |
762 | ||
727be1a7 | 763 | ahci_guest_io(ahci, port, ide_cmd, ptr, bufsize, sector); |
ae029620 | 764 | |
b1b66c3b | 765 | if (bufsize && props->read) { |
91d0374a | 766 | bufread(ptr, buffer, bufsize); |
ae029620 JS |
767 | } |
768 | ||
769 | ahci_free(ahci, ptr); | |
770 | } | |
771 | ||
64a5a272 JS |
772 | /** |
773 | * Initializes a basic command header in memory. | |
774 | * We assume that this is for an ATA command using RegH2DFIS. | |
775 | */ | |
776 | static void command_header_init(AHCICommand *cmd) | |
777 | { | |
778 | AHCICommandHeader *hdr = &cmd->header; | |
779 | AHCICommandProp *props = cmd->props; | |
780 | ||
781 | hdr->flags = 5; /* RegH2DFIS is 5 DW long. Must be < 32 */ | |
782 | hdr->flags |= CMDH_CLR_BSY; /* Clear the BSY bit when done */ | |
783 | if (props->write) { | |
784 | hdr->flags |= CMDH_WRITE; | |
785 | } | |
786 | if (props->atapi) { | |
787 | hdr->flags |= CMDH_ATAPI; | |
788 | } | |
789 | /* Other flags: PREFETCH, RESET, and BIST */ | |
790 | hdr->prdtl = size_to_prdtl(cmd->xbytes, cmd->prd_size); | |
791 | hdr->prdbc = 0; | |
792 | hdr->ctba = 0; | |
793 | } | |
794 | ||
795 | static void command_table_init(AHCICommand *cmd) | |
796 | { | |
797 | RegH2DFIS *fis = &(cmd->fis); | |
cb453041 | 798 | uint16_t sect_count = (cmd->xbytes / AHCI_SECTOR_SIZE); |
64a5a272 JS |
799 | |
800 | fis->fis_type = REG_H2D_FIS; | |
801 | fis->flags = REG_H2D_FIS_CMD; /* "Command" bit */ | |
802 | fis->command = cmd->name; | |
cb453041 JS |
803 | |
804 | if (cmd->props->ncq) { | |
805 | NCQFIS *ncqfis = (NCQFIS *)fis; | |
806 | /* NCQ is weird and re-uses FIS frames for unrelated data. | |
807 | * See SATA 3.2, 13.6.4.1 READ FPDMA QUEUED for an example. */ | |
808 | ncqfis->sector_low = sect_count & 0xFF; | |
809 | ncqfis->sector_hi = (sect_count >> 8) & 0xFF; | |
810 | ncqfis->device = NCQ_DEVICE_MAGIC; | |
811 | /* Force Unit Access is bit 7 in the device register */ | |
812 | ncqfis->tag = 0; /* bits 3-7 are the NCQ tag */ | |
813 | ncqfis->prio = 0; /* bits 6,7 are a prio tag */ | |
814 | /* RARC bit is bit 0 of TAG field */ | |
815 | } else { | |
816 | fis->feature_low = 0x00; | |
817 | fis->feature_high = 0x00; | |
818 | if (cmd->props->lba28 || cmd->props->lba48) { | |
819 | fis->device = ATA_DEVICE_LBA; | |
820 | } | |
821 | fis->count = (cmd->xbytes / AHCI_SECTOR_SIZE); | |
64a5a272 | 822 | } |
cb453041 JS |
823 | fis->icc = 0x00; |
824 | fis->control = 0x00; | |
825 | memset(fis->aux, 0x00, ARRAY_SIZE(fis->aux)); | |
64a5a272 JS |
826 | } |
827 | ||
54d268b2 JS |
828 | void ahci_command_enable_atapi_dma(AHCICommand *cmd) |
829 | { | |
830 | RegH2DFIS *fis = &(cmd->fis); | |
831 | g_assert(cmd->props->atapi); | |
832 | fis->feature_low |= 0x01; | |
b88641e2 JS |
833 | cmd->interrupts &= ~AHCI_PX_IS_PSS; |
834 | cmd->props->dma = true; | |
835 | cmd->props->pio = false; | |
836 | /* BUG: We expect the DMA Setup interrupt for DMA commands */ | |
837 | /* cmd->interrupts |= AHCI_PX_IS_DSS; */ | |
54d268b2 JS |
838 | } |
839 | ||
64a5a272 JS |
840 | AHCICommand *ahci_command_create(uint8_t command_name) |
841 | { | |
842 | AHCICommandProp *props = ahci_command_find(command_name); | |
843 | AHCICommand *cmd; | |
844 | ||
845 | g_assert(props); | |
846 | cmd = g_malloc0(sizeof(AHCICommand)); | |
847 | g_assert(!(props->dma && props->pio)); | |
848 | g_assert(!(props->lba28 && props->lba48)); | |
849 | g_assert(!(props->read && props->write)); | |
850 | g_assert(!props->size || props->data); | |
3d937150 | 851 | g_assert(!props->ncq || props->lba48); |
64a5a272 JS |
852 | |
853 | /* Defaults and book-keeping */ | |
b88641e2 | 854 | cmd->props = g_memdup(props, sizeof(AHCICommandProp)); |
64a5a272 JS |
855 | cmd->name = command_name; |
856 | cmd->xbytes = props->size; | |
857 | cmd->prd_size = 4096; | |
858 | cmd->buffer = 0xabad1dea; | |
859 | ||
359790c2 JS |
860 | if (!cmd->props->ncq) { |
861 | cmd->interrupts = AHCI_PX_IS_DHRS; | |
862 | } | |
64a5a272 JS |
863 | /* BUG: We expect the DPS interrupt for data commands */ |
864 | /* cmd->interrupts |= props->data ? AHCI_PX_IS_DPS : 0; */ | |
865 | /* BUG: We expect the DMA Setup interrupt for DMA commands */ | |
866 | /* cmd->interrupts |= props->dma ? AHCI_PX_IS_DSS : 0; */ | |
867 | cmd->interrupts |= props->pio ? AHCI_PX_IS_PSS : 0; | |
359790c2 | 868 | cmd->interrupts |= props->ncq ? AHCI_PX_IS_SDBS : 0; |
64a5a272 JS |
869 | |
870 | command_header_init(cmd); | |
871 | command_table_init(cmd); | |
872 | ||
873 | return cmd; | |
874 | } | |
875 | ||
ebde93bf | 876 | AHCICommand *ahci_atapi_command_create(uint8_t scsi_cmd, uint16_t bcl) |
54d268b2 JS |
877 | { |
878 | AHCICommand *cmd = ahci_command_create(CMD_PACKET); | |
879 | cmd->atapi_cmd = g_malloc0(16); | |
880 | cmd->atapi_cmd[0] = scsi_cmd; | |
ebde93bf | 881 | stw_le_p(&cmd->fis.lba_lo[1], bcl); |
54d268b2 JS |
882 | return cmd; |
883 | } | |
884 | ||
64a5a272 JS |
885 | void ahci_command_free(AHCICommand *cmd) |
886 | { | |
54d268b2 | 887 | g_free(cmd->atapi_cmd); |
b88641e2 | 888 | g_free(cmd->props); |
64a5a272 JS |
889 | g_free(cmd); |
890 | } | |
891 | ||
f9f963e0 JS |
892 | void ahci_command_set_flags(AHCICommand *cmd, uint16_t cmdh_flags) |
893 | { | |
894 | cmd->header.flags |= cmdh_flags; | |
895 | } | |
896 | ||
897 | void ahci_command_clr_flags(AHCICommand *cmd, uint16_t cmdh_flags) | |
898 | { | |
899 | cmd->header.flags &= ~cmdh_flags; | |
900 | } | |
901 | ||
54d268b2 JS |
902 | static void ahci_atapi_command_set_offset(AHCICommand *cmd, uint64_t lba) |
903 | { | |
904 | unsigned char *cbd = cmd->atapi_cmd; | |
905 | g_assert(cbd); | |
906 | ||
907 | switch (cbd[0]) { | |
908 | case CMD_ATAPI_READ_10: | |
ebde93bf | 909 | case CMD_ATAPI_READ_CD: |
54d268b2 JS |
910 | g_assert_cmpuint(lba, <=, UINT32_MAX); |
911 | stl_be_p(&cbd[2], lba); | |
912 | break; | |
913 | default: | |
914 | /* SCSI doesn't have uniform packet formats, | |
915 | * so you have to add support for it manually. Sorry! */ | |
ebde93bf JS |
916 | fprintf(stderr, "The Libqos AHCI driver does not support the " |
917 | "set_offset operation for ATAPI command 0x%02x, " | |
918 | "please add support.\n", | |
919 | cbd[0]); | |
54d268b2 JS |
920 | g_assert_not_reached(); |
921 | } | |
922 | } | |
923 | ||
f9f963e0 JS |
924 | void ahci_command_set_offset(AHCICommand *cmd, uint64_t lba_sect) |
925 | { | |
926 | RegH2DFIS *fis = &(cmd->fis); | |
54d268b2 JS |
927 | |
928 | if (cmd->props->atapi) { | |
929 | ahci_atapi_command_set_offset(cmd, lba_sect); | |
930 | return; | |
b682d3a7 JS |
931 | } else if (!cmd->props->data && !lba_sect) { |
932 | /* Not meaningful, ignore. */ | |
933 | return; | |
54d268b2 | 934 | } else if (cmd->props->lba28) { |
f9f963e0 | 935 | g_assert_cmphex(lba_sect, <=, 0xFFFFFFF); |
e38cc93a | 936 | } else if (cmd->props->lba48 || cmd->props->ncq) { |
f9f963e0 JS |
937 | g_assert_cmphex(lba_sect, <=, 0xFFFFFFFFFFFF); |
938 | } else { | |
939 | /* Can't set offset if we don't know the format. */ | |
940 | g_assert_not_reached(); | |
941 | } | |
942 | ||
943 | /* LBA28 uses the low nibble of the device/control register for LBA24:27 */ | |
944 | fis->lba_lo[0] = (lba_sect & 0xFF); | |
945 | fis->lba_lo[1] = (lba_sect >> 8) & 0xFF; | |
946 | fis->lba_lo[2] = (lba_sect >> 16) & 0xFF; | |
947 | if (cmd->props->lba28) { | |
455e861c | 948 | fis->device = (fis->device & 0xF0) | ((lba_sect >> 24) & 0x0F); |
f9f963e0 JS |
949 | } |
950 | fis->lba_hi[0] = (lba_sect >> 24) & 0xFF; | |
951 | fis->lba_hi[1] = (lba_sect >> 32) & 0xFF; | |
952 | fis->lba_hi[2] = (lba_sect >> 40) & 0xFF; | |
953 | } | |
954 | ||
64a5a272 JS |
955 | void ahci_command_set_buffer(AHCICommand *cmd, uint64_t buffer) |
956 | { | |
957 | cmd->buffer = buffer; | |
958 | } | |
959 | ||
54d268b2 JS |
960 | static void ahci_atapi_set_size(AHCICommand *cmd, uint64_t xbytes) |
961 | { | |
962 | unsigned char *cbd = cmd->atapi_cmd; | |
963 | uint64_t nsectors = xbytes / 2048; | |
ebde93bf | 964 | uint32_t tmp; |
54d268b2 JS |
965 | g_assert(cbd); |
966 | ||
967 | switch (cbd[0]) { | |
968 | case CMD_ATAPI_READ_10: | |
969 | g_assert_cmpuint(nsectors, <=, UINT16_MAX); | |
970 | stw_be_p(&cbd[7], nsectors); | |
971 | break; | |
ebde93bf JS |
972 | case CMD_ATAPI_READ_CD: |
973 | /* 24bit BE store */ | |
974 | g_assert_cmpuint(nsectors, <, 1ULL << 24); | |
975 | tmp = nsectors; | |
976 | cbd[6] = (tmp & 0xFF0000) >> 16; | |
977 | cbd[7] = (tmp & 0xFF00) >> 8; | |
978 | cbd[8] = (tmp & 0xFF); | |
979 | break; | |
54d268b2 JS |
980 | default: |
981 | /* SCSI doesn't have uniform packet formats, | |
982 | * so you have to add support for it manually. Sorry! */ | |
ebde93bf JS |
983 | fprintf(stderr, "The Libqos AHCI driver does not support the set_size " |
984 | "operation for ATAPI command 0x%02x, please add support.\n", | |
985 | cbd[0]); | |
54d268b2 JS |
986 | g_assert_not_reached(); |
987 | } | |
988 | } | |
989 | ||
cbc97569 JS |
990 | void ahci_command_set_sizes(AHCICommand *cmd, uint64_t xbytes, |
991 | unsigned prd_size) | |
992 | { | |
cb453041 JS |
993 | uint16_t sect_count; |
994 | ||
cbc97569 JS |
995 | /* Each PRD can describe up to 4MiB, and must not be odd. */ |
996 | g_assert_cmphex(prd_size, <=, 4096 * 1024); | |
997 | g_assert_cmphex(prd_size & 0x01, ==, 0x00); | |
455e861c JS |
998 | if (prd_size) { |
999 | cmd->prd_size = prd_size; | |
1000 | } | |
cbc97569 | 1001 | cmd->xbytes = xbytes; |
cb453041 JS |
1002 | sect_count = (cmd->xbytes / AHCI_SECTOR_SIZE); |
1003 | ||
1004 | if (cmd->props->ncq) { | |
1005 | NCQFIS *nfis = (NCQFIS *)&(cmd->fis); | |
1006 | nfis->sector_low = sect_count & 0xFF; | |
1007 | nfis->sector_hi = (sect_count >> 8) & 0xFF; | |
54d268b2 JS |
1008 | } else if (cmd->props->atapi) { |
1009 | ahci_atapi_set_size(cmd, xbytes); | |
cb453041 JS |
1010 | } else { |
1011 | cmd->fis.count = sect_count; | |
1012 | } | |
cbc97569 JS |
1013 | cmd->header.prdtl = size_to_prdtl(cmd->xbytes, cmd->prd_size); |
1014 | } | |
1015 | ||
1016 | void ahci_command_set_size(AHCICommand *cmd, uint64_t xbytes) | |
1017 | { | |
1018 | ahci_command_set_sizes(cmd, xbytes, cmd->prd_size); | |
1019 | } | |
1020 | ||
1021 | void ahci_command_set_prd_size(AHCICommand *cmd, unsigned prd_size) | |
1022 | { | |
1023 | ahci_command_set_sizes(cmd, cmd->xbytes, prd_size); | |
1024 | } | |
1025 | ||
f9f963e0 JS |
1026 | void ahci_command_adjust(AHCICommand *cmd, uint64_t offset, uint64_t buffer, |
1027 | uint64_t xbytes, unsigned prd_size) | |
1028 | { | |
1029 | ahci_command_set_sizes(cmd, xbytes, prd_size); | |
1030 | ahci_command_set_buffer(cmd, buffer); | |
1031 | ahci_command_set_offset(cmd, offset); | |
1032 | } | |
1033 | ||
64a5a272 JS |
1034 | void ahci_command_commit(AHCIQState *ahci, AHCICommand *cmd, uint8_t port) |
1035 | { | |
1036 | uint16_t i, prdtl; | |
1037 | uint64_t table_size, table_ptr, remaining; | |
1038 | PRD prd; | |
1039 | ||
1040 | /* This command is now tied to this port/command slot */ | |
1041 | cmd->port = port; | |
1042 | cmd->slot = ahci_pick_cmd(ahci, port); | |
1043 | ||
a8973ff5 JS |
1044 | if (cmd->props->ncq) { |
1045 | NCQFIS *nfis = (NCQFIS *)&cmd->fis; | |
1046 | nfis->tag = (cmd->slot << 3) & 0xFC; | |
1047 | } | |
1048 | ||
64a5a272 JS |
1049 | /* Create a buffer for the command table */ |
1050 | prdtl = size_to_prdtl(cmd->xbytes, cmd->prd_size); | |
1051 | table_size = CMD_TBL_SIZ(prdtl); | |
1052 | table_ptr = ahci_alloc(ahci, table_size); | |
1053 | g_assert(table_ptr); | |
1054 | /* AHCI 1.3: Must be aligned to 0x80 */ | |
1055 | g_assert((table_ptr & 0x7F) == 0x00); | |
1056 | cmd->header.ctba = table_ptr; | |
1057 | ||
54d268b2 | 1058 | /* Commit the command header (part of the Command List Buffer) */ |
64a5a272 | 1059 | ahci_set_command_header(ahci, port, cmd->slot, &(cmd->header)); |
54d268b2 | 1060 | /* Now, write the command table (FIS, ACMD, and PRDT) -- FIS first, */ |
9ab9993f | 1061 | ahci_write_fis(ahci, cmd); |
54d268b2 JS |
1062 | /* Then ATAPI CMD, if needed */ |
1063 | if (cmd->props->atapi) { | |
1064 | memwrite(table_ptr + 0x40, cmd->atapi_cmd, 16); | |
1065 | } | |
64a5a272 JS |
1066 | |
1067 | /* Construct and write the PRDs to the command table */ | |
1068 | g_assert_cmphex(prdtl, ==, cmd->header.prdtl); | |
1069 | remaining = cmd->xbytes; | |
1070 | for (i = 0; i < prdtl; ++i) { | |
1071 | prd.dba = cpu_to_le64(cmd->buffer + (cmd->prd_size * i)); | |
1072 | prd.res = 0; | |
1073 | if (remaining > cmd->prd_size) { | |
1074 | /* Note that byte count is 0-based. */ | |
1075 | prd.dbc = cpu_to_le32(cmd->prd_size - 1); | |
1076 | remaining -= cmd->prd_size; | |
1077 | } else { | |
1078 | /* Again, dbc is 0-based. */ | |
1079 | prd.dbc = cpu_to_le32(remaining - 1); | |
1080 | remaining = 0; | |
1081 | } | |
1082 | prd.dbc |= cpu_to_le32(0x80000000); /* Request DPS Interrupt */ | |
1083 | ||
1084 | /* Commit the PRD entry to the Command Table */ | |
1085 | memwrite(table_ptr + 0x80 + (i * sizeof(PRD)), | |
1086 | &prd, sizeof(PRD)); | |
1087 | } | |
1088 | ||
1089 | /* Bookmark the PRDTL and CTBA values */ | |
1090 | ahci->port[port].ctba[cmd->slot] = table_ptr; | |
1091 | ahci->port[port].prdtl[cmd->slot] = prdtl; | |
1092 | } | |
1093 | ||
1094 | void ahci_command_issue_async(AHCIQState *ahci, AHCICommand *cmd) | |
1095 | { | |
1096 | if (cmd->props->ncq) { | |
1097 | ahci_px_wreg(ahci, cmd->port, AHCI_PX_SACT, (1 << cmd->slot)); | |
1098 | } | |
1099 | ||
1100 | ahci_px_wreg(ahci, cmd->port, AHCI_PX_CI, (1 << cmd->slot)); | |
1101 | } | |
1102 | ||
1103 | void ahci_command_wait(AHCIQState *ahci, AHCICommand *cmd) | |
1104 | { | |
1105 | /* We can't rely on STS_BSY until the command has started processing. | |
1106 | * Therefore, we also use the Command Issue bit as indication of | |
1107 | * a command in-flight. */ | |
4de48469 JS |
1108 | |
1109 | #define RSET(REG, MASK) (BITSET(ahci_px_rreg(ahci, cmd->port, (REG)), (MASK))) | |
1110 | ||
1111 | while (RSET(AHCI_PX_TFD, AHCI_PX_TFD_STS_BSY) || | |
1112 | RSET(AHCI_PX_CI, 1 << cmd->slot) || | |
1113 | (cmd->props->ncq && RSET(AHCI_PX_SACT, 1 << cmd->slot))) { | |
64a5a272 JS |
1114 | usleep(50); |
1115 | } | |
4de48469 | 1116 | |
64a5a272 JS |
1117 | } |
1118 | ||
1119 | void ahci_command_issue(AHCIQState *ahci, AHCICommand *cmd) | |
1120 | { | |
1121 | ahci_command_issue_async(ahci, cmd); | |
1122 | ahci_command_wait(ahci, cmd); | |
1123 | } | |
1124 | ||
ea41deb6 JS |
1125 | void ahci_command_verify(AHCIQState *ahci, AHCICommand *cmd) |
1126 | { | |
1127 | uint8_t slot = cmd->slot; | |
1128 | uint8_t port = cmd->port; | |
1129 | ||
f697b0ed | 1130 | ahci_port_check_error(ahci, port, cmd->interrupts, cmd->errors); |
ea41deb6 JS |
1131 | ahci_port_check_interrupts(ahci, port, cmd->interrupts); |
1132 | ahci_port_check_nonbusy(ahci, port, slot); | |
40d29928 | 1133 | ahci_port_check_cmd_sanity(ahci, cmd); |
359790c2 JS |
1134 | if (cmd->interrupts & AHCI_PX_IS_DHRS) { |
1135 | ahci_port_check_d2h_sanity(ahci, port, slot); | |
1136 | } | |
ea41deb6 JS |
1137 | if (cmd->props->pio) { |
1138 | ahci_port_check_pio_sanity(ahci, port, slot, cmd->xbytes); | |
1139 | } | |
1140 | } | |
1141 | ||
64a5a272 JS |
1142 | uint8_t ahci_command_slot(AHCICommand *cmd) |
1143 | { | |
1144 | return cmd->slot; | |
1145 | } |