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6bc12fd0 RH |
1 | /* |
2 | * SPDX-License-Identifier: GPL-2.0-or-later | |
d02d06f8 | 3 | * Host specific cpu identification for x86. |
6bc12fd0 RH |
4 | */ |
5 | ||
6 | #include "qemu/osdep.h" | |
7 | #include "host/cpuinfo.h" | |
8 | #ifdef CONFIG_CPUID_H | |
9 | # include "qemu/cpuid.h" | |
10 | #endif | |
11 | ||
12 | unsigned cpuinfo; | |
13 | ||
14 | /* Called both as constructor and (possibly) via other constructors. */ | |
15 | unsigned __attribute__((constructor)) cpuinfo_init(void) | |
16 | { | |
17 | unsigned info = cpuinfo; | |
18 | ||
19 | if (info) { | |
20 | return info; | |
21 | } | |
22 | ||
23 | #ifdef CONFIG_CPUID_H | |
24 | unsigned max, a, b, c, d, b7 = 0, c7 = 0; | |
25 | ||
26 | max = __get_cpuid_max(0, 0); | |
27 | ||
28 | if (max >= 7) { | |
29 | __cpuid_count(7, 0, a, b7, c7, d); | |
30 | info |= (b7 & bit_BMI ? CPUINFO_BMI1 : 0); | |
31 | info |= (b7 & bit_BMI2 ? CPUINFO_BMI2 : 0); | |
32 | } | |
33 | ||
34 | if (max >= 1) { | |
35 | __cpuid(1, a, b, c, d); | |
36 | ||
37 | info |= (d & bit_CMOV ? CPUINFO_CMOV : 0); | |
38 | info |= (d & bit_SSE2 ? CPUINFO_SSE2 : 0); | |
39 | info |= (c & bit_SSE4_1 ? CPUINFO_SSE4 : 0); | |
40 | info |= (c & bit_MOVBE ? CPUINFO_MOVBE : 0); | |
41 | info |= (c & bit_POPCNT ? CPUINFO_POPCNT : 0); | |
42 | ||
d6a24436 RH |
43 | /* Our AES support requires PSHUFB as well. */ |
44 | info |= ((c & bit_AES) && (c & bit_SSSE3) ? CPUINFO_AES : 0); | |
45 | ||
6bc12fd0 RH |
46 | /* For AVX features, we must check available and usable. */ |
47 | if ((c & bit_AVX) && (c & bit_OSXSAVE)) { | |
48 | unsigned bv = xgetbv_low(0); | |
49 | ||
50 | if ((bv & 6) == 6) { | |
51 | info |= CPUINFO_AVX1; | |
52 | info |= (b7 & bit_AVX2 ? CPUINFO_AVX2 : 0); | |
53 | ||
54 | if ((bv & 0xe0) == 0xe0) { | |
55 | info |= (b7 & bit_AVX512F ? CPUINFO_AVX512F : 0); | |
56 | info |= (b7 & bit_AVX512VL ? CPUINFO_AVX512VL : 0); | |
57 | info |= (b7 & bit_AVX512BW ? CPUINFO_AVX512BW : 0); | |
58 | info |= (b7 & bit_AVX512DQ ? CPUINFO_AVX512DQ : 0); | |
59 | info |= (c7 & bit_AVX512VBMI2 ? CPUINFO_AVX512VBMI2 : 0); | |
60 | } | |
61 | ||
62 | /* | |
63 | * The Intel SDM has added: | |
64 | * Processors that enumerate support for IntelĀ® AVX | |
65 | * (by setting the feature flag CPUID.01H:ECX.AVX[bit 28]) | |
66 | * guarantee that the 16-byte memory operations performed | |
67 | * by the following instructions will always be carried | |
68 | * out atomically: | |
69 | * - MOVAPD, MOVAPS, and MOVDQA. | |
70 | * - VMOVAPD, VMOVAPS, and VMOVDQA when encoded with VEX.128. | |
71 | * - VMOVAPD, VMOVAPS, VMOVDQA32, and VMOVDQA64 when encoded | |
72 | * with EVEX.128 and k0 (masking disabled). | |
73 | * Note that these instructions require the linear addresses | |
74 | * of their memory operands to be 16-byte aligned. | |
75 | * | |
76 | * AMD has provided an even stronger guarantee that processors | |
d02d06f8 | 77 | * with AVX provide 16-byte atomicity for all cacheable, |
6bc12fd0 RH |
78 | * naturally aligned single loads and stores, e.g. MOVDQU. |
79 | * | |
80 | * See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688 | |
81 | */ | |
82 | __cpuid(0, a, b, c, d); | |
a48b6afe | 83 | if (c == signature_INTEL_ecx) { |
6bc12fd0 | 84 | info |= CPUINFO_ATOMIC_VMOVDQA; |
a48b6afe RH |
85 | } else if (c == signature_AMD_ecx) { |
86 | info |= CPUINFO_ATOMIC_VMOVDQA | CPUINFO_ATOMIC_VMOVDQU; | |
6bc12fd0 RH |
87 | } |
88 | } | |
89 | } | |
90 | } | |
91 | ||
92 | max = __get_cpuid_max(0x8000000, 0); | |
93 | if (max >= 1) { | |
94 | __cpuid(0x80000001, a, b, c, d); | |
95 | info |= (c & bit_LZCNT ? CPUINFO_LZCNT : 0); | |
96 | } | |
97 | #endif | |
98 | ||
99 | info |= CPUINFO_ALWAYS; | |
100 | cpuinfo = info; | |
101 | return info; | |
102 | } |