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1 | #/** @file\r | |
2 | #\r | |
3 | # Copyright (c) 2011-2018, ARM Limited. All rights reserved.\r | |
4 | # Copyright (c) 2015, Intel Corporation. All rights reserved.\r | |
5 | #\r | |
6 | # SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
7 | #\r | |
8 | #**/\r | |
9 | \r | |
10 | [Defines]\r | |
11 | DEC_SPECIFICATION = 0x00010005\r | |
12 | PACKAGE_NAME = ArmPlatformPkg\r | |
13 | PACKAGE_GUID = 3308e0a0-1d94-11e0-915c-0002a5d5c51b\r | |
14 | PACKAGE_VERSION = 0.1\r | |
15 | \r | |
16 | ################################################################################\r | |
17 | #\r | |
18 | # Include Section - list of Include Paths that are provided by this package.\r | |
19 | # Comments are used for Keywords and Module Types.\r | |
20 | #\r | |
21 | # Supported Module Types:\r | |
22 | # BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r | |
23 | #\r | |
24 | ################################################################################\r | |
25 | [Includes.common]\r | |
26 | Include # Root include for the package\r | |
27 | \r | |
28 | [LibraryClasses]\r | |
29 | ArmPlatformLib|Include/Library/ArmPlatformLib.h\r | |
30 | LcdHwLib|Include/Library/LcdHwLib.h\r | |
31 | LcdPlatformLib|Include/Library/LcdPlatformLib.h\r | |
32 | NorFlashPlatformLib|Include/Library/NorFlashPlatformLib.h\r | |
33 | PL011UartClockLib|Include/Library/PL011UartClockLib.h\r | |
34 | PL011UartLib|Include/Library/PL011UartLib.h\r | |
35 | \r | |
36 | [Guids.common]\r | |
37 | gArmPlatformTokenSpaceGuid = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }\r | |
38 | \r | |
39 | [PcdsFeatureFlag.common]\r | |
40 | gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004\r | |
41 | \r | |
42 | gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked|FALSE|BOOLEAN|0x0000003C\r | |
43 | \r | |
44 | # Disable the GOP controller on ExitBootServices(). By default the value is FALSE,\r | |
45 | # we assume the OS will handle the FrameBuffer from the UEFI GOP information.\r | |
46 | gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D\r | |
47 | \r | |
48 | [PcdsFixedAtBuild.common]\r | |
49 | gArmPlatformTokenSpaceGuid.PcdCoreCount|1|UINT32|0x00000039\r | |
50 | gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038\r | |
51 | \r | |
52 | # Stack for CPU Cores in Non Secure Mode\r | |
53 | gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT64|0x00000009\r | |
54 | gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037\r | |
55 | gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A\r | |
56 | \r | |
57 | # Size of the region used by UEFI in permanent memory (Reserved 128MB by default)\r | |
58 | gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015\r | |
59 | \r | |
60 | #\r | |
61 | # ARM Primecells\r | |
62 | #\r | |
63 | \r | |
64 | ## SP805 Watchdog\r | |
65 | gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0|UINT32|0x00000023\r | |
66 | gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021\r | |
67 | gArmPlatformTokenSpaceGuid.PcdSP805WatchdogInterrupt|0|UINT32|0x0000002E\r | |
68 | \r | |
69 | ## PL011 UART\r | |
70 | gArmPlatformTokenSpaceGuid.PL011UartClkInHz|24000000|UINT32|0x0000001F\r | |
71 | gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020\r | |
72 | gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D\r | |
73 | gArmPlatformTokenSpaceGuid.PL011UartInterrupt|0x00000000|UINT32|0x0000002F\r | |
74 | gArmPlatformTokenSpaceGuid.PL011UartRegOffsetVariant|0|UINT8|0x0000003E\r | |
75 | \r | |
76 | ## PL011 Serial Debug UART\r | |
77 | gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x00000000|UINT64|0x00000030\r | |
78 | gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|0x00000000|UINT64|0x00000031\r | |
79 | gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|0x00000000|UINT32|0x00000032\r | |
80 | \r | |
81 | ## PL061 GPIO\r | |
82 | gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025\r | |
83 | \r | |
84 | ## PL111 Lcd & HdLcd\r | |
85 | gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026\r | |
86 | gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027\r | |
87 | \r | |
88 | ## Default size for display modes upto 1920x1080 (1920 * 1080 * 4 Bytes Per Pixel)\r | |
89 | gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferSize|0x7E9000|UINT32|0x00000043\r | |
90 | ## If set, framebuffer memory will be reserved and mapped in the system RAM\r | |
91 | gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferBase|0x0|UINT64|0x00000044\r | |
92 | \r | |
93 | ## ARM Mali Display Processor DP500/DP550/DP650\r | |
94 | gArmPlatformTokenSpaceGuid.PcdArmMaliDpBase|0x0|UINT64|0x00000050\r | |
95 | gArmPlatformTokenSpaceGuid.PcdArmMaliDpMemoryRegionLength|0x0|UINT32|0x00000051\r | |
96 | \r | |
97 | ## PL180 MCI\r | |
98 | gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028\r | |
99 | gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029\r | |
100 | \r | |
101 | # Graphics Output Pixel format\r | |
102 | # 0 : PixelRedGreenBlueReserved8BitPerColor\r | |
103 | # 1 : PixelBlueGreenRedReserved8BitPerColor\r | |
104 | # 2 : PixelBitMask\r | |
105 | # Default is set to UEFI console font format PixelBlueGreenRedReserved8BitPerColor\r | |
106 | gArmPlatformTokenSpaceGuid.PcdGopPixelFormat|0x00000001|UINT32|0x00000040\r | |
107 | \r | |
108 | ## If set, this will swap settings for HDLCD RED_SELECT and BLUE_SELECT registers\r | |
109 | gArmPlatformTokenSpaceGuid.PcdArmHdLcdSwapBlueRedSelect|FALSE|BOOLEAN|0x00000045\r | |
110 | \r | |
111 | [PcdsFixedAtBuild.common,PcdsDynamic.common]\r | |
112 | ## PL031 RealTimeClock\r | |
113 | gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024\r | |
114 | gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022\r | |
115 | \r | |
116 | gArmPlatformTokenSpaceGuid.PcdWatchdogCount|0x0|UINT32|0x00000033\r |