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1 | /** @file\r | |
2 | This file declares Sec Platform Information PPI.\r | |
3 | \r | |
4 | This service is the primary handoff state into the PEI Foundation.\r | |
5 | The Security (SEC) component creates the early, transitory memory\r | |
6 | environment and also encapsulates knowledge of at least the\r | |
7 | location of the Boot Firmware Volume (BFV).\r | |
8 | \r | |
9 | Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r | |
10 | This program and the accompanying materials are licensed and made available under\r | |
11 | the terms and conditions of the BSD License that accompanies this distribution.\r | |
12 | The full text of the license may be found at\r | |
13 | http://opensource.org/licenses/bsd-license.php.\r | |
14 | \r | |
15 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
16 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
17 | \r | |
18 | @par Revision Reference:\r | |
19 | This PPI is introduced in PI Version 1.0.\r | |
20 | \r | |
21 | **/\r | |
22 | \r | |
23 | #ifndef __SEC_PLATFORM_INFORMATION_PPI_H__\r | |
24 | #define __SEC_PLATFORM_INFORMATION_PPI_H__\r | |
25 | \r | |
26 | #include <Pi/PiPeiCis.h>\r | |
27 | \r | |
28 | #define EFI_SEC_PLATFORM_INFORMATION_GUID \\r | |
29 | { \\r | |
30 | 0x6f8c2b35, 0xfef4, 0x448d, {0x82, 0x56, 0xe1, 0x1b, 0x19, 0xd6, 0x10, 0x77 } \\r | |
31 | }\r | |
32 | \r | |
33 | typedef struct _EFI_SEC_PLATFORM_INFORMATION_PPI EFI_SEC_PLATFORM_INFORMATION_PPI;\r | |
34 | \r | |
35 | \r | |
36 | ///\r | |
37 | /// EFI_HEALTH_FLAGS\r | |
38 | /// Contains information generated by microcode, hardware, and/or the Itanium\r | |
39 | /// processor PAL code about the state of the processor upon reset.\r | |
40 | ///\r | |
41 | typedef union {\r | |
42 | struct {\r | |
43 | ///\r | |
44 | /// A 2-bit field indicating self-test state after reset.\r | |
45 | ///\r | |
46 | UINT32 Status : 2;\r | |
47 | ///\r | |
48 | /// A 1-bit field indicating whether testing has occurred.\r | |
49 | /// If this field is zero, the processor has not been tested,\r | |
50 | /// and no further fields in the self-test State parameter are valid.\r | |
51 | ///\r | |
52 | UINT32 Tested : 1;\r | |
53 | ///\r | |
54 | /// Reserved 13 bits.\r | |
55 | ///\r | |
56 | UINT32 Reserved1 :13;\r | |
57 | ///\r | |
58 | /// A 1-bit field. If set to 1, this indicates that virtual\r | |
59 | /// memory features are not available.\r | |
60 | ///\r | |
61 | UINT32 VirtualMemoryUnavailable : 1;\r | |
62 | ///\r | |
63 | /// A 1-bit field. If set to 1, this indicates that IA-32 execution\r | |
64 | /// is not available.\r | |
65 | ///\r | |
66 | UINT32 Ia32ExecutionUnavailable : 1;\r | |
67 | ///\r | |
68 | /// A 1-bit field. If set to 1, this indicates that the floating\r | |
69 | /// point unit is not available.\r | |
70 | ///\r | |
71 | UINT32 FloatingPointUnavailable : 1;\r | |
72 | ///\r | |
73 | /// A 1-bit field. If set to 1, this indicates miscellaneous\r | |
74 | /// functional failure other than vm, ia, or fp.\r | |
75 | /// The test status field provides additional information on\r | |
76 | /// test failures when the State field returns a value of\r | |
77 | /// performance restricted or functionally restricted.\r | |
78 | /// The value returned is implementation dependent.\r | |
79 | ///\r | |
80 | UINT32 MiscFeaturesUnavailable : 1;\r | |
81 | ///\r | |
82 | /// Reserved 12 bits.\r | |
83 | ///\r | |
84 | UINT32 Reserved2 :12;\r | |
85 | } Bits;\r | |
86 | UINT32 Uint32;\r | |
87 | } EFI_HEALTH_FLAGS;\r | |
88 | \r | |
89 | #define NORMAL_BOOT_CALL 0x0\r | |
90 | #define RECOVERY_CHECK_CALL 0x3\r | |
91 | \r | |
92 | typedef EFI_HEALTH_FLAGS X64_HANDOFF_STATUS;\r | |
93 | typedef EFI_HEALTH_FLAGS IA32_HANDOFF_STATUS;\r | |
94 | ///\r | |
95 | /// The hand-off status structure for Itanium architecture.\r | |
96 | ///\r | |
97 | typedef struct {\r | |
98 | ///\r | |
99 | /// SALE_ENTRY state : 3 = Recovery_Check\r | |
100 | /// and 0 = RESET or Normal_Boot phase.\r | |
101 | ///\r | |
102 | UINT8 BootPhase;\r | |
103 | ///\r | |
104 | /// Firmware status on entry to SALE.\r | |
105 | ///\r | |
106 | UINT8 FWStatus;\r | |
107 | UINT16 Reserved1;\r | |
108 | UINT32 Reserved2;\r | |
109 | ///\r | |
110 | /// Geographically significant unique processor ID assigned by PAL.\r | |
111 | ///\r | |
112 | UINT16 ProcId;\r | |
113 | UINT16 Reserved3;\r | |
114 | UINT8 IdMask;\r | |
115 | UINT8 EidMask;\r | |
116 | UINT16 Reserved4;\r | |
117 | ///\r | |
118 | /// Address to make PAL calls.\r | |
119 | ///\r | |
120 | UINT64 PalCallAddress;\r | |
121 | ///\r | |
122 | /// If the entry state is RECOVERY_CHECK, this contains the PAL_RESET\r | |
123 | /// return address, and if entry state is RESET, this contains\r | |
124 | /// address for PAL_authentication call.\r | |
125 | ///\r | |
126 | UINT64 PalSpecialAddress;\r | |
127 | ///\r | |
128 | /// GR35 from PALE_EXIT state.\r | |
129 | ///\r | |
130 | UINT64 SelfTestStatus;\r | |
131 | ///\r | |
132 | /// GR37 from PALE_EXIT state.\r | |
133 | ///\r | |
134 | UINT64 SelfTestControl;\r | |
135 | UINT64 MemoryBufferRequired;\r | |
136 | } ITANIUM_HANDOFF_STATUS;\r | |
137 | \r | |
138 | ///\r | |
139 | /// EFI_SEC_PLATFORM_INFORMATION_RECORD.\r | |
140 | ///\r | |
141 | typedef union {\r | |
142 | IA32_HANDOFF_STATUS IA32HealthFlags;\r | |
143 | X64_HANDOFF_STATUS x64HealthFlags;\r | |
144 | ITANIUM_HANDOFF_STATUS ItaniumHealthFlags;\r | |
145 | } EFI_SEC_PLATFORM_INFORMATION_RECORD;\r | |
146 | \r | |
147 | /**\r | |
148 | This interface conveys state information out of the Security (SEC) phase into PEI.\r | |
149 | \r | |
150 | This service is published by the SEC phase. The SEC phase handoff has an optional\r | |
151 | EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed from SEC into the\r | |
152 | PEI Foundation. As such, if the platform supports the built-in self test (BIST) on IA-32 Intel\r | |
153 | architecture or the PAL-A handoff state for Itanium architecture, this information is encapsulated\r | |
154 | into the data structure abstracted by this service. This information is collected for the boot-strap\r | |
155 | processor (BSP) on IA-32. For Itanium architecture, it is available on all processors that execute\r | |
156 | the PEI Foundation.\r | |
157 | \r | |
158 | @param PeiServices The pointer to the PEI Services Table.\r | |
159 | @param StructureSize The pointer to the variable describing size of the input buffer.\r | |
160 | @param PlatformInformationRecord The pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.\r | |
161 | \r | |
162 | @retval EFI_SUCCESS The data was successfully returned.\r | |
163 | @retval EFI_BUFFER_TOO_SMALL The buffer was too small. The current buffer size needed to\r | |
164 | hold the record is returned in StructureSize.\r | |
165 | \r | |
166 | **/\r | |
167 | typedef\r | |
168 | EFI_STATUS\r | |
169 | (EFIAPI *EFI_SEC_PLATFORM_INFORMATION)(\r | |
170 | IN CONST EFI_PEI_SERVICES **PeiServices,\r | |
171 | IN OUT UINT64 *StructureSize,\r | |
172 | OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord\r | |
173 | );\r | |
174 | \r | |
175 | \r | |
176 | ///\r | |
177 | /// This service abstracts platform-specific information. It is necessary\r | |
178 | /// to convey this information to the PEI Foundation so that it can\r | |
179 | /// discover where to begin dispatching PEIMs.\r | |
180 | ///\r | |
181 | struct _EFI_SEC_PLATFORM_INFORMATION_PPI {\r | |
182 | EFI_SEC_PLATFORM_INFORMATION PlatformInformation;\r | |
183 | };\r | |
184 | \r | |
185 | \r | |
186 | extern EFI_GUID gEfiSecPlatformInformationPpiGuid;\r | |
187 | \r | |
188 | #endif\r |