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1 | /** @file\r | |
2 | PCI Library Services for PCI Segment #0\r | |
3 | \r | |
4 | Copyright (c) 2006, Intel Corporation\r | |
5 | All rights reserved. This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | Module Name: PciLib.h\r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
17 | #ifndef __PCI_LIB_H__\r | |
18 | #define __PCI_LIB_H__\r | |
19 | \r | |
20 | /**\r | |
21 | Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an\r | |
22 | address that can be passed to the PCI Library functions.\r | |
23 | \r | |
24 | @param Bus PCI Bus number. Range 0..255.\r | |
25 | @param Device PCI Device number. Range 0..31.\r | |
26 | @param Function PCI Function number. Range 0..7.\r | |
27 | @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095\r | |
28 | for PCI Express.\r | |
29 | \r | |
30 | @return The encoded PCI address.\r | |
31 | \r | |
32 | **/\r | |
33 | #define PCI_LIB_ADDRESS(Bus,Device,Function,Offset) \\r | |
34 | (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r | |
35 | \r | |
36 | /**\r | |
37 | Reads an 8-bit PCI configuration register.\r | |
38 | \r | |
39 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
40 | This function must guarantee that all PCI read and write operations are\r | |
41 | serialized.\r | |
42 | \r | |
43 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
44 | \r | |
45 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
46 | Register.\r | |
47 | \r | |
48 | @return The read value from the PCI configuration register.\r | |
49 | \r | |
50 | **/\r | |
51 | UINT8\r | |
52 | EFIAPI\r | |
53 | PciRead8 (\r | |
54 | IN UINTN Address\r | |
55 | );\r | |
56 | \r | |
57 | /**\r | |
58 | Writes an 8-bit PCI configuration register.\r | |
59 | \r | |
60 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
61 | value specified by Value. Value is returned. This function must guarantee\r | |
62 | that all PCI read and write operations are serialized.\r | |
63 | \r | |
64 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
65 | \r | |
66 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
67 | Register.\r | |
68 | @param Value The value to write.\r | |
69 | \r | |
70 | @return The value written to the PCI configuration register.\r | |
71 | \r | |
72 | **/\r | |
73 | UINT8\r | |
74 | EFIAPI\r | |
75 | PciWrite8 (\r | |
76 | IN UINTN Address,\r | |
77 | IN UINT8 Data\r | |
78 | );\r | |
79 | \r | |
80 | /**\r | |
81 | Performs a bitwise inclusive OR of an 8-bit PCI configuration register with\r | |
82 | an 8-bit value.\r | |
83 | \r | |
84 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
85 | bitwise inclusive OR between the read result and the value specified by\r | |
86 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
87 | specified by Address. The value written to the PCI configuration register is\r | |
88 | returned. This function must guarantee that all PCI read and write operations\r | |
89 | are serialized.\r | |
90 | \r | |
91 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
92 | \r | |
93 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
94 | Register.\r | |
95 | @param OrData The value to OR with the PCI configuration register.\r | |
96 | \r | |
97 | @return The value written back to the PCI configuration register.\r | |
98 | \r | |
99 | **/\r | |
100 | UINT8\r | |
101 | EFIAPI\r | |
102 | PciOr8 (\r | |
103 | IN UINTN Address,\r | |
104 | IN UINT8 OrData\r | |
105 | );\r | |
106 | \r | |
107 | /**\r | |
108 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
109 | value.\r | |
110 | \r | |
111 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
112 | bitwise AND between the read result and the value specified by AndData, and\r | |
113 | writes the result to the 8-bit PCI configuration register specified by\r | |
114 | Address. The value written to the PCI configuration register is returned.\r | |
115 | This function must guarantee that all PCI read and write operations are\r | |
116 | serialized.\r | |
117 | \r | |
118 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
119 | \r | |
120 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
121 | Register.\r | |
122 | @param AndData The value to AND with the PCI configuration register.\r | |
123 | \r | |
124 | @return The value written back to the PCI configuration register.\r | |
125 | \r | |
126 | **/\r | |
127 | UINT8\r | |
128 | EFIAPI\r | |
129 | PciAnd8 (\r | |
130 | IN UINTN Address,\r | |
131 | IN UINT8 AndData\r | |
132 | );\r | |
133 | \r | |
134 | /**\r | |
135 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
136 | value, followed a bitwise inclusive OR with another 8-bit value.\r | |
137 | \r | |
138 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
139 | bitwise AND between the read result and the value specified by AndData,\r | |
140 | performs a bitwise inclusive OR between the result of the AND operation and\r | |
141 | the value specified by OrData, and writes the result to the 8-bit PCI\r | |
142 | configuration register specified by Address. The value written to the PCI\r | |
143 | configuration register is returned. This function must guarantee that all PCI\r | |
144 | read and write operations are serialized.\r | |
145 | \r | |
146 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
147 | \r | |
148 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
149 | Register.\r | |
150 | @param AndData The value to AND with the PCI configuration register.\r | |
151 | @param OrData The value to OR with the result of the AND operation.\r | |
152 | \r | |
153 | @return The value written back to the PCI configuration register.\r | |
154 | \r | |
155 | **/\r | |
156 | UINT8\r | |
157 | EFIAPI\r | |
158 | PciAndThenOr8 (\r | |
159 | IN UINTN Address,\r | |
160 | IN UINT8 AndData,\r | |
161 | IN UINT8 OrData\r | |
162 | );\r | |
163 | \r | |
164 | /**\r | |
165 | Reads a bit field of a PCI configuration register.\r | |
166 | \r | |
167 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
168 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
169 | returned.\r | |
170 | \r | |
171 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
172 | If StartBit is greater than 7, then ASSERT().\r | |
173 | If EndBit is greater than 7, then ASSERT().\r | |
174 | If EndBit is less than StartBit, then ASSERT().\r | |
175 | \r | |
176 | @param Address PCI configuration register to read.\r | |
177 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
178 | Range 0..7.\r | |
179 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
180 | Range 0..7.\r | |
181 | \r | |
182 | @return The value of the bit field read from the PCI configuration register.\r | |
183 | \r | |
184 | **/\r | |
185 | UINT8\r | |
186 | EFIAPI\r | |
187 | PciBitFieldRead8 (\r | |
188 | IN UINTN Address,\r | |
189 | IN UINTN StartBit,\r | |
190 | IN UINTN EndBit\r | |
191 | );\r | |
192 | \r | |
193 | /**\r | |
194 | Writes a bit field to a PCI configuration register.\r | |
195 | \r | |
196 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
197 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
198 | destination PCI configuration register are preserved. The new value of the\r | |
199 | 8-bit register is returned.\r | |
200 | \r | |
201 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
202 | If StartBit is greater than 7, then ASSERT().\r | |
203 | If EndBit is greater than 7, then ASSERT().\r | |
204 | If EndBit is less than StartBit, then ASSERT().\r | |
205 | \r | |
206 | @param Address PCI configuration register to write.\r | |
207 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
208 | Range 0..7.\r | |
209 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
210 | Range 0..7.\r | |
211 | @param Value New value of the bit field.\r | |
212 | \r | |
213 | @return The value written back to the PCI configuration register.\r | |
214 | \r | |
215 | **/\r | |
216 | UINT8\r | |
217 | EFIAPI\r | |
218 | PciBitFieldWrite8 (\r | |
219 | IN UINTN Address,\r | |
220 | IN UINTN StartBit,\r | |
221 | IN UINTN EndBit,\r | |
222 | IN UINT8 Value\r | |
223 | );\r | |
224 | \r | |
225 | /**\r | |
226 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
227 | writes the result back to the bit field in the 8-bit port.\r | |
228 | \r | |
229 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
230 | bitwise inclusive OR between the read result and the value specified by\r | |
231 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
232 | specified by Address. The value written to the PCI configuration register is\r | |
233 | returned. This function must guarantee that all PCI read and write operations\r | |
234 | are serialized. Extra left bits in OrData are stripped.\r | |
235 | \r | |
236 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
237 | If StartBit is greater than 7, then ASSERT().\r | |
238 | If EndBit is greater than 7, then ASSERT().\r | |
239 | If EndBit is less than StartBit, then ASSERT().\r | |
240 | \r | |
241 | @param Address PCI configuration register to write.\r | |
242 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
243 | Range 0..7.\r | |
244 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
245 | Range 0..7.\r | |
246 | @param OrData The value to OR with the PCI configuration register.\r | |
247 | \r | |
248 | @return The value written back to the PCI configuration register.\r | |
249 | \r | |
250 | **/\r | |
251 | UINT8\r | |
252 | EFIAPI\r | |
253 | PciBitFieldOr8 (\r | |
254 | IN UINTN Address,\r | |
255 | IN UINTN StartBit,\r | |
256 | IN UINTN EndBit,\r | |
257 | IN UINT8 OrData\r | |
258 | );\r | |
259 | \r | |
260 | /**\r | |
261 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
262 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
263 | \r | |
264 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
265 | bitwise AND between the read result and the value specified by AndData, and\r | |
266 | writes the result to the 8-bit PCI configuration register specified by\r | |
267 | Address. The value written to the PCI configuration register is returned.\r | |
268 | This function must guarantee that all PCI read and write operations are\r | |
269 | serialized. Extra left bits in AndData are stripped.\r | |
270 | \r | |
271 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
272 | If StartBit is greater than 7, then ASSERT().\r | |
273 | If EndBit is greater than 7, then ASSERT().\r | |
274 | If EndBit is less than StartBit, then ASSERT().\r | |
275 | \r | |
276 | @param Address PCI configuration register to write.\r | |
277 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
278 | Range 0..7.\r | |
279 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
280 | Range 0..7.\r | |
281 | @param AndData The value to AND with the PCI configuration register.\r | |
282 | \r | |
283 | @return The value written back to the PCI configuration register.\r | |
284 | \r | |
285 | **/\r | |
286 | UINT8\r | |
287 | EFIAPI\r | |
288 | PciBitFieldAnd8 (\r | |
289 | IN UINTN Address,\r | |
290 | IN UINTN StartBit,\r | |
291 | IN UINTN EndBit,\r | |
292 | IN UINT8 AndData\r | |
293 | );\r | |
294 | \r | |
295 | /**\r | |
296 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
297 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
298 | 8-bit port.\r | |
299 | \r | |
300 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
301 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
302 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
303 | configuration register specified by Address. The value written to the PCI\r | |
304 | configuration register is returned. This function must guarantee that all PCI\r | |
305 | read and write operations are serialized. Extra left bits in both AndData and\r | |
306 | OrData are stripped.\r | |
307 | \r | |
308 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
309 | If StartBit is greater than 7, then ASSERT().\r | |
310 | If EndBit is greater than 7, then ASSERT().\r | |
311 | If EndBit is less than StartBit, then ASSERT().\r | |
312 | \r | |
313 | @param Address PCI configuration register to write.\r | |
314 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
315 | Range 0..7.\r | |
316 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
317 | Range 0..7.\r | |
318 | @param AndData The value to AND with the PCI configuration register.\r | |
319 | @param OrData The value to OR with the result of the AND operation.\r | |
320 | \r | |
321 | @return The value written back to the PCI configuration register.\r | |
322 | \r | |
323 | **/\r | |
324 | UINT8\r | |
325 | EFIAPI\r | |
326 | PciBitFieldAndThenOr8 (\r | |
327 | IN UINTN Address,\r | |
328 | IN UINTN StartBit,\r | |
329 | IN UINTN EndBit,\r | |
330 | IN UINT8 AndData,\r | |
331 | IN UINT8 OrData\r | |
332 | );\r | |
333 | \r | |
334 | /**\r | |
335 | Reads a 16-bit PCI configuration register.\r | |
336 | \r | |
337 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
338 | This function must guarantee that all PCI read and write operations are\r | |
339 | serialized.\r | |
340 | \r | |
341 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
342 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
343 | \r | |
344 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
345 | Register.\r | |
346 | \r | |
347 | @return The read value from the PCI configuration register.\r | |
348 | \r | |
349 | **/\r | |
350 | UINT16\r | |
351 | EFIAPI\r | |
352 | PciRead16 (\r | |
353 | IN UINTN Address\r | |
354 | );\r | |
355 | \r | |
356 | /**\r | |
357 | Writes a 16-bit PCI configuration register.\r | |
358 | \r | |
359 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
360 | value specified by Value. Value is returned. This function must guarantee\r | |
361 | that all PCI read and write operations are serialized.\r | |
362 | \r | |
363 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
364 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
365 | \r | |
366 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
367 | Register.\r | |
368 | @param Value The value to write.\r | |
369 | \r | |
370 | @return The value written to the PCI configuration register.\r | |
371 | \r | |
372 | **/\r | |
373 | UINT16\r | |
374 | EFIAPI\r | |
375 | PciWrite16 (\r | |
376 | IN UINTN Address,\r | |
377 | IN UINT16 Data\r | |
378 | );\r | |
379 | \r | |
380 | /**\r | |
381 | Performs a bitwise inclusive OR of a 16-bit PCI configuration register with\r | |
382 | a 16-bit value.\r | |
383 | \r | |
384 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
385 | bitwise inclusive OR between the read result and the value specified by\r | |
386 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
387 | specified by Address. The value written to the PCI configuration register is\r | |
388 | returned. This function must guarantee that all PCI read and write operations\r | |
389 | are serialized.\r | |
390 | \r | |
391 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
392 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
393 | \r | |
394 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
395 | Register.\r | |
396 | @param OrData The value to OR with the PCI configuration register.\r | |
397 | \r | |
398 | @return The value written back to the PCI configuration register.\r | |
399 | \r | |
400 | **/\r | |
401 | UINT16\r | |
402 | EFIAPI\r | |
403 | PciOr16 (\r | |
404 | IN UINTN Address,\r | |
405 | IN UINT16 OrData\r | |
406 | );\r | |
407 | \r | |
408 | /**\r | |
409 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
410 | value.\r | |
411 | \r | |
412 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
413 | bitwise AND between the read result and the value specified by AndData, and\r | |
414 | writes the result to the 16-bit PCI configuration register specified by\r | |
415 | Address. The value written to the PCI configuration register is returned.\r | |
416 | This function must guarantee that all PCI read and write operations are\r | |
417 | serialized.\r | |
418 | \r | |
419 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
420 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
421 | \r | |
422 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
423 | Register.\r | |
424 | @param AndData The value to AND with the PCI configuration register.\r | |
425 | \r | |
426 | @return The value written back to the PCI configuration register.\r | |
427 | \r | |
428 | **/\r | |
429 | UINT16\r | |
430 | EFIAPI\r | |
431 | PciAnd16 (\r | |
432 | IN UINTN Address,\r | |
433 | IN UINT16 AndData\r | |
434 | );\r | |
435 | \r | |
436 | /**\r | |
437 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
438 | value, followed a bitwise inclusive OR with another 16-bit value.\r | |
439 | \r | |
440 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
441 | bitwise AND between the read result and the value specified by AndData,\r | |
442 | performs a bitwise inclusive OR between the result of the AND operation and\r | |
443 | the value specified by OrData, and writes the result to the 16-bit PCI\r | |
444 | configuration register specified by Address. The value written to the PCI\r | |
445 | configuration register is returned. This function must guarantee that all PCI\r | |
446 | read and write operations are serialized.\r | |
447 | \r | |
448 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
449 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
450 | \r | |
451 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
452 | Register.\r | |
453 | @param AndData The value to AND with the PCI configuration register.\r | |
454 | @param OrData The value to OR with the result of the AND operation.\r | |
455 | \r | |
456 | @return The value written back to the PCI configuration register.\r | |
457 | \r | |
458 | **/\r | |
459 | UINT16\r | |
460 | EFIAPI\r | |
461 | PciAndThenOr16 (\r | |
462 | IN UINTN Address,\r | |
463 | IN UINT16 AndData,\r | |
464 | IN UINT16 OrData\r | |
465 | );\r | |
466 | \r | |
467 | /**\r | |
468 | Reads a bit field of a PCI configuration register.\r | |
469 | \r | |
470 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
471 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
472 | returned.\r | |
473 | \r | |
474 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
475 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
476 | If StartBit is greater than 15, then ASSERT().\r | |
477 | If EndBit is greater than 15, then ASSERT().\r | |
478 | If EndBit is less than StartBit, then ASSERT().\r | |
479 | \r | |
480 | @param Address PCI configuration register to read.\r | |
481 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
482 | Range 0..15.\r | |
483 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
484 | Range 0..15.\r | |
485 | \r | |
486 | @return The value of the bit field read from the PCI configuration register.\r | |
487 | \r | |
488 | **/\r | |
489 | UINT16\r | |
490 | EFIAPI\r | |
491 | PciBitFieldRead16 (\r | |
492 | IN UINTN Address,\r | |
493 | IN UINTN StartBit,\r | |
494 | IN UINTN EndBit\r | |
495 | );\r | |
496 | \r | |
497 | /**\r | |
498 | Writes a bit field to a PCI configuration register.\r | |
499 | \r | |
500 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
501 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
502 | destination PCI configuration register are preserved. The new value of the\r | |
503 | 16-bit register is returned.\r | |
504 | \r | |
505 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
506 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
507 | If StartBit is greater than 15, then ASSERT().\r | |
508 | If EndBit is greater than 15, then ASSERT().\r | |
509 | If EndBit is less than StartBit, then ASSERT().\r | |
510 | \r | |
511 | @param Address PCI configuration register to write.\r | |
512 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
513 | Range 0..15.\r | |
514 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
515 | Range 0..15.\r | |
516 | @param Value New value of the bit field.\r | |
517 | \r | |
518 | @return The value written back to the PCI configuration register.\r | |
519 | \r | |
520 | **/\r | |
521 | UINT16\r | |
522 | EFIAPI\r | |
523 | PciBitFieldWrite16 (\r | |
524 | IN UINTN Address,\r | |
525 | IN UINTN StartBit,\r | |
526 | IN UINTN EndBit,\r | |
527 | IN UINT16 Value\r | |
528 | );\r | |
529 | \r | |
530 | /**\r | |
531 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
532 | writes the result back to the bit field in the 16-bit port.\r | |
533 | \r | |
534 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
535 | bitwise inclusive OR between the read result and the value specified by\r | |
536 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
537 | specified by Address. The value written to the PCI configuration register is\r | |
538 | returned. This function must guarantee that all PCI read and write operations\r | |
539 | are serialized. Extra left bits in OrData are stripped.\r | |
540 | \r | |
541 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
542 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
543 | If StartBit is greater than 15, then ASSERT().\r | |
544 | If EndBit is greater than 15, then ASSERT().\r | |
545 | If EndBit is less than StartBit, then ASSERT().\r | |
546 | \r | |
547 | @param Address PCI configuration register to write.\r | |
548 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
549 | Range 0..15.\r | |
550 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
551 | Range 0..15.\r | |
552 | @param OrData The value to OR with the PCI configuration register.\r | |
553 | \r | |
554 | @return The value written back to the PCI configuration register.\r | |
555 | \r | |
556 | **/\r | |
557 | UINT16\r | |
558 | EFIAPI\r | |
559 | PciBitFieldOr16 (\r | |
560 | IN UINTN Address,\r | |
561 | IN UINTN StartBit,\r | |
562 | IN UINTN EndBit,\r | |
563 | IN UINT16 OrData\r | |
564 | );\r | |
565 | \r | |
566 | /**\r | |
567 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
568 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
569 | \r | |
570 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
571 | bitwise AND between the read result and the value specified by AndData, and\r | |
572 | writes the result to the 16-bit PCI configuration register specified by\r | |
573 | Address. The value written to the PCI configuration register is returned.\r | |
574 | This function must guarantee that all PCI read and write operations are\r | |
575 | serialized. Extra left bits in AndData are stripped.\r | |
576 | \r | |
577 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
578 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
579 | If StartBit is greater than 15, then ASSERT().\r | |
580 | If EndBit is greater than 15, then ASSERT().\r | |
581 | If EndBit is less than StartBit, then ASSERT().\r | |
582 | \r | |
583 | @param Address PCI configuration register to write.\r | |
584 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
585 | Range 0..15.\r | |
586 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
587 | Range 0..15.\r | |
588 | @param AndData The value to AND with the PCI configuration register.\r | |
589 | \r | |
590 | @return The value written back to the PCI configuration register.\r | |
591 | \r | |
592 | **/\r | |
593 | UINT16\r | |
594 | EFIAPI\r | |
595 | PciBitFieldAnd16 (\r | |
596 | IN UINTN Address,\r | |
597 | IN UINTN StartBit,\r | |
598 | IN UINTN EndBit,\r | |
599 | IN UINT16 AndData\r | |
600 | );\r | |
601 | \r | |
602 | /**\r | |
603 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
604 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
605 | 16-bit port.\r | |
606 | \r | |
607 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
608 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
609 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
610 | configuration register specified by Address. The value written to the PCI\r | |
611 | configuration register is returned. This function must guarantee that all PCI\r | |
612 | read and write operations are serialized. Extra left bits in both AndData and\r | |
613 | OrData are stripped.\r | |
614 | \r | |
615 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
616 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
617 | If StartBit is greater than 15, then ASSERT().\r | |
618 | If EndBit is greater than 15, then ASSERT().\r | |
619 | If EndBit is less than StartBit, then ASSERT().\r | |
620 | \r | |
621 | @param Address PCI configuration register to write.\r | |
622 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
623 | Range 0..15.\r | |
624 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
625 | Range 0..15.\r | |
626 | @param AndData The value to AND with the PCI configuration register.\r | |
627 | @param OrData The value to OR with the result of the AND operation.\r | |
628 | \r | |
629 | @return The value written back to the PCI configuration register.\r | |
630 | \r | |
631 | **/\r | |
632 | UINT16\r | |
633 | EFIAPI\r | |
634 | PciBitFieldAndThenOr16 (\r | |
635 | IN UINTN Address,\r | |
636 | IN UINTN StartBit,\r | |
637 | IN UINTN EndBit,\r | |
638 | IN UINT16 AndData,\r | |
639 | IN UINT16 OrData\r | |
640 | );\r | |
641 | \r | |
642 | /**\r | |
643 | Reads a 32-bit PCI configuration register.\r | |
644 | \r | |
645 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
646 | This function must guarantee that all PCI read and write operations are\r | |
647 | serialized.\r | |
648 | \r | |
649 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
650 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
651 | \r | |
652 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
653 | Register.\r | |
654 | \r | |
655 | @return The read value from the PCI configuration register.\r | |
656 | \r | |
657 | **/\r | |
658 | UINT32\r | |
659 | EFIAPI\r | |
660 | PciRead32 (\r | |
661 | IN UINTN Address\r | |
662 | );\r | |
663 | \r | |
664 | /**\r | |
665 | Writes a 32-bit PCI configuration register.\r | |
666 | \r | |
667 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
668 | value specified by Value. Value is returned. This function must guarantee\r | |
669 | that all PCI read and write operations are serialized.\r | |
670 | \r | |
671 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
672 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
673 | \r | |
674 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
675 | Register.\r | |
676 | @param Value The value to write.\r | |
677 | \r | |
678 | @return The value written to the PCI configuration register.\r | |
679 | \r | |
680 | **/\r | |
681 | UINT32\r | |
682 | EFIAPI\r | |
683 | PciWrite32 (\r | |
684 | IN UINTN Address,\r | |
685 | IN UINT32 Data\r | |
686 | );\r | |
687 | \r | |
688 | /**\r | |
689 | Performs a bitwise inclusive OR of a 32-bit PCI configuration register with\r | |
690 | a 32-bit value.\r | |
691 | \r | |
692 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
693 | bitwise inclusive OR between the read result and the value specified by\r | |
694 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
695 | specified by Address. The value written to the PCI configuration register is\r | |
696 | returned. This function must guarantee that all PCI read and write operations\r | |
697 | are serialized.\r | |
698 | \r | |
699 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
700 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
701 | \r | |
702 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
703 | Register.\r | |
704 | @param OrData The value to OR with the PCI configuration register.\r | |
705 | \r | |
706 | @return The value written back to the PCI configuration register.\r | |
707 | \r | |
708 | **/\r | |
709 | UINT32\r | |
710 | EFIAPI\r | |
711 | PciOr32 (\r | |
712 | IN UINTN Address,\r | |
713 | IN UINT32 OrData\r | |
714 | );\r | |
715 | \r | |
716 | /**\r | |
717 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
718 | value.\r | |
719 | \r | |
720 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
721 | bitwise AND between the read result and the value specified by AndData, and\r | |
722 | writes the result to the 32-bit PCI configuration register specified by\r | |
723 | Address. The value written to the PCI configuration register is returned.\r | |
724 | This function must guarantee that all PCI read and write operations are\r | |
725 | serialized.\r | |
726 | \r | |
727 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
728 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
729 | \r | |
730 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
731 | Register.\r | |
732 | @param AndData The value to AND with the PCI configuration register.\r | |
733 | \r | |
734 | @return The value written back to the PCI configuration register.\r | |
735 | \r | |
736 | **/\r | |
737 | UINT32\r | |
738 | EFIAPI\r | |
739 | PciAnd32 (\r | |
740 | IN UINTN Address,\r | |
741 | IN UINT32 AndData\r | |
742 | );\r | |
743 | \r | |
744 | /**\r | |
745 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
746 | value, followed a bitwise inclusive OR with another 32-bit value.\r | |
747 | \r | |
748 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
749 | bitwise AND between the read result and the value specified by AndData,\r | |
750 | performs a bitwise inclusive OR between the result of the AND operation and\r | |
751 | the value specified by OrData, and writes the result to the 32-bit PCI\r | |
752 | configuration register specified by Address. The value written to the PCI\r | |
753 | configuration register is returned. This function must guarantee that all PCI\r | |
754 | read and write operations are serialized.\r | |
755 | \r | |
756 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
757 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
758 | \r | |
759 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
760 | Register.\r | |
761 | @param AndData The value to AND with the PCI configuration register.\r | |
762 | @param OrData The value to OR with the result of the AND operation.\r | |
763 | \r | |
764 | @return The value written back to the PCI configuration register.\r | |
765 | \r | |
766 | **/\r | |
767 | UINT32\r | |
768 | EFIAPI\r | |
769 | PciAndThenOr32 (\r | |
770 | IN UINTN Address,\r | |
771 | IN UINT32 AndData,\r | |
772 | IN UINT32 OrData\r | |
773 | );\r | |
774 | \r | |
775 | /**\r | |
776 | Reads a bit field of a PCI configuration register.\r | |
777 | \r | |
778 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
779 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
780 | returned.\r | |
781 | \r | |
782 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
783 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
784 | If StartBit is greater than 31, then ASSERT().\r | |
785 | If EndBit is greater than 31, then ASSERT().\r | |
786 | If EndBit is less than StartBit, then ASSERT().\r | |
787 | \r | |
788 | @param Address PCI configuration register to read.\r | |
789 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
790 | Range 0..31.\r | |
791 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
792 | Range 0..31.\r | |
793 | \r | |
794 | @return The value of the bit field read from the PCI configuration register.\r | |
795 | \r | |
796 | **/\r | |
797 | UINT32\r | |
798 | EFIAPI\r | |
799 | PciBitFieldRead32 (\r | |
800 | IN UINTN Address,\r | |
801 | IN UINTN StartBit,\r | |
802 | IN UINTN EndBit\r | |
803 | );\r | |
804 | \r | |
805 | /**\r | |
806 | Writes a bit field to a PCI configuration register.\r | |
807 | \r | |
808 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
809 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
810 | destination PCI configuration register are preserved. The new value of the\r | |
811 | 32-bit register is returned.\r | |
812 | \r | |
813 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
814 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
815 | If StartBit is greater than 31, then ASSERT().\r | |
816 | If EndBit is greater than 31, then ASSERT().\r | |
817 | If EndBit is less than StartBit, then ASSERT().\r | |
818 | \r | |
819 | @param Address PCI configuration register to write.\r | |
820 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
821 | Range 0..31.\r | |
822 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
823 | Range 0..31.\r | |
824 | @param Value New value of the bit field.\r | |
825 | \r | |
826 | @return The value written back to the PCI configuration register.\r | |
827 | \r | |
828 | **/\r | |
829 | UINT32\r | |
830 | EFIAPI\r | |
831 | PciBitFieldWrite32 (\r | |
832 | IN UINTN Address,\r | |
833 | IN UINTN StartBit,\r | |
834 | IN UINTN EndBit,\r | |
835 | IN UINT32 Value\r | |
836 | );\r | |
837 | \r | |
838 | /**\r | |
839 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
840 | writes the result back to the bit field in the 32-bit port.\r | |
841 | \r | |
842 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
843 | bitwise inclusive OR between the read result and the value specified by\r | |
844 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
845 | specified by Address. The value written to the PCI configuration register is\r | |
846 | returned. This function must guarantee that all PCI read and write operations\r | |
847 | are serialized. Extra left bits in OrData are stripped.\r | |
848 | \r | |
849 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
850 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
851 | If StartBit is greater than 31, then ASSERT().\r | |
852 | If EndBit is greater than 31, then ASSERT().\r | |
853 | If EndBit is less than StartBit, then ASSERT().\r | |
854 | \r | |
855 | @param Address PCI configuration register to write.\r | |
856 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
857 | Range 0..31.\r | |
858 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
859 | Range 0..31.\r | |
860 | @param OrData The value to OR with the PCI configuration register.\r | |
861 | \r | |
862 | @return The value written back to the PCI configuration register.\r | |
863 | \r | |
864 | **/\r | |
865 | UINT32\r | |
866 | EFIAPI\r | |
867 | PciBitFieldOr32 (\r | |
868 | IN UINTN Address,\r | |
869 | IN UINTN StartBit,\r | |
870 | IN UINTN EndBit,\r | |
871 | IN UINT32 OrData\r | |
872 | );\r | |
873 | \r | |
874 | /**\r | |
875 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
876 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
877 | \r | |
878 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
879 | bitwise AND between the read result and the value specified by AndData, and\r | |
880 | writes the result to the 32-bit PCI configuration register specified by\r | |
881 | Address. The value written to the PCI configuration register is returned.\r | |
882 | This function must guarantee that all PCI read and write operations are\r | |
883 | serialized. Extra left bits in AndData are stripped.\r | |
884 | \r | |
885 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
886 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
887 | If StartBit is greater than 31, then ASSERT().\r | |
888 | If EndBit is greater than 31, then ASSERT().\r | |
889 | If EndBit is less than StartBit, then ASSERT().\r | |
890 | \r | |
891 | @param Address PCI configuration register to write.\r | |
892 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
893 | Range 0..31.\r | |
894 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
895 | Range 0..31.\r | |
896 | @param AndData The value to AND with the PCI configuration register.\r | |
897 | \r | |
898 | @return The value written back to the PCI configuration register.\r | |
899 | \r | |
900 | **/\r | |
901 | UINT32\r | |
902 | EFIAPI\r | |
903 | PciBitFieldAnd32 (\r | |
904 | IN UINTN Address,\r | |
905 | IN UINTN StartBit,\r | |
906 | IN UINTN EndBit,\r | |
907 | IN UINT32 AndData\r | |
908 | );\r | |
909 | \r | |
910 | /**\r | |
911 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
912 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
913 | 32-bit port.\r | |
914 | \r | |
915 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
916 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
917 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
918 | configuration register specified by Address. The value written to the PCI\r | |
919 | configuration register is returned. This function must guarantee that all PCI\r | |
920 | read and write operations are serialized. Extra left bits in both AndData and\r | |
921 | OrData are stripped.\r | |
922 | \r | |
923 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
924 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
925 | If StartBit is greater than 31, then ASSERT().\r | |
926 | If EndBit is greater than 31, then ASSERT().\r | |
927 | If EndBit is less than StartBit, then ASSERT().\r | |
928 | \r | |
929 | @param Address PCI configuration register to write.\r | |
930 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
931 | Range 0..31.\r | |
932 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
933 | Range 0..31.\r | |
934 | @param AndData The value to AND with the PCI configuration register.\r | |
935 | @param OrData The value to OR with the result of the AND operation.\r | |
936 | \r | |
937 | @return The value written back to the PCI configuration register.\r | |
938 | \r | |
939 | **/\r | |
940 | UINT32\r | |
941 | EFIAPI\r | |
942 | PciBitFieldAndThenOr32 (\r | |
943 | IN UINTN Address,\r | |
944 | IN UINTN StartBit,\r | |
945 | IN UINTN EndBit,\r | |
946 | IN UINT32 AndData,\r | |
947 | IN UINT32 OrData\r | |
948 | );\r | |
949 | \r | |
950 | /**\r | |
951 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
952 | \r | |
953 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
954 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
955 | configuration registers from a single PCI function to be read. Size is\r | |
956 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
957 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
958 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
959 | end of the range.\r | |
960 | \r | |
961 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
962 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
963 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
964 | \r | |
965 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
966 | Function and Register.\r | |
967 | @param Size Size in bytes of the transfer.\r | |
968 | @param Buffer Pointer to a buffer receiving the data read.\r | |
969 | \r | |
970 | @return Size\r | |
971 | \r | |
972 | **/\r | |
973 | UINTN\r | |
974 | EFIAPI\r | |
975 | PciReadBuffer (\r | |
976 | IN UINTN StartAddress,\r | |
977 | IN UINTN Size,\r | |
978 | OUT VOID *Buffer\r | |
979 | );\r | |
980 | \r | |
981 | /**\r | |
982 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
983 | configuration space.\r | |
984 | \r | |
985 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
986 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
987 | configuration registers from a single PCI function to be written. Size is\r | |
988 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
989 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
990 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
991 | and the end of the range.\r | |
992 | \r | |
993 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
994 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
995 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
996 | \r | |
997 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
998 | Function and Register.\r | |
999 | @param Size Size in bytes of the transfer.\r | |
1000 | @param Buffer Pointer to a buffer containing the data to write.\r | |
1001 | \r | |
1002 | @return Size\r | |
1003 | \r | |
1004 | **/\r | |
1005 | UINTN\r | |
1006 | EFIAPI\r | |
1007 | PciWriteBuffer (\r | |
1008 | IN UINTN StartAddress,\r | |
1009 | IN UINTN Size,\r | |
1010 | IN VOID *Buffer\r | |
1011 | );\r | |
1012 | \r | |
1013 | #endif\r |