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1 | /** @file\r | |
2 | Contains root level name space objects for the platform\r | |
3 | \r | |
4 | Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>\r | |
5 | This program and the accompanying materials are\r | |
6 | licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | DefinitionBlock ("Dsdt.aml", "DSDT", 1, "INTEL ", "OVMF ", 4) {\r | |
16 | //\r | |
17 | // System Sleep States\r | |
18 | //\r | |
19 | // We build S3 and S4 with GetSuspendStates() in\r | |
20 | // "OvmfPkg/AcpiPlatformDxe/Qemu.c".\r | |
21 | //\r | |
22 | Name (\_S0, Package () {5, 0, 0, 0}) // Working\r | |
23 | Name (\_S5, Package () {0, 0, 0, 0}) // Soft Off\r | |
24 | \r | |
25 | //\r | |
26 | // System Bus\r | |
27 | //\r | |
28 | Scope (\_SB) {\r | |
29 | //\r | |
30 | // PCI Root Bridge\r | |
31 | //\r | |
32 | Device (PCI0) {\r | |
33 | Name (_HID, EISAID ("PNP0A03"))\r | |
34 | Name (_ADR, 0x00000000)\r | |
35 | Name (_BBN, 0x00)\r | |
36 | Name (_UID, 0x00)\r | |
37 | \r | |
38 | //\r | |
39 | // BUS, I/O, and MMIO resources\r | |
40 | //\r | |
41 | Name (CRES, ResourceTemplate () {\r | |
42 | WORDBusNumber ( // Bus number resource (0); the bridge produces bus numbers for its subsequent buses\r | |
43 | ResourceProducer, // bit 0 of general flags is 1\r | |
44 | MinFixed, // Range is fixed\r | |
45 | MaxFixed, // Range is fixed\r | |
46 | PosDecode, // PosDecode\r | |
47 | 0x0000, // Granularity\r | |
48 | 0x0000, // Min\r | |
49 | 0x00FF, // Max\r | |
50 | 0x0000, // Translation\r | |
51 | 0x0100 // Range Length = Max-Min+1\r | |
52 | )\r | |
53 | \r | |
54 | IO (Decode16, 0xCF8, 0xCF8, 0x01, 0x08) //Consumed resource (0xCF8-0xCFF)\r | |
55 | \r | |
56 | WORDIO ( // Consumed-and-produced resource (all I/O below CF8)\r | |
57 | ResourceProducer, // bit 0 of general flags is 0\r | |
58 | MinFixed, // Range is fixed\r | |
59 | MaxFixed, // Range is fixed\r | |
60 | PosDecode,\r | |
61 | EntireRange,\r | |
62 | 0x0000, // Granularity\r | |
63 | 0x0000, // Min\r | |
64 | 0x0CF7, // Max\r | |
65 | 0x0000, // Translation\r | |
66 | 0x0CF8 // Range Length\r | |
67 | )\r | |
68 | \r | |
69 | WORDIO ( // Consumed-and-produced resource (all I/O above CFF)\r | |
70 | ResourceProducer, // bit 0 of general flags is 0\r | |
71 | MinFixed, // Range is fixed\r | |
72 | MaxFixed, // Range is fixed\r | |
73 | PosDecode,\r | |
74 | EntireRange,\r | |
75 | 0x0000, // Granularity\r | |
76 | 0x0D00, // Min\r | |
77 | 0xFFFF, // Max\r | |
78 | 0x0000, // Translation\r | |
79 | 0xF300 // Range Length\r | |
80 | )\r | |
81 | \r | |
82 | DWORDMEMORY ( // Descriptor for legacy VGA video RAM\r | |
83 | ResourceProducer, // bit 0 of general flags is 0\r | |
84 | PosDecode,\r | |
85 | MinFixed, // Range is fixed\r | |
86 | MaxFixed, // Range is Fixed\r | |
87 | Cacheable,\r | |
88 | ReadWrite,\r | |
89 | 0x00000000, // Granularity\r | |
90 | 0x000A0000, // Min\r | |
91 | 0x000BFFFF, // Max\r | |
92 | 0x00000000, // Translation\r | |
93 | 0x00020000 // Range Length\r | |
94 | )\r | |
95 | \r | |
96 | DWORDMEMORY ( // Descriptor for 32-bit MMIO\r | |
97 | ResourceProducer, // bit 0 of general flags is 0\r | |
98 | PosDecode,\r | |
99 | MinFixed, // Range is fixed\r | |
100 | MaxFixed, // Range is Fixed\r | |
101 | NonCacheable,\r | |
102 | ReadWrite,\r | |
103 | 0x00000000, // Granularity\r | |
104 | 0xF8000000, // Min\r | |
105 | 0xFFFBFFFF, // Max\r | |
106 | 0x00000000, // Translation\r | |
107 | 0x07FC0000, // Range Length\r | |
108 | , // ResourceSourceIndex\r | |
109 | , // ResourceSource\r | |
110 | PW32 // DescriptorName\r | |
111 | )\r | |
112 | })\r | |
113 | \r | |
114 | Name (CR64, ResourceTemplate () {\r | |
115 | QWordMemory ( // Descriptor for 64-bit MMIO\r | |
116 | ResourceProducer, // bit 0 of general flags is 0\r | |
117 | PosDecode,\r | |
118 | MinFixed, // Range is fixed\r | |
119 | MaxFixed, // Range is Fixed\r | |
120 | Cacheable,\r | |
121 | ReadWrite,\r | |
122 | 0x00000000, // Granularity\r | |
123 | 0x8000000000, // Min\r | |
124 | 0xFFFFFFFFFF, // Max\r | |
125 | 0x00000000, // Translation\r | |
126 | 0x8000000000, // Range Length\r | |
127 | , // ResourceSourceIndex\r | |
128 | , // ResourceSource\r | |
129 | PW64 // DescriptorName\r | |
130 | )\r | |
131 | })\r | |
132 | \r | |
133 | Method (_CRS, 0, Serialized) {\r | |
134 | //\r | |
135 | // see the FIRMWARE_DATA structure in "OvmfPkg/AcpiPlatformDxe/Qemu.c"\r | |
136 | //\r | |
137 | External (FWDT, OpRegionObj)\r | |
138 | Field(FWDT, QWordAcc, NoLock, Preserve) {\r | |
139 | P0S, 64, // PciWindow32.Base\r | |
140 | P0E, 64, // PciWindow32.End\r | |
141 | P0L, 64, // PciWindow32.Length\r | |
142 | P1S, 64, // PciWindow64.Base\r | |
143 | P1E, 64, // PciWindow64.End\r | |
144 | P1L, 64 // PciWindow64.Length\r | |
145 | }\r | |
146 | Field(FWDT, DWordAcc, NoLock, Preserve) {\r | |
147 | P0SL, 32, // PciWindow32.Base, low 32 bits\r | |
148 | P0SH, 32, // PciWindow32.Base, high 32 bits\r | |
149 | P0EL, 32, // PciWindow32.End, low 32 bits\r | |
150 | P0EH, 32, // PciWindow32.End, high 32 bits\r | |
151 | P0LL, 32, // PciWindow32.Length, low 32 bits\r | |
152 | P0LH, 32, // PciWindow32.Length, high 32 bits\r | |
153 | P1SL, 32, // PciWindow64.Base, low 32 bits\r | |
154 | P1SH, 32, // PciWindow64.Base, high 32 bits\r | |
155 | P1EL, 32, // PciWindow64.End, low 32 bits\r | |
156 | P1EH, 32, // PciWindow64.End, high 32 bits\r | |
157 | P1LL, 32, // PciWindow64.Length, low 32 bits\r | |
158 | P1LH, 32 // PciWindow64.Length, high 32 bits\r | |
159 | }\r | |
160 | \r | |
161 | //\r | |
162 | // fixup 32-bit PCI IO window\r | |
163 | //\r | |
164 | CreateDWordField (CRES, \_SB.PCI0.PW32._MIN, PS32)\r | |
165 | CreateDWordField (CRES, \_SB.PCI0.PW32._MAX, PE32)\r | |
166 | CreateDWordField (CRES, \_SB.PCI0.PW32._LEN, PL32)\r | |
167 | Store (P0SL, PS32)\r | |
168 | Store (P0EL, PE32)\r | |
169 | Store (P0LL, PL32)\r | |
170 | \r | |
171 | If (LAnd (LEqual (P1SL, 0x00), LEqual (P1SH, 0x00))) {\r | |
172 | Return (CRES)\r | |
173 | } Else {\r | |
174 | //\r | |
175 | // fixup 64-bit PCI IO window\r | |
176 | //\r | |
177 | CreateQWordField (CR64, \_SB.PCI0.PW64._MIN, PS64)\r | |
178 | CreateQWordField (CR64, \_SB.PCI0.PW64._MAX, PE64)\r | |
179 | CreateQWordField (CR64, \_SB.PCI0.PW64._LEN, PL64)\r | |
180 | Store (P1S, PS64)\r | |
181 | Store (P1E, PE64)\r | |
182 | Store (P1L, PL64)\r | |
183 | \r | |
184 | //\r | |
185 | // add window and return result\r | |
186 | //\r | |
187 | ConcatenateResTemplate (CRES, CR64, Local0)\r | |
188 | Return (Local0)\r | |
189 | }\r | |
190 | }\r | |
191 | \r | |
192 | //\r | |
193 | // PCI Interrupt Routing Table - PIC Mode Only\r | |
194 | //\r | |
195 | Method (_PRT, 0, NotSerialized) {\r | |
196 | Return (\r | |
197 | Package () {\r | |
198 | //\r | |
199 | // Bus 0; Devices 0 to 15\r | |
200 | //\r | |
201 | Package () {0x0000FFFF, 0x00, \_SB.PCI0.LPC.LNKD, 0x00},\r | |
202 | Package () {0x0000FFFF, 0x01, \_SB.PCI0.LPC.LNKA, 0x00},\r | |
203 | Package () {0x0000FFFF, 0x02, \_SB.PCI0.LPC.LNKB, 0x00},\r | |
204 | Package () {0x0000FFFF, 0x03, \_SB.PCI0.LPC.LNKC, 0x00},\r | |
205 | \r | |
206 | //\r | |
207 | // Bus 0, Device 1, Pin 0 (INTA) is special; it corresponds to the\r | |
208 | // internally generated SCI (System Control Interrupt), which is\r | |
209 | // always routed to GSI 9. By setting the third (= Source) field to\r | |
210 | // zero, we could use the fourth (= Source Index) field to hardwire\r | |
211 | // the pin to GSI 9 directly.\r | |
212 | //\r | |
213 | // That way however, in accordance with the ACPI spec's description\r | |
214 | // of SCI, the interrupt would be treated as "active low,\r | |
215 | // shareable, level", and that doesn't match qemu.\r | |
216 | //\r | |
217 | // In QemuInstallAcpiMadtTable() [OvmfPkg/AcpiPlatformDxe/Qemu.c]\r | |
218 | // we install an Interrupt Override Structure for the identity\r | |
219 | // mapped IRQ#9 / GSI 9 (the corresponding bit being set in\r | |
220 | // Pcd8259LegacyModeEdgeLevel), which describes the correct\r | |
221 | // polarity (active high). As a consequence, some OS'en (eg. Linux)\r | |
222 | // override the default (active low) polarity originating from the\r | |
223 | // _PRT; others (eg. FreeBSD) don't. Therefore we need a separate\r | |
224 | // link device just to specify a polarity that matches the MADT.\r | |
225 | //\r | |
226 | Package () {0x0001FFFF, 0x00, \_SB.PCI0.LPC.LNKS, 0x00},\r | |
227 | \r | |
228 | Package () {0x0001FFFF, 0x01, \_SB.PCI0.LPC.LNKB, 0x00},\r | |
229 | Package () {0x0001FFFF, 0x02, \_SB.PCI0.LPC.LNKC, 0x00},\r | |
230 | Package () {0x0001FFFF, 0x03, \_SB.PCI0.LPC.LNKD, 0x00},\r | |
231 | \r | |
232 | Package () {0x0002FFFF, 0x00, \_SB.PCI0.LPC.LNKB, 0x00},\r | |
233 | Package () {0x0002FFFF, 0x01, \_SB.PCI0.LPC.LNKC, 0x00},\r | |
234 | Package () {0x0002FFFF, 0x02, \_SB.PCI0.LPC.LNKD, 0x00},\r | |
235 | Package () {0x0002FFFF, 0x03, \_SB.PCI0.LPC.LNKA, 0x00},\r | |
236 | \r | |
237 | Package () {0x0003FFFF, 0x00, \_SB.PCI0.LPC.LNKC, 0x00},\r | |
238 | Package () {0x0003FFFF, 0x01, \_SB.PCI0.LPC.LNKD, 0x00},\r | |
239 | Package () {0x0003FFFF, 0x02, \_SB.PCI0.LPC.LNKA, 0x00},\r | |
240 | Package () {0x0003FFFF, 0x03, \_SB.PCI0.LPC.LNKB, 0x00},\r | |
241 | \r | |
242 | Package () {0x0004FFFF, 0x00, \_SB.PCI0.LPC.LNKD, 0x00},\r | |
243 | Package () {0x0004FFFF, 0x01, \_SB.PCI0.LPC.LNKA, 0x00},\r | |
244 | Package () {0x0004FFFF, 0x02, \_SB.PCI0.LPC.LNKB, 0x00},\r | |
245 | Package () {0x0004FFFF, 0x03, \_SB.PCI0.LPC.LNKC, 0x00},\r | |
246 | \r | |
247 | Package () {0x0005FFFF, 0x00, \_SB.PCI0.LPC.LNKA, 0x00},\r | |
248 | Package () {0x0005FFFF, 0x01, \_SB.PCI0.LPC.LNKB, 0x00},\r | |
249 | Package () {0x0005FFFF, 0x02, \_SB.PCI0.LPC.LNKC, 0x00},\r | |
250 | Package () {0x0005FFFF, 0x03, \_SB.PCI0.LPC.LNKD, 0x00},\r | |
251 | \r | |
252 | Package () {0x0006FFFF, 0x00, \_SB.PCI0.LPC.LNKB, 0x00},\r | |
253 | Package () {0x0006FFFF, 0x01, \_SB.PCI0.LPC.LNKC, 0x00},\r | |
254 | Package () {0x0006FFFF, 0x02, \_SB.PCI0.LPC.LNKD, 0x00},\r | |
255 | Package () {0x0006FFFF, 0x03, \_SB.PCI0.LPC.LNKA, 0x00},\r | |
256 | \r | |
257 | Package () {0x0007FFFF, 0x00, \_SB.PCI0.LPC.LNKC, 0x00},\r | |
258 | Package () {0x0007FFFF, 0x01, \_SB.PCI0.LPC.LNKD, 0x00},\r | |
259 | Package () {0x0007FFFF, 0x02, \_SB.PCI0.LPC.LNKA, 0x00},\r | |
260 | Package () {0x0007FFFF, 0x03, \_SB.PCI0.LPC.LNKB, 0x00},\r | |
261 | \r | |
262 | Package () {0x0008FFFF, 0x00, \_SB.PCI0.LPC.LNKD, 0x00},\r | |
263 | Package () {0x0008FFFF, 0x01, \_SB.PCI0.LPC.LNKA, 0x00},\r | |
264 | Package () {0x0008FFFF, 0x02, \_SB.PCI0.LPC.LNKB, 0x00},\r | |
265 | Package () {0x0008FFFF, 0x03, \_SB.PCI0.LPC.LNKC, 0x00},\r | |
266 | \r | |
267 | Package () {0x0009FFFF, 0x00, \_SB.PCI0.LPC.LNKA, 0x00},\r | |
268 | Package () {0x0009FFFF, 0x01, \_SB.PCI0.LPC.LNKB, 0x00},\r | |
269 | Package () {0x0009FFFF, 0x02, \_SB.PCI0.LPC.LNKC, 0x00},\r | |
270 | Package () {0x0009FFFF, 0x03, \_SB.PCI0.LPC.LNKD, 0x00},\r | |
271 | \r | |
272 | Package () {0x000AFFFF, 0x00, \_SB.PCI0.LPC.LNKB, 0x00},\r | |
273 | Package () {0x000AFFFF, 0x01, \_SB.PCI0.LPC.LNKC, 0x00},\r | |
274 | Package () {0x000AFFFF, 0x02, \_SB.PCI0.LPC.LNKD, 0x00},\r | |
275 | Package () {0x000AFFFF, 0x03, \_SB.PCI0.LPC.LNKA, 0x00},\r | |
276 | \r | |
277 | Package () {0x000BFFFF, 0x00, \_SB.PCI0.LPC.LNKC, 0x00},\r | |
278 | Package () {0x000BFFFF, 0x01, \_SB.PCI0.LPC.LNKD, 0x00},\r | |
279 | Package () {0x000BFFFF, 0x02, \_SB.PCI0.LPC.LNKA, 0x00},\r | |
280 | Package () {0x000BFFFF, 0x03, \_SB.PCI0.LPC.LNKB, 0x00},\r | |
281 | \r | |
282 | Package () {0x000CFFFF, 0x00, \_SB.PCI0.LPC.LNKD, 0x00},\r | |
283 | Package () {0x000CFFFF, 0x01, \_SB.PCI0.LPC.LNKA, 0x00},\r | |
284 | Package () {0x000CFFFF, 0x02, \_SB.PCI0.LPC.LNKB, 0x00},\r | |
285 | Package () {0x000CFFFF, 0x03, \_SB.PCI0.LPC.LNKC, 0x00},\r | |
286 | \r | |
287 | Package () {0x000DFFFF, 0x00, \_SB.PCI0.LPC.LNKA, 0x00},\r | |
288 | Package () {0x000DFFFF, 0x01, \_SB.PCI0.LPC.LNKB, 0x00},\r | |
289 | Package () {0x000DFFFF, 0x02, \_SB.PCI0.LPC.LNKC, 0x00},\r | |
290 | Package () {0x000DFFFF, 0x03, \_SB.PCI0.LPC.LNKD, 0x00},\r | |
291 | \r | |
292 | Package () {0x000EFFFF, 0x00, \_SB.PCI0.LPC.LNKB, 0x00},\r | |
293 | Package () {0x000EFFFF, 0x01, \_SB.PCI0.LPC.LNKC, 0x00},\r | |
294 | Package () {0x000EFFFF, 0x02, \_SB.PCI0.LPC.LNKD, 0x00},\r | |
295 | Package () {0x000EFFFF, 0x03, \_SB.PCI0.LPC.LNKA, 0x00},\r | |
296 | \r | |
297 | Package () {0x000FFFFF, 0x00, \_SB.PCI0.LPC.LNKC, 0x00},\r | |
298 | Package () {0x000FFFFF, 0x01, \_SB.PCI0.LPC.LNKD, 0x00},\r | |
299 | Package () {0x000FFFFF, 0x02, \_SB.PCI0.LPC.LNKA, 0x00},\r | |
300 | Package () {0x000FFFFF, 0x03, \_SB.PCI0.LPC.LNKB, 0x00}\r | |
301 | }\r | |
302 | )\r | |
303 | }\r | |
304 | \r | |
305 | //\r | |
306 | // PCI to ISA Bridge (Bus 0, Device 1, Function 0)\r | |
307 | // "Low Pin Count"\r | |
308 | //\r | |
309 | Device (LPC) {\r | |
310 | Name (_ADR, 0x00010000)\r | |
311 | \r | |
312 | //\r | |
313 | // The SCI cannot be rerouted or disabled with PIRQRC[A:D]; we only\r | |
314 | // need this link device in order to specify the polarity.\r | |
315 | //\r | |
316 | Device (LNKS) {\r | |
317 | Name (_HID, EISAID("PNP0C0F"))\r | |
318 | Name (_UID, 0)\r | |
319 | \r | |
320 | Name (_STA, 0xB) // 0x1: device present\r | |
321 | // 0x2: enabled and decoding resources\r | |
322 | // 0x8: functioning properly\r | |
323 | \r | |
324 | Method (_SRS, 1, NotSerialized) { /* no-op */ }\r | |
325 | Method (_DIS, 0, NotSerialized) { /* no-op */ }\r | |
326 | \r | |
327 | Name (_PRS, ResourceTemplate () {\r | |
328 | Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) { 9 }\r | |
329 | //\r | |
330 | // list of IRQs occupied thus far: 9\r | |
331 | //\r | |
332 | })\r | |
333 | Method (_CRS, 0, NotSerialized) { Return (_PRS) }\r | |
334 | }\r | |
335 | \r | |
336 | //\r | |
337 | // PCI Interrupt Routing Configuration Registers, PIRQRC[A:D]\r | |
338 | //\r | |
339 | OperationRegion (PRR0, PCI_Config, 0x60, 0x04)\r | |
340 | Field (PRR0, ANYACC, NOLOCK, PRESERVE) {\r | |
341 | PIRA, 8,\r | |
342 | PIRB, 8,\r | |
343 | PIRC, 8,\r | |
344 | PIRD, 8\r | |
345 | }\r | |
346 | \r | |
347 | //\r | |
348 | // _STA method for LNKA, LNKB, LNKC, LNKD\r | |
349 | // Arg0[in]: value of PIRA / PIRB / PIRC / PIRD\r | |
350 | //\r | |
351 | Method (PSTA, 1, NotSerialized) {\r | |
352 | If (And (Arg0, 0x80)) { // disable-bit set?\r | |
353 | Return (0x9) // "device present" | "functioning properly"\r | |
354 | } Else {\r | |
355 | Return (0xB) // same | "enabled and decoding resources"\r | |
356 | }\r | |
357 | }\r | |
358 | \r | |
359 | //\r | |
360 | // _CRS method for LNKA, LNKB, LNKC, LNKD\r | |
361 | // Arg0[in]: value of PIRA / PIRB / PIRC / PIRD\r | |
362 | //\r | |
363 | Method (PCRS, 1, Serialized) {\r | |
364 | //\r | |
365 | // create temporary buffer with an Extended Interrupt Descriptor\r | |
366 | // whose single vector defaults to zero\r | |
367 | //\r | |
368 | Name (BUF0, ResourceTemplate () {\r | |
369 | Interrupt (ResourceConsumer, Level, ActiveHigh, Shared){0}\r | |
370 | }\r | |
371 | )\r | |
372 | \r | |
373 | //\r | |
374 | // define reference to first interrupt vector in buffer\r | |
375 | //\r | |
376 | CreateDWordField (BUF0, 0x05, IRQW)\r | |
377 | \r | |
378 | //\r | |
379 | // If the disable-bit is clear, overwrite the default zero vector\r | |
380 | // with the value in Arg0 (ie. PIRQRC[A:D]). Reserved bits are read\r | |
381 | // as 0.\r | |
382 | //\r | |
383 | If (LNot (And (Arg0, 0x80))) {\r | |
384 | Store (Arg0, IRQW)\r | |
385 | }\r | |
386 | Return (BUF0)\r | |
387 | }\r | |
388 | \r | |
389 | //\r | |
390 | // _PRS resource for LNKA, LNKB, LNKC, LNKD\r | |
391 | //\r | |
392 | Name (PPRS, ResourceTemplate () {\r | |
393 | Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) {5, 10, 11}\r | |
394 | //\r | |
395 | // list of IRQs occupied thus far: 9, 5, 10, 11\r | |
396 | //\r | |
397 | })\r | |
398 | \r | |
399 | //\r | |
400 | // PCI IRQ Link A\r | |
401 | //\r | |
402 | Device (LNKA) {\r | |
403 | Name (_HID, EISAID("PNP0C0F"))\r | |
404 | Name (_UID, 1)\r | |
405 | \r | |
406 | Method (_STA, 0, NotSerialized) { Return (PSTA (PIRA)) }\r | |
407 | Method (_DIS, 0, NotSerialized) {\r | |
408 | Or (PIRA, 0x80, PIRA) // set disable-bit\r | |
409 | }\r | |
410 | Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRA)) }\r | |
411 | Method (_PRS, 0, NotSerialized) { Return (PPRS) }\r | |
412 | Method (_SRS, 1, NotSerialized) {\r | |
413 | CreateDWordField (Arg0, 0x05, IRQW)\r | |
414 | Store (IRQW, PIRA)\r | |
415 | }\r | |
416 | }\r | |
417 | \r | |
418 | //\r | |
419 | // PCI IRQ Link B\r | |
420 | //\r | |
421 | Device (LNKB) {\r | |
422 | Name (_HID, EISAID("PNP0C0F"))\r | |
423 | Name (_UID, 2)\r | |
424 | \r | |
425 | Method (_STA, 0, NotSerialized) { Return (PSTA (PIRB)) }\r | |
426 | Method (_DIS, 0, NotSerialized) {\r | |
427 | Or (PIRB, 0x80, PIRB) // set disable-bit\r | |
428 | }\r | |
429 | Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRB)) }\r | |
430 | Method (_PRS, 0, NotSerialized) { Return (PPRS) }\r | |
431 | Method (_SRS, 1, NotSerialized) {\r | |
432 | CreateDWordField (Arg0, 0x05, IRQW)\r | |
433 | Store (IRQW, PIRB)\r | |
434 | }\r | |
435 | }\r | |
436 | \r | |
437 | //\r | |
438 | // PCI IRQ Link C\r | |
439 | //\r | |
440 | Device (LNKC) {\r | |
441 | Name (_HID, EISAID("PNP0C0F"))\r | |
442 | Name (_UID, 3)\r | |
443 | \r | |
444 | Method (_STA, 0, NotSerialized) { Return (PSTA (PIRC)) }\r | |
445 | Method (_DIS, 0, NotSerialized) {\r | |
446 | Or (PIRC, 0x80, PIRC) // set disable-bit\r | |
447 | }\r | |
448 | Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRC)) }\r | |
449 | Method (_PRS, 0, NotSerialized) { Return (PPRS) }\r | |
450 | Method (_SRS, 1, NotSerialized) {\r | |
451 | CreateDWordField (Arg0, 0x05, IRQW)\r | |
452 | Store (IRQW, PIRC)\r | |
453 | }\r | |
454 | }\r | |
455 | \r | |
456 | //\r | |
457 | // PCI IRQ Link D\r | |
458 | //\r | |
459 | Device (LNKD) {\r | |
460 | Name (_HID, EISAID("PNP0C0F"))\r | |
461 | Name (_UID, 4)\r | |
462 | \r | |
463 | Method (_STA, 0, NotSerialized) { Return (PSTA (PIRD)) }\r | |
464 | Method (_DIS, 0, NotSerialized) {\r | |
465 | Or (PIRD, 0x80, PIRD) // set disable-bit\r | |
466 | }\r | |
467 | Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRD)) }\r | |
468 | Method (_PRS, 0, NotSerialized) { Return (PPRS) }\r | |
469 | Method (_SRS, 1, NotSerialized) {\r | |
470 | CreateDWordField (Arg0, 0x05, IRQW)\r | |
471 | Store (IRQW, PIRD)\r | |
472 | }\r | |
473 | }\r | |
474 | \r | |
475 | //\r | |
476 | // Programmable Interrupt Controller (PIC)\r | |
477 | //\r | |
478 | Device(PIC) {\r | |
479 | Name (_HID, EISAID ("PNP0000"))\r | |
480 | Name (_CRS, ResourceTemplate () {\r | |
481 | IO (Decode16, 0x020, 0x020, 0x00, 0x02)\r | |
482 | IO (Decode16, 0x0A0, 0x0A0, 0x00, 0x02)\r | |
483 | IO (Decode16, 0x4D0, 0x4D0, 0x00, 0x02)\r | |
484 | IRQNoFlags () {2}\r | |
485 | //\r | |
486 | // list of IRQs occupied thus far: 9, 5, 10, 11, 2\r | |
487 | //\r | |
488 | })\r | |
489 | }\r | |
490 | \r | |
491 | //\r | |
492 | // ISA DMA\r | |
493 | //\r | |
494 | Device (DMAC) {\r | |
495 | Name (_HID, EISAID ("PNP0200"))\r | |
496 | Name (_CRS, ResourceTemplate () {\r | |
497 | IO (Decode16, 0x00, 0x00, 0, 0x10)\r | |
498 | IO (Decode16, 0x81, 0x81, 0, 0x03)\r | |
499 | IO (Decode16, 0x87, 0x87, 0, 0x01)\r | |
500 | IO (Decode16, 0x89, 0x89, 0, 0x03)\r | |
501 | IO (Decode16, 0x8f, 0x8f, 0, 0x01)\r | |
502 | IO (Decode16, 0xc0, 0xc0, 0, 0x20)\r | |
503 | DMA (Compatibility, NotBusMaster, Transfer8) {4}\r | |
504 | })\r | |
505 | }\r | |
506 | \r | |
507 | //\r | |
508 | // 8254 Timer\r | |
509 | //\r | |
510 | Device(TMR) {\r | |
511 | Name(_HID,EISAID("PNP0100"))\r | |
512 | Name(_CRS, ResourceTemplate () {\r | |
513 | IO (Decode16, 0x40, 0x40, 0x00, 0x04)\r | |
514 | IRQNoFlags () {0}\r | |
515 | //\r | |
516 | // list of IRQs occupied thus far: 9, 5, 10, 11, 2, 0\r | |
517 | //\r | |
518 | })\r | |
519 | }\r | |
520 | \r | |
521 | //\r | |
522 | // Real Time Clock\r | |
523 | //\r | |
524 | Device (RTC) {\r | |
525 | Name (_HID, EISAID ("PNP0B00"))\r | |
526 | Name (_CRS, ResourceTemplate () {\r | |
527 | IO (Decode16, 0x70, 0x70, 0x00, 0x02)\r | |
528 | IRQNoFlags () {8}\r | |
529 | //\r | |
530 | // list of IRQs occupied thus far: 9, 5, 10, 11, 2, 0, 8\r | |
531 | //\r | |
532 | })\r | |
533 | }\r | |
534 | \r | |
535 | //\r | |
536 | // PCAT Speaker\r | |
537 | //\r | |
538 | Device(SPKR) {\r | |
539 | Name (_HID, EISAID("PNP0800"))\r | |
540 | Name (_CRS, ResourceTemplate () {\r | |
541 | IO (Decode16, 0x61, 0x61, 0x01, 0x01)\r | |
542 | })\r | |
543 | }\r | |
544 | \r | |
545 | //\r | |
546 | // Floating Point Coprocessor\r | |
547 | //\r | |
548 | Device(FPU) {\r | |
549 | Name (_HID, EISAID("PNP0C04"))\r | |
550 | Name (_CRS, ResourceTemplate () {\r | |
551 | IO (Decode16, 0xF0, 0xF0, 0x00, 0x10)\r | |
552 | IRQNoFlags () {13}\r | |
553 | //\r | |
554 | // list of IRQs occupied thus far: 9, 5, 10, 11, 2, 0, 8, 13\r | |
555 | //\r | |
556 | })\r | |
557 | }\r | |
558 | \r | |
559 | //\r | |
560 | // Generic motherboard devices and pieces that don't fit anywhere else\r | |
561 | //\r | |
562 | Device(XTRA) {\r | |
563 | Name (_HID, EISAID ("PNP0C02"))\r | |
564 | Name (_UID, 0x01)\r | |
565 | Name (_CRS, ResourceTemplate () {\r | |
566 | IO (Decode16, 0x010, 0x010, 0x00, 0x10)\r | |
567 | IO (Decode16, 0x022, 0x022, 0x00, 0x1E)\r | |
568 | IO (Decode16, 0x044, 0x044, 0x00, 0x1C)\r | |
569 | IO (Decode16, 0x062, 0x062, 0x00, 0x02)\r | |
570 | IO (Decode16, 0x065, 0x065, 0x00, 0x0B)\r | |
571 | IO (Decode16, 0x072, 0x072, 0x00, 0x0E)\r | |
572 | IO (Decode16, 0x080, 0x080, 0x00, 0x01)\r | |
573 | IO (Decode16, 0x084, 0x084, 0x00, 0x03)\r | |
574 | IO (Decode16, 0x088, 0x088, 0x00, 0x01)\r | |
575 | IO (Decode16, 0x08c, 0x08c, 0x00, 0x03)\r | |
576 | IO (Decode16, 0x090, 0x090, 0x00, 0x10)\r | |
577 | IO (Decode16, 0x0A2, 0x0A2, 0x00, 0x1E)\r | |
578 | IO (Decode16, 0x0E0, 0x0E0, 0x00, 0x10)\r | |
579 | IO (Decode16, 0x1E0, 0x1E0, 0x00, 0x10)\r | |
580 | IO (Decode16, 0x160, 0x160, 0x00, 0x10)\r | |
581 | IO (Decode16, 0x278, 0x278, 0x00, 0x08)\r | |
582 | IO (Decode16, 0x370, 0x370, 0x00, 0x02)\r | |
583 | IO (Decode16, 0x378, 0x378, 0x00, 0x08)\r | |
584 | IO (Decode16, FixedPcdGet16 (PcdDebugIoPort), FixedPcdGet16 (PcdDebugIoPort), 0x00, 0x01)\r | |
585 | IO (Decode16, 0x440, 0x440, 0x00, 0x10)\r | |
586 | IO (Decode16, 0x678, 0x678, 0x00, 0x08)\r | |
587 | IO (Decode16, 0x778, 0x778, 0x00, 0x08)\r | |
588 | IO (Decode16, 0xafe0, 0xafe0, 0x00, 0x04) // QEMU GPE0 BLK\r | |
589 | IO (Decode16, 0xb000, 0xb000, 0x00, 0x40) // PMBLK1\r | |
590 | Memory32Fixed (ReadOnly, 0xFEC00000, 0x1000) // IO APIC\r | |
591 | Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000) // LAPIC\r | |
592 | })\r | |
593 | }\r | |
594 | \r | |
595 | //\r | |
596 | // PS/2 Keyboard and PC/AT Enhanced Keyboard 101/102\r | |
597 | //\r | |
598 | Device (PS2K) {\r | |
599 | Name (_HID, EISAID ("PNP0303"))\r | |
600 | Name (_CID, EISAID ("PNP030B"))\r | |
601 | Name(_CRS,ResourceTemplate() {\r | |
602 | IO (Decode16, 0x60, 0x60, 0x00, 0x01)\r | |
603 | IO (Decode16, 0x64, 0x64, 0x00, 0x01)\r | |
604 | IRQNoFlags () {1}\r | |
605 | //\r | |
606 | // list of IRQs occupied thus far: 9, 5, 10, 11, 2, 0, 8, 13, 1\r | |
607 | //\r | |
608 | })\r | |
609 | }\r | |
610 | \r | |
611 | //\r | |
612 | // PS/2 Mouse and Microsoft Mouse\r | |
613 | //\r | |
614 | Device (PS2M) { // PS/2 stype mouse port\r | |
615 | Name (_HID, EISAID ("PNP0F03"))\r | |
616 | Name (_CID, EISAID ("PNP0F13"))\r | |
617 | Name (_CRS, ResourceTemplate() {\r | |
618 | IRQNoFlags () {12}\r | |
619 | //\r | |
620 | // list of IRQs occupied thus far:\r | |
621 | // 9, 5, 10, 11, 2, 0, 8, 13, 1, 12\r | |
622 | //\r | |
623 | })\r | |
624 | }\r | |
625 | \r | |
626 | //\r | |
627 | // UART Serial Port - COM1\r | |
628 | //\r | |
629 | Device (UAR1) {\r | |
630 | Name (_HID, EISAID ("PNP0501"))\r | |
631 | Name (_DDN, "COM1")\r | |
632 | Name (_UID, 0x01)\r | |
633 | Name(_CRS,ResourceTemplate() {\r | |
634 | IO (Decode16, 0x3F8, 0x3F8, 0x01, 0x08)\r | |
635 | IRQ (Edge, ActiveHigh, Exclusive, ) {4}\r | |
636 | //\r | |
637 | // list of IRQs occupied thus far:\r | |
638 | // 9, 5, 10, 11, 2, 0, 8, 13, 1, 12, 4\r | |
639 | //\r | |
640 | })\r | |
641 | }\r | |
642 | \r | |
643 | //\r | |
644 | // UART Serial Port - COM2\r | |
645 | //\r | |
646 | Device (UAR2) {\r | |
647 | Name (_HID, EISAID ("PNP0501"))\r | |
648 | Name (_DDN, "COM2")\r | |
649 | Name (_UID, 0x02)\r | |
650 | Name(_CRS,ResourceTemplate() {\r | |
651 | IO (Decode16, 0x2F8, 0x2F8, 0x01, 0x08)\r | |
652 | IRQ (Edge, ActiveHigh, Exclusive, ) {3}\r | |
653 | //\r | |
654 | // list of IRQs occupied thus far:\r | |
655 | // 9, 5, 10, 11, 2, 0, 8, 13, 1, 12, 4, 3\r | |
656 | //\r | |
657 | })\r | |
658 | }\r | |
659 | \r | |
660 | //\r | |
661 | // Floppy Disk Controller\r | |
662 | //\r | |
663 | Device (FDC) {\r | |
664 | Name (_HID, EISAID ("PNP0700"))\r | |
665 | Name (_CRS,ResourceTemplate() {\r | |
666 | IO (Decode16, 0x3F0, 0x3F0, 0x01, 0x06)\r | |
667 | IO (Decode16, 0x3F7, 0x3F7, 0x01, 0x01)\r | |
668 | IRQNoFlags () {6}\r | |
669 | //\r | |
670 | // list of IRQs occupied thus far:\r | |
671 | // 9, 5, 10, 11, 2, 0, 8, 13, 1, 12, 4, 3, 6\r | |
672 | //\r | |
673 | DMA (Compatibility, NotBusMaster, Transfer8) {2}\r | |
674 | })\r | |
675 | }\r | |
676 | \r | |
677 | //\r | |
678 | // parallel port -- no DMA for now\r | |
679 | //\r | |
680 | Device (PAR1) {\r | |
681 | Name (_HID, EISAID ("PNP0400"))\r | |
682 | Name (_DDN, "LPT1")\r | |
683 | Name (_UID, 0x01)\r | |
684 | Name(_CRS, ResourceTemplate() {\r | |
685 | IO (Decode16, 0x0378, 0x0378, 0x00, 0x08)\r | |
686 | IRQNoFlags () {7}\r | |
687 | //\r | |
688 | // list of IRQs occupied thus far:\r | |
689 | // 9, 5, 10, 11, 2, 0, 8, 13, 1, 12, 4, 3, 6, 7\r | |
690 | // in order:\r | |
691 | // 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13\r | |
692 | //\r | |
693 | })\r | |
694 | }\r | |
695 | }\r | |
696 | }\r | |
697 | }\r | |
698 | }\r |