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1 | /**@file\r | |
2 | Platform PEI driver\r | |
3 | \r | |
4 | Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r | |
5 | Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r | |
6 | \r | |
7 | This program and the accompanying materials\r | |
8 | are licensed and made available under the terms and conditions of the BSD License\r | |
9 | which accompanies this distribution. The full text of the license may be found at\r | |
10 | http://opensource.org/licenses/bsd-license.php\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
17 | //\r | |
18 | // The package level header files this module uses\r | |
19 | //\r | |
20 | #include <PiPei.h>\r | |
21 | \r | |
22 | //\r | |
23 | // The Library classes this module consumes\r | |
24 | //\r | |
25 | #include <Library/BaseLib.h>\r | |
26 | #include <Library/DebugLib.h>\r | |
27 | #include <Library/HobLib.h>\r | |
28 | #include <Library/IoLib.h>\r | |
29 | #include <Library/MemoryAllocationLib.h>\r | |
30 | #include <Library/PcdLib.h>\r | |
31 | #include <Library/PciLib.h>\r | |
32 | #include <Library/PeimEntryPoint.h>\r | |
33 | #include <Library/PeiServicesLib.h>\r | |
34 | #include <Library/QemuFwCfgLib.h>\r | |
35 | #include <Library/ResourcePublicationLib.h>\r | |
36 | #include <Guid/MemoryTypeInformation.h>\r | |
37 | #include <Ppi/MasterBootMode.h>\r | |
38 | #include <IndustryStandard/Pci22.h>\r | |
39 | #include <OvmfPlatforms.h>\r | |
40 | \r | |
41 | #include "Platform.h"\r | |
42 | #include "Cmos.h"\r | |
43 | \r | |
44 | EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r | |
45 | { EfiACPIMemoryNVS, 0x004 },\r | |
46 | { EfiACPIReclaimMemory, 0x008 },\r | |
47 | { EfiReservedMemoryType, 0x004 },\r | |
48 | { EfiRuntimeServicesData, 0x024 },\r | |
49 | { EfiRuntimeServicesCode, 0x030 },\r | |
50 | { EfiBootServicesCode, 0x180 },\r | |
51 | { EfiBootServicesData, 0xF00 },\r | |
52 | { EfiMaxMemoryType, 0x000 }\r | |
53 | };\r | |
54 | \r | |
55 | \r | |
56 | EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r | |
57 | {\r | |
58 | EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r | |
59 | &gEfiPeiMasterBootModePpiGuid,\r | |
60 | NULL\r | |
61 | }\r | |
62 | };\r | |
63 | \r | |
64 | \r | |
65 | UINT16 mHostBridgeDevId;\r | |
66 | \r | |
67 | EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r | |
68 | \r | |
69 | BOOLEAN mS3Supported = FALSE;\r | |
70 | \r | |
71 | \r | |
72 | VOID\r | |
73 | AddIoMemoryBaseSizeHob (\r | |
74 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
75 | UINT64 MemorySize\r | |
76 | )\r | |
77 | {\r | |
78 | BuildResourceDescriptorHob (\r | |
79 | EFI_RESOURCE_MEMORY_MAPPED_IO,\r | |
80 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
81 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
82 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
83 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r | |
84 | MemoryBase,\r | |
85 | MemorySize\r | |
86 | );\r | |
87 | }\r | |
88 | \r | |
89 | VOID\r | |
90 | AddReservedMemoryBaseSizeHob (\r | |
91 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
92 | UINT64 MemorySize,\r | |
93 | BOOLEAN Cacheable\r | |
94 | )\r | |
95 | {\r | |
96 | BuildResourceDescriptorHob (\r | |
97 | EFI_RESOURCE_MEMORY_RESERVED,\r | |
98 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
99 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
100 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
101 | (Cacheable ?\r | |
102 | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r | |
103 | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r | |
104 | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :\r | |
105 | 0\r | |
106 | ) |\r | |
107 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r | |
108 | MemoryBase,\r | |
109 | MemorySize\r | |
110 | );\r | |
111 | }\r | |
112 | \r | |
113 | VOID\r | |
114 | AddIoMemoryRangeHob (\r | |
115 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
116 | EFI_PHYSICAL_ADDRESS MemoryLimit\r | |
117 | )\r | |
118 | {\r | |
119 | AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r | |
120 | }\r | |
121 | \r | |
122 | \r | |
123 | VOID\r | |
124 | AddMemoryBaseSizeHob (\r | |
125 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
126 | UINT64 MemorySize\r | |
127 | )\r | |
128 | {\r | |
129 | BuildResourceDescriptorHob (\r | |
130 | EFI_RESOURCE_SYSTEM_MEMORY,\r | |
131 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
132 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
133 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
134 | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r | |
135 | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r | |
136 | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r | |
137 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r | |
138 | MemoryBase,\r | |
139 | MemorySize\r | |
140 | );\r | |
141 | }\r | |
142 | \r | |
143 | \r | |
144 | VOID\r | |
145 | AddMemoryRangeHob (\r | |
146 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
147 | EFI_PHYSICAL_ADDRESS MemoryLimit\r | |
148 | )\r | |
149 | {\r | |
150 | AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r | |
151 | }\r | |
152 | \r | |
153 | \r | |
154 | VOID\r | |
155 | MemMapInitialization (\r | |
156 | VOID\r | |
157 | )\r | |
158 | {\r | |
159 | UINT64 PciIoBase;\r | |
160 | UINT64 PciIoSize;\r | |
161 | \r | |
162 | PciIoBase = 0xC000;\r | |
163 | PciIoSize = 0x4000;\r | |
164 | \r | |
165 | //\r | |
166 | // Create Memory Type Information HOB\r | |
167 | //\r | |
168 | BuildGuidDataHob (\r | |
169 | &gEfiMemoryTypeInformationGuid,\r | |
170 | mDefaultMemoryTypeInformation,\r | |
171 | sizeof(mDefaultMemoryTypeInformation)\r | |
172 | );\r | |
173 | \r | |
174 | //\r | |
175 | // Video memory + Legacy BIOS region\r | |
176 | //\r | |
177 | AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r | |
178 | \r | |
179 | if (!mXen) {\r | |
180 | UINT32 TopOfLowRam;\r | |
181 | UINT64 PciExBarBase;\r | |
182 | UINT32 PciBase;\r | |
183 | UINT32 PciSize;\r | |
184 | \r | |
185 | TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r | |
186 | PciExBarBase = 0;\r | |
187 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r | |
188 | //\r | |
189 | // The MMCONFIG area is expected to fall between the top of low RAM and\r | |
190 | // the base of the 32-bit PCI host aperture.\r | |
191 | //\r | |
192 | PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);\r | |
193 | ASSERT (TopOfLowRam <= PciExBarBase);\r | |
194 | ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);\r | |
195 | PciBase = (UINT32)(PciExBarBase + SIZE_256MB);\r | |
196 | } else {\r | |
197 | PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;\r | |
198 | }\r | |
199 | \r | |
200 | //\r | |
201 | // address purpose size\r | |
202 | // ------------ -------- -------------------------\r | |
203 | // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r | |
204 | // 0xFC000000 gap 44 MB\r | |
205 | // 0xFEC00000 IO-APIC 4 KB\r | |
206 | // 0xFEC01000 gap 1020 KB\r | |
207 | // 0xFED00000 HPET 1 KB\r | |
208 | // 0xFED00400 gap 111 KB\r | |
209 | // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB\r | |
210 | // 0xFED20000 gap 896 KB\r | |
211 | // 0xFEE00000 LAPIC 1 MB\r | |
212 | //\r | |
213 | PciSize = 0xFC000000 - PciBase;\r | |
214 | AddIoMemoryBaseSizeHob (PciBase, PciSize);\r | |
215 | PcdSet64 (PcdPciMmio32Base, PciBase);\r | |
216 | PcdSet64 (PcdPciMmio32Size, PciSize);\r | |
217 | AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r | |
218 | AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r | |
219 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r | |
220 | AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r | |
221 | //\r | |
222 | // Note: there should be an\r | |
223 | //\r | |
224 | // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);\r | |
225 | //\r | |
226 | // call below, just like the one above for RCBA. However, Linux insists\r | |
227 | // that the MMCONFIG area be marked in the E820 or UEFI memory map as\r | |
228 | // "reserved memory" -- Linux does not content itself with a simple gap\r | |
229 | // in the memory map wherever the MCFG ACPI table points to.\r | |
230 | //\r | |
231 | // This appears to be a safety measure. The PCI Firmware Specification\r | |
232 | // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can\r | |
233 | // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory\r | |
234 | // [...]". (Emphasis added here.)\r | |
235 | //\r | |
236 | // Normally we add memory resource descriptor HOBs in\r | |
237 | // QemuInitializeRam(), and pre-allocate from those with memory\r | |
238 | // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area\r | |
239 | // is most definitely not RAM; so, as an exception, cover it with\r | |
240 | // uncacheable reserved memory right here.\r | |
241 | //\r | |
242 | AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);\r | |
243 | BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,\r | |
244 | EfiReservedMemoryType);\r | |
245 | }\r | |
246 | AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r | |
247 | \r | |
248 | //\r | |
249 | // On Q35, the IO Port space is available for PCI resource allocations from\r | |
250 | // 0x6000 up.\r | |
251 | //\r | |
252 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r | |
253 | PciIoBase = 0x6000;\r | |
254 | PciIoSize = 0xA000;\r | |
255 | ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);\r | |
256 | }\r | |
257 | }\r | |
258 | \r | |
259 | //\r | |
260 | // Add PCI IO Port space available for PCI resource allocations.\r | |
261 | //\r | |
262 | BuildResourceDescriptorHob (\r | |
263 | EFI_RESOURCE_IO,\r | |
264 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
265 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r | |
266 | PciIoBase,\r | |
267 | PciIoSize\r | |
268 | );\r | |
269 | PcdSet64 (PcdPciIoBase, PciIoBase);\r | |
270 | PcdSet64 (PcdPciIoSize, PciIoSize);\r | |
271 | }\r | |
272 | \r | |
273 | EFI_STATUS\r | |
274 | GetNamedFwCfgBoolean (\r | |
275 | IN CHAR8 *FwCfgFileName,\r | |
276 | OUT BOOLEAN *Setting\r | |
277 | )\r | |
278 | {\r | |
279 | EFI_STATUS Status;\r | |
280 | FIRMWARE_CONFIG_ITEM FwCfgItem;\r | |
281 | UINTN FwCfgSize;\r | |
282 | UINT8 Value[3];\r | |
283 | \r | |
284 | Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);\r | |
285 | if (EFI_ERROR (Status)) {\r | |
286 | return Status;\r | |
287 | }\r | |
288 | if (FwCfgSize > sizeof Value) {\r | |
289 | return EFI_BAD_BUFFER_SIZE;\r | |
290 | }\r | |
291 | QemuFwCfgSelectItem (FwCfgItem);\r | |
292 | QemuFwCfgReadBytes (FwCfgSize, Value);\r | |
293 | \r | |
294 | if ((FwCfgSize == 1) ||\r | |
295 | (FwCfgSize == 2 && Value[1] == '\n') ||\r | |
296 | (FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {\r | |
297 | switch (Value[0]) {\r | |
298 | case '0':\r | |
299 | case 'n':\r | |
300 | case 'N':\r | |
301 | *Setting = FALSE;\r | |
302 | return EFI_SUCCESS;\r | |
303 | \r | |
304 | case '1':\r | |
305 | case 'y':\r | |
306 | case 'Y':\r | |
307 | *Setting = TRUE;\r | |
308 | return EFI_SUCCESS;\r | |
309 | \r | |
310 | default:\r | |
311 | break;\r | |
312 | }\r | |
313 | }\r | |
314 | return EFI_PROTOCOL_ERROR;\r | |
315 | }\r | |
316 | \r | |
317 | #define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \\r | |
318 | do { \\r | |
319 | BOOLEAN Setting; \\r | |
320 | \\r | |
321 | if (!EFI_ERROR (GetNamedFwCfgBoolean ( \\r | |
322 | "opt/ovmf/" #TokenName, &Setting))) { \\r | |
323 | PcdSetBool (TokenName, Setting); \\r | |
324 | } \\r | |
325 | } while (0)\r | |
326 | \r | |
327 | VOID\r | |
328 | NoexecDxeInitialization (\r | |
329 | VOID\r | |
330 | )\r | |
331 | {\r | |
332 | UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);\r | |
333 | UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);\r | |
334 | }\r | |
335 | \r | |
336 | VOID\r | |
337 | PciExBarInitialization (\r | |
338 | VOID\r | |
339 | )\r | |
340 | {\r | |
341 | union {\r | |
342 | UINT64 Uint64;\r | |
343 | UINT32 Uint32[2];\r | |
344 | } PciExBarBase;\r | |
345 | \r | |
346 | //\r | |
347 | // We only support the 256MB size for the MMCONFIG area:\r | |
348 | // 256 buses * 32 devices * 8 functions * 4096 bytes config space.\r | |
349 | //\r | |
350 | // The masks used below enforce the Q35 requirements that the MMCONFIG area\r | |
351 | // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.\r | |
352 | //\r | |
353 | // Note that (b) also ensures that the minimum address width we have\r | |
354 | // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice\r | |
355 | // for DXE's page tables to cover the MMCONFIG area.\r | |
356 | //\r | |
357 | PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);\r | |
358 | ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);\r | |
359 | ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);\r | |
360 | \r | |
361 | //\r | |
362 | // Clear the PCIEXBAREN bit first, before programming the high register.\r | |
363 | //\r | |
364 | PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);\r | |
365 | \r | |
366 | //\r | |
367 | // Program the high register. Then program the low register, setting the\r | |
368 | // MMCONFIG area size and enabling decoding at once.\r | |
369 | //\r | |
370 | PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);\r | |
371 | PciWrite32 (\r | |
372 | DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),\r | |
373 | PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN\r | |
374 | );\r | |
375 | }\r | |
376 | \r | |
377 | VOID\r | |
378 | MiscInitialization (\r | |
379 | VOID\r | |
380 | )\r | |
381 | {\r | |
382 | UINTN PmCmd;\r | |
383 | UINTN Pmba;\r | |
384 | UINT32 PmbaAndVal;\r | |
385 | UINT32 PmbaOrVal;\r | |
386 | UINTN AcpiCtlReg;\r | |
387 | UINT8 AcpiEnBit;\r | |
388 | \r | |
389 | //\r | |
390 | // Disable A20 Mask\r | |
391 | //\r | |
392 | IoOr8 (0x92, BIT1);\r | |
393 | \r | |
394 | //\r | |
395 | // Build the CPU HOB with guest RAM size dependent address width and 16-bits\r | |
396 | // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r | |
397 | // S3 resume as well, so we build it unconditionally.)\r | |
398 | //\r | |
399 | BuildCpuHob (mPhysMemAddressWidth, 16);\r | |
400 | \r | |
401 | //\r | |
402 | // Determine platform type and save Host Bridge DID to PCD\r | |
403 | //\r | |
404 | switch (mHostBridgeDevId) {\r | |
405 | case INTEL_82441_DEVICE_ID:\r | |
406 | PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r | |
407 | Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r | |
408 | PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;\r | |
409 | PmbaOrVal = PIIX4_PMBA_VALUE;\r | |
410 | AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r | |
411 | AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r | |
412 | break;\r | |
413 | case INTEL_Q35_MCH_DEVICE_ID:\r | |
414 | PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r | |
415 | Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r | |
416 | PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;\r | |
417 | PmbaOrVal = ICH9_PMBASE_VALUE;\r | |
418 | AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r | |
419 | AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r | |
420 | break;\r | |
421 | default:\r | |
422 | DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r | |
423 | __FUNCTION__, mHostBridgeDevId));\r | |
424 | ASSERT (FALSE);\r | |
425 | return;\r | |
426 | }\r | |
427 | PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r | |
428 | \r | |
429 | //\r | |
430 | // If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r | |
431 | // has been configured (e.g., by Xen) and skip the setup here.\r | |
432 | // This matches the logic in AcpiTimerLibConstructor ().\r | |
433 | //\r | |
434 | if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r | |
435 | //\r | |
436 | // The PEI phase should be exited with fully accessibe ACPI PM IO space:\r | |
437 | // 1. set PMBA\r | |
438 | //\r | |
439 | PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);\r | |
440 | \r | |
441 | //\r | |
442 | // 2. set PCICMD/IOSE\r | |
443 | //\r | |
444 | PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r | |
445 | \r | |
446 | //\r | |
447 | // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r | |
448 | //\r | |
449 | PciOr8 (AcpiCtlReg, AcpiEnBit);\r | |
450 | }\r | |
451 | \r | |
452 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r | |
453 | //\r | |
454 | // Set Root Complex Register Block BAR\r | |
455 | //\r | |
456 | PciWrite32 (\r | |
457 | POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r | |
458 | ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r | |
459 | );\r | |
460 | \r | |
461 | //\r | |
462 | // Set PCI Express Register Range Base Address\r | |
463 | //\r | |
464 | PciExBarInitialization ();\r | |
465 | }\r | |
466 | }\r | |
467 | \r | |
468 | \r | |
469 | VOID\r | |
470 | BootModeInitialization (\r | |
471 | VOID\r | |
472 | )\r | |
473 | {\r | |
474 | EFI_STATUS Status;\r | |
475 | \r | |
476 | if (CmosRead8 (0xF) == 0xFE) {\r | |
477 | mBootMode = BOOT_ON_S3_RESUME;\r | |
478 | }\r | |
479 | CmosWrite8 (0xF, 0x00);\r | |
480 | \r | |
481 | Status = PeiServicesSetBootMode (mBootMode);\r | |
482 | ASSERT_EFI_ERROR (Status);\r | |
483 | \r | |
484 | Status = PeiServicesInstallPpi (mPpiBootMode);\r | |
485 | ASSERT_EFI_ERROR (Status);\r | |
486 | }\r | |
487 | \r | |
488 | \r | |
489 | VOID\r | |
490 | ReserveEmuVariableNvStore (\r | |
491 | )\r | |
492 | {\r | |
493 | EFI_PHYSICAL_ADDRESS VariableStore;\r | |
494 | \r | |
495 | //\r | |
496 | // Allocate storage for NV variables early on so it will be\r | |
497 | // at a consistent address. Since VM memory is preserved\r | |
498 | // across reboots, this allows the NV variable storage to survive\r | |
499 | // a VM reboot.\r | |
500 | //\r | |
501 | VariableStore =\r | |
502 | (EFI_PHYSICAL_ADDRESS)(UINTN)\r | |
503 | AllocateAlignedRuntimePages (\r | |
504 | EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r | |
505 | PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r | |
506 | );\r | |
507 | DEBUG ((EFI_D_INFO,\r | |
508 | "Reserved variable store memory: 0x%lX; size: %dkb\n",\r | |
509 | VariableStore,\r | |
510 | (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r | |
511 | ));\r | |
512 | PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);\r | |
513 | }\r | |
514 | \r | |
515 | \r | |
516 | VOID\r | |
517 | DebugDumpCmos (\r | |
518 | VOID\r | |
519 | )\r | |
520 | {\r | |
521 | UINT32 Loop;\r | |
522 | \r | |
523 | DEBUG ((EFI_D_INFO, "CMOS:\n"));\r | |
524 | \r | |
525 | for (Loop = 0; Loop < 0x80; Loop++) {\r | |
526 | if ((Loop % 0x10) == 0) {\r | |
527 | DEBUG ((EFI_D_INFO, "%02x:", Loop));\r | |
528 | }\r | |
529 | DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r | |
530 | if ((Loop % 0x10) == 0xf) {\r | |
531 | DEBUG ((EFI_D_INFO, "\n"));\r | |
532 | }\r | |
533 | }\r | |
534 | }\r | |
535 | \r | |
536 | \r | |
537 | VOID\r | |
538 | S3Verification (\r | |
539 | VOID\r | |
540 | )\r | |
541 | {\r | |
542 | #if defined (MDE_CPU_X64)\r | |
543 | if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {\r | |
544 | DEBUG ((EFI_D_ERROR,\r | |
545 | "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));\r | |
546 | DEBUG ((EFI_D_ERROR,\r | |
547 | "%a: Please disable S3 on the QEMU command line (see the README),\n",\r | |
548 | __FUNCTION__));\r | |
549 | DEBUG ((EFI_D_ERROR,\r | |
550 | "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));\r | |
551 | ASSERT (FALSE);\r | |
552 | CpuDeadLoop ();\r | |
553 | }\r | |
554 | #endif\r | |
555 | }\r | |
556 | \r | |
557 | \r | |
558 | /**\r | |
559 | Perform Platform PEI initialization.\r | |
560 | \r | |
561 | @param FileHandle Handle of the file being invoked.\r | |
562 | @param PeiServices Describes the list of possible PEI Services.\r | |
563 | \r | |
564 | @return EFI_SUCCESS The PEIM initialized successfully.\r | |
565 | \r | |
566 | **/\r | |
567 | EFI_STATUS\r | |
568 | EFIAPI\r | |
569 | InitializePlatform (\r | |
570 | IN EFI_PEI_FILE_HANDLE FileHandle,\r | |
571 | IN CONST EFI_PEI_SERVICES **PeiServices\r | |
572 | )\r | |
573 | {\r | |
574 | EFI_STATUS Status;\r | |
575 | \r | |
576 | DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r | |
577 | \r | |
578 | DebugDumpCmos ();\r | |
579 | \r | |
580 | XenDetect ();\r | |
581 | \r | |
582 | if (QemuFwCfgS3Enabled ()) {\r | |
583 | DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r | |
584 | mS3Supported = TRUE;\r | |
585 | Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);\r | |
586 | ASSERT_EFI_ERROR (Status);\r | |
587 | }\r | |
588 | \r | |
589 | S3Verification ();\r | |
590 | BootModeInitialization ();\r | |
591 | AddressWidthInitialization ();\r | |
592 | \r | |
593 | PublishPeiMemory ();\r | |
594 | \r | |
595 | InitializeRamRegions ();\r | |
596 | \r | |
597 | if (mXen) {\r | |
598 | DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r | |
599 | InitializeXen ();\r | |
600 | }\r | |
601 | \r | |
602 | //\r | |
603 | // Query Host Bridge DID\r | |
604 | //\r | |
605 | mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r | |
606 | \r | |
607 | if (mBootMode != BOOT_ON_S3_RESUME) {\r | |
608 | ReserveEmuVariableNvStore ();\r | |
609 | PeiFvInitialization ();\r | |
610 | MemMapInitialization ();\r | |
611 | NoexecDxeInitialization ();\r | |
612 | }\r | |
613 | \r | |
614 | MiscInitialization ();\r | |
615 | \r | |
616 | return EFI_SUCCESS;\r | |
617 | }\r |