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1 | \r | |
2 | /*++\r | |
3 | \r | |
4 | Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r | |
5 | \r\r | |
6 | This program and the accompanying materials are licensed and made available under\r\r | |
7 | the terms and conditions of the BSD License that accompanies this distribution. \r\r | |
8 | The full text of the license may be found at \r\r | |
9 | http://opensource.org/licenses/bsd-license.php. \r\r | |
10 | \r\r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r | |
13 | \r\r | |
14 | \r | |
15 | \r | |
16 | Module Name:\r | |
17 | \r | |
18 | VlvPlatformInit.c\r | |
19 | \r | |
20 | Abstract:\r | |
21 | \r | |
22 | This is the driver that initializes the Intel ValleyView.\r | |
23 | \r | |
24 | --*/\r | |
25 | \r | |
26 | #include "VlvPlatformInit.h"\r | |
27 | #include <Protocol/VlvPlatformPolicy.h>\r | |
28 | \r | |
29 | extern DXE_VLV_PLATFORM_POLICY_PROTOCOL *DxePlatformSaPolicy;\r | |
30 | UINT64 GTTMMADR;\r | |
31 | \r | |
32 | DXE_VLV_PLATFORM_POLICY_PROTOCOL *DxePlatformSaPolicy;\r | |
33 | \r | |
34 | /**\r | |
35 | "Poll Status" for GT Readiness\r | |
36 | \r | |
37 | @param Base Base address of MMIO\r | |
38 | @param Offset MMIO Offset\r | |
39 | @param Mask Mask\r | |
40 | @param Result Value to wait for\r | |
41 | \r | |
42 | @retval None\r | |
43 | \r | |
44 | **/\r | |
45 | VOID\r | |
46 | PollGtReady_hang (\r | |
47 | UINT64 Base,\r | |
48 | UINT32 Offset,\r | |
49 | UINT32 Mask,\r | |
50 | UINT32 Result\r | |
51 | )\r | |
52 | {\r | |
53 | UINT32 GtStatus;\r | |
54 | \r | |
55 | //\r | |
56 | // Register read\r | |
57 | //\r | |
58 | GtStatus = MmioRead32 ((UINTN)Base+ Offset);\r | |
59 | \r | |
60 | while (((GtStatus & Mask) != Result)) {\r | |
61 | \r | |
62 | GtStatus = MmioRead32 ((UINTN)Base + Offset);\r | |
63 | }\r | |
64 | \r | |
65 | }\r | |
66 | \r | |
67 | /**\r | |
68 | Do Post GT PM Init Steps after VBIOS Initialization.\r | |
69 | \r | |
70 | @param Event A pointer to the Event that triggered the callback.\r | |
71 | @param Context A pointer to private data registered with the callback function.\r | |
72 | \r | |
73 | @retval EFI_SUCCESS GC_TODO\r | |
74 | \r | |
75 | \r | |
76 | **/\r | |
77 | EFI_STATUS\r | |
78 | EFIAPI \r | |
79 | PostPmInitCallBack (\r | |
80 | IN EFI_EVENT Event,\r | |
81 | IN VOID *Context\r | |
82 | )\r | |
83 | {\r | |
84 | UINT64 OriginalGTTMMADR;\r | |
85 | UINT32 LoGTBaseAddress;\r | |
86 | UINT32 HiGTBaseAddress;\r | |
87 | \r | |
88 | //\r | |
89 | // Enable Bus Master, I/O and Memory access on 0:2:0\r | |
90 | //\r | |
91 | PciOr8 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_CMD), (BIT2 | BIT1));\r | |
92 | \r | |
93 | //\r | |
94 | // only 32bit read/write is legal for device 0:2:0\r | |
95 | //\r | |
96 | OriginalGTTMMADR = (UINT64) PciRead32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR));\r | |
97 | OriginalGTTMMADR = LShiftU64 ((UINT64) PciRead32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR + 4)), 32) | (OriginalGTTMMADR);\r | |
98 | \r | |
99 | //\r | |
100 | // 64bit GTTMADR does not work for S3 save script table since it is executed in PEIM phase\r | |
101 | // Program temporarily 32bits GTTMMADR for POST and S3 resume\r | |
102 | //\r | |
103 | LoGTBaseAddress = (UINT32) (GTTMMADR & 0xFFFFFFFF);\r | |
104 | HiGTBaseAddress = (UINT32) RShiftU64 ((GTTMMADR & 0xFFFFFFFF00000000), 32);\r | |
105 | S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR), LoGTBaseAddress);\r | |
106 | S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR+4), HiGTBaseAddress);\r | |
107 | \r | |
108 | \r | |
109 | \r | |
110 | //\r | |
111 | // Restore original GTTMMADR\r | |
112 | //\r | |
113 | LoGTBaseAddress = (UINT32) (OriginalGTTMMADR & 0xFFFFFFFF);\r | |
114 | HiGTBaseAddress = (UINT32) RShiftU64 ((OriginalGTTMMADR & 0xFFFFFFFF00000000), 32);\r | |
115 | \r | |
116 | S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR), LoGTBaseAddress);\r | |
117 | S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR+4), HiGTBaseAddress);\r | |
118 | \r | |
119 | \r | |
120 | //\r | |
121 | // Lock the following registers, GGC, BDSM, BGSM\r | |
122 | //\r | |
123 | PciOr32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_MGGC_OFFSET), LockBit);\r | |
124 | PciOr32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_BSM_OFFSET), LockBit);\r | |
125 | PciOr32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_BGSM), LockBit);\r | |
126 | \r | |
127 | gBS->CloseEvent (Event);\r | |
128 | \r | |
129 | //\r | |
130 | // Return final status\r | |
131 | //\r | |
132 | return EFI_SUCCESS;\r | |
133 | }\r | |
134 | \r | |
135 | /**\r | |
136 | \r | |
137 | Routine Description:\r | |
138 | \r | |
139 | Initialize GT Post Routines.\r | |
140 | \r | |
141 | @param ImageHandle Handle for the image of this driver\r | |
142 | @param DxePlatformSaPolicy SA DxePlatformPolicy protocol\r | |
143 | \r | |
144 | @retval EFI_SUCCESS GT POST initialization complete\r | |
145 | \r | |
146 | **/\r | |
147 | EFI_STATUS\r | |
148 | IgdPmHook (\r | |
149 | IN EFI_HANDLE ImageHandle,\r | |
150 | IN DXE_VLV_PLATFORM_POLICY_PROTOCOL *DxePlatformSaPolicy\r | |
151 | )\r | |
152 | {\r | |
153 | \r | |
154 | EFI_EVENT mConOutEvent;\r | |
155 | VOID *gConOutNotifyReg;\r | |
156 | \r | |
157 | EFI_STATUS Status;\r | |
158 | \r | |
159 | EFI_PHYSICAL_ADDRESS MemBaseAddress;\r | |
160 | UINT32 LoGTBaseAddress;\r | |
161 | UINT32 HiGTBaseAddress;\r | |
162 | \r | |
163 | GTTMMADR = 0;\r | |
164 | Status = EFI_SUCCESS;\r | |
165 | \r | |
166 | //\r | |
167 | // If device 0:2:0 (Internal Graphics Device, or GT) is enabled, then Program GTTMMADR,\r | |
168 | //\r | |
169 | if (PciRead16(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_VID)) != 0xFFFF) {\r | |
170 | \r | |
171 | ASSERT (gDS!=NULL);\r | |
172 | \r | |
173 | //\r | |
174 | // Enable Bus Master, I/O and Memory access on 0:2:0\r | |
175 | //\r | |
176 | PciOr8(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_CMD), (BIT2 | BIT1 | BIT0));\r | |
177 | \r | |
178 | //\r | |
179 | // Means Allocate 4MB for GTTMADDR\r | |
180 | //\r | |
181 | MemBaseAddress = 0x0ffffffff;\r | |
182 | \r | |
183 | Status = gDS->AllocateMemorySpace (\r | |
184 | EfiGcdAllocateMaxAddressSearchBottomUp,\r | |
185 | EfiGcdMemoryTypeMemoryMappedIo,\r | |
186 | GTT_MEM_ALIGN,\r | |
187 | GTTMMADR_SIZE_4MB,\r | |
188 | &MemBaseAddress,\r | |
189 | ImageHandle,\r | |
190 | NULL\r | |
191 | );\r | |
192 | ASSERT_EFI_ERROR (Status);\r | |
193 | \r | |
194 | //\r | |
195 | // Program GT PM Settings if GTTMMADR allocation is Successful\r | |
196 | //\r | |
197 | GTTMMADR = (UINTN) MemBaseAddress;\r | |
198 | \r | |
199 | LoGTBaseAddress = (UINT32) (MemBaseAddress & 0xFFFFFFFF);\r | |
200 | HiGTBaseAddress = (UINT32) RShiftU64 ((MemBaseAddress & 0xFFFFFFFF00000000), 32);\r | |
201 | \r | |
202 | PciWrite32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_GTTMMADR), LoGTBaseAddress);\r | |
203 | PciWrite32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_GTTMMADR+4), HiGTBaseAddress);\r | |
204 | \r | |
205 | \r | |
206 | S3PciRead32(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_GTTMMADR));\r | |
207 | \r | |
208 | \r | |
209 | S3MmioRead32(IGD_R_GTTMMADR + 4);\r | |
210 | \r | |
211 | \r | |
212 | S3PciRead8(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_CMD));\r | |
213 | \r | |
214 | //\r | |
215 | // Do POST GT PM Init Steps after VBIOS Initialization in DoPostPmInitCallBack\r | |
216 | //\r | |
217 | Status = gBS->CreateEvent (\r | |
218 | EVT_NOTIFY_SIGNAL,\r | |
219 | TPL_CALLBACK,\r | |
220 | (EFI_EVENT_NOTIFY)PostPmInitCallBack,\r | |
221 | NULL,\r | |
222 | &mConOutEvent\r | |
223 | );\r | |
224 | \r | |
225 | ASSERT_EFI_ERROR (Status);\r | |
226 | if (EFI_ERROR (Status)) {\r | |
227 | return Status;\r | |
228 | }\r | |
229 | \r | |
230 | \r | |
231 | Status = gBS->RegisterProtocolNotify (\r | |
232 | &gEfiGraphicsOutputProtocolGuid,\r | |
233 | mConOutEvent,\r | |
234 | &gConOutNotifyReg\r | |
235 | );\r | |
236 | \r | |
237 | \r | |
238 | \r | |
239 | MmioWrite64 (IGD_R_GTTMMADR, 0);\r | |
240 | \r | |
241 | //\r | |
242 | // Free allocated resources\r | |
243 | //\r | |
244 | gDS->FreeMemorySpace (\r | |
245 | MemBaseAddress,\r | |
246 | GTTMMADR_SIZE_4MB\r | |
247 | );\r | |
248 | \r | |
249 | }\r | |
250 | \r | |
251 | return EFI_SUCCESS;\r | |
252 | }\r | |
253 | \r | |
254 | /**\r | |
255 | \r | |
256 | This is the standard EFI driver point that detects\r | |
257 | whether there is an ICH southbridge in the system\r | |
258 | and if so, initializes the chip.\r | |
259 | \r | |
260 | @param ImageHandle Handle for the image of this driver\r | |
261 | @param SystemTable Pointer to the EFI System Table\r | |
262 | \r | |
263 | @retval EFI_SUCCESS The function completed successfully\r | |
264 | \r | |
265 | **/\r | |
266 | EFI_STATUS\r | |
267 | EFIAPI\r | |
268 | VlvPlatformInitEntryPoint (\r | |
269 | IN EFI_HANDLE ImageHandle,\r | |
270 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
271 | )\r | |
272 | {\r | |
273 | EFI_STATUS Status;\r | |
274 | \r | |
275 | Status = gBS->LocateProtocol (&gDxeVlvPlatformPolicyGuid, NULL, (void **)&DxePlatformSaPolicy);\r | |
276 | ASSERT_EFI_ERROR (Status);\r | |
277 | \r | |
278 | //\r | |
279 | // GtPostInit Initialization\r | |
280 | //\r | |
281 | DEBUG ((EFI_D_ERROR, "Initializing GT PowerManagement and other GT POST related\n"));\r | |
282 | IgdPmHook (ImageHandle, DxePlatformSaPolicy);\r | |
283 | \r | |
284 | //\r | |
285 | // IgdOpRegion Install Initialization\r | |
286 | //\r | |
287 | DEBUG ((EFI_D_ERROR, "Initializing IGD OpRegion\n"));\r | |
288 | IgdOpRegionInit ();\r | |
289 | \r | |
290 | return EFI_SUCCESS;\r | |
291 | }\r | |
292 | \r |