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1 | /* | |
2 | * arch/arm/mach-pxa/time.c | |
3 | * | |
4 | * PXA clocksource, clockevents, and OST interrupt handlers. | |
5 | * Copyright (c) 2007 by Bill Gatliff <bgat@billgatliff.com>. | |
6 | * | |
7 | * Derived from Nicolas Pitre's PXA timer handler Copyright (c) 2001 | |
8 | * by MontaVista Software, Inc. (Nico, your code rocks!) | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/kernel.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/clk.h> | |
19 | #include <linux/clockchips.h> | |
20 | #include <linux/of_address.h> | |
21 | #include <linux/of_irq.h> | |
22 | #include <linux/sched_clock.h> | |
23 | ||
24 | #include <clocksource/pxa.h> | |
25 | ||
26 | #include <asm/div64.h> | |
27 | ||
28 | #define OSMR0 0x00 /* OS Timer 0 Match Register */ | |
29 | #define OSMR1 0x04 /* OS Timer 1 Match Register */ | |
30 | #define OSMR2 0x08 /* OS Timer 2 Match Register */ | |
31 | #define OSMR3 0x0C /* OS Timer 3 Match Register */ | |
32 | ||
33 | #define OSCR 0x10 /* OS Timer Counter Register */ | |
34 | #define OSSR 0x14 /* OS Timer Status Register */ | |
35 | #define OWER 0x18 /* OS Timer Watchdog Enable Register */ | |
36 | #define OIER 0x1C /* OS Timer Interrupt Enable Register */ | |
37 | ||
38 | #define OSSR_M3 (1 << 3) /* Match status channel 3 */ | |
39 | #define OSSR_M2 (1 << 2) /* Match status channel 2 */ | |
40 | #define OSSR_M1 (1 << 1) /* Match status channel 1 */ | |
41 | #define OSSR_M0 (1 << 0) /* Match status channel 0 */ | |
42 | ||
43 | #define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */ | |
44 | ||
45 | /* | |
46 | * This is PXA's sched_clock implementation. This has a resolution | |
47 | * of at least 308 ns and a maximum value of 208 days. | |
48 | * | |
49 | * The return value is guaranteed to be monotonic in that range as | |
50 | * long as there is always less than 582 seconds between successive | |
51 | * calls to sched_clock() which should always be the case in practice. | |
52 | */ | |
53 | ||
54 | #define timer_readl(reg) readl_relaxed(timer_base + (reg)) | |
55 | #define timer_writel(val, reg) writel_relaxed((val), timer_base + (reg)) | |
56 | ||
57 | static void __iomem *timer_base; | |
58 | ||
59 | static u64 notrace pxa_read_sched_clock(void) | |
60 | { | |
61 | return timer_readl(OSCR); | |
62 | } | |
63 | ||
64 | ||
65 | #define MIN_OSCR_DELTA 16 | |
66 | ||
67 | static irqreturn_t | |
68 | pxa_ost0_interrupt(int irq, void *dev_id) | |
69 | { | |
70 | struct clock_event_device *c = dev_id; | |
71 | ||
72 | /* Disarm the compare/match, signal the event. */ | |
73 | timer_writel(timer_readl(OIER) & ~OIER_E0, OIER); | |
74 | timer_writel(OSSR_M0, OSSR); | |
75 | c->event_handler(c); | |
76 | ||
77 | return IRQ_HANDLED; | |
78 | } | |
79 | ||
80 | static int | |
81 | pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev) | |
82 | { | |
83 | unsigned long next, oscr; | |
84 | ||
85 | timer_writel(timer_readl(OIER) | OIER_E0, OIER); | |
86 | next = timer_readl(OSCR) + delta; | |
87 | timer_writel(next, OSMR0); | |
88 | oscr = timer_readl(OSCR); | |
89 | ||
90 | return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0; | |
91 | } | |
92 | ||
93 | static int pxa_osmr0_shutdown(struct clock_event_device *evt) | |
94 | { | |
95 | /* initializing, released, or preparing for suspend */ | |
96 | timer_writel(timer_readl(OIER) & ~OIER_E0, OIER); | |
97 | timer_writel(OSSR_M0, OSSR); | |
98 | return 0; | |
99 | } | |
100 | ||
101 | #ifdef CONFIG_PM | |
102 | static unsigned long osmr[4], oier, oscr; | |
103 | ||
104 | static void pxa_timer_suspend(struct clock_event_device *cedev) | |
105 | { | |
106 | osmr[0] = timer_readl(OSMR0); | |
107 | osmr[1] = timer_readl(OSMR1); | |
108 | osmr[2] = timer_readl(OSMR2); | |
109 | osmr[3] = timer_readl(OSMR3); | |
110 | oier = timer_readl(OIER); | |
111 | oscr = timer_readl(OSCR); | |
112 | } | |
113 | ||
114 | static void pxa_timer_resume(struct clock_event_device *cedev) | |
115 | { | |
116 | /* | |
117 | * Ensure that we have at least MIN_OSCR_DELTA between match | |
118 | * register 0 and the OSCR, to guarantee that we will receive | |
119 | * the one-shot timer interrupt. We adjust OSMR0 in preference | |
120 | * to OSCR to guarantee that OSCR is monotonically incrementing. | |
121 | */ | |
122 | if (osmr[0] - oscr < MIN_OSCR_DELTA) | |
123 | osmr[0] += MIN_OSCR_DELTA; | |
124 | ||
125 | timer_writel(osmr[0], OSMR0); | |
126 | timer_writel(osmr[1], OSMR1); | |
127 | timer_writel(osmr[2], OSMR2); | |
128 | timer_writel(osmr[3], OSMR3); | |
129 | timer_writel(oier, OIER); | |
130 | timer_writel(oscr, OSCR); | |
131 | } | |
132 | #else | |
133 | #define pxa_timer_suspend NULL | |
134 | #define pxa_timer_resume NULL | |
135 | #endif | |
136 | ||
137 | static struct clock_event_device ckevt_pxa_osmr0 = { | |
138 | .name = "osmr0", | |
139 | .features = CLOCK_EVT_FEAT_ONESHOT, | |
140 | .rating = 200, | |
141 | .set_next_event = pxa_osmr0_set_next_event, | |
142 | .set_state_shutdown = pxa_osmr0_shutdown, | |
143 | .set_state_oneshot = pxa_osmr0_shutdown, | |
144 | .suspend = pxa_timer_suspend, | |
145 | .resume = pxa_timer_resume, | |
146 | }; | |
147 | ||
148 | static struct irqaction pxa_ost0_irq = { | |
149 | .name = "ost0", | |
150 | .flags = IRQF_TIMER | IRQF_IRQPOLL, | |
151 | .handler = pxa_ost0_interrupt, | |
152 | .dev_id = &ckevt_pxa_osmr0, | |
153 | }; | |
154 | ||
155 | static int __init pxa_timer_common_init(int irq, unsigned long clock_tick_rate) | |
156 | { | |
157 | int ret; | |
158 | ||
159 | timer_writel(0, OIER); | |
160 | timer_writel(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR); | |
161 | ||
162 | sched_clock_register(pxa_read_sched_clock, 32, clock_tick_rate); | |
163 | ||
164 | ckevt_pxa_osmr0.cpumask = cpumask_of(0); | |
165 | ||
166 | ret = setup_irq(irq, &pxa_ost0_irq); | |
167 | if (ret) { | |
168 | pr_err("Failed to setup irq"); | |
169 | return ret; | |
170 | } | |
171 | ||
172 | ret = clocksource_mmio_init(timer_base + OSCR, "oscr0", clock_tick_rate, 200, | |
173 | 32, clocksource_mmio_readl_up); | |
174 | if (ret) { | |
175 | pr_err("Failed to init clocksource"); | |
176 | return ret; | |
177 | } | |
178 | ||
179 | clockevents_config_and_register(&ckevt_pxa_osmr0, clock_tick_rate, | |
180 | MIN_OSCR_DELTA * 2, 0x7fffffff); | |
181 | ||
182 | return 0; | |
183 | } | |
184 | ||
185 | static int __init pxa_timer_dt_init(struct device_node *np) | |
186 | { | |
187 | struct clk *clk; | |
188 | int irq, ret; | |
189 | ||
190 | /* timer registers are shared with watchdog timer */ | |
191 | timer_base = of_iomap(np, 0); | |
192 | if (!timer_base) { | |
193 | pr_err("%s: unable to map resource\n", np->name); | |
194 | return -ENXIO; | |
195 | } | |
196 | ||
197 | clk = of_clk_get(np, 0); | |
198 | if (IS_ERR(clk)) { | |
199 | pr_crit("%s: unable to get clk\n", np->name); | |
200 | return PTR_ERR(clk); | |
201 | } | |
202 | ||
203 | ret = clk_prepare_enable(clk); | |
204 | if (ret) { | |
205 | pr_crit("Failed to prepare clock"); | |
206 | return ret; | |
207 | } | |
208 | ||
209 | /* we are only interested in OS-timer0 irq */ | |
210 | irq = irq_of_parse_and_map(np, 0); | |
211 | if (irq <= 0) { | |
212 | pr_crit("%s: unable to parse OS-timer0 irq\n", np->name); | |
213 | return -EINVAL; | |
214 | } | |
215 | ||
216 | return pxa_timer_common_init(irq, clk_get_rate(clk)); | |
217 | } | |
218 | CLOCKSOURCE_OF_DECLARE(pxa_timer, "marvell,pxa-timer", pxa_timer_dt_init); | |
219 | ||
220 | /* | |
221 | * Legacy timer init for non device-tree boards. | |
222 | */ | |
223 | void __init pxa_timer_nodt_init(int irq, void __iomem *base) | |
224 | { | |
225 | struct clk *clk; | |
226 | ||
227 | timer_base = base; | |
228 | clk = clk_get(NULL, "OSTIMER0"); | |
229 | if (clk && !IS_ERR(clk)) { | |
230 | clk_prepare_enable(clk); | |
231 | pxa_timer_common_init(irq, clk_get_rate(clk)); | |
232 | } else { | |
233 | pr_crit("%s: unable to get clk\n", __func__); | |
234 | } | |
235 | } |