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1 | /* | |
2 | * Copyright Altera Corporation (C) 2014-2016. All rights reserved. | |
3 | * Copyright 2011-2012 Calxeda, Inc. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | * | |
17 | * Adapted from the highbank_mc_edac driver. | |
18 | */ | |
19 | ||
20 | #include <asm/cacheflush.h> | |
21 | #include <linux/ctype.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/edac.h> | |
24 | #include <linux/genalloc.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/irqchip/chained_irq.h> | |
27 | #include <linux/kernel.h> | |
28 | #include <linux/mfd/syscon.h> | |
29 | #include <linux/of_address.h> | |
30 | #include <linux/of_irq.h> | |
31 | #include <linux/of_platform.h> | |
32 | #include <linux/platform_device.h> | |
33 | #include <linux/regmap.h> | |
34 | #include <linux/types.h> | |
35 | #include <linux/uaccess.h> | |
36 | ||
37 | #include "altera_edac.h" | |
38 | #include "edac_module.h" | |
39 | ||
40 | #define EDAC_MOD_STR "altera_edac" | |
41 | #define EDAC_VERSION "1" | |
42 | #define EDAC_DEVICE "Altera" | |
43 | ||
44 | static const struct altr_sdram_prv_data c5_data = { | |
45 | .ecc_ctrl_offset = CV_CTLCFG_OFST, | |
46 | .ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN, | |
47 | .ecc_stat_offset = CV_DRAMSTS_OFST, | |
48 | .ecc_stat_ce_mask = CV_DRAMSTS_SBEERR, | |
49 | .ecc_stat_ue_mask = CV_DRAMSTS_DBEERR, | |
50 | .ecc_saddr_offset = CV_ERRADDR_OFST, | |
51 | .ecc_daddr_offset = CV_ERRADDR_OFST, | |
52 | .ecc_cecnt_offset = CV_SBECOUNT_OFST, | |
53 | .ecc_uecnt_offset = CV_DBECOUNT_OFST, | |
54 | .ecc_irq_en_offset = CV_DRAMINTR_OFST, | |
55 | .ecc_irq_en_mask = CV_DRAMINTR_INTREN, | |
56 | .ecc_irq_clr_offset = CV_DRAMINTR_OFST, | |
57 | .ecc_irq_clr_mask = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN), | |
58 | .ecc_cnt_rst_offset = CV_DRAMINTR_OFST, | |
59 | .ecc_cnt_rst_mask = CV_DRAMINTR_INTRCLR, | |
60 | .ce_ue_trgr_offset = CV_CTLCFG_OFST, | |
61 | .ce_set_mask = CV_CTLCFG_GEN_SB_ERR, | |
62 | .ue_set_mask = CV_CTLCFG_GEN_DB_ERR, | |
63 | }; | |
64 | ||
65 | static const struct altr_sdram_prv_data a10_data = { | |
66 | .ecc_ctrl_offset = A10_ECCCTRL1_OFST, | |
67 | .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN, | |
68 | .ecc_stat_offset = A10_INTSTAT_OFST, | |
69 | .ecc_stat_ce_mask = A10_INTSTAT_SBEERR, | |
70 | .ecc_stat_ue_mask = A10_INTSTAT_DBEERR, | |
71 | .ecc_saddr_offset = A10_SERRADDR_OFST, | |
72 | .ecc_daddr_offset = A10_DERRADDR_OFST, | |
73 | .ecc_irq_en_offset = A10_ERRINTEN_OFST, | |
74 | .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK, | |
75 | .ecc_irq_clr_offset = A10_INTSTAT_OFST, | |
76 | .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR), | |
77 | .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST, | |
78 | .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK, | |
79 | .ce_ue_trgr_offset = A10_DIAGINTTEST_OFST, | |
80 | .ce_set_mask = A10_DIAGINT_TSERRA_MASK, | |
81 | .ue_set_mask = A10_DIAGINT_TDERRA_MASK, | |
82 | }; | |
83 | ||
84 | /*********************** EDAC Memory Controller Functions ****************/ | |
85 | ||
86 | /* The SDRAM controller uses the EDAC Memory Controller framework. */ | |
87 | ||
88 | static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id) | |
89 | { | |
90 | struct mem_ctl_info *mci = dev_id; | |
91 | struct altr_sdram_mc_data *drvdata = mci->pvt_info; | |
92 | const struct altr_sdram_prv_data *priv = drvdata->data; | |
93 | u32 status, err_count = 1, err_addr; | |
94 | ||
95 | regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status); | |
96 | ||
97 | if (status & priv->ecc_stat_ue_mask) { | |
98 | regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset, | |
99 | &err_addr); | |
100 | if (priv->ecc_uecnt_offset) | |
101 | regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset, | |
102 | &err_count); | |
103 | panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n", | |
104 | err_count, err_addr); | |
105 | } | |
106 | if (status & priv->ecc_stat_ce_mask) { | |
107 | regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset, | |
108 | &err_addr); | |
109 | if (priv->ecc_uecnt_offset) | |
110 | regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset, | |
111 | &err_count); | |
112 | edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count, | |
113 | err_addr >> PAGE_SHIFT, | |
114 | err_addr & ~PAGE_MASK, 0, | |
115 | 0, 0, -1, mci->ctl_name, ""); | |
116 | /* Clear IRQ to resume */ | |
117 | regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset, | |
118 | priv->ecc_irq_clr_mask); | |
119 | ||
120 | return IRQ_HANDLED; | |
121 | } | |
122 | return IRQ_NONE; | |
123 | } | |
124 | ||
125 | static ssize_t altr_sdr_mc_err_inject_write(struct file *file, | |
126 | const char __user *data, | |
127 | size_t count, loff_t *ppos) | |
128 | { | |
129 | struct mem_ctl_info *mci = file->private_data; | |
130 | struct altr_sdram_mc_data *drvdata = mci->pvt_info; | |
131 | const struct altr_sdram_prv_data *priv = drvdata->data; | |
132 | u32 *ptemp; | |
133 | dma_addr_t dma_handle; | |
134 | u32 reg, read_reg; | |
135 | ||
136 | ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL); | |
137 | if (!ptemp) { | |
138 | dma_free_coherent(mci->pdev, 16, ptemp, dma_handle); | |
139 | edac_printk(KERN_ERR, EDAC_MC, | |
140 | "Inject: Buffer Allocation error\n"); | |
141 | return -ENOMEM; | |
142 | } | |
143 | ||
144 | regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset, | |
145 | &read_reg); | |
146 | read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask); | |
147 | ||
148 | /* Error are injected by writing a word while the SBE or DBE | |
149 | * bit in the CTLCFG register is set. Reading the word will | |
150 | * trigger the SBE or DBE error and the corresponding IRQ. | |
151 | */ | |
152 | if (count == 3) { | |
153 | edac_printk(KERN_ALERT, EDAC_MC, | |
154 | "Inject Double bit error\n"); | |
155 | local_irq_disable(); | |
156 | regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, | |
157 | (read_reg | priv->ue_set_mask)); | |
158 | local_irq_enable(); | |
159 | } else { | |
160 | edac_printk(KERN_ALERT, EDAC_MC, | |
161 | "Inject Single bit error\n"); | |
162 | local_irq_disable(); | |
163 | regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, | |
164 | (read_reg | priv->ce_set_mask)); | |
165 | local_irq_enable(); | |
166 | } | |
167 | ||
168 | ptemp[0] = 0x5A5A5A5A; | |
169 | ptemp[1] = 0xA5A5A5A5; | |
170 | ||
171 | /* Clear the error injection bits */ | |
172 | regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg); | |
173 | /* Ensure it has been written out */ | |
174 | wmb(); | |
175 | ||
176 | /* | |
177 | * To trigger the error, we need to read the data back | |
178 | * (the data was written with errors above). | |
179 | * The ACCESS_ONCE macros and printk are used to prevent the | |
180 | * the compiler optimizing these reads out. | |
181 | */ | |
182 | reg = ACCESS_ONCE(ptemp[0]); | |
183 | read_reg = ACCESS_ONCE(ptemp[1]); | |
184 | /* Force Read */ | |
185 | rmb(); | |
186 | ||
187 | edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n", | |
188 | reg, read_reg); | |
189 | ||
190 | dma_free_coherent(mci->pdev, 16, ptemp, dma_handle); | |
191 | ||
192 | return count; | |
193 | } | |
194 | ||
195 | static const struct file_operations altr_sdr_mc_debug_inject_fops = { | |
196 | .open = simple_open, | |
197 | .write = altr_sdr_mc_err_inject_write, | |
198 | .llseek = generic_file_llseek, | |
199 | }; | |
200 | ||
201 | static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci) | |
202 | { | |
203 | if (!IS_ENABLED(CONFIG_EDAC_DEBUG)) | |
204 | return; | |
205 | ||
206 | if (!mci->debugfs) | |
207 | return; | |
208 | ||
209 | edac_debugfs_create_file("altr_trigger", S_IWUSR, mci->debugfs, mci, | |
210 | &altr_sdr_mc_debug_inject_fops); | |
211 | } | |
212 | ||
213 | /* Get total memory size from Open Firmware DTB */ | |
214 | static unsigned long get_total_mem(void) | |
215 | { | |
216 | struct device_node *np = NULL; | |
217 | struct resource res; | |
218 | int ret; | |
219 | unsigned long total_mem = 0; | |
220 | ||
221 | for_each_node_by_type(np, "memory") { | |
222 | ret = of_address_to_resource(np, 0, &res); | |
223 | if (ret) | |
224 | continue; | |
225 | ||
226 | total_mem += resource_size(&res); | |
227 | } | |
228 | edac_dbg(0, "total_mem 0x%lx\n", total_mem); | |
229 | return total_mem; | |
230 | } | |
231 | ||
232 | static const struct of_device_id altr_sdram_ctrl_of_match[] = { | |
233 | { .compatible = "altr,sdram-edac", .data = &c5_data}, | |
234 | { .compatible = "altr,sdram-edac-a10", .data = &a10_data}, | |
235 | {}, | |
236 | }; | |
237 | MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match); | |
238 | ||
239 | static int a10_init(struct regmap *mc_vbase) | |
240 | { | |
241 | if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST, | |
242 | A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) { | |
243 | edac_printk(KERN_ERR, EDAC_MC, | |
244 | "Error setting SB IRQ mode\n"); | |
245 | return -ENODEV; | |
246 | } | |
247 | ||
248 | if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) { | |
249 | edac_printk(KERN_ERR, EDAC_MC, | |
250 | "Error setting trigger count\n"); | |
251 | return -ENODEV; | |
252 | } | |
253 | ||
254 | return 0; | |
255 | } | |
256 | ||
257 | static int a10_unmask_irq(struct platform_device *pdev, u32 mask) | |
258 | { | |
259 | void __iomem *sm_base; | |
260 | int ret = 0; | |
261 | ||
262 | if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32), | |
263 | dev_name(&pdev->dev))) { | |
264 | edac_printk(KERN_ERR, EDAC_MC, | |
265 | "Unable to request mem region\n"); | |
266 | return -EBUSY; | |
267 | } | |
268 | ||
269 | sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32)); | |
270 | if (!sm_base) { | |
271 | edac_printk(KERN_ERR, EDAC_MC, | |
272 | "Unable to ioremap device\n"); | |
273 | ||
274 | ret = -ENOMEM; | |
275 | goto release; | |
276 | } | |
277 | ||
278 | iowrite32(mask, sm_base); | |
279 | ||
280 | iounmap(sm_base); | |
281 | ||
282 | release: | |
283 | release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32)); | |
284 | ||
285 | return ret; | |
286 | } | |
287 | ||
288 | static int altr_sdram_probe(struct platform_device *pdev) | |
289 | { | |
290 | const struct of_device_id *id; | |
291 | struct edac_mc_layer layers[2]; | |
292 | struct mem_ctl_info *mci; | |
293 | struct altr_sdram_mc_data *drvdata; | |
294 | const struct altr_sdram_prv_data *priv; | |
295 | struct regmap *mc_vbase; | |
296 | struct dimm_info *dimm; | |
297 | u32 read_reg; | |
298 | int irq, irq2, res = 0; | |
299 | unsigned long mem_size, irqflags = 0; | |
300 | ||
301 | id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev); | |
302 | if (!id) | |
303 | return -ENODEV; | |
304 | ||
305 | /* Grab the register range from the sdr controller in device tree */ | |
306 | mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, | |
307 | "altr,sdr-syscon"); | |
308 | if (IS_ERR(mc_vbase)) { | |
309 | edac_printk(KERN_ERR, EDAC_MC, | |
310 | "regmap for altr,sdr-syscon lookup failed.\n"); | |
311 | return -ENODEV; | |
312 | } | |
313 | ||
314 | /* Check specific dependencies for the module */ | |
315 | priv = of_match_node(altr_sdram_ctrl_of_match, | |
316 | pdev->dev.of_node)->data; | |
317 | ||
318 | /* Validate the SDRAM controller has ECC enabled */ | |
319 | if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) || | |
320 | ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) { | |
321 | edac_printk(KERN_ERR, EDAC_MC, | |
322 | "No ECC/ECC disabled [0x%08X]\n", read_reg); | |
323 | return -ENODEV; | |
324 | } | |
325 | ||
326 | /* Grab memory size from device tree. */ | |
327 | mem_size = get_total_mem(); | |
328 | if (!mem_size) { | |
329 | edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n"); | |
330 | return -ENODEV; | |
331 | } | |
332 | ||
333 | /* Ensure the SDRAM Interrupt is disabled */ | |
334 | if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset, | |
335 | priv->ecc_irq_en_mask, 0)) { | |
336 | edac_printk(KERN_ERR, EDAC_MC, | |
337 | "Error disabling SDRAM ECC IRQ\n"); | |
338 | return -ENODEV; | |
339 | } | |
340 | ||
341 | /* Toggle to clear the SDRAM Error count */ | |
342 | if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset, | |
343 | priv->ecc_cnt_rst_mask, | |
344 | priv->ecc_cnt_rst_mask)) { | |
345 | edac_printk(KERN_ERR, EDAC_MC, | |
346 | "Error clearing SDRAM ECC count\n"); | |
347 | return -ENODEV; | |
348 | } | |
349 | ||
350 | if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset, | |
351 | priv->ecc_cnt_rst_mask, 0)) { | |
352 | edac_printk(KERN_ERR, EDAC_MC, | |
353 | "Error clearing SDRAM ECC count\n"); | |
354 | return -ENODEV; | |
355 | } | |
356 | ||
357 | irq = platform_get_irq(pdev, 0); | |
358 | if (irq < 0) { | |
359 | edac_printk(KERN_ERR, EDAC_MC, | |
360 | "No irq %d in DT\n", irq); | |
361 | return -ENODEV; | |
362 | } | |
363 | ||
364 | /* Arria10 has a 2nd IRQ */ | |
365 | irq2 = platform_get_irq(pdev, 1); | |
366 | ||
367 | layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; | |
368 | layers[0].size = 1; | |
369 | layers[0].is_virt_csrow = true; | |
370 | layers[1].type = EDAC_MC_LAYER_CHANNEL; | |
371 | layers[1].size = 1; | |
372 | layers[1].is_virt_csrow = false; | |
373 | mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, | |
374 | sizeof(struct altr_sdram_mc_data)); | |
375 | if (!mci) | |
376 | return -ENOMEM; | |
377 | ||
378 | mci->pdev = &pdev->dev; | |
379 | drvdata = mci->pvt_info; | |
380 | drvdata->mc_vbase = mc_vbase; | |
381 | drvdata->data = priv; | |
382 | platform_set_drvdata(pdev, mci); | |
383 | ||
384 | if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) { | |
385 | edac_printk(KERN_ERR, EDAC_MC, | |
386 | "Unable to get managed device resource\n"); | |
387 | res = -ENOMEM; | |
388 | goto free; | |
389 | } | |
390 | ||
391 | mci->mtype_cap = MEM_FLAG_DDR3; | |
392 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; | |
393 | mci->edac_cap = EDAC_FLAG_SECDED; | |
394 | mci->mod_name = EDAC_MOD_STR; | |
395 | mci->mod_ver = EDAC_VERSION; | |
396 | mci->ctl_name = dev_name(&pdev->dev); | |
397 | mci->scrub_mode = SCRUB_SW_SRC; | |
398 | mci->dev_name = dev_name(&pdev->dev); | |
399 | ||
400 | dimm = *mci->dimms; | |
401 | dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1; | |
402 | dimm->grain = 8; | |
403 | dimm->dtype = DEV_X8; | |
404 | dimm->mtype = MEM_DDR3; | |
405 | dimm->edac_mode = EDAC_SECDED; | |
406 | ||
407 | res = edac_mc_add_mc(mci); | |
408 | if (res < 0) | |
409 | goto err; | |
410 | ||
411 | /* Only the Arria10 has separate IRQs */ | |
412 | if (irq2 > 0) { | |
413 | /* Arria10 specific initialization */ | |
414 | res = a10_init(mc_vbase); | |
415 | if (res < 0) | |
416 | goto err2; | |
417 | ||
418 | res = devm_request_irq(&pdev->dev, irq2, | |
419 | altr_sdram_mc_err_handler, | |
420 | IRQF_SHARED, dev_name(&pdev->dev), mci); | |
421 | if (res < 0) { | |
422 | edac_mc_printk(mci, KERN_ERR, | |
423 | "Unable to request irq %d\n", irq2); | |
424 | res = -ENODEV; | |
425 | goto err2; | |
426 | } | |
427 | ||
428 | res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK); | |
429 | if (res < 0) | |
430 | goto err2; | |
431 | ||
432 | irqflags = IRQF_SHARED; | |
433 | } | |
434 | ||
435 | res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler, | |
436 | irqflags, dev_name(&pdev->dev), mci); | |
437 | if (res < 0) { | |
438 | edac_mc_printk(mci, KERN_ERR, | |
439 | "Unable to request irq %d\n", irq); | |
440 | res = -ENODEV; | |
441 | goto err2; | |
442 | } | |
443 | ||
444 | /* Infrastructure ready - enable the IRQ */ | |
445 | if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset, | |
446 | priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) { | |
447 | edac_mc_printk(mci, KERN_ERR, | |
448 | "Error enabling SDRAM ECC IRQ\n"); | |
449 | res = -ENODEV; | |
450 | goto err2; | |
451 | } | |
452 | ||
453 | altr_sdr_mc_create_debugfs_nodes(mci); | |
454 | ||
455 | devres_close_group(&pdev->dev, NULL); | |
456 | ||
457 | return 0; | |
458 | ||
459 | err2: | |
460 | edac_mc_del_mc(&pdev->dev); | |
461 | err: | |
462 | devres_release_group(&pdev->dev, NULL); | |
463 | free: | |
464 | edac_mc_free(mci); | |
465 | edac_printk(KERN_ERR, EDAC_MC, | |
466 | "EDAC Probe Failed; Error %d\n", res); | |
467 | ||
468 | return res; | |
469 | } | |
470 | ||
471 | static int altr_sdram_remove(struct platform_device *pdev) | |
472 | { | |
473 | struct mem_ctl_info *mci = platform_get_drvdata(pdev); | |
474 | ||
475 | edac_mc_del_mc(&pdev->dev); | |
476 | edac_mc_free(mci); | |
477 | platform_set_drvdata(pdev, NULL); | |
478 | ||
479 | return 0; | |
480 | } | |
481 | ||
482 | /* | |
483 | * If you want to suspend, need to disable EDAC by removing it | |
484 | * from the device tree or defconfig. | |
485 | */ | |
486 | #ifdef CONFIG_PM | |
487 | static int altr_sdram_prepare(struct device *dev) | |
488 | { | |
489 | pr_err("Suspend not allowed when EDAC is enabled.\n"); | |
490 | ||
491 | return -EPERM; | |
492 | } | |
493 | ||
494 | static const struct dev_pm_ops altr_sdram_pm_ops = { | |
495 | .prepare = altr_sdram_prepare, | |
496 | }; | |
497 | #endif | |
498 | ||
499 | static struct platform_driver altr_sdram_edac_driver = { | |
500 | .probe = altr_sdram_probe, | |
501 | .remove = altr_sdram_remove, | |
502 | .driver = { | |
503 | .name = "altr_sdram_edac", | |
504 | #ifdef CONFIG_PM | |
505 | .pm = &altr_sdram_pm_ops, | |
506 | #endif | |
507 | .of_match_table = altr_sdram_ctrl_of_match, | |
508 | }, | |
509 | }; | |
510 | ||
511 | module_platform_driver(altr_sdram_edac_driver); | |
512 | ||
513 | /************************* EDAC Parent Probe *************************/ | |
514 | ||
515 | static const struct of_device_id altr_edac_device_of_match[]; | |
516 | ||
517 | static const struct of_device_id altr_edac_of_match[] = { | |
518 | { .compatible = "altr,socfpga-ecc-manager" }, | |
519 | {}, | |
520 | }; | |
521 | MODULE_DEVICE_TABLE(of, altr_edac_of_match); | |
522 | ||
523 | static int altr_edac_probe(struct platform_device *pdev) | |
524 | { | |
525 | of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match, | |
526 | NULL, &pdev->dev); | |
527 | return 0; | |
528 | } | |
529 | ||
530 | static struct platform_driver altr_edac_driver = { | |
531 | .probe = altr_edac_probe, | |
532 | .driver = { | |
533 | .name = "socfpga_ecc_manager", | |
534 | .of_match_table = altr_edac_of_match, | |
535 | }, | |
536 | }; | |
537 | module_platform_driver(altr_edac_driver); | |
538 | ||
539 | /************************* EDAC Device Functions *************************/ | |
540 | ||
541 | /* | |
542 | * EDAC Device Functions (shared between various IPs). | |
543 | * The discrete memories use the EDAC Device framework. The probe | |
544 | * and error handling functions are very similar between memories | |
545 | * so they are shared. The memory allocation and freeing for EDAC | |
546 | * trigger testing are different for each memory. | |
547 | */ | |
548 | ||
549 | static const struct edac_device_prv_data ocramecc_data; | |
550 | static const struct edac_device_prv_data l2ecc_data; | |
551 | static const struct edac_device_prv_data a10_ocramecc_data; | |
552 | static const struct edac_device_prv_data a10_l2ecc_data; | |
553 | ||
554 | static irqreturn_t altr_edac_device_handler(int irq, void *dev_id) | |
555 | { | |
556 | irqreturn_t ret_value = IRQ_NONE; | |
557 | struct edac_device_ctl_info *dci = dev_id; | |
558 | struct altr_edac_device_dev *drvdata = dci->pvt_info; | |
559 | const struct edac_device_prv_data *priv = drvdata->data; | |
560 | ||
561 | if (irq == drvdata->sb_irq) { | |
562 | if (priv->ce_clear_mask) | |
563 | writel(priv->ce_clear_mask, drvdata->base); | |
564 | edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name); | |
565 | ret_value = IRQ_HANDLED; | |
566 | } else if (irq == drvdata->db_irq) { | |
567 | if (priv->ue_clear_mask) | |
568 | writel(priv->ue_clear_mask, drvdata->base); | |
569 | edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name); | |
570 | panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); | |
571 | ret_value = IRQ_HANDLED; | |
572 | } else { | |
573 | WARN_ON(1); | |
574 | } | |
575 | ||
576 | return ret_value; | |
577 | } | |
578 | ||
579 | static ssize_t altr_edac_device_trig(struct file *file, | |
580 | const char __user *user_buf, | |
581 | size_t count, loff_t *ppos) | |
582 | ||
583 | { | |
584 | u32 *ptemp, i, error_mask; | |
585 | int result = 0; | |
586 | u8 trig_type; | |
587 | unsigned long flags; | |
588 | struct edac_device_ctl_info *edac_dci = file->private_data; | |
589 | struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; | |
590 | const struct edac_device_prv_data *priv = drvdata->data; | |
591 | void *generic_ptr = edac_dci->dev; | |
592 | ||
593 | if (!user_buf || get_user(trig_type, user_buf)) | |
594 | return -EFAULT; | |
595 | ||
596 | if (!priv->alloc_mem) | |
597 | return -ENOMEM; | |
598 | ||
599 | /* | |
600 | * Note that generic_ptr is initialized to the device * but in | |
601 | * some alloc_functions, this is overridden and returns data. | |
602 | */ | |
603 | ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr); | |
604 | if (!ptemp) { | |
605 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
606 | "Inject: Buffer Allocation error\n"); | |
607 | return -ENOMEM; | |
608 | } | |
609 | ||
610 | if (trig_type == ALTR_UE_TRIGGER_CHAR) | |
611 | error_mask = priv->ue_set_mask; | |
612 | else | |
613 | error_mask = priv->ce_set_mask; | |
614 | ||
615 | edac_printk(KERN_ALERT, EDAC_DEVICE, | |
616 | "Trigger Error Mask (0x%X)\n", error_mask); | |
617 | ||
618 | local_irq_save(flags); | |
619 | /* write ECC corrupted data out. */ | |
620 | for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) { | |
621 | /* Read data so we're in the correct state */ | |
622 | rmb(); | |
623 | if (ACCESS_ONCE(ptemp[i])) | |
624 | result = -1; | |
625 | /* Toggle Error bit (it is latched), leave ECC enabled */ | |
626 | writel(error_mask, (drvdata->base + priv->set_err_ofst)); | |
627 | writel(priv->ecc_enable_mask, (drvdata->base + | |
628 | priv->set_err_ofst)); | |
629 | ptemp[i] = i; | |
630 | } | |
631 | /* Ensure it has been written out */ | |
632 | wmb(); | |
633 | local_irq_restore(flags); | |
634 | ||
635 | if (result) | |
636 | edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n"); | |
637 | ||
638 | /* Read out written data. ECC error caused here */ | |
639 | for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++) | |
640 | if (ACCESS_ONCE(ptemp[i]) != i) | |
641 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
642 | "Read doesn't match written data\n"); | |
643 | ||
644 | if (priv->free_mem) | |
645 | priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr); | |
646 | ||
647 | return count; | |
648 | } | |
649 | ||
650 | static const struct file_operations altr_edac_device_inject_fops = { | |
651 | .open = simple_open, | |
652 | .write = altr_edac_device_trig, | |
653 | .llseek = generic_file_llseek, | |
654 | }; | |
655 | ||
656 | static ssize_t altr_edac_a10_device_trig(struct file *file, | |
657 | const char __user *user_buf, | |
658 | size_t count, loff_t *ppos); | |
659 | ||
660 | static const struct file_operations altr_edac_a10_device_inject_fops = { | |
661 | .open = simple_open, | |
662 | .write = altr_edac_a10_device_trig, | |
663 | .llseek = generic_file_llseek, | |
664 | }; | |
665 | ||
666 | static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci, | |
667 | const struct edac_device_prv_data *priv) | |
668 | { | |
669 | struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; | |
670 | ||
671 | if (!IS_ENABLED(CONFIG_EDAC_DEBUG)) | |
672 | return; | |
673 | ||
674 | drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name); | |
675 | if (!drvdata->debugfs_dir) | |
676 | return; | |
677 | ||
678 | if (!edac_debugfs_create_file("altr_trigger", S_IWUSR, | |
679 | drvdata->debugfs_dir, edac_dci, | |
680 | priv->inject_fops)) | |
681 | debugfs_remove_recursive(drvdata->debugfs_dir); | |
682 | } | |
683 | ||
684 | static const struct of_device_id altr_edac_device_of_match[] = { | |
685 | #ifdef CONFIG_EDAC_ALTERA_L2C | |
686 | { .compatible = "altr,socfpga-l2-ecc", .data = &l2ecc_data }, | |
687 | #endif | |
688 | #ifdef CONFIG_EDAC_ALTERA_OCRAM | |
689 | { .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data }, | |
690 | #endif | |
691 | {}, | |
692 | }; | |
693 | MODULE_DEVICE_TABLE(of, altr_edac_device_of_match); | |
694 | ||
695 | /* | |
696 | * altr_edac_device_probe() | |
697 | * This is a generic EDAC device driver that will support | |
698 | * various Altera memory devices such as the L2 cache ECC and | |
699 | * OCRAM ECC as well as the memories for other peripherals. | |
700 | * Module specific initialization is done by passing the | |
701 | * function index in the device tree. | |
702 | */ | |
703 | static int altr_edac_device_probe(struct platform_device *pdev) | |
704 | { | |
705 | struct edac_device_ctl_info *dci; | |
706 | struct altr_edac_device_dev *drvdata; | |
707 | struct resource *r; | |
708 | int res = 0; | |
709 | struct device_node *np = pdev->dev.of_node; | |
710 | char *ecc_name = (char *)np->name; | |
711 | static int dev_instance; | |
712 | ||
713 | if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) { | |
714 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
715 | "Unable to open devm\n"); | |
716 | return -ENOMEM; | |
717 | } | |
718 | ||
719 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
720 | if (!r) { | |
721 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
722 | "Unable to get mem resource\n"); | |
723 | res = -ENODEV; | |
724 | goto fail; | |
725 | } | |
726 | ||
727 | if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r), | |
728 | dev_name(&pdev->dev))) { | |
729 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
730 | "%s:Error requesting mem region\n", ecc_name); | |
731 | res = -EBUSY; | |
732 | goto fail; | |
733 | } | |
734 | ||
735 | dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name, | |
736 | 1, ecc_name, 1, 0, NULL, 0, | |
737 | dev_instance++); | |
738 | ||
739 | if (!dci) { | |
740 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
741 | "%s: Unable to allocate EDAC device\n", ecc_name); | |
742 | res = -ENOMEM; | |
743 | goto fail; | |
744 | } | |
745 | ||
746 | drvdata = dci->pvt_info; | |
747 | dci->dev = &pdev->dev; | |
748 | platform_set_drvdata(pdev, dci); | |
749 | drvdata->edac_dev_name = ecc_name; | |
750 | ||
751 | drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r)); | |
752 | if (!drvdata->base) | |
753 | goto fail1; | |
754 | ||
755 | /* Get driver specific data for this EDAC device */ | |
756 | drvdata->data = of_match_node(altr_edac_device_of_match, np)->data; | |
757 | ||
758 | /* Check specific dependencies for the module */ | |
759 | if (drvdata->data->setup) { | |
760 | res = drvdata->data->setup(drvdata); | |
761 | if (res) | |
762 | goto fail1; | |
763 | } | |
764 | ||
765 | drvdata->sb_irq = platform_get_irq(pdev, 0); | |
766 | res = devm_request_irq(&pdev->dev, drvdata->sb_irq, | |
767 | altr_edac_device_handler, | |
768 | 0, dev_name(&pdev->dev), dci); | |
769 | if (res) | |
770 | goto fail1; | |
771 | ||
772 | drvdata->db_irq = platform_get_irq(pdev, 1); | |
773 | res = devm_request_irq(&pdev->dev, drvdata->db_irq, | |
774 | altr_edac_device_handler, | |
775 | 0, dev_name(&pdev->dev), dci); | |
776 | if (res) | |
777 | goto fail1; | |
778 | ||
779 | dci->mod_name = "Altera ECC Manager"; | |
780 | dci->dev_name = drvdata->edac_dev_name; | |
781 | ||
782 | res = edac_device_add_device(dci); | |
783 | if (res) | |
784 | goto fail1; | |
785 | ||
786 | altr_create_edacdev_dbgfs(dci, drvdata->data); | |
787 | ||
788 | devres_close_group(&pdev->dev, NULL); | |
789 | ||
790 | return 0; | |
791 | ||
792 | fail1: | |
793 | edac_device_free_ctl_info(dci); | |
794 | fail: | |
795 | devres_release_group(&pdev->dev, NULL); | |
796 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
797 | "%s:Error setting up EDAC device: %d\n", ecc_name, res); | |
798 | ||
799 | return res; | |
800 | } | |
801 | ||
802 | static int altr_edac_device_remove(struct platform_device *pdev) | |
803 | { | |
804 | struct edac_device_ctl_info *dci = platform_get_drvdata(pdev); | |
805 | struct altr_edac_device_dev *drvdata = dci->pvt_info; | |
806 | ||
807 | debugfs_remove_recursive(drvdata->debugfs_dir); | |
808 | edac_device_del_device(&pdev->dev); | |
809 | edac_device_free_ctl_info(dci); | |
810 | ||
811 | return 0; | |
812 | } | |
813 | ||
814 | static struct platform_driver altr_edac_device_driver = { | |
815 | .probe = altr_edac_device_probe, | |
816 | .remove = altr_edac_device_remove, | |
817 | .driver = { | |
818 | .name = "altr_edac_device", | |
819 | .of_match_table = altr_edac_device_of_match, | |
820 | }, | |
821 | }; | |
822 | module_platform_driver(altr_edac_device_driver); | |
823 | ||
824 | /******************* Arria10 Device ECC Shared Functions *****************/ | |
825 | ||
826 | /* | |
827 | * Test for memory's ECC dependencies upon entry because platform specific | |
828 | * startup should have initialized the memory and enabled the ECC. | |
829 | * Can't turn on ECC here because accessing un-initialized memory will | |
830 | * cause CE/UE errors possibly causing an ABORT. | |
831 | */ | |
832 | static int __maybe_unused | |
833 | altr_check_ecc_deps(struct altr_edac_device_dev *device) | |
834 | { | |
835 | void __iomem *base = device->base; | |
836 | const struct edac_device_prv_data *prv = device->data; | |
837 | ||
838 | if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask) | |
839 | return 0; | |
840 | ||
841 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
842 | "%s: No ECC present or ECC disabled.\n", | |
843 | device->edac_dev_name); | |
844 | return -ENODEV; | |
845 | } | |
846 | ||
847 | static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id) | |
848 | { | |
849 | struct altr_edac_device_dev *dci = dev_id; | |
850 | void __iomem *base = dci->base; | |
851 | ||
852 | if (irq == dci->sb_irq) { | |
853 | writel(ALTR_A10_ECC_SERRPENA, | |
854 | base + ALTR_A10_ECC_INTSTAT_OFST); | |
855 | edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name); | |
856 | ||
857 | return IRQ_HANDLED; | |
858 | } else if (irq == dci->db_irq) { | |
859 | writel(ALTR_A10_ECC_DERRPENA, | |
860 | base + ALTR_A10_ECC_INTSTAT_OFST); | |
861 | edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name); | |
862 | if (dci->data->panic) | |
863 | panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); | |
864 | ||
865 | return IRQ_HANDLED; | |
866 | } | |
867 | ||
868 | WARN_ON(1); | |
869 | ||
870 | return IRQ_NONE; | |
871 | } | |
872 | ||
873 | /******************* Arria10 Memory Buffer Functions *********************/ | |
874 | ||
875 | static inline int a10_get_irq_mask(struct device_node *np) | |
876 | { | |
877 | int irq; | |
878 | const u32 *handle = of_get_property(np, "interrupts", NULL); | |
879 | ||
880 | if (!handle) | |
881 | return -ENODEV; | |
882 | irq = be32_to_cpup(handle); | |
883 | return irq; | |
884 | } | |
885 | ||
886 | static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr) | |
887 | { | |
888 | u32 value = readl(ioaddr); | |
889 | ||
890 | value |= bit_mask; | |
891 | writel(value, ioaddr); | |
892 | } | |
893 | ||
894 | static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr) | |
895 | { | |
896 | u32 value = readl(ioaddr); | |
897 | ||
898 | value &= ~bit_mask; | |
899 | writel(value, ioaddr); | |
900 | } | |
901 | ||
902 | static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr) | |
903 | { | |
904 | u32 value = readl(ioaddr); | |
905 | ||
906 | return (value & bit_mask) ? 1 : 0; | |
907 | } | |
908 | ||
909 | /* | |
910 | * This function uses the memory initialization block in the Arria10 ECC | |
911 | * controller to initialize/clear the entire memory data and ECC data. | |
912 | */ | |
913 | static int __maybe_unused altr_init_memory_port(void __iomem *ioaddr, int port) | |
914 | { | |
915 | int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US; | |
916 | u32 init_mask, stat_mask, clear_mask; | |
917 | int ret = 0; | |
918 | ||
919 | if (port) { | |
920 | init_mask = ALTR_A10_ECC_INITB; | |
921 | stat_mask = ALTR_A10_ECC_INITCOMPLETEB; | |
922 | clear_mask = ALTR_A10_ECC_ERRPENB_MASK; | |
923 | } else { | |
924 | init_mask = ALTR_A10_ECC_INITA; | |
925 | stat_mask = ALTR_A10_ECC_INITCOMPLETEA; | |
926 | clear_mask = ALTR_A10_ECC_ERRPENA_MASK; | |
927 | } | |
928 | ||
929 | ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST)); | |
930 | while (limit--) { | |
931 | if (ecc_test_bits(stat_mask, | |
932 | (ioaddr + ALTR_A10_ECC_INITSTAT_OFST))) | |
933 | break; | |
934 | udelay(1); | |
935 | } | |
936 | if (limit < 0) | |
937 | ret = -EBUSY; | |
938 | ||
939 | /* Clear any pending ECC interrupts */ | |
940 | writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST)); | |
941 | ||
942 | return ret; | |
943 | } | |
944 | ||
945 | static __init int __maybe_unused | |
946 | altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask, | |
947 | u32 ecc_ctrl_en_mask, bool dual_port) | |
948 | { | |
949 | int ret = 0; | |
950 | void __iomem *ecc_block_base; | |
951 | struct regmap *ecc_mgr_map; | |
952 | char *ecc_name; | |
953 | struct device_node *np_eccmgr; | |
954 | ||
955 | ecc_name = (char *)np->name; | |
956 | ||
957 | /* Get the ECC Manager - parent of the device EDACs */ | |
958 | np_eccmgr = of_get_parent(np); | |
959 | ecc_mgr_map = syscon_regmap_lookup_by_phandle(np_eccmgr, | |
960 | "altr,sysmgr-syscon"); | |
961 | of_node_put(np_eccmgr); | |
962 | if (IS_ERR(ecc_mgr_map)) { | |
963 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
964 | "Unable to get syscon altr,sysmgr-syscon\n"); | |
965 | return -ENODEV; | |
966 | } | |
967 | ||
968 | /* Map the ECC Block */ | |
969 | ecc_block_base = of_iomap(np, 0); | |
970 | if (!ecc_block_base) { | |
971 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
972 | "Unable to map %s ECC block\n", ecc_name); | |
973 | return -ENODEV; | |
974 | } | |
975 | ||
976 | /* Disable ECC */ | |
977 | regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, irq_mask); | |
978 | writel(ALTR_A10_ECC_SERRINTEN, | |
979 | (ecc_block_base + ALTR_A10_ECC_ERRINTENR_OFST)); | |
980 | ecc_clear_bits(ecc_ctrl_en_mask, | |
981 | (ecc_block_base + ALTR_A10_ECC_CTRL_OFST)); | |
982 | /* Ensure all writes complete */ | |
983 | wmb(); | |
984 | /* Use HW initialization block to initialize memory for ECC */ | |
985 | ret = altr_init_memory_port(ecc_block_base, 0); | |
986 | if (ret) { | |
987 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
988 | "ECC: cannot init %s PORTA memory\n", ecc_name); | |
989 | goto out; | |
990 | } | |
991 | ||
992 | if (dual_port) { | |
993 | ret = altr_init_memory_port(ecc_block_base, 1); | |
994 | if (ret) { | |
995 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
996 | "ECC: cannot init %s PORTB memory\n", | |
997 | ecc_name); | |
998 | goto out; | |
999 | } | |
1000 | } | |
1001 | ||
1002 | /* Interrupt mode set to every SBERR */ | |
1003 | regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST, | |
1004 | ALTR_A10_ECC_INTMODE); | |
1005 | /* Enable ECC */ | |
1006 | ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base + | |
1007 | ALTR_A10_ECC_CTRL_OFST)); | |
1008 | writel(ALTR_A10_ECC_SERRINTEN, | |
1009 | (ecc_block_base + ALTR_A10_ECC_ERRINTENS_OFST)); | |
1010 | regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, irq_mask); | |
1011 | /* Ensure all writes complete */ | |
1012 | wmb(); | |
1013 | out: | |
1014 | iounmap(ecc_block_base); | |
1015 | return ret; | |
1016 | } | |
1017 | ||
1018 | static int socfpga_is_a10(void) | |
1019 | { | |
1020 | return of_machine_is_compatible("altr,socfpga-arria10"); | |
1021 | } | |
1022 | ||
1023 | static int validate_parent_available(struct device_node *np); | |
1024 | static const struct of_device_id altr_edac_a10_device_of_match[]; | |
1025 | static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat) | |
1026 | { | |
1027 | int irq; | |
1028 | struct device_node *child, *np; | |
1029 | ||
1030 | if (!socfpga_is_a10()) | |
1031 | return -ENODEV; | |
1032 | ||
1033 | np = of_find_compatible_node(NULL, NULL, | |
1034 | "altr,socfpga-a10-ecc-manager"); | |
1035 | if (!np) { | |
1036 | edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n"); | |
1037 | return -ENODEV; | |
1038 | } | |
1039 | ||
1040 | for_each_child_of_node(np, child) { | |
1041 | const struct of_device_id *pdev_id; | |
1042 | const struct edac_device_prv_data *prv; | |
1043 | ||
1044 | if (!of_device_is_available(child)) | |
1045 | continue; | |
1046 | if (!of_device_is_compatible(child, compat)) | |
1047 | continue; | |
1048 | ||
1049 | if (validate_parent_available(child)) | |
1050 | continue; | |
1051 | ||
1052 | irq = a10_get_irq_mask(child); | |
1053 | if (irq < 0) | |
1054 | continue; | |
1055 | ||
1056 | /* Get matching node and check for valid result */ | |
1057 | pdev_id = of_match_node(altr_edac_a10_device_of_match, child); | |
1058 | if (IS_ERR_OR_NULL(pdev_id)) | |
1059 | continue; | |
1060 | ||
1061 | /* Validate private data pointer before dereferencing */ | |
1062 | prv = pdev_id->data; | |
1063 | if (!prv) | |
1064 | continue; | |
1065 | ||
1066 | altr_init_a10_ecc_block(child, BIT(irq), | |
1067 | prv->ecc_enable_mask, 0); | |
1068 | } | |
1069 | ||
1070 | of_node_put(np); | |
1071 | return 0; | |
1072 | } | |
1073 | ||
1074 | /*********************** OCRAM EDAC Device Functions *********************/ | |
1075 | ||
1076 | #ifdef CONFIG_EDAC_ALTERA_OCRAM | |
1077 | ||
1078 | static void *ocram_alloc_mem(size_t size, void **other) | |
1079 | { | |
1080 | struct device_node *np; | |
1081 | struct gen_pool *gp; | |
1082 | void *sram_addr; | |
1083 | ||
1084 | np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc"); | |
1085 | if (!np) | |
1086 | return NULL; | |
1087 | ||
1088 | gp = of_gen_pool_get(np, "iram", 0); | |
1089 | of_node_put(np); | |
1090 | if (!gp) | |
1091 | return NULL; | |
1092 | ||
1093 | sram_addr = (void *)gen_pool_alloc(gp, size); | |
1094 | if (!sram_addr) | |
1095 | return NULL; | |
1096 | ||
1097 | memset(sram_addr, 0, size); | |
1098 | /* Ensure data is written out */ | |
1099 | wmb(); | |
1100 | ||
1101 | /* Remember this handle for freeing later */ | |
1102 | *other = gp; | |
1103 | ||
1104 | return sram_addr; | |
1105 | } | |
1106 | ||
1107 | static void ocram_free_mem(void *p, size_t size, void *other) | |
1108 | { | |
1109 | gen_pool_free((struct gen_pool *)other, (u32)p, size); | |
1110 | } | |
1111 | ||
1112 | static const struct edac_device_prv_data ocramecc_data = { | |
1113 | .setup = altr_check_ecc_deps, | |
1114 | .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR), | |
1115 | .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR), | |
1116 | .alloc_mem = ocram_alloc_mem, | |
1117 | .free_mem = ocram_free_mem, | |
1118 | .ecc_enable_mask = ALTR_OCR_ECC_EN, | |
1119 | .ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET, | |
1120 | .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS), | |
1121 | .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD), | |
1122 | .set_err_ofst = ALTR_OCR_ECC_REG_OFFSET, | |
1123 | .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE, | |
1124 | .inject_fops = &altr_edac_device_inject_fops, | |
1125 | }; | |
1126 | ||
1127 | static const struct edac_device_prv_data a10_ocramecc_data = { | |
1128 | .setup = altr_check_ecc_deps, | |
1129 | .ce_clear_mask = ALTR_A10_ECC_SERRPENA, | |
1130 | .ue_clear_mask = ALTR_A10_ECC_DERRPENA, | |
1131 | .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM, | |
1132 | .ecc_enable_mask = ALTR_A10_OCRAM_ECC_EN_CTL, | |
1133 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1134 | .ce_set_mask = ALTR_A10_ECC_TSERRA, | |
1135 | .ue_set_mask = ALTR_A10_ECC_TDERRA, | |
1136 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1137 | .ecc_irq_handler = altr_edac_a10_ecc_irq, | |
1138 | .inject_fops = &altr_edac_a10_device_inject_fops, | |
1139 | /* | |
1140 | * OCRAM panic on uncorrectable error because sleep/resume | |
1141 | * functions and FPGA contents are stored in OCRAM. Prefer | |
1142 | * a kernel panic over executing/loading corrupted data. | |
1143 | */ | |
1144 | .panic = true, | |
1145 | }; | |
1146 | ||
1147 | #endif /* CONFIG_EDAC_ALTERA_OCRAM */ | |
1148 | ||
1149 | /********************* L2 Cache EDAC Device Functions ********************/ | |
1150 | ||
1151 | #ifdef CONFIG_EDAC_ALTERA_L2C | |
1152 | ||
1153 | static void *l2_alloc_mem(size_t size, void **other) | |
1154 | { | |
1155 | struct device *dev = *other; | |
1156 | void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL); | |
1157 | ||
1158 | if (!ptemp) | |
1159 | return NULL; | |
1160 | ||
1161 | /* Make sure everything is written out */ | |
1162 | wmb(); | |
1163 | ||
1164 | /* | |
1165 | * Clean all cache levels up to LoC (includes L2) | |
1166 | * This ensures the corrupted data is written into | |
1167 | * L2 cache for readback test (which causes ECC error). | |
1168 | */ | |
1169 | flush_cache_all(); | |
1170 | ||
1171 | return ptemp; | |
1172 | } | |
1173 | ||
1174 | static void l2_free_mem(void *p, size_t size, void *other) | |
1175 | { | |
1176 | struct device *dev = other; | |
1177 | ||
1178 | if (dev && p) | |
1179 | devm_kfree(dev, p); | |
1180 | } | |
1181 | ||
1182 | /* | |
1183 | * altr_l2_check_deps() | |
1184 | * Test for L2 cache ECC dependencies upon entry because | |
1185 | * platform specific startup should have initialized the L2 | |
1186 | * memory and enabled the ECC. | |
1187 | * Bail if ECC is not enabled. | |
1188 | * Note that L2 Cache Enable is forced at build time. | |
1189 | */ | |
1190 | static int altr_l2_check_deps(struct altr_edac_device_dev *device) | |
1191 | { | |
1192 | void __iomem *base = device->base; | |
1193 | const struct edac_device_prv_data *prv = device->data; | |
1194 | ||
1195 | if ((readl(base) & prv->ecc_enable_mask) == | |
1196 | prv->ecc_enable_mask) | |
1197 | return 0; | |
1198 | ||
1199 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1200 | "L2: No ECC present, or ECC disabled\n"); | |
1201 | return -ENODEV; | |
1202 | } | |
1203 | ||
1204 | static irqreturn_t altr_edac_a10_l2_irq(int irq, void *dev_id) | |
1205 | { | |
1206 | struct altr_edac_device_dev *dci = dev_id; | |
1207 | ||
1208 | if (irq == dci->sb_irq) { | |
1209 | regmap_write(dci->edac->ecc_mgr_map, | |
1210 | A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST, | |
1211 | A10_SYSGMR_MPU_CLEAR_L2_ECC_SB); | |
1212 | edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name); | |
1213 | ||
1214 | return IRQ_HANDLED; | |
1215 | } else if (irq == dci->db_irq) { | |
1216 | regmap_write(dci->edac->ecc_mgr_map, | |
1217 | A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST, | |
1218 | A10_SYSGMR_MPU_CLEAR_L2_ECC_MB); | |
1219 | edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name); | |
1220 | panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); | |
1221 | ||
1222 | return IRQ_HANDLED; | |
1223 | } | |
1224 | ||
1225 | WARN_ON(1); | |
1226 | ||
1227 | return IRQ_NONE; | |
1228 | } | |
1229 | ||
1230 | static const struct edac_device_prv_data l2ecc_data = { | |
1231 | .setup = altr_l2_check_deps, | |
1232 | .ce_clear_mask = 0, | |
1233 | .ue_clear_mask = 0, | |
1234 | .alloc_mem = l2_alloc_mem, | |
1235 | .free_mem = l2_free_mem, | |
1236 | .ecc_enable_mask = ALTR_L2_ECC_EN, | |
1237 | .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS), | |
1238 | .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD), | |
1239 | .set_err_ofst = ALTR_L2_ECC_REG_OFFSET, | |
1240 | .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE, | |
1241 | .inject_fops = &altr_edac_device_inject_fops, | |
1242 | }; | |
1243 | ||
1244 | static const struct edac_device_prv_data a10_l2ecc_data = { | |
1245 | .setup = altr_l2_check_deps, | |
1246 | .ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR, | |
1247 | .ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR, | |
1248 | .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2, | |
1249 | .alloc_mem = l2_alloc_mem, | |
1250 | .free_mem = l2_free_mem, | |
1251 | .ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL, | |
1252 | .ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK, | |
1253 | .ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK, | |
1254 | .set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST, | |
1255 | .ecc_irq_handler = altr_edac_a10_l2_irq, | |
1256 | .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE, | |
1257 | .inject_fops = &altr_edac_device_inject_fops, | |
1258 | }; | |
1259 | ||
1260 | #endif /* CONFIG_EDAC_ALTERA_L2C */ | |
1261 | ||
1262 | /********************* Ethernet Device Functions ********************/ | |
1263 | ||
1264 | #ifdef CONFIG_EDAC_ALTERA_ETHERNET | |
1265 | ||
1266 | static const struct edac_device_prv_data a10_enetecc_data = { | |
1267 | .setup = altr_check_ecc_deps, | |
1268 | .ce_clear_mask = ALTR_A10_ECC_SERRPENA, | |
1269 | .ue_clear_mask = ALTR_A10_ECC_DERRPENA, | |
1270 | .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, | |
1271 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1272 | .ce_set_mask = ALTR_A10_ECC_TSERRA, | |
1273 | .ue_set_mask = ALTR_A10_ECC_TDERRA, | |
1274 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1275 | .ecc_irq_handler = altr_edac_a10_ecc_irq, | |
1276 | .inject_fops = &altr_edac_a10_device_inject_fops, | |
1277 | }; | |
1278 | ||
1279 | static int __init socfpga_init_ethernet_ecc(void) | |
1280 | { | |
1281 | return altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc"); | |
1282 | } | |
1283 | ||
1284 | early_initcall(socfpga_init_ethernet_ecc); | |
1285 | ||
1286 | #endif /* CONFIG_EDAC_ALTERA_ETHERNET */ | |
1287 | ||
1288 | /********************** NAND Device Functions **********************/ | |
1289 | ||
1290 | #ifdef CONFIG_EDAC_ALTERA_NAND | |
1291 | ||
1292 | static const struct edac_device_prv_data a10_nandecc_data = { | |
1293 | .setup = altr_check_ecc_deps, | |
1294 | .ce_clear_mask = ALTR_A10_ECC_SERRPENA, | |
1295 | .ue_clear_mask = ALTR_A10_ECC_DERRPENA, | |
1296 | .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, | |
1297 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1298 | .ce_set_mask = ALTR_A10_ECC_TSERRA, | |
1299 | .ue_set_mask = ALTR_A10_ECC_TDERRA, | |
1300 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1301 | .ecc_irq_handler = altr_edac_a10_ecc_irq, | |
1302 | .inject_fops = &altr_edac_a10_device_inject_fops, | |
1303 | }; | |
1304 | ||
1305 | static int __init socfpga_init_nand_ecc(void) | |
1306 | { | |
1307 | return altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc"); | |
1308 | } | |
1309 | ||
1310 | early_initcall(socfpga_init_nand_ecc); | |
1311 | ||
1312 | #endif /* CONFIG_EDAC_ALTERA_NAND */ | |
1313 | ||
1314 | /********************** DMA Device Functions **********************/ | |
1315 | ||
1316 | #ifdef CONFIG_EDAC_ALTERA_DMA | |
1317 | ||
1318 | static const struct edac_device_prv_data a10_dmaecc_data = { | |
1319 | .setup = altr_check_ecc_deps, | |
1320 | .ce_clear_mask = ALTR_A10_ECC_SERRPENA, | |
1321 | .ue_clear_mask = ALTR_A10_ECC_DERRPENA, | |
1322 | .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, | |
1323 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1324 | .ce_set_mask = ALTR_A10_ECC_TSERRA, | |
1325 | .ue_set_mask = ALTR_A10_ECC_TDERRA, | |
1326 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1327 | .ecc_irq_handler = altr_edac_a10_ecc_irq, | |
1328 | .inject_fops = &altr_edac_a10_device_inject_fops, | |
1329 | }; | |
1330 | ||
1331 | static int __init socfpga_init_dma_ecc(void) | |
1332 | { | |
1333 | return altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc"); | |
1334 | } | |
1335 | ||
1336 | early_initcall(socfpga_init_dma_ecc); | |
1337 | ||
1338 | #endif /* CONFIG_EDAC_ALTERA_DMA */ | |
1339 | ||
1340 | /********************** USB Device Functions **********************/ | |
1341 | ||
1342 | #ifdef CONFIG_EDAC_ALTERA_USB | |
1343 | ||
1344 | static const struct edac_device_prv_data a10_usbecc_data = { | |
1345 | .setup = altr_check_ecc_deps, | |
1346 | .ce_clear_mask = ALTR_A10_ECC_SERRPENA, | |
1347 | .ue_clear_mask = ALTR_A10_ECC_DERRPENA, | |
1348 | .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, | |
1349 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1350 | .ce_set_mask = ALTR_A10_ECC_TSERRA, | |
1351 | .ue_set_mask = ALTR_A10_ECC_TDERRA, | |
1352 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1353 | .ecc_irq_handler = altr_edac_a10_ecc_irq, | |
1354 | .inject_fops = &altr_edac_a10_device_inject_fops, | |
1355 | }; | |
1356 | ||
1357 | static int __init socfpga_init_usb_ecc(void) | |
1358 | { | |
1359 | return altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc"); | |
1360 | } | |
1361 | ||
1362 | early_initcall(socfpga_init_usb_ecc); | |
1363 | ||
1364 | #endif /* CONFIG_EDAC_ALTERA_USB */ | |
1365 | ||
1366 | /********************** QSPI Device Functions **********************/ | |
1367 | ||
1368 | #ifdef CONFIG_EDAC_ALTERA_QSPI | |
1369 | ||
1370 | static const struct edac_device_prv_data a10_qspiecc_data = { | |
1371 | .setup = altr_check_ecc_deps, | |
1372 | .ce_clear_mask = ALTR_A10_ECC_SERRPENA, | |
1373 | .ue_clear_mask = ALTR_A10_ECC_DERRPENA, | |
1374 | .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, | |
1375 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1376 | .ce_set_mask = ALTR_A10_ECC_TSERRA, | |
1377 | .ue_set_mask = ALTR_A10_ECC_TDERRA, | |
1378 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1379 | .ecc_irq_handler = altr_edac_a10_ecc_irq, | |
1380 | .inject_fops = &altr_edac_a10_device_inject_fops, | |
1381 | }; | |
1382 | ||
1383 | static int __init socfpga_init_qspi_ecc(void) | |
1384 | { | |
1385 | return altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc"); | |
1386 | } | |
1387 | ||
1388 | early_initcall(socfpga_init_qspi_ecc); | |
1389 | ||
1390 | #endif /* CONFIG_EDAC_ALTERA_QSPI */ | |
1391 | ||
1392 | /********************* SDMMC Device Functions **********************/ | |
1393 | ||
1394 | #ifdef CONFIG_EDAC_ALTERA_SDMMC | |
1395 | ||
1396 | static const struct edac_device_prv_data a10_sdmmceccb_data; | |
1397 | static int altr_portb_setup(struct altr_edac_device_dev *device) | |
1398 | { | |
1399 | struct edac_device_ctl_info *dci; | |
1400 | struct altr_edac_device_dev *altdev; | |
1401 | char *ecc_name = "sdmmcb-ecc"; | |
1402 | int edac_idx, rc; | |
1403 | struct device_node *np; | |
1404 | const struct edac_device_prv_data *prv = &a10_sdmmceccb_data; | |
1405 | ||
1406 | rc = altr_check_ecc_deps(device); | |
1407 | if (rc) | |
1408 | return rc; | |
1409 | ||
1410 | np = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc"); | |
1411 | if (!np) { | |
1412 | edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n"); | |
1413 | return -ENODEV; | |
1414 | } | |
1415 | ||
1416 | /* Create the PortB EDAC device */ | |
1417 | edac_idx = edac_device_alloc_index(); | |
1418 | dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1, | |
1419 | ecc_name, 1, 0, NULL, 0, edac_idx); | |
1420 | if (!dci) { | |
1421 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1422 | "%s: Unable to allocate PortB EDAC device\n", | |
1423 | ecc_name); | |
1424 | return -ENOMEM; | |
1425 | } | |
1426 | ||
1427 | /* Initialize the PortB EDAC device structure from PortA structure */ | |
1428 | altdev = dci->pvt_info; | |
1429 | *altdev = *device; | |
1430 | ||
1431 | if (!devres_open_group(&altdev->ddev, altr_portb_setup, GFP_KERNEL)) | |
1432 | return -ENOMEM; | |
1433 | ||
1434 | /* Update PortB specific values */ | |
1435 | altdev->edac_dev_name = ecc_name; | |
1436 | altdev->edac_idx = edac_idx; | |
1437 | altdev->edac_dev = dci; | |
1438 | altdev->data = prv; | |
1439 | dci->dev = &altdev->ddev; | |
1440 | dci->ctl_name = "Altera ECC Manager"; | |
1441 | dci->mod_name = ecc_name; | |
1442 | dci->dev_name = ecc_name; | |
1443 | ||
1444 | /* Update the IRQs for PortB */ | |
1445 | altdev->sb_irq = irq_of_parse_and_map(np, 2); | |
1446 | if (!altdev->sb_irq) { | |
1447 | edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB SBIRQ alloc\n"); | |
1448 | rc = -ENODEV; | |
1449 | goto err_release_group_1; | |
1450 | } | |
1451 | rc = devm_request_irq(&altdev->ddev, altdev->sb_irq, | |
1452 | prv->ecc_irq_handler, | |
1453 | IRQF_ONESHOT | IRQF_TRIGGER_HIGH, | |
1454 | ecc_name, altdev); | |
1455 | if (rc) { | |
1456 | edac_printk(KERN_ERR, EDAC_DEVICE, "PortB SBERR IRQ error\n"); | |
1457 | goto err_release_group_1; | |
1458 | } | |
1459 | ||
1460 | altdev->db_irq = irq_of_parse_and_map(np, 3); | |
1461 | if (!altdev->db_irq) { | |
1462 | edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB DBIRQ alloc\n"); | |
1463 | rc = -ENODEV; | |
1464 | goto err_release_group_1; | |
1465 | } | |
1466 | rc = devm_request_irq(&altdev->ddev, altdev->db_irq, | |
1467 | prv->ecc_irq_handler, | |
1468 | IRQF_ONESHOT | IRQF_TRIGGER_HIGH, | |
1469 | ecc_name, altdev); | |
1470 | if (rc) { | |
1471 | edac_printk(KERN_ERR, EDAC_DEVICE, "PortB DBERR IRQ error\n"); | |
1472 | goto err_release_group_1; | |
1473 | } | |
1474 | ||
1475 | rc = edac_device_add_device(dci); | |
1476 | if (rc) { | |
1477 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1478 | "edac_device_add_device portB failed\n"); | |
1479 | rc = -ENOMEM; | |
1480 | goto err_release_group_1; | |
1481 | } | |
1482 | altr_create_edacdev_dbgfs(dci, prv); | |
1483 | ||
1484 | list_add(&altdev->next, &altdev->edac->a10_ecc_devices); | |
1485 | ||
1486 | devres_remove_group(&altdev->ddev, altr_portb_setup); | |
1487 | ||
1488 | return 0; | |
1489 | ||
1490 | err_release_group_1: | |
1491 | edac_device_free_ctl_info(dci); | |
1492 | devres_release_group(&altdev->ddev, altr_portb_setup); | |
1493 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1494 | "%s:Error setting up EDAC device: %d\n", ecc_name, rc); | |
1495 | return rc; | |
1496 | } | |
1497 | ||
1498 | static irqreturn_t altr_edac_a10_ecc_irq_portb(int irq, void *dev_id) | |
1499 | { | |
1500 | struct altr_edac_device_dev *ad = dev_id; | |
1501 | void __iomem *base = ad->base; | |
1502 | const struct edac_device_prv_data *priv = ad->data; | |
1503 | ||
1504 | if (irq == ad->sb_irq) { | |
1505 | writel(priv->ce_clear_mask, | |
1506 | base + ALTR_A10_ECC_INTSTAT_OFST); | |
1507 | edac_device_handle_ce(ad->edac_dev, 0, 0, ad->edac_dev_name); | |
1508 | return IRQ_HANDLED; | |
1509 | } else if (irq == ad->db_irq) { | |
1510 | writel(priv->ue_clear_mask, | |
1511 | base + ALTR_A10_ECC_INTSTAT_OFST); | |
1512 | edac_device_handle_ue(ad->edac_dev, 0, 0, ad->edac_dev_name); | |
1513 | return IRQ_HANDLED; | |
1514 | } | |
1515 | ||
1516 | WARN_ONCE(1, "Unhandled IRQ%d on Port B.", irq); | |
1517 | ||
1518 | return IRQ_NONE; | |
1519 | } | |
1520 | ||
1521 | static const struct edac_device_prv_data a10_sdmmcecca_data = { | |
1522 | .setup = altr_portb_setup, | |
1523 | .ce_clear_mask = ALTR_A10_ECC_SERRPENA, | |
1524 | .ue_clear_mask = ALTR_A10_ECC_DERRPENA, | |
1525 | .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, | |
1526 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1527 | .ce_set_mask = ALTR_A10_ECC_SERRPENA, | |
1528 | .ue_set_mask = ALTR_A10_ECC_DERRPENA, | |
1529 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1530 | .ecc_irq_handler = altr_edac_a10_ecc_irq, | |
1531 | .inject_fops = &altr_edac_a10_device_inject_fops, | |
1532 | }; | |
1533 | ||
1534 | static const struct edac_device_prv_data a10_sdmmceccb_data = { | |
1535 | .setup = altr_portb_setup, | |
1536 | .ce_clear_mask = ALTR_A10_ECC_SERRPENB, | |
1537 | .ue_clear_mask = ALTR_A10_ECC_DERRPENB, | |
1538 | .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, | |
1539 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1540 | .ce_set_mask = ALTR_A10_ECC_TSERRB, | |
1541 | .ue_set_mask = ALTR_A10_ECC_TDERRB, | |
1542 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1543 | .ecc_irq_handler = altr_edac_a10_ecc_irq_portb, | |
1544 | .inject_fops = &altr_edac_a10_device_inject_fops, | |
1545 | }; | |
1546 | ||
1547 | static int __init socfpga_init_sdmmc_ecc(void) | |
1548 | { | |
1549 | int rc = -ENODEV; | |
1550 | struct device_node *child; | |
1551 | ||
1552 | if (!socfpga_is_a10()) | |
1553 | return -ENODEV; | |
1554 | ||
1555 | child = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc"); | |
1556 | if (!child) { | |
1557 | edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n"); | |
1558 | return -ENODEV; | |
1559 | } | |
1560 | ||
1561 | if (!of_device_is_available(child)) | |
1562 | goto exit; | |
1563 | ||
1564 | if (validate_parent_available(child)) | |
1565 | goto exit; | |
1566 | ||
1567 | rc = altr_init_a10_ecc_block(child, ALTR_A10_SDMMC_IRQ_MASK, | |
1568 | a10_sdmmcecca_data.ecc_enable_mask, 1); | |
1569 | exit: | |
1570 | of_node_put(child); | |
1571 | return rc; | |
1572 | } | |
1573 | ||
1574 | early_initcall(socfpga_init_sdmmc_ecc); | |
1575 | ||
1576 | #endif /* CONFIG_EDAC_ALTERA_SDMMC */ | |
1577 | ||
1578 | /********************* Arria10 EDAC Device Functions *************************/ | |
1579 | static const struct of_device_id altr_edac_a10_device_of_match[] = { | |
1580 | #ifdef CONFIG_EDAC_ALTERA_L2C | |
1581 | { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data }, | |
1582 | #endif | |
1583 | #ifdef CONFIG_EDAC_ALTERA_OCRAM | |
1584 | { .compatible = "altr,socfpga-a10-ocram-ecc", | |
1585 | .data = &a10_ocramecc_data }, | |
1586 | #endif | |
1587 | #ifdef CONFIG_EDAC_ALTERA_ETHERNET | |
1588 | { .compatible = "altr,socfpga-eth-mac-ecc", | |
1589 | .data = &a10_enetecc_data }, | |
1590 | #endif | |
1591 | #ifdef CONFIG_EDAC_ALTERA_NAND | |
1592 | { .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data }, | |
1593 | #endif | |
1594 | #ifdef CONFIG_EDAC_ALTERA_DMA | |
1595 | { .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data }, | |
1596 | #endif | |
1597 | #ifdef CONFIG_EDAC_ALTERA_USB | |
1598 | { .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data }, | |
1599 | #endif | |
1600 | #ifdef CONFIG_EDAC_ALTERA_QSPI | |
1601 | { .compatible = "altr,socfpga-qspi-ecc", .data = &a10_qspiecc_data }, | |
1602 | #endif | |
1603 | #ifdef CONFIG_EDAC_ALTERA_SDMMC | |
1604 | { .compatible = "altr,socfpga-sdmmc-ecc", .data = &a10_sdmmcecca_data }, | |
1605 | #endif | |
1606 | {}, | |
1607 | }; | |
1608 | MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match); | |
1609 | ||
1610 | /* | |
1611 | * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5 | |
1612 | * because 2 IRQs are shared among the all ECC peripherals. The ECC | |
1613 | * manager manages the IRQs and the children. | |
1614 | * Based on xgene_edac.c peripheral code. | |
1615 | */ | |
1616 | ||
1617 | static ssize_t altr_edac_a10_device_trig(struct file *file, | |
1618 | const char __user *user_buf, | |
1619 | size_t count, loff_t *ppos) | |
1620 | { | |
1621 | struct edac_device_ctl_info *edac_dci = file->private_data; | |
1622 | struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; | |
1623 | const struct edac_device_prv_data *priv = drvdata->data; | |
1624 | void __iomem *set_addr = (drvdata->base + priv->set_err_ofst); | |
1625 | unsigned long flags; | |
1626 | u8 trig_type; | |
1627 | ||
1628 | if (!user_buf || get_user(trig_type, user_buf)) | |
1629 | return -EFAULT; | |
1630 | ||
1631 | local_irq_save(flags); | |
1632 | if (trig_type == ALTR_UE_TRIGGER_CHAR) | |
1633 | writel(priv->ue_set_mask, set_addr); | |
1634 | else | |
1635 | writel(priv->ce_set_mask, set_addr); | |
1636 | /* Ensure the interrupt test bits are set */ | |
1637 | wmb(); | |
1638 | local_irq_restore(flags); | |
1639 | ||
1640 | return count; | |
1641 | } | |
1642 | ||
1643 | static void altr_edac_a10_irq_handler(struct irq_desc *desc) | |
1644 | { | |
1645 | int dberr, bit, sm_offset, irq_status; | |
1646 | struct altr_arria10_edac *edac = irq_desc_get_handler_data(desc); | |
1647 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
1648 | int irq = irq_desc_get_irq(desc); | |
1649 | ||
1650 | dberr = (irq == edac->db_irq) ? 1 : 0; | |
1651 | sm_offset = dberr ? A10_SYSMGR_ECC_INTSTAT_DERR_OFST : | |
1652 | A10_SYSMGR_ECC_INTSTAT_SERR_OFST; | |
1653 | ||
1654 | chained_irq_enter(chip, desc); | |
1655 | ||
1656 | regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status); | |
1657 | ||
1658 | for_each_set_bit(bit, (unsigned long *)&irq_status, 32) { | |
1659 | irq = irq_linear_revmap(edac->domain, dberr * 32 + bit); | |
1660 | if (irq) | |
1661 | generic_handle_irq(irq); | |
1662 | } | |
1663 | ||
1664 | chained_irq_exit(chip, desc); | |
1665 | } | |
1666 | ||
1667 | static int validate_parent_available(struct device_node *np) | |
1668 | { | |
1669 | struct device_node *parent; | |
1670 | int ret = 0; | |
1671 | ||
1672 | /* Ensure parent device is enabled if parent node exists */ | |
1673 | parent = of_parse_phandle(np, "altr,ecc-parent", 0); | |
1674 | if (parent && !of_device_is_available(parent)) | |
1675 | ret = -ENODEV; | |
1676 | ||
1677 | of_node_put(parent); | |
1678 | return ret; | |
1679 | } | |
1680 | ||
1681 | static int altr_edac_a10_device_add(struct altr_arria10_edac *edac, | |
1682 | struct device_node *np) | |
1683 | { | |
1684 | struct edac_device_ctl_info *dci; | |
1685 | struct altr_edac_device_dev *altdev; | |
1686 | char *ecc_name = (char *)np->name; | |
1687 | struct resource res; | |
1688 | int edac_idx; | |
1689 | int rc = 0; | |
1690 | const struct edac_device_prv_data *prv; | |
1691 | /* Get matching node and check for valid result */ | |
1692 | const struct of_device_id *pdev_id = | |
1693 | of_match_node(altr_edac_a10_device_of_match, np); | |
1694 | if (IS_ERR_OR_NULL(pdev_id)) | |
1695 | return -ENODEV; | |
1696 | ||
1697 | /* Get driver specific data for this EDAC device */ | |
1698 | prv = pdev_id->data; | |
1699 | if (IS_ERR_OR_NULL(prv)) | |
1700 | return -ENODEV; | |
1701 | ||
1702 | if (validate_parent_available(np)) | |
1703 | return -ENODEV; | |
1704 | ||
1705 | if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL)) | |
1706 | return -ENOMEM; | |
1707 | ||
1708 | rc = of_address_to_resource(np, 0, &res); | |
1709 | if (rc < 0) { | |
1710 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1711 | "%s: no resource address\n", ecc_name); | |
1712 | goto err_release_group; | |
1713 | } | |
1714 | ||
1715 | edac_idx = edac_device_alloc_index(); | |
1716 | dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, | |
1717 | 1, ecc_name, 1, 0, NULL, 0, | |
1718 | edac_idx); | |
1719 | ||
1720 | if (!dci) { | |
1721 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1722 | "%s: Unable to allocate EDAC device\n", ecc_name); | |
1723 | rc = -ENOMEM; | |
1724 | goto err_release_group; | |
1725 | } | |
1726 | ||
1727 | altdev = dci->pvt_info; | |
1728 | dci->dev = edac->dev; | |
1729 | altdev->edac_dev_name = ecc_name; | |
1730 | altdev->edac_idx = edac_idx; | |
1731 | altdev->edac = edac; | |
1732 | altdev->edac_dev = dci; | |
1733 | altdev->data = prv; | |
1734 | altdev->ddev = *edac->dev; | |
1735 | dci->dev = &altdev->ddev; | |
1736 | dci->ctl_name = "Altera ECC Manager"; | |
1737 | dci->mod_name = ecc_name; | |
1738 | dci->dev_name = ecc_name; | |
1739 | ||
1740 | altdev->base = devm_ioremap_resource(edac->dev, &res); | |
1741 | if (IS_ERR(altdev->base)) { | |
1742 | rc = PTR_ERR(altdev->base); | |
1743 | goto err_release_group1; | |
1744 | } | |
1745 | ||
1746 | /* Check specific dependencies for the module */ | |
1747 | if (altdev->data->setup) { | |
1748 | rc = altdev->data->setup(altdev); | |
1749 | if (rc) | |
1750 | goto err_release_group1; | |
1751 | } | |
1752 | ||
1753 | altdev->sb_irq = irq_of_parse_and_map(np, 0); | |
1754 | if (!altdev->sb_irq) { | |
1755 | edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating SBIRQ\n"); | |
1756 | rc = -ENODEV; | |
1757 | goto err_release_group1; | |
1758 | } | |
1759 | rc = devm_request_irq(edac->dev, altdev->sb_irq, prv->ecc_irq_handler, | |
1760 | IRQF_ONESHOT | IRQF_TRIGGER_HIGH, | |
1761 | ecc_name, altdev); | |
1762 | if (rc) { | |
1763 | edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n"); | |
1764 | goto err_release_group1; | |
1765 | } | |
1766 | ||
1767 | altdev->db_irq = irq_of_parse_and_map(np, 1); | |
1768 | if (!altdev->db_irq) { | |
1769 | edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating DBIRQ\n"); | |
1770 | rc = -ENODEV; | |
1771 | goto err_release_group1; | |
1772 | } | |
1773 | rc = devm_request_irq(edac->dev, altdev->db_irq, prv->ecc_irq_handler, | |
1774 | IRQF_ONESHOT | IRQF_TRIGGER_HIGH, | |
1775 | ecc_name, altdev); | |
1776 | if (rc) { | |
1777 | edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n"); | |
1778 | goto err_release_group1; | |
1779 | } | |
1780 | ||
1781 | rc = edac_device_add_device(dci); | |
1782 | if (rc) { | |
1783 | dev_err(edac->dev, "edac_device_add_device failed\n"); | |
1784 | rc = -ENOMEM; | |
1785 | goto err_release_group1; | |
1786 | } | |
1787 | ||
1788 | altr_create_edacdev_dbgfs(dci, prv); | |
1789 | ||
1790 | list_add(&altdev->next, &edac->a10_ecc_devices); | |
1791 | ||
1792 | devres_remove_group(edac->dev, altr_edac_a10_device_add); | |
1793 | ||
1794 | return 0; | |
1795 | ||
1796 | err_release_group1: | |
1797 | edac_device_free_ctl_info(dci); | |
1798 | err_release_group: | |
1799 | devres_release_group(edac->dev, NULL); | |
1800 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1801 | "%s:Error setting up EDAC device: %d\n", ecc_name, rc); | |
1802 | ||
1803 | return rc; | |
1804 | } | |
1805 | ||
1806 | static void a10_eccmgr_irq_mask(struct irq_data *d) | |
1807 | { | |
1808 | struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d); | |
1809 | ||
1810 | regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, | |
1811 | BIT(d->hwirq)); | |
1812 | } | |
1813 | ||
1814 | static void a10_eccmgr_irq_unmask(struct irq_data *d) | |
1815 | { | |
1816 | struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d); | |
1817 | ||
1818 | regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, | |
1819 | BIT(d->hwirq)); | |
1820 | } | |
1821 | ||
1822 | static int a10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq, | |
1823 | irq_hw_number_t hwirq) | |
1824 | { | |
1825 | struct altr_arria10_edac *edac = d->host_data; | |
1826 | ||
1827 | irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq); | |
1828 | irq_set_chip_data(irq, edac); | |
1829 | irq_set_noprobe(irq); | |
1830 | ||
1831 | return 0; | |
1832 | } | |
1833 | ||
1834 | static const struct irq_domain_ops a10_eccmgr_ic_ops = { | |
1835 | .map = a10_eccmgr_irqdomain_map, | |
1836 | .xlate = irq_domain_xlate_twocell, | |
1837 | }; | |
1838 | ||
1839 | static int altr_edac_a10_probe(struct platform_device *pdev) | |
1840 | { | |
1841 | struct altr_arria10_edac *edac; | |
1842 | struct device_node *child; | |
1843 | ||
1844 | edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL); | |
1845 | if (!edac) | |
1846 | return -ENOMEM; | |
1847 | ||
1848 | edac->dev = &pdev->dev; | |
1849 | platform_set_drvdata(pdev, edac); | |
1850 | INIT_LIST_HEAD(&edac->a10_ecc_devices); | |
1851 | ||
1852 | edac->ecc_mgr_map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, | |
1853 | "altr,sysmgr-syscon"); | |
1854 | if (IS_ERR(edac->ecc_mgr_map)) { | |
1855 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1856 | "Unable to get syscon altr,sysmgr-syscon\n"); | |
1857 | return PTR_ERR(edac->ecc_mgr_map); | |
1858 | } | |
1859 | ||
1860 | edac->irq_chip.name = pdev->dev.of_node->name; | |
1861 | edac->irq_chip.irq_mask = a10_eccmgr_irq_mask; | |
1862 | edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask; | |
1863 | edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64, | |
1864 | &a10_eccmgr_ic_ops, edac); | |
1865 | if (!edac->domain) { | |
1866 | dev_err(&pdev->dev, "Error adding IRQ domain\n"); | |
1867 | return -ENOMEM; | |
1868 | } | |
1869 | ||
1870 | edac->sb_irq = platform_get_irq(pdev, 0); | |
1871 | if (edac->sb_irq < 0) { | |
1872 | dev_err(&pdev->dev, "No SBERR IRQ resource\n"); | |
1873 | return edac->sb_irq; | |
1874 | } | |
1875 | ||
1876 | irq_set_chained_handler_and_data(edac->sb_irq, | |
1877 | altr_edac_a10_irq_handler, | |
1878 | edac); | |
1879 | ||
1880 | edac->db_irq = platform_get_irq(pdev, 1); | |
1881 | if (edac->db_irq < 0) { | |
1882 | dev_err(&pdev->dev, "No DBERR IRQ resource\n"); | |
1883 | return edac->db_irq; | |
1884 | } | |
1885 | irq_set_chained_handler_and_data(edac->db_irq, | |
1886 | altr_edac_a10_irq_handler, | |
1887 | edac); | |
1888 | ||
1889 | for_each_child_of_node(pdev->dev.of_node, child) { | |
1890 | if (!of_device_is_available(child)) | |
1891 | continue; | |
1892 | ||
1893 | if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc") || | |
1894 | of_device_is_compatible(child, "altr,socfpga-a10-ocram-ecc") || | |
1895 | of_device_is_compatible(child, "altr,socfpga-eth-mac-ecc") || | |
1896 | of_device_is_compatible(child, "altr,socfpga-nand-ecc") || | |
1897 | of_device_is_compatible(child, "altr,socfpga-dma-ecc") || | |
1898 | of_device_is_compatible(child, "altr,socfpga-usb-ecc") || | |
1899 | of_device_is_compatible(child, "altr,socfpga-qspi-ecc") || | |
1900 | of_device_is_compatible(child, "altr,socfpga-sdmmc-ecc")) | |
1901 | ||
1902 | altr_edac_a10_device_add(edac, child); | |
1903 | ||
1904 | else if (of_device_is_compatible(child, "altr,sdram-edac-a10")) | |
1905 | of_platform_populate(pdev->dev.of_node, | |
1906 | altr_sdram_ctrl_of_match, | |
1907 | NULL, &pdev->dev); | |
1908 | } | |
1909 | ||
1910 | return 0; | |
1911 | } | |
1912 | ||
1913 | static const struct of_device_id altr_edac_a10_of_match[] = { | |
1914 | { .compatible = "altr,socfpga-a10-ecc-manager" }, | |
1915 | {}, | |
1916 | }; | |
1917 | MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match); | |
1918 | ||
1919 | static struct platform_driver altr_edac_a10_driver = { | |
1920 | .probe = altr_edac_a10_probe, | |
1921 | .driver = { | |
1922 | .name = "socfpga_a10_ecc_manager", | |
1923 | .of_match_table = altr_edac_a10_of_match, | |
1924 | }, | |
1925 | }; | |
1926 | module_platform_driver(altr_edac_a10_driver); | |
1927 | ||
1928 | MODULE_LICENSE("GPL v2"); | |
1929 | MODULE_AUTHOR("Thor Thayer"); | |
1930 | MODULE_DESCRIPTION("EDAC Driver for Altera Memories"); |