]>
Commit | Line | Data |
---|---|---|
1 | /* | |
2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #include <net/tc_act/tc_gact.h> | |
34 | #include <linux/crash_dump.h> | |
35 | #include <net/pkt_cls.h> | |
36 | #include <linux/mlx5/fs.h> | |
37 | #include <net/vxlan.h> | |
38 | #include <linux/bpf.h> | |
39 | #include "en.h" | |
40 | #include "en_tc.h" | |
41 | #include "eswitch.h" | |
42 | #include "vxlan.h" | |
43 | ||
44 | struct mlx5e_rq_param { | |
45 | u32 rqc[MLX5_ST_SZ_DW(rqc)]; | |
46 | struct mlx5_wq_param wq; | |
47 | bool am_enabled; | |
48 | }; | |
49 | ||
50 | struct mlx5e_sq_param { | |
51 | u32 sqc[MLX5_ST_SZ_DW(sqc)]; | |
52 | struct mlx5_wq_param wq; | |
53 | u16 max_inline; | |
54 | u8 min_inline_mode; | |
55 | enum mlx5e_sq_type type; | |
56 | }; | |
57 | ||
58 | struct mlx5e_cq_param { | |
59 | u32 cqc[MLX5_ST_SZ_DW(cqc)]; | |
60 | struct mlx5_wq_param wq; | |
61 | u16 eq_ix; | |
62 | u8 cq_period_mode; | |
63 | }; | |
64 | ||
65 | struct mlx5e_channel_param { | |
66 | struct mlx5e_rq_param rq; | |
67 | struct mlx5e_sq_param sq; | |
68 | struct mlx5e_sq_param xdp_sq; | |
69 | struct mlx5e_sq_param icosq; | |
70 | struct mlx5e_cq_param rx_cq; | |
71 | struct mlx5e_cq_param tx_cq; | |
72 | struct mlx5e_cq_param icosq_cq; | |
73 | }; | |
74 | ||
75 | static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev) | |
76 | { | |
77 | return MLX5_CAP_GEN(mdev, striding_rq) && | |
78 | MLX5_CAP_GEN(mdev, umr_ptr_rlky) && | |
79 | MLX5_CAP_ETH(mdev, reg_umr_sq); | |
80 | } | |
81 | ||
82 | void mlx5e_set_rq_type_params(struct mlx5e_priv *priv, u8 rq_type) | |
83 | { | |
84 | priv->params.rq_wq_type = rq_type; | |
85 | priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ; | |
86 | switch (priv->params.rq_wq_type) { | |
87 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
88 | priv->params.log_rq_size = is_kdump_kernel() ? | |
89 | MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW : | |
90 | MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW; | |
91 | priv->params.mpwqe_log_stride_sz = | |
92 | MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS) ? | |
93 | MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(priv->mdev) : | |
94 | MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(priv->mdev); | |
95 | priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - | |
96 | priv->params.mpwqe_log_stride_sz; | |
97 | break; | |
98 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
99 | priv->params.log_rq_size = is_kdump_kernel() ? | |
100 | MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE : | |
101 | MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE; | |
102 | ||
103 | /* Extra room needed for build_skb */ | |
104 | priv->params.lro_wqe_sz -= MLX5_RX_HEADROOM + | |
105 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
106 | } | |
107 | priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type, | |
108 | BIT(priv->params.log_rq_size)); | |
109 | ||
110 | mlx5_core_info(priv->mdev, | |
111 | "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n", | |
112 | priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ, | |
113 | BIT(priv->params.log_rq_size), | |
114 | BIT(priv->params.mpwqe_log_stride_sz), | |
115 | MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS)); | |
116 | } | |
117 | ||
118 | static void mlx5e_set_rq_priv_params(struct mlx5e_priv *priv) | |
119 | { | |
120 | u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(priv->mdev) && | |
121 | !priv->xdp_prog ? | |
122 | MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ : | |
123 | MLX5_WQ_TYPE_LINKED_LIST; | |
124 | mlx5e_set_rq_type_params(priv, rq_type); | |
125 | } | |
126 | ||
127 | static void mlx5e_update_carrier(struct mlx5e_priv *priv) | |
128 | { | |
129 | struct mlx5_core_dev *mdev = priv->mdev; | |
130 | u8 port_state; | |
131 | ||
132 | port_state = mlx5_query_vport_state(mdev, | |
133 | MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0); | |
134 | ||
135 | if (port_state == VPORT_STATE_UP) { | |
136 | netdev_info(priv->netdev, "Link up\n"); | |
137 | netif_carrier_on(priv->netdev); | |
138 | } else { | |
139 | netdev_info(priv->netdev, "Link down\n"); | |
140 | netif_carrier_off(priv->netdev); | |
141 | } | |
142 | } | |
143 | ||
144 | static void mlx5e_update_carrier_work(struct work_struct *work) | |
145 | { | |
146 | struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, | |
147 | update_carrier_work); | |
148 | ||
149 | mutex_lock(&priv->state_lock); | |
150 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
151 | mlx5e_update_carrier(priv); | |
152 | mutex_unlock(&priv->state_lock); | |
153 | } | |
154 | ||
155 | static void mlx5e_tx_timeout_work(struct work_struct *work) | |
156 | { | |
157 | struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, | |
158 | tx_timeout_work); | |
159 | int err; | |
160 | ||
161 | rtnl_lock(); | |
162 | mutex_lock(&priv->state_lock); | |
163 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
164 | goto unlock; | |
165 | mlx5e_close_locked(priv->netdev); | |
166 | err = mlx5e_open_locked(priv->netdev); | |
167 | if (err) | |
168 | netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n", | |
169 | err); | |
170 | unlock: | |
171 | mutex_unlock(&priv->state_lock); | |
172 | rtnl_unlock(); | |
173 | } | |
174 | ||
175 | static void mlx5e_update_sw_counters(struct mlx5e_priv *priv) | |
176 | { | |
177 | struct mlx5e_sw_stats *s = &priv->stats.sw; | |
178 | struct mlx5e_rq_stats *rq_stats; | |
179 | struct mlx5e_sq_stats *sq_stats; | |
180 | u64 tx_offload_none = 0; | |
181 | int i, j; | |
182 | ||
183 | memset(s, 0, sizeof(*s)); | |
184 | for (i = 0; i < priv->params.num_channels; i++) { | |
185 | rq_stats = &priv->channel[i]->rq.stats; | |
186 | ||
187 | s->rx_packets += rq_stats->packets; | |
188 | s->rx_bytes += rq_stats->bytes; | |
189 | s->rx_lro_packets += rq_stats->lro_packets; | |
190 | s->rx_lro_bytes += rq_stats->lro_bytes; | |
191 | s->rx_csum_none += rq_stats->csum_none; | |
192 | s->rx_csum_complete += rq_stats->csum_complete; | |
193 | s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner; | |
194 | s->rx_xdp_drop += rq_stats->xdp_drop; | |
195 | s->rx_xdp_tx += rq_stats->xdp_tx; | |
196 | s->rx_xdp_tx_full += rq_stats->xdp_tx_full; | |
197 | s->rx_wqe_err += rq_stats->wqe_err; | |
198 | s->rx_mpwqe_filler += rq_stats->mpwqe_filler; | |
199 | s->rx_buff_alloc_err += rq_stats->buff_alloc_err; | |
200 | s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks; | |
201 | s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts; | |
202 | s->rx_cache_reuse += rq_stats->cache_reuse; | |
203 | s->rx_cache_full += rq_stats->cache_full; | |
204 | s->rx_cache_empty += rq_stats->cache_empty; | |
205 | s->rx_cache_busy += rq_stats->cache_busy; | |
206 | ||
207 | for (j = 0; j < priv->params.num_tc; j++) { | |
208 | sq_stats = &priv->channel[i]->sq[j].stats; | |
209 | ||
210 | s->tx_packets += sq_stats->packets; | |
211 | s->tx_bytes += sq_stats->bytes; | |
212 | s->tx_tso_packets += sq_stats->tso_packets; | |
213 | s->tx_tso_bytes += sq_stats->tso_bytes; | |
214 | s->tx_tso_inner_packets += sq_stats->tso_inner_packets; | |
215 | s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes; | |
216 | s->tx_queue_stopped += sq_stats->stopped; | |
217 | s->tx_queue_wake += sq_stats->wake; | |
218 | s->tx_queue_dropped += sq_stats->dropped; | |
219 | s->tx_xmit_more += sq_stats->xmit_more; | |
220 | s->tx_csum_partial_inner += sq_stats->csum_partial_inner; | |
221 | tx_offload_none += sq_stats->csum_none; | |
222 | } | |
223 | } | |
224 | ||
225 | /* Update calculated offload counters */ | |
226 | s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner; | |
227 | s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete; | |
228 | ||
229 | s->link_down_events_phy = MLX5_GET(ppcnt_reg, | |
230 | priv->stats.pport.phy_counters, | |
231 | counter_set.phys_layer_cntrs.link_down_events); | |
232 | } | |
233 | ||
234 | static void mlx5e_update_vport_counters(struct mlx5e_priv *priv) | |
235 | { | |
236 | int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out); | |
237 | u32 *out = (u32 *)priv->stats.vport.query_vport_out; | |
238 | u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0}; | |
239 | struct mlx5_core_dev *mdev = priv->mdev; | |
240 | ||
241 | MLX5_SET(query_vport_counter_in, in, opcode, | |
242 | MLX5_CMD_OP_QUERY_VPORT_COUNTER); | |
243 | MLX5_SET(query_vport_counter_in, in, op_mod, 0); | |
244 | MLX5_SET(query_vport_counter_in, in, other_vport, 0); | |
245 | ||
246 | memset(out, 0, outlen); | |
247 | mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen); | |
248 | } | |
249 | ||
250 | static void mlx5e_update_pport_counters(struct mlx5e_priv *priv) | |
251 | { | |
252 | struct mlx5e_pport_stats *pstats = &priv->stats.pport; | |
253 | struct mlx5_core_dev *mdev = priv->mdev; | |
254 | int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); | |
255 | int prio; | |
256 | void *out; | |
257 | u32 *in; | |
258 | ||
259 | in = mlx5_vzalloc(sz); | |
260 | if (!in) | |
261 | goto free_out; | |
262 | ||
263 | MLX5_SET(ppcnt_reg, in, local_port, 1); | |
264 | ||
265 | out = pstats->IEEE_802_3_counters; | |
266 | MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP); | |
267 | mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); | |
268 | ||
269 | out = pstats->RFC_2863_counters; | |
270 | MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP); | |
271 | mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); | |
272 | ||
273 | out = pstats->RFC_2819_counters; | |
274 | MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP); | |
275 | mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); | |
276 | ||
277 | out = pstats->phy_counters; | |
278 | MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP); | |
279 | mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); | |
280 | ||
281 | if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) { | |
282 | out = pstats->phy_statistical_counters; | |
283 | MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP); | |
284 | mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); | |
285 | } | |
286 | ||
287 | MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP); | |
288 | for (prio = 0; prio < NUM_PPORT_PRIO; prio++) { | |
289 | out = pstats->per_prio_counters[prio]; | |
290 | MLX5_SET(ppcnt_reg, in, prio_tc, prio); | |
291 | mlx5_core_access_reg(mdev, in, sz, out, sz, | |
292 | MLX5_REG_PPCNT, 0, 0); | |
293 | } | |
294 | ||
295 | free_out: | |
296 | kvfree(in); | |
297 | } | |
298 | ||
299 | static void mlx5e_update_q_counter(struct mlx5e_priv *priv) | |
300 | { | |
301 | struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt; | |
302 | ||
303 | if (!priv->q_counter) | |
304 | return; | |
305 | ||
306 | mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter, | |
307 | &qcnt->rx_out_of_buffer); | |
308 | } | |
309 | ||
310 | static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv) | |
311 | { | |
312 | struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie; | |
313 | struct mlx5_core_dev *mdev = priv->mdev; | |
314 | int sz = MLX5_ST_SZ_BYTES(mpcnt_reg); | |
315 | void *out; | |
316 | u32 *in; | |
317 | ||
318 | if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group)) | |
319 | return; | |
320 | ||
321 | in = mlx5_vzalloc(sz); | |
322 | if (!in) | |
323 | return; | |
324 | ||
325 | out = pcie_stats->pcie_perf_counters; | |
326 | MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP); | |
327 | mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); | |
328 | ||
329 | kvfree(in); | |
330 | } | |
331 | ||
332 | void mlx5e_update_stats(struct mlx5e_priv *priv) | |
333 | { | |
334 | mlx5e_update_pcie_counters(priv); | |
335 | mlx5e_update_pport_counters(priv); | |
336 | mlx5e_update_vport_counters(priv); | |
337 | mlx5e_update_q_counter(priv); | |
338 | mlx5e_update_sw_counters(priv); | |
339 | } | |
340 | ||
341 | void mlx5e_update_stats_work(struct work_struct *work) | |
342 | { | |
343 | struct delayed_work *dwork = to_delayed_work(work); | |
344 | struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv, | |
345 | update_stats_work); | |
346 | mutex_lock(&priv->state_lock); | |
347 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) { | |
348 | priv->profile->update_stats(priv); | |
349 | queue_delayed_work(priv->wq, dwork, | |
350 | msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL)); | |
351 | } | |
352 | mutex_unlock(&priv->state_lock); | |
353 | } | |
354 | ||
355 | static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv, | |
356 | enum mlx5_dev_event event, unsigned long param) | |
357 | { | |
358 | struct mlx5e_priv *priv = vpriv; | |
359 | struct ptp_clock_event ptp_event; | |
360 | struct mlx5_eqe *eqe = NULL; | |
361 | ||
362 | if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state)) | |
363 | return; | |
364 | ||
365 | switch (event) { | |
366 | case MLX5_DEV_EVENT_PORT_UP: | |
367 | case MLX5_DEV_EVENT_PORT_DOWN: | |
368 | queue_work(priv->wq, &priv->update_carrier_work); | |
369 | break; | |
370 | case MLX5_DEV_EVENT_PPS: | |
371 | eqe = (struct mlx5_eqe *)param; | |
372 | ptp_event.type = PTP_CLOCK_EXTTS; | |
373 | ptp_event.index = eqe->data.pps.pin; | |
374 | ptp_event.timestamp = | |
375 | timecounter_cyc2time(&priv->tstamp.clock, | |
376 | be64_to_cpu(eqe->data.pps.time_stamp)); | |
377 | mlx5e_pps_event_handler(vpriv, &ptp_event); | |
378 | break; | |
379 | default: | |
380 | break; | |
381 | } | |
382 | } | |
383 | ||
384 | static void mlx5e_enable_async_events(struct mlx5e_priv *priv) | |
385 | { | |
386 | set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state); | |
387 | } | |
388 | ||
389 | static void mlx5e_disable_async_events(struct mlx5e_priv *priv) | |
390 | { | |
391 | clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state); | |
392 | synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC)); | |
393 | } | |
394 | ||
395 | static inline int mlx5e_get_wqe_mtt_sz(void) | |
396 | { | |
397 | /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes. | |
398 | * To avoid copying garbage after the mtt array, we allocate | |
399 | * a little more. | |
400 | */ | |
401 | return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64), | |
402 | MLX5_UMR_MTT_ALIGNMENT); | |
403 | } | |
404 | ||
405 | static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, struct mlx5e_sq *sq, | |
406 | struct mlx5e_umr_wqe *wqe, u16 ix) | |
407 | { | |
408 | struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; | |
409 | struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl; | |
410 | struct mlx5_wqe_data_seg *dseg = &wqe->data; | |
411 | struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; | |
412 | u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS); | |
413 | u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix); | |
414 | ||
415 | cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) | | |
416 | ds_cnt); | |
417 | cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE; | |
418 | cseg->imm = rq->mkey_be; | |
419 | ||
420 | ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN; | |
421 | ucseg->xlt_octowords = | |
422 | cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE)); | |
423 | ucseg->bsf_octowords = | |
424 | cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset)); | |
425 | ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); | |
426 | ||
427 | dseg->lkey = sq->mkey_be; | |
428 | dseg->addr = cpu_to_be64(wi->umr.mtt_addr); | |
429 | } | |
430 | ||
431 | static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, | |
432 | struct mlx5e_channel *c) | |
433 | { | |
434 | int wq_sz = mlx5_wq_ll_get_size(&rq->wq); | |
435 | int mtt_sz = mlx5e_get_wqe_mtt_sz(); | |
436 | int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1; | |
437 | int i; | |
438 | ||
439 | rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info), | |
440 | GFP_KERNEL, cpu_to_node(c->cpu)); | |
441 | if (!rq->mpwqe.info) | |
442 | goto err_out; | |
443 | ||
444 | /* We allocate more than mtt_sz as we will align the pointer */ | |
445 | rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL, | |
446 | cpu_to_node(c->cpu)); | |
447 | if (unlikely(!rq->mpwqe.mtt_no_align)) | |
448 | goto err_free_wqe_info; | |
449 | ||
450 | for (i = 0; i < wq_sz; i++) { | |
451 | struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i]; | |
452 | ||
453 | wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc, | |
454 | MLX5_UMR_ALIGN); | |
455 | wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz, | |
456 | PCI_DMA_TODEVICE); | |
457 | if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr))) | |
458 | goto err_unmap_mtts; | |
459 | ||
460 | mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i); | |
461 | } | |
462 | ||
463 | return 0; | |
464 | ||
465 | err_unmap_mtts: | |
466 | while (--i >= 0) { | |
467 | struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i]; | |
468 | ||
469 | dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz, | |
470 | PCI_DMA_TODEVICE); | |
471 | } | |
472 | kfree(rq->mpwqe.mtt_no_align); | |
473 | err_free_wqe_info: | |
474 | kfree(rq->mpwqe.info); | |
475 | ||
476 | err_out: | |
477 | return -ENOMEM; | |
478 | } | |
479 | ||
480 | static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq) | |
481 | { | |
482 | int wq_sz = mlx5_wq_ll_get_size(&rq->wq); | |
483 | int mtt_sz = mlx5e_get_wqe_mtt_sz(); | |
484 | int i; | |
485 | ||
486 | for (i = 0; i < wq_sz; i++) { | |
487 | struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i]; | |
488 | ||
489 | dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz, | |
490 | PCI_DMA_TODEVICE); | |
491 | } | |
492 | kfree(rq->mpwqe.mtt_no_align); | |
493 | kfree(rq->mpwqe.info); | |
494 | } | |
495 | ||
496 | static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv, | |
497 | u64 npages, u8 page_shift, | |
498 | struct mlx5_core_mkey *umr_mkey) | |
499 | { | |
500 | struct mlx5_core_dev *mdev = priv->mdev; | |
501 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); | |
502 | void *mkc; | |
503 | u32 *in; | |
504 | int err; | |
505 | ||
506 | if (!MLX5E_VALID_NUM_MTTS(npages)) | |
507 | return -EINVAL; | |
508 | ||
509 | in = mlx5_vzalloc(inlen); | |
510 | if (!in) | |
511 | return -ENOMEM; | |
512 | ||
513 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); | |
514 | ||
515 | MLX5_SET(mkc, mkc, free, 1); | |
516 | MLX5_SET(mkc, mkc, umr_en, 1); | |
517 | MLX5_SET(mkc, mkc, lw, 1); | |
518 | MLX5_SET(mkc, mkc, lr, 1); | |
519 | MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT); | |
520 | ||
521 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
522 | MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn); | |
523 | MLX5_SET64(mkc, mkc, len, npages << page_shift); | |
524 | MLX5_SET(mkc, mkc, translations_octword_size, | |
525 | MLX5_MTT_OCTW(npages)); | |
526 | MLX5_SET(mkc, mkc, log_page_size, page_shift); | |
527 | ||
528 | err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen); | |
529 | ||
530 | kvfree(in); | |
531 | return err; | |
532 | } | |
533 | ||
534 | static int mlx5e_create_rq_umr_mkey(struct mlx5e_rq *rq) | |
535 | { | |
536 | struct mlx5e_priv *priv = rq->priv; | |
537 | u64 num_mtts = MLX5E_REQUIRED_MTTS(BIT(priv->params.log_rq_size)); | |
538 | ||
539 | return mlx5e_create_umr_mkey(priv, num_mtts, PAGE_SHIFT, &rq->umr_mkey); | |
540 | } | |
541 | ||
542 | static int mlx5e_create_rq(struct mlx5e_channel *c, | |
543 | struct mlx5e_rq_param *param, | |
544 | struct mlx5e_rq *rq) | |
545 | { | |
546 | struct mlx5e_priv *priv = c->priv; | |
547 | struct mlx5_core_dev *mdev = priv->mdev; | |
548 | void *rqc = param->rqc; | |
549 | void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
550 | u32 byte_count; | |
551 | u32 frag_sz; | |
552 | int npages; | |
553 | int wq_sz; | |
554 | int err; | |
555 | int i; | |
556 | ||
557 | param->wq.db_numa_node = cpu_to_node(c->cpu); | |
558 | ||
559 | err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq, | |
560 | &rq->wq_ctrl); | |
561 | if (err) | |
562 | return err; | |
563 | ||
564 | rq->wq.db = &rq->wq.db[MLX5_RCV_DBR]; | |
565 | ||
566 | wq_sz = mlx5_wq_ll_get_size(&rq->wq); | |
567 | ||
568 | rq->wq_type = priv->params.rq_wq_type; | |
569 | rq->pdev = c->pdev; | |
570 | rq->netdev = c->netdev; | |
571 | rq->tstamp = &priv->tstamp; | |
572 | rq->channel = c; | |
573 | rq->ix = c->ix; | |
574 | rq->priv = c->priv; | |
575 | ||
576 | rq->xdp_prog = priv->xdp_prog ? bpf_prog_inc(priv->xdp_prog) : NULL; | |
577 | if (IS_ERR(rq->xdp_prog)) { | |
578 | err = PTR_ERR(rq->xdp_prog); | |
579 | rq->xdp_prog = NULL; | |
580 | goto err_rq_wq_destroy; | |
581 | } | |
582 | ||
583 | if (rq->xdp_prog) { | |
584 | rq->buff.map_dir = DMA_BIDIRECTIONAL; | |
585 | rq->rx_headroom = XDP_PACKET_HEADROOM; | |
586 | } else { | |
587 | rq->buff.map_dir = DMA_FROM_DEVICE; | |
588 | rq->rx_headroom = MLX5_RX_HEADROOM; | |
589 | } | |
590 | ||
591 | switch (priv->params.rq_wq_type) { | |
592 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
593 | if (mlx5e_is_vf_vport_rep(priv)) { | |
594 | err = -EINVAL; | |
595 | goto err_rq_wq_destroy; | |
596 | } | |
597 | ||
598 | rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq; | |
599 | rq->alloc_wqe = mlx5e_alloc_rx_mpwqe; | |
600 | rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe; | |
601 | ||
602 | rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz); | |
603 | rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides); | |
604 | ||
605 | rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides; | |
606 | byte_count = rq->buff.wqe_sz; | |
607 | ||
608 | err = mlx5e_create_rq_umr_mkey(rq); | |
609 | if (err) | |
610 | goto err_rq_wq_destroy; | |
611 | rq->mkey_be = cpu_to_be32(rq->umr_mkey.key); | |
612 | ||
613 | err = mlx5e_rq_alloc_mpwqe_info(rq, c); | |
614 | if (err) | |
615 | goto err_destroy_umr_mkey; | |
616 | break; | |
617 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
618 | rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info), | |
619 | GFP_KERNEL, cpu_to_node(c->cpu)); | |
620 | if (!rq->dma_info) { | |
621 | err = -ENOMEM; | |
622 | goto err_rq_wq_destroy; | |
623 | } | |
624 | ||
625 | if (mlx5e_is_vf_vport_rep(priv)) | |
626 | rq->handle_rx_cqe = mlx5e_handle_rx_cqe_rep; | |
627 | else | |
628 | rq->handle_rx_cqe = mlx5e_handle_rx_cqe; | |
629 | ||
630 | rq->alloc_wqe = mlx5e_alloc_rx_wqe; | |
631 | rq->dealloc_wqe = mlx5e_dealloc_rx_wqe; | |
632 | ||
633 | rq->buff.wqe_sz = (priv->params.lro_en) ? | |
634 | priv->params.lro_wqe_sz : | |
635 | MLX5E_SW2HW_MTU(priv->netdev->mtu); | |
636 | byte_count = rq->buff.wqe_sz; | |
637 | ||
638 | /* calc the required page order */ | |
639 | frag_sz = rq->rx_headroom + | |
640 | byte_count /* packet data */ + | |
641 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
642 | frag_sz = SKB_DATA_ALIGN(frag_sz); | |
643 | ||
644 | npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE); | |
645 | rq->buff.page_order = order_base_2(npages); | |
646 | ||
647 | byte_count |= MLX5_HW_START_PADDING; | |
648 | rq->mkey_be = c->mkey_be; | |
649 | } | |
650 | ||
651 | for (i = 0; i < wq_sz; i++) { | |
652 | struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i); | |
653 | ||
654 | wqe->data.byte_count = cpu_to_be32(byte_count); | |
655 | wqe->data.lkey = rq->mkey_be; | |
656 | } | |
657 | ||
658 | INIT_WORK(&rq->am.work, mlx5e_rx_am_work); | |
659 | rq->am.mode = priv->params.rx_cq_period_mode; | |
660 | ||
661 | rq->page_cache.head = 0; | |
662 | rq->page_cache.tail = 0; | |
663 | ||
664 | return 0; | |
665 | ||
666 | err_destroy_umr_mkey: | |
667 | mlx5_core_destroy_mkey(mdev, &rq->umr_mkey); | |
668 | ||
669 | err_rq_wq_destroy: | |
670 | if (rq->xdp_prog) | |
671 | bpf_prog_put(rq->xdp_prog); | |
672 | mlx5_wq_destroy(&rq->wq_ctrl); | |
673 | ||
674 | return err; | |
675 | } | |
676 | ||
677 | static void mlx5e_destroy_rq(struct mlx5e_rq *rq) | |
678 | { | |
679 | int i; | |
680 | ||
681 | if (rq->xdp_prog) | |
682 | bpf_prog_put(rq->xdp_prog); | |
683 | ||
684 | switch (rq->wq_type) { | |
685 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
686 | mlx5e_rq_free_mpwqe_info(rq); | |
687 | mlx5_core_destroy_mkey(rq->priv->mdev, &rq->umr_mkey); | |
688 | break; | |
689 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
690 | kfree(rq->dma_info); | |
691 | } | |
692 | ||
693 | for (i = rq->page_cache.head; i != rq->page_cache.tail; | |
694 | i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) { | |
695 | struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i]; | |
696 | ||
697 | mlx5e_page_release(rq, dma_info, false); | |
698 | } | |
699 | mlx5_wq_destroy(&rq->wq_ctrl); | |
700 | } | |
701 | ||
702 | static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param) | |
703 | { | |
704 | struct mlx5e_priv *priv = rq->priv; | |
705 | struct mlx5_core_dev *mdev = priv->mdev; | |
706 | ||
707 | void *in; | |
708 | void *rqc; | |
709 | void *wq; | |
710 | int inlen; | |
711 | int err; | |
712 | ||
713 | inlen = MLX5_ST_SZ_BYTES(create_rq_in) + | |
714 | sizeof(u64) * rq->wq_ctrl.buf.npages; | |
715 | in = mlx5_vzalloc(inlen); | |
716 | if (!in) | |
717 | return -ENOMEM; | |
718 | ||
719 | rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); | |
720 | wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
721 | ||
722 | memcpy(rqc, param->rqc, sizeof(param->rqc)); | |
723 | ||
724 | MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn); | |
725 | MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); | |
726 | MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable); | |
727 | MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift - | |
728 | MLX5_ADAPTER_PAGE_SHIFT); | |
729 | MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma); | |
730 | ||
731 | mlx5_fill_page_array(&rq->wq_ctrl.buf, | |
732 | (__be64 *)MLX5_ADDR_OF(wq, wq, pas)); | |
733 | ||
734 | err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn); | |
735 | ||
736 | kvfree(in); | |
737 | ||
738 | return err; | |
739 | } | |
740 | ||
741 | static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, | |
742 | int next_state) | |
743 | { | |
744 | struct mlx5e_channel *c = rq->channel; | |
745 | struct mlx5e_priv *priv = c->priv; | |
746 | struct mlx5_core_dev *mdev = priv->mdev; | |
747 | ||
748 | void *in; | |
749 | void *rqc; | |
750 | int inlen; | |
751 | int err; | |
752 | ||
753 | inlen = MLX5_ST_SZ_BYTES(modify_rq_in); | |
754 | in = mlx5_vzalloc(inlen); | |
755 | if (!in) | |
756 | return -ENOMEM; | |
757 | ||
758 | rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); | |
759 | ||
760 | MLX5_SET(modify_rq_in, in, rq_state, curr_state); | |
761 | MLX5_SET(rqc, rqc, state, next_state); | |
762 | ||
763 | err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen); | |
764 | ||
765 | kvfree(in); | |
766 | ||
767 | return err; | |
768 | } | |
769 | ||
770 | static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd) | |
771 | { | |
772 | struct mlx5e_channel *c = rq->channel; | |
773 | struct mlx5e_priv *priv = c->priv; | |
774 | struct mlx5_core_dev *mdev = priv->mdev; | |
775 | ||
776 | void *in; | |
777 | void *rqc; | |
778 | int inlen; | |
779 | int err; | |
780 | ||
781 | inlen = MLX5_ST_SZ_BYTES(modify_rq_in); | |
782 | in = mlx5_vzalloc(inlen); | |
783 | if (!in) | |
784 | return -ENOMEM; | |
785 | ||
786 | rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); | |
787 | ||
788 | MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY); | |
789 | MLX5_SET64(modify_rq_in, in, modify_bitmask, | |
790 | MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); | |
791 | MLX5_SET(rqc, rqc, vsd, vsd); | |
792 | MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY); | |
793 | ||
794 | err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen); | |
795 | ||
796 | kvfree(in); | |
797 | ||
798 | return err; | |
799 | } | |
800 | ||
801 | static void mlx5e_disable_rq(struct mlx5e_rq *rq) | |
802 | { | |
803 | mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn); | |
804 | } | |
805 | ||
806 | static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq) | |
807 | { | |
808 | unsigned long exp_time = jiffies + msecs_to_jiffies(20000); | |
809 | struct mlx5e_channel *c = rq->channel; | |
810 | struct mlx5e_priv *priv = c->priv; | |
811 | struct mlx5_wq_ll *wq = &rq->wq; | |
812 | ||
813 | while (time_before(jiffies, exp_time)) { | |
814 | if (wq->cur_sz >= priv->params.min_rx_wqes) | |
815 | return 0; | |
816 | ||
817 | msleep(20); | |
818 | } | |
819 | ||
820 | return -ETIMEDOUT; | |
821 | } | |
822 | ||
823 | static void mlx5e_free_rx_descs(struct mlx5e_rq *rq) | |
824 | { | |
825 | struct mlx5_wq_ll *wq = &rq->wq; | |
826 | struct mlx5e_rx_wqe *wqe; | |
827 | __be16 wqe_ix_be; | |
828 | u16 wqe_ix; | |
829 | ||
830 | /* UMR WQE (if in progress) is always at wq->head */ | |
831 | if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state)) | |
832 | mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]); | |
833 | ||
834 | while (!mlx5_wq_ll_is_empty(wq)) { | |
835 | wqe_ix_be = *wq->tail_next; | |
836 | wqe_ix = be16_to_cpu(wqe_ix_be); | |
837 | wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix); | |
838 | rq->dealloc_wqe(rq, wqe_ix); | |
839 | mlx5_wq_ll_pop(&rq->wq, wqe_ix_be, | |
840 | &wqe->next.next_wqe_index); | |
841 | } | |
842 | } | |
843 | ||
844 | static int mlx5e_open_rq(struct mlx5e_channel *c, | |
845 | struct mlx5e_rq_param *param, | |
846 | struct mlx5e_rq *rq) | |
847 | { | |
848 | struct mlx5e_sq *sq = &c->icosq; | |
849 | u16 pi = sq->pc & sq->wq.sz_m1; | |
850 | int err; | |
851 | ||
852 | err = mlx5e_create_rq(c, param, rq); | |
853 | if (err) | |
854 | return err; | |
855 | ||
856 | err = mlx5e_enable_rq(rq, param); | |
857 | if (err) | |
858 | goto err_destroy_rq; | |
859 | ||
860 | set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state); | |
861 | err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); | |
862 | if (err) | |
863 | goto err_disable_rq; | |
864 | ||
865 | if (param->am_enabled) | |
866 | set_bit(MLX5E_RQ_STATE_AM, &c->rq.state); | |
867 | ||
868 | sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP; | |
869 | sq->db.ico_wqe[pi].num_wqebbs = 1; | |
870 | mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */ | |
871 | ||
872 | return 0; | |
873 | ||
874 | err_disable_rq: | |
875 | clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state); | |
876 | mlx5e_disable_rq(rq); | |
877 | err_destroy_rq: | |
878 | mlx5e_destroy_rq(rq); | |
879 | ||
880 | return err; | |
881 | } | |
882 | ||
883 | static void mlx5e_close_rq(struct mlx5e_rq *rq) | |
884 | { | |
885 | clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state); | |
886 | napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */ | |
887 | cancel_work_sync(&rq->am.work); | |
888 | ||
889 | mlx5e_disable_rq(rq); | |
890 | mlx5e_free_rx_descs(rq); | |
891 | mlx5e_destroy_rq(rq); | |
892 | } | |
893 | ||
894 | static void mlx5e_free_sq_xdp_db(struct mlx5e_sq *sq) | |
895 | { | |
896 | kfree(sq->db.xdp.di); | |
897 | kfree(sq->db.xdp.wqe_info); | |
898 | } | |
899 | ||
900 | static int mlx5e_alloc_sq_xdp_db(struct mlx5e_sq *sq, int numa) | |
901 | { | |
902 | int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); | |
903 | ||
904 | sq->db.xdp.di = kzalloc_node(sizeof(*sq->db.xdp.di) * wq_sz, | |
905 | GFP_KERNEL, numa); | |
906 | sq->db.xdp.wqe_info = kzalloc_node(sizeof(*sq->db.xdp.wqe_info) * wq_sz, | |
907 | GFP_KERNEL, numa); | |
908 | if (!sq->db.xdp.di || !sq->db.xdp.wqe_info) { | |
909 | mlx5e_free_sq_xdp_db(sq); | |
910 | return -ENOMEM; | |
911 | } | |
912 | ||
913 | return 0; | |
914 | } | |
915 | ||
916 | static void mlx5e_free_sq_ico_db(struct mlx5e_sq *sq) | |
917 | { | |
918 | kfree(sq->db.ico_wqe); | |
919 | } | |
920 | ||
921 | static int mlx5e_alloc_sq_ico_db(struct mlx5e_sq *sq, int numa) | |
922 | { | |
923 | u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq); | |
924 | ||
925 | sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz, | |
926 | GFP_KERNEL, numa); | |
927 | if (!sq->db.ico_wqe) | |
928 | return -ENOMEM; | |
929 | ||
930 | return 0; | |
931 | } | |
932 | ||
933 | static void mlx5e_free_sq_txq_db(struct mlx5e_sq *sq) | |
934 | { | |
935 | kfree(sq->db.txq.wqe_info); | |
936 | kfree(sq->db.txq.dma_fifo); | |
937 | kfree(sq->db.txq.skb); | |
938 | } | |
939 | ||
940 | static int mlx5e_alloc_sq_txq_db(struct mlx5e_sq *sq, int numa) | |
941 | { | |
942 | int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); | |
943 | int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS; | |
944 | ||
945 | sq->db.txq.skb = kzalloc_node(wq_sz * sizeof(*sq->db.txq.skb), | |
946 | GFP_KERNEL, numa); | |
947 | sq->db.txq.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.txq.dma_fifo), | |
948 | GFP_KERNEL, numa); | |
949 | sq->db.txq.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.txq.wqe_info), | |
950 | GFP_KERNEL, numa); | |
951 | if (!sq->db.txq.skb || !sq->db.txq.dma_fifo || !sq->db.txq.wqe_info) { | |
952 | mlx5e_free_sq_txq_db(sq); | |
953 | return -ENOMEM; | |
954 | } | |
955 | ||
956 | sq->dma_fifo_mask = df_sz - 1; | |
957 | ||
958 | return 0; | |
959 | } | |
960 | ||
961 | static void mlx5e_free_sq_db(struct mlx5e_sq *sq) | |
962 | { | |
963 | switch (sq->type) { | |
964 | case MLX5E_SQ_TXQ: | |
965 | mlx5e_free_sq_txq_db(sq); | |
966 | break; | |
967 | case MLX5E_SQ_ICO: | |
968 | mlx5e_free_sq_ico_db(sq); | |
969 | break; | |
970 | case MLX5E_SQ_XDP: | |
971 | mlx5e_free_sq_xdp_db(sq); | |
972 | break; | |
973 | } | |
974 | } | |
975 | ||
976 | static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa) | |
977 | { | |
978 | switch (sq->type) { | |
979 | case MLX5E_SQ_TXQ: | |
980 | return mlx5e_alloc_sq_txq_db(sq, numa); | |
981 | case MLX5E_SQ_ICO: | |
982 | return mlx5e_alloc_sq_ico_db(sq, numa); | |
983 | case MLX5E_SQ_XDP: | |
984 | return mlx5e_alloc_sq_xdp_db(sq, numa); | |
985 | } | |
986 | ||
987 | return 0; | |
988 | } | |
989 | ||
990 | static int mlx5e_sq_get_max_wqebbs(u8 sq_type) | |
991 | { | |
992 | switch (sq_type) { | |
993 | case MLX5E_SQ_ICO: | |
994 | return MLX5E_ICOSQ_MAX_WQEBBS; | |
995 | case MLX5E_SQ_XDP: | |
996 | return MLX5E_XDP_TX_WQEBBS; | |
997 | } | |
998 | return MLX5_SEND_WQE_MAX_WQEBBS; | |
999 | } | |
1000 | ||
1001 | static int mlx5e_create_sq(struct mlx5e_channel *c, | |
1002 | int tc, | |
1003 | struct mlx5e_sq_param *param, | |
1004 | struct mlx5e_sq *sq) | |
1005 | { | |
1006 | struct mlx5e_priv *priv = c->priv; | |
1007 | struct mlx5_core_dev *mdev = priv->mdev; | |
1008 | ||
1009 | void *sqc = param->sqc; | |
1010 | void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
1011 | int err; | |
1012 | ||
1013 | sq->type = param->type; | |
1014 | sq->pdev = c->pdev; | |
1015 | sq->tstamp = &priv->tstamp; | |
1016 | sq->mkey_be = c->mkey_be; | |
1017 | sq->channel = c; | |
1018 | sq->tc = tc; | |
1019 | sq->uar_map = mdev->mlx5e_res.bfreg.map; | |
1020 | ||
1021 | param->wq.db_numa_node = cpu_to_node(c->cpu); | |
1022 | ||
1023 | err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, | |
1024 | &sq->wq_ctrl); | |
1025 | if (err) | |
1026 | return err; | |
1027 | ||
1028 | sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; | |
1029 | ||
1030 | sq->max_inline = param->max_inline; | |
1031 | sq->min_inline_mode = param->min_inline_mode; | |
1032 | ||
1033 | err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu)); | |
1034 | if (err) | |
1035 | goto err_sq_wq_destroy; | |
1036 | ||
1037 | if (sq->type == MLX5E_SQ_TXQ) { | |
1038 | int txq_ix; | |
1039 | ||
1040 | txq_ix = c->ix + tc * priv->params.num_channels; | |
1041 | sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix); | |
1042 | priv->txq_to_sq_map[txq_ix] = sq; | |
1043 | } | |
1044 | ||
1045 | sq->edge = (sq->wq.sz_m1 + 1) - mlx5e_sq_get_max_wqebbs(sq->type); | |
1046 | ||
1047 | return 0; | |
1048 | ||
1049 | err_sq_wq_destroy: | |
1050 | mlx5_wq_destroy(&sq->wq_ctrl); | |
1051 | ||
1052 | return err; | |
1053 | } | |
1054 | ||
1055 | static void mlx5e_destroy_sq(struct mlx5e_sq *sq) | |
1056 | { | |
1057 | mlx5e_free_sq_db(sq); | |
1058 | mlx5_wq_destroy(&sq->wq_ctrl); | |
1059 | } | |
1060 | ||
1061 | static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param) | |
1062 | { | |
1063 | struct mlx5e_channel *c = sq->channel; | |
1064 | struct mlx5e_priv *priv = c->priv; | |
1065 | struct mlx5_core_dev *mdev = priv->mdev; | |
1066 | ||
1067 | void *in; | |
1068 | void *sqc; | |
1069 | void *wq; | |
1070 | int inlen; | |
1071 | int err; | |
1072 | ||
1073 | inlen = MLX5_ST_SZ_BYTES(create_sq_in) + | |
1074 | sizeof(u64) * sq->wq_ctrl.buf.npages; | |
1075 | in = mlx5_vzalloc(inlen); | |
1076 | if (!in) | |
1077 | return -ENOMEM; | |
1078 | ||
1079 | sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); | |
1080 | wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
1081 | ||
1082 | memcpy(sqc, param->sqc, sizeof(param->sqc)); | |
1083 | ||
1084 | MLX5_SET(sqc, sqc, tis_num_0, param->type == MLX5E_SQ_ICO ? | |
1085 | 0 : priv->tisn[sq->tc]); | |
1086 | MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn); | |
1087 | ||
1088 | if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) | |
1089 | MLX5_SET(sqc, sqc, min_wqe_inline_mode, sq->min_inline_mode); | |
1090 | ||
1091 | MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); | |
1092 | MLX5_SET(sqc, sqc, tis_lst_sz, param->type == MLX5E_SQ_ICO ? 0 : 1); | |
1093 | ||
1094 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); | |
1095 | MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index); | |
1096 | MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift - | |
1097 | MLX5_ADAPTER_PAGE_SHIFT); | |
1098 | MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma); | |
1099 | ||
1100 | mlx5_fill_page_array(&sq->wq_ctrl.buf, | |
1101 | (__be64 *)MLX5_ADDR_OF(wq, wq, pas)); | |
1102 | ||
1103 | err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn); | |
1104 | ||
1105 | kvfree(in); | |
1106 | ||
1107 | return err; | |
1108 | } | |
1109 | ||
1110 | static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, | |
1111 | int next_state, bool update_rl, int rl_index) | |
1112 | { | |
1113 | struct mlx5e_channel *c = sq->channel; | |
1114 | struct mlx5e_priv *priv = c->priv; | |
1115 | struct mlx5_core_dev *mdev = priv->mdev; | |
1116 | ||
1117 | void *in; | |
1118 | void *sqc; | |
1119 | int inlen; | |
1120 | int err; | |
1121 | ||
1122 | inlen = MLX5_ST_SZ_BYTES(modify_sq_in); | |
1123 | in = mlx5_vzalloc(inlen); | |
1124 | if (!in) | |
1125 | return -ENOMEM; | |
1126 | ||
1127 | sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); | |
1128 | ||
1129 | MLX5_SET(modify_sq_in, in, sq_state, curr_state); | |
1130 | MLX5_SET(sqc, sqc, state, next_state); | |
1131 | if (update_rl && next_state == MLX5_SQC_STATE_RDY) { | |
1132 | MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); | |
1133 | MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); | |
1134 | } | |
1135 | ||
1136 | err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen); | |
1137 | ||
1138 | kvfree(in); | |
1139 | ||
1140 | return err; | |
1141 | } | |
1142 | ||
1143 | static void mlx5e_disable_sq(struct mlx5e_sq *sq) | |
1144 | { | |
1145 | struct mlx5e_channel *c = sq->channel; | |
1146 | struct mlx5e_priv *priv = c->priv; | |
1147 | struct mlx5_core_dev *mdev = priv->mdev; | |
1148 | ||
1149 | mlx5_core_destroy_sq(mdev, sq->sqn); | |
1150 | if (sq->rate_limit) | |
1151 | mlx5_rl_remove_rate(mdev, sq->rate_limit); | |
1152 | } | |
1153 | ||
1154 | static int mlx5e_open_sq(struct mlx5e_channel *c, | |
1155 | int tc, | |
1156 | struct mlx5e_sq_param *param, | |
1157 | struct mlx5e_sq *sq) | |
1158 | { | |
1159 | int err; | |
1160 | ||
1161 | err = mlx5e_create_sq(c, tc, param, sq); | |
1162 | if (err) | |
1163 | return err; | |
1164 | ||
1165 | err = mlx5e_enable_sq(sq, param); | |
1166 | if (err) | |
1167 | goto err_destroy_sq; | |
1168 | ||
1169 | set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); | |
1170 | err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY, | |
1171 | false, 0); | |
1172 | if (err) | |
1173 | goto err_disable_sq; | |
1174 | ||
1175 | if (sq->txq) { | |
1176 | netdev_tx_reset_queue(sq->txq); | |
1177 | netif_tx_start_queue(sq->txq); | |
1178 | } | |
1179 | ||
1180 | return 0; | |
1181 | ||
1182 | err_disable_sq: | |
1183 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); | |
1184 | mlx5e_disable_sq(sq); | |
1185 | err_destroy_sq: | |
1186 | mlx5e_destroy_sq(sq); | |
1187 | ||
1188 | return err; | |
1189 | } | |
1190 | ||
1191 | static inline void netif_tx_disable_queue(struct netdev_queue *txq) | |
1192 | { | |
1193 | __netif_tx_lock_bh(txq); | |
1194 | netif_tx_stop_queue(txq); | |
1195 | __netif_tx_unlock_bh(txq); | |
1196 | } | |
1197 | ||
1198 | static void mlx5e_close_sq(struct mlx5e_sq *sq) | |
1199 | { | |
1200 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); | |
1201 | /* prevent netif_tx_wake_queue */ | |
1202 | napi_synchronize(&sq->channel->napi); | |
1203 | ||
1204 | if (sq->txq) { | |
1205 | netif_tx_disable_queue(sq->txq); | |
1206 | ||
1207 | /* last doorbell out, godspeed .. */ | |
1208 | if (mlx5e_sq_has_room_for(sq, 1)) { | |
1209 | sq->db.txq.skb[(sq->pc & sq->wq.sz_m1)] = NULL; | |
1210 | mlx5e_send_nop(sq, true); | |
1211 | } | |
1212 | } | |
1213 | ||
1214 | mlx5e_disable_sq(sq); | |
1215 | mlx5e_free_sq_descs(sq); | |
1216 | mlx5e_destroy_sq(sq); | |
1217 | } | |
1218 | ||
1219 | static int mlx5e_create_cq(struct mlx5e_channel *c, | |
1220 | struct mlx5e_cq_param *param, | |
1221 | struct mlx5e_cq *cq) | |
1222 | { | |
1223 | struct mlx5e_priv *priv = c->priv; | |
1224 | struct mlx5_core_dev *mdev = priv->mdev; | |
1225 | struct mlx5_core_cq *mcq = &cq->mcq; | |
1226 | int eqn_not_used; | |
1227 | unsigned int irqn; | |
1228 | int err; | |
1229 | u32 i; | |
1230 | ||
1231 | param->wq.buf_numa_node = cpu_to_node(c->cpu); | |
1232 | param->wq.db_numa_node = cpu_to_node(c->cpu); | |
1233 | param->eq_ix = c->ix; | |
1234 | ||
1235 | err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, | |
1236 | &cq->wq_ctrl); | |
1237 | if (err) | |
1238 | return err; | |
1239 | ||
1240 | mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn); | |
1241 | ||
1242 | cq->napi = &c->napi; | |
1243 | ||
1244 | mcq->cqe_sz = 64; | |
1245 | mcq->set_ci_db = cq->wq_ctrl.db.db; | |
1246 | mcq->arm_db = cq->wq_ctrl.db.db + 1; | |
1247 | *mcq->set_ci_db = 0; | |
1248 | *mcq->arm_db = 0; | |
1249 | mcq->vector = param->eq_ix; | |
1250 | mcq->comp = mlx5e_completion_event; | |
1251 | mcq->event = mlx5e_cq_error_event; | |
1252 | mcq->irqn = irqn; | |
1253 | ||
1254 | for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) { | |
1255 | struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i); | |
1256 | ||
1257 | cqe->op_own = 0xf1; | |
1258 | } | |
1259 | ||
1260 | cq->channel = c; | |
1261 | cq->priv = priv; | |
1262 | ||
1263 | return 0; | |
1264 | } | |
1265 | ||
1266 | static void mlx5e_destroy_cq(struct mlx5e_cq *cq) | |
1267 | { | |
1268 | mlx5_cqwq_destroy(&cq->wq_ctrl); | |
1269 | } | |
1270 | ||
1271 | static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param) | |
1272 | { | |
1273 | struct mlx5e_priv *priv = cq->priv; | |
1274 | struct mlx5_core_dev *mdev = priv->mdev; | |
1275 | struct mlx5_core_cq *mcq = &cq->mcq; | |
1276 | ||
1277 | void *in; | |
1278 | void *cqc; | |
1279 | int inlen; | |
1280 | unsigned int irqn_not_used; | |
1281 | int eqn; | |
1282 | int err; | |
1283 | ||
1284 | inlen = MLX5_ST_SZ_BYTES(create_cq_in) + | |
1285 | sizeof(u64) * cq->wq_ctrl.frag_buf.npages; | |
1286 | in = mlx5_vzalloc(inlen); | |
1287 | if (!in) | |
1288 | return -ENOMEM; | |
1289 | ||
1290 | cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); | |
1291 | ||
1292 | memcpy(cqc, param->cqc, sizeof(param->cqc)); | |
1293 | ||
1294 | mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf, | |
1295 | (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas)); | |
1296 | ||
1297 | mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used); | |
1298 | ||
1299 | MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode); | |
1300 | MLX5_SET(cqc, cqc, c_eqn, eqn); | |
1301 | MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index); | |
1302 | MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift - | |
1303 | MLX5_ADAPTER_PAGE_SHIFT); | |
1304 | MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); | |
1305 | ||
1306 | err = mlx5_core_create_cq(mdev, mcq, in, inlen); | |
1307 | ||
1308 | kvfree(in); | |
1309 | ||
1310 | if (err) | |
1311 | return err; | |
1312 | ||
1313 | mlx5e_cq_arm(cq); | |
1314 | ||
1315 | return 0; | |
1316 | } | |
1317 | ||
1318 | static void mlx5e_disable_cq(struct mlx5e_cq *cq) | |
1319 | { | |
1320 | struct mlx5e_priv *priv = cq->priv; | |
1321 | struct mlx5_core_dev *mdev = priv->mdev; | |
1322 | ||
1323 | mlx5_core_destroy_cq(mdev, &cq->mcq); | |
1324 | } | |
1325 | ||
1326 | static int mlx5e_open_cq(struct mlx5e_channel *c, | |
1327 | struct mlx5e_cq_param *param, | |
1328 | struct mlx5e_cq *cq, | |
1329 | struct mlx5e_cq_moder moderation) | |
1330 | { | |
1331 | int err; | |
1332 | struct mlx5e_priv *priv = c->priv; | |
1333 | struct mlx5_core_dev *mdev = priv->mdev; | |
1334 | ||
1335 | err = mlx5e_create_cq(c, param, cq); | |
1336 | if (err) | |
1337 | return err; | |
1338 | ||
1339 | err = mlx5e_enable_cq(cq, param); | |
1340 | if (err) | |
1341 | goto err_destroy_cq; | |
1342 | ||
1343 | if (MLX5_CAP_GEN(mdev, cq_moderation)) | |
1344 | mlx5_core_modify_cq_moderation(mdev, &cq->mcq, | |
1345 | moderation.usec, | |
1346 | moderation.pkts); | |
1347 | return 0; | |
1348 | ||
1349 | err_destroy_cq: | |
1350 | mlx5e_destroy_cq(cq); | |
1351 | ||
1352 | return err; | |
1353 | } | |
1354 | ||
1355 | static void mlx5e_close_cq(struct mlx5e_cq *cq) | |
1356 | { | |
1357 | mlx5e_disable_cq(cq); | |
1358 | mlx5e_destroy_cq(cq); | |
1359 | } | |
1360 | ||
1361 | static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix) | |
1362 | { | |
1363 | return cpumask_first(priv->mdev->priv.irq_info[ix].mask); | |
1364 | } | |
1365 | ||
1366 | static int mlx5e_open_tx_cqs(struct mlx5e_channel *c, | |
1367 | struct mlx5e_channel_param *cparam) | |
1368 | { | |
1369 | struct mlx5e_priv *priv = c->priv; | |
1370 | int err; | |
1371 | int tc; | |
1372 | ||
1373 | for (tc = 0; tc < c->num_tc; tc++) { | |
1374 | err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq, | |
1375 | priv->params.tx_cq_moderation); | |
1376 | if (err) | |
1377 | goto err_close_tx_cqs; | |
1378 | } | |
1379 | ||
1380 | return 0; | |
1381 | ||
1382 | err_close_tx_cqs: | |
1383 | for (tc--; tc >= 0; tc--) | |
1384 | mlx5e_close_cq(&c->sq[tc].cq); | |
1385 | ||
1386 | return err; | |
1387 | } | |
1388 | ||
1389 | static void mlx5e_close_tx_cqs(struct mlx5e_channel *c) | |
1390 | { | |
1391 | int tc; | |
1392 | ||
1393 | for (tc = 0; tc < c->num_tc; tc++) | |
1394 | mlx5e_close_cq(&c->sq[tc].cq); | |
1395 | } | |
1396 | ||
1397 | static int mlx5e_open_sqs(struct mlx5e_channel *c, | |
1398 | struct mlx5e_channel_param *cparam) | |
1399 | { | |
1400 | int err; | |
1401 | int tc; | |
1402 | ||
1403 | for (tc = 0; tc < c->num_tc; tc++) { | |
1404 | err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]); | |
1405 | if (err) | |
1406 | goto err_close_sqs; | |
1407 | } | |
1408 | ||
1409 | return 0; | |
1410 | ||
1411 | err_close_sqs: | |
1412 | for (tc--; tc >= 0; tc--) | |
1413 | mlx5e_close_sq(&c->sq[tc]); | |
1414 | ||
1415 | return err; | |
1416 | } | |
1417 | ||
1418 | static void mlx5e_close_sqs(struct mlx5e_channel *c) | |
1419 | { | |
1420 | int tc; | |
1421 | ||
1422 | for (tc = 0; tc < c->num_tc; tc++) | |
1423 | mlx5e_close_sq(&c->sq[tc]); | |
1424 | } | |
1425 | ||
1426 | static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix) | |
1427 | { | |
1428 | int i; | |
1429 | ||
1430 | for (i = 0; i < priv->profile->max_tc; i++) | |
1431 | priv->channeltc_to_txq_map[ix][i] = | |
1432 | ix + i * priv->params.num_channels; | |
1433 | } | |
1434 | ||
1435 | static int mlx5e_set_sq_maxrate(struct net_device *dev, | |
1436 | struct mlx5e_sq *sq, u32 rate) | |
1437 | { | |
1438 | struct mlx5e_priv *priv = netdev_priv(dev); | |
1439 | struct mlx5_core_dev *mdev = priv->mdev; | |
1440 | u16 rl_index = 0; | |
1441 | int err; | |
1442 | ||
1443 | if (rate == sq->rate_limit) | |
1444 | /* nothing to do */ | |
1445 | return 0; | |
1446 | ||
1447 | if (sq->rate_limit) | |
1448 | /* remove current rl index to free space to next ones */ | |
1449 | mlx5_rl_remove_rate(mdev, sq->rate_limit); | |
1450 | ||
1451 | sq->rate_limit = 0; | |
1452 | ||
1453 | if (rate) { | |
1454 | err = mlx5_rl_add_rate(mdev, rate, &rl_index); | |
1455 | if (err) { | |
1456 | netdev_err(dev, "Failed configuring rate %u: %d\n", | |
1457 | rate, err); | |
1458 | return err; | |
1459 | } | |
1460 | } | |
1461 | ||
1462 | err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, | |
1463 | MLX5_SQC_STATE_RDY, true, rl_index); | |
1464 | if (err) { | |
1465 | netdev_err(dev, "Failed configuring rate %u: %d\n", | |
1466 | rate, err); | |
1467 | /* remove the rate from the table */ | |
1468 | if (rate) | |
1469 | mlx5_rl_remove_rate(mdev, rate); | |
1470 | return err; | |
1471 | } | |
1472 | ||
1473 | sq->rate_limit = rate; | |
1474 | return 0; | |
1475 | } | |
1476 | ||
1477 | static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate) | |
1478 | { | |
1479 | struct mlx5e_priv *priv = netdev_priv(dev); | |
1480 | struct mlx5_core_dev *mdev = priv->mdev; | |
1481 | struct mlx5e_sq *sq = priv->txq_to_sq_map[index]; | |
1482 | int err = 0; | |
1483 | ||
1484 | if (!mlx5_rl_is_supported(mdev)) { | |
1485 | netdev_err(dev, "Rate limiting is not supported on this device\n"); | |
1486 | return -EINVAL; | |
1487 | } | |
1488 | ||
1489 | /* rate is given in Mb/sec, HW config is in Kb/sec */ | |
1490 | rate = rate << 10; | |
1491 | ||
1492 | /* Check whether rate in valid range, 0 is always valid */ | |
1493 | if (rate && !mlx5_rl_is_in_range(mdev, rate)) { | |
1494 | netdev_err(dev, "TX rate %u, is not in range\n", rate); | |
1495 | return -ERANGE; | |
1496 | } | |
1497 | ||
1498 | mutex_lock(&priv->state_lock); | |
1499 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
1500 | err = mlx5e_set_sq_maxrate(dev, sq, rate); | |
1501 | if (!err) | |
1502 | priv->tx_rates[index] = rate; | |
1503 | mutex_unlock(&priv->state_lock); | |
1504 | ||
1505 | return err; | |
1506 | } | |
1507 | ||
1508 | static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) | |
1509 | { | |
1510 | return is_kdump_kernel() ? | |
1511 | MLX5E_MIN_NUM_CHANNELS : | |
1512 | min_t(int, mdev->priv.eq_table.num_comp_vectors, | |
1513 | MLX5E_MAX_NUM_CHANNELS); | |
1514 | } | |
1515 | ||
1516 | static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix, | |
1517 | struct mlx5e_channel_param *cparam, | |
1518 | struct mlx5e_channel **cp) | |
1519 | { | |
1520 | struct mlx5e_cq_moder icosq_cq_moder = {0, 0}; | |
1521 | struct net_device *netdev = priv->netdev; | |
1522 | struct mlx5e_cq_moder rx_cq_profile; | |
1523 | int cpu = mlx5e_get_cpu(priv, ix); | |
1524 | struct mlx5e_channel *c; | |
1525 | struct mlx5e_sq *sq; | |
1526 | int err; | |
1527 | int i; | |
1528 | ||
1529 | c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu)); | |
1530 | if (!c) | |
1531 | return -ENOMEM; | |
1532 | ||
1533 | c->priv = priv; | |
1534 | c->ix = ix; | |
1535 | c->cpu = cpu; | |
1536 | c->pdev = &priv->mdev->pdev->dev; | |
1537 | c->netdev = priv->netdev; | |
1538 | c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key); | |
1539 | c->num_tc = priv->params.num_tc; | |
1540 | c->xdp = !!priv->xdp_prog; | |
1541 | ||
1542 | if (priv->params.rx_am_enabled) | |
1543 | rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode); | |
1544 | else | |
1545 | rx_cq_profile = priv->params.rx_cq_moderation; | |
1546 | ||
1547 | mlx5e_build_channeltc_to_txq_map(priv, ix); | |
1548 | ||
1549 | netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64); | |
1550 | ||
1551 | err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder); | |
1552 | if (err) | |
1553 | goto err_napi_del; | |
1554 | ||
1555 | err = mlx5e_open_tx_cqs(c, cparam); | |
1556 | if (err) | |
1557 | goto err_close_icosq_cq; | |
1558 | ||
1559 | err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq, | |
1560 | rx_cq_profile); | |
1561 | if (err) | |
1562 | goto err_close_tx_cqs; | |
1563 | ||
1564 | /* XDP SQ CQ params are same as normal TXQ sq CQ params */ | |
1565 | err = c->xdp ? mlx5e_open_cq(c, &cparam->tx_cq, &c->xdp_sq.cq, | |
1566 | priv->params.tx_cq_moderation) : 0; | |
1567 | if (err) | |
1568 | goto err_close_rx_cq; | |
1569 | ||
1570 | napi_enable(&c->napi); | |
1571 | ||
1572 | err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq); | |
1573 | if (err) | |
1574 | goto err_disable_napi; | |
1575 | ||
1576 | err = mlx5e_open_sqs(c, cparam); | |
1577 | if (err) | |
1578 | goto err_close_icosq; | |
1579 | ||
1580 | for (i = 0; i < priv->params.num_tc; i++) { | |
1581 | u32 txq_ix = priv->channeltc_to_txq_map[ix][i]; | |
1582 | ||
1583 | if (priv->tx_rates[txq_ix]) { | |
1584 | sq = priv->txq_to_sq_map[txq_ix]; | |
1585 | mlx5e_set_sq_maxrate(priv->netdev, sq, | |
1586 | priv->tx_rates[txq_ix]); | |
1587 | } | |
1588 | } | |
1589 | ||
1590 | err = c->xdp ? mlx5e_open_sq(c, 0, &cparam->xdp_sq, &c->xdp_sq) : 0; | |
1591 | if (err) | |
1592 | goto err_close_sqs; | |
1593 | ||
1594 | err = mlx5e_open_rq(c, &cparam->rq, &c->rq); | |
1595 | if (err) | |
1596 | goto err_close_xdp_sq; | |
1597 | ||
1598 | netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix); | |
1599 | *cp = c; | |
1600 | ||
1601 | return 0; | |
1602 | err_close_xdp_sq: | |
1603 | if (c->xdp) | |
1604 | mlx5e_close_sq(&c->xdp_sq); | |
1605 | ||
1606 | err_close_sqs: | |
1607 | mlx5e_close_sqs(c); | |
1608 | ||
1609 | err_close_icosq: | |
1610 | mlx5e_close_sq(&c->icosq); | |
1611 | ||
1612 | err_disable_napi: | |
1613 | napi_disable(&c->napi); | |
1614 | if (c->xdp) | |
1615 | mlx5e_close_cq(&c->xdp_sq.cq); | |
1616 | ||
1617 | err_close_rx_cq: | |
1618 | mlx5e_close_cq(&c->rq.cq); | |
1619 | ||
1620 | err_close_tx_cqs: | |
1621 | mlx5e_close_tx_cqs(c); | |
1622 | ||
1623 | err_close_icosq_cq: | |
1624 | mlx5e_close_cq(&c->icosq.cq); | |
1625 | ||
1626 | err_napi_del: | |
1627 | netif_napi_del(&c->napi); | |
1628 | kfree(c); | |
1629 | ||
1630 | return err; | |
1631 | } | |
1632 | ||
1633 | static void mlx5e_close_channel(struct mlx5e_channel *c) | |
1634 | { | |
1635 | mlx5e_close_rq(&c->rq); | |
1636 | if (c->xdp) | |
1637 | mlx5e_close_sq(&c->xdp_sq); | |
1638 | mlx5e_close_sqs(c); | |
1639 | mlx5e_close_sq(&c->icosq); | |
1640 | napi_disable(&c->napi); | |
1641 | if (c->xdp) | |
1642 | mlx5e_close_cq(&c->xdp_sq.cq); | |
1643 | mlx5e_close_cq(&c->rq.cq); | |
1644 | mlx5e_close_tx_cqs(c); | |
1645 | mlx5e_close_cq(&c->icosq.cq); | |
1646 | netif_napi_del(&c->napi); | |
1647 | ||
1648 | kfree(c); | |
1649 | } | |
1650 | ||
1651 | static void mlx5e_build_rq_param(struct mlx5e_priv *priv, | |
1652 | struct mlx5e_rq_param *param) | |
1653 | { | |
1654 | void *rqc = param->rqc; | |
1655 | void *wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
1656 | ||
1657 | switch (priv->params.rq_wq_type) { | |
1658 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
1659 | MLX5_SET(wq, wq, log_wqe_num_of_strides, | |
1660 | priv->params.mpwqe_log_num_strides - 9); | |
1661 | MLX5_SET(wq, wq, log_wqe_stride_size, | |
1662 | priv->params.mpwqe_log_stride_sz - 6); | |
1663 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ); | |
1664 | break; | |
1665 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
1666 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); | |
1667 | } | |
1668 | ||
1669 | MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); | |
1670 | MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe))); | |
1671 | MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size); | |
1672 | MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn); | |
1673 | MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter); | |
1674 | ||
1675 | param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev); | |
1676 | param->wq.linear = 1; | |
1677 | ||
1678 | param->am_enabled = priv->params.rx_am_enabled; | |
1679 | } | |
1680 | ||
1681 | static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param) | |
1682 | { | |
1683 | void *rqc = param->rqc; | |
1684 | void *wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
1685 | ||
1686 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); | |
1687 | MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe))); | |
1688 | } | |
1689 | ||
1690 | static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv, | |
1691 | struct mlx5e_sq_param *param) | |
1692 | { | |
1693 | void *sqc = param->sqc; | |
1694 | void *wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
1695 | ||
1696 | MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); | |
1697 | MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn); | |
1698 | ||
1699 | param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev); | |
1700 | } | |
1701 | ||
1702 | static void mlx5e_build_sq_param(struct mlx5e_priv *priv, | |
1703 | struct mlx5e_sq_param *param) | |
1704 | { | |
1705 | void *sqc = param->sqc; | |
1706 | void *wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
1707 | ||
1708 | mlx5e_build_sq_param_common(priv, param); | |
1709 | MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size); | |
1710 | ||
1711 | param->max_inline = priv->params.tx_max_inline; | |
1712 | param->min_inline_mode = priv->params.tx_min_inline_mode; | |
1713 | param->type = MLX5E_SQ_TXQ; | |
1714 | } | |
1715 | ||
1716 | static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv, | |
1717 | struct mlx5e_cq_param *param) | |
1718 | { | |
1719 | void *cqc = param->cqc; | |
1720 | ||
1721 | MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index); | |
1722 | } | |
1723 | ||
1724 | static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv, | |
1725 | struct mlx5e_cq_param *param) | |
1726 | { | |
1727 | void *cqc = param->cqc; | |
1728 | u8 log_cq_size; | |
1729 | ||
1730 | switch (priv->params.rq_wq_type) { | |
1731 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
1732 | log_cq_size = priv->params.log_rq_size + | |
1733 | priv->params.mpwqe_log_num_strides; | |
1734 | break; | |
1735 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
1736 | log_cq_size = priv->params.log_rq_size; | |
1737 | } | |
1738 | ||
1739 | MLX5_SET(cqc, cqc, log_cq_size, log_cq_size); | |
1740 | if (MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS)) { | |
1741 | MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM); | |
1742 | MLX5_SET(cqc, cqc, cqe_comp_en, 1); | |
1743 | } | |
1744 | ||
1745 | mlx5e_build_common_cq_param(priv, param); | |
1746 | ||
1747 | param->cq_period_mode = priv->params.rx_cq_period_mode; | |
1748 | } | |
1749 | ||
1750 | static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv, | |
1751 | struct mlx5e_cq_param *param) | |
1752 | { | |
1753 | void *cqc = param->cqc; | |
1754 | ||
1755 | MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size); | |
1756 | ||
1757 | mlx5e_build_common_cq_param(priv, param); | |
1758 | ||
1759 | param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE; | |
1760 | } | |
1761 | ||
1762 | static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv, | |
1763 | struct mlx5e_cq_param *param, | |
1764 | u8 log_wq_size) | |
1765 | { | |
1766 | void *cqc = param->cqc; | |
1767 | ||
1768 | MLX5_SET(cqc, cqc, log_cq_size, log_wq_size); | |
1769 | ||
1770 | mlx5e_build_common_cq_param(priv, param); | |
1771 | ||
1772 | param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE; | |
1773 | } | |
1774 | ||
1775 | static void mlx5e_build_icosq_param(struct mlx5e_priv *priv, | |
1776 | struct mlx5e_sq_param *param, | |
1777 | u8 log_wq_size) | |
1778 | { | |
1779 | void *sqc = param->sqc; | |
1780 | void *wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
1781 | ||
1782 | mlx5e_build_sq_param_common(priv, param); | |
1783 | ||
1784 | MLX5_SET(wq, wq, log_wq_sz, log_wq_size); | |
1785 | MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq)); | |
1786 | ||
1787 | param->type = MLX5E_SQ_ICO; | |
1788 | } | |
1789 | ||
1790 | static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv, | |
1791 | struct mlx5e_sq_param *param) | |
1792 | { | |
1793 | void *sqc = param->sqc; | |
1794 | void *wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
1795 | ||
1796 | mlx5e_build_sq_param_common(priv, param); | |
1797 | MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size); | |
1798 | ||
1799 | param->max_inline = priv->params.tx_max_inline; | |
1800 | param->min_inline_mode = priv->params.tx_min_inline_mode; | |
1801 | param->type = MLX5E_SQ_XDP; | |
1802 | } | |
1803 | ||
1804 | static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam) | |
1805 | { | |
1806 | u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE; | |
1807 | ||
1808 | mlx5e_build_rq_param(priv, &cparam->rq); | |
1809 | mlx5e_build_sq_param(priv, &cparam->sq); | |
1810 | mlx5e_build_xdpsq_param(priv, &cparam->xdp_sq); | |
1811 | mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz); | |
1812 | mlx5e_build_rx_cq_param(priv, &cparam->rx_cq); | |
1813 | mlx5e_build_tx_cq_param(priv, &cparam->tx_cq); | |
1814 | mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz); | |
1815 | } | |
1816 | ||
1817 | static int mlx5e_open_channels(struct mlx5e_priv *priv) | |
1818 | { | |
1819 | struct mlx5e_channel_param *cparam; | |
1820 | int nch = priv->params.num_channels; | |
1821 | int err = -ENOMEM; | |
1822 | int i; | |
1823 | int j; | |
1824 | ||
1825 | priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *), | |
1826 | GFP_KERNEL); | |
1827 | ||
1828 | priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc, | |
1829 | sizeof(struct mlx5e_sq *), GFP_KERNEL); | |
1830 | ||
1831 | cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL); | |
1832 | ||
1833 | if (!priv->channel || !priv->txq_to_sq_map || !cparam) | |
1834 | goto err_free_txq_to_sq_map; | |
1835 | ||
1836 | mlx5e_build_channel_param(priv, cparam); | |
1837 | ||
1838 | for (i = 0; i < nch; i++) { | |
1839 | err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]); | |
1840 | if (err) | |
1841 | goto err_close_channels; | |
1842 | } | |
1843 | ||
1844 | for (j = 0; j < nch; j++) { | |
1845 | err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq); | |
1846 | if (err) | |
1847 | goto err_close_channels; | |
1848 | } | |
1849 | ||
1850 | /* FIXME: This is a W/A for tx timeout watch dog false alarm when | |
1851 | * polling for inactive tx queues. | |
1852 | */ | |
1853 | netif_tx_start_all_queues(priv->netdev); | |
1854 | ||
1855 | kfree(cparam); | |
1856 | return 0; | |
1857 | ||
1858 | err_close_channels: | |
1859 | for (i--; i >= 0; i--) | |
1860 | mlx5e_close_channel(priv->channel[i]); | |
1861 | ||
1862 | err_free_txq_to_sq_map: | |
1863 | kfree(priv->txq_to_sq_map); | |
1864 | kfree(priv->channel); | |
1865 | kfree(cparam); | |
1866 | ||
1867 | return err; | |
1868 | } | |
1869 | ||
1870 | static void mlx5e_close_channels(struct mlx5e_priv *priv) | |
1871 | { | |
1872 | int i; | |
1873 | ||
1874 | /* FIXME: This is a W/A only for tx timeout watch dog false alarm when | |
1875 | * polling for inactive tx queues. | |
1876 | */ | |
1877 | netif_tx_stop_all_queues(priv->netdev); | |
1878 | netif_tx_disable(priv->netdev); | |
1879 | ||
1880 | for (i = 0; i < priv->params.num_channels; i++) | |
1881 | mlx5e_close_channel(priv->channel[i]); | |
1882 | ||
1883 | kfree(priv->txq_to_sq_map); | |
1884 | kfree(priv->channel); | |
1885 | } | |
1886 | ||
1887 | static int mlx5e_rx_hash_fn(int hfunc) | |
1888 | { | |
1889 | return (hfunc == ETH_RSS_HASH_TOP) ? | |
1890 | MLX5_RX_HASH_FN_TOEPLITZ : | |
1891 | MLX5_RX_HASH_FN_INVERTED_XOR8; | |
1892 | } | |
1893 | ||
1894 | static int mlx5e_bits_invert(unsigned long a, int size) | |
1895 | { | |
1896 | int inv = 0; | |
1897 | int i; | |
1898 | ||
1899 | for (i = 0; i < size; i++) | |
1900 | inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i; | |
1901 | ||
1902 | return inv; | |
1903 | } | |
1904 | ||
1905 | static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc) | |
1906 | { | |
1907 | int i; | |
1908 | ||
1909 | for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) { | |
1910 | int ix = i; | |
1911 | u32 rqn; | |
1912 | ||
1913 | if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR) | |
1914 | ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE); | |
1915 | ||
1916 | ix = priv->params.indirection_rqt[ix]; | |
1917 | rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ? | |
1918 | priv->channel[ix]->rq.rqn : | |
1919 | priv->drop_rq.rqn; | |
1920 | MLX5_SET(rqtc, rqtc, rq_num[i], rqn); | |
1921 | } | |
1922 | } | |
1923 | ||
1924 | static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc, | |
1925 | int ix) | |
1926 | { | |
1927 | u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ? | |
1928 | priv->channel[ix]->rq.rqn : | |
1929 | priv->drop_rq.rqn; | |
1930 | ||
1931 | MLX5_SET(rqtc, rqtc, rq_num[0], rqn); | |
1932 | } | |
1933 | ||
1934 | static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, | |
1935 | int ix, struct mlx5e_rqt *rqt) | |
1936 | { | |
1937 | struct mlx5_core_dev *mdev = priv->mdev; | |
1938 | void *rqtc; | |
1939 | int inlen; | |
1940 | int err; | |
1941 | u32 *in; | |
1942 | ||
1943 | inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; | |
1944 | in = mlx5_vzalloc(inlen); | |
1945 | if (!in) | |
1946 | return -ENOMEM; | |
1947 | ||
1948 | rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); | |
1949 | ||
1950 | MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); | |
1951 | MLX5_SET(rqtc, rqtc, rqt_max_size, sz); | |
1952 | ||
1953 | if (sz > 1) /* RSS */ | |
1954 | mlx5e_fill_indir_rqt_rqns(priv, rqtc); | |
1955 | else | |
1956 | mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix); | |
1957 | ||
1958 | err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn); | |
1959 | if (!err) | |
1960 | rqt->enabled = true; | |
1961 | ||
1962 | kvfree(in); | |
1963 | return err; | |
1964 | } | |
1965 | ||
1966 | void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt) | |
1967 | { | |
1968 | rqt->enabled = false; | |
1969 | mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn); | |
1970 | } | |
1971 | ||
1972 | static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv) | |
1973 | { | |
1974 | struct mlx5e_rqt *rqt = &priv->indir_rqt; | |
1975 | ||
1976 | return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt); | |
1977 | } | |
1978 | ||
1979 | int mlx5e_create_direct_rqts(struct mlx5e_priv *priv) | |
1980 | { | |
1981 | struct mlx5e_rqt *rqt; | |
1982 | int err; | |
1983 | int ix; | |
1984 | ||
1985 | for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) { | |
1986 | rqt = &priv->direct_tir[ix].rqt; | |
1987 | err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt); | |
1988 | if (err) | |
1989 | goto err_destroy_rqts; | |
1990 | } | |
1991 | ||
1992 | return 0; | |
1993 | ||
1994 | err_destroy_rqts: | |
1995 | for (ix--; ix >= 0; ix--) | |
1996 | mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt); | |
1997 | ||
1998 | return err; | |
1999 | } | |
2000 | ||
2001 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix) | |
2002 | { | |
2003 | struct mlx5_core_dev *mdev = priv->mdev; | |
2004 | void *rqtc; | |
2005 | int inlen; | |
2006 | u32 *in; | |
2007 | int err; | |
2008 | ||
2009 | inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz; | |
2010 | in = mlx5_vzalloc(inlen); | |
2011 | if (!in) | |
2012 | return -ENOMEM; | |
2013 | ||
2014 | rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx); | |
2015 | ||
2016 | MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); | |
2017 | if (sz > 1) /* RSS */ | |
2018 | mlx5e_fill_indir_rqt_rqns(priv, rqtc); | |
2019 | else | |
2020 | mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix); | |
2021 | ||
2022 | MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1); | |
2023 | ||
2024 | err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen); | |
2025 | ||
2026 | kvfree(in); | |
2027 | ||
2028 | return err; | |
2029 | } | |
2030 | ||
2031 | static void mlx5e_redirect_rqts(struct mlx5e_priv *priv) | |
2032 | { | |
2033 | u32 rqtn; | |
2034 | int ix; | |
2035 | ||
2036 | if (priv->indir_rqt.enabled) { | |
2037 | rqtn = priv->indir_rqt.rqtn; | |
2038 | mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0); | |
2039 | } | |
2040 | ||
2041 | for (ix = 0; ix < priv->params.num_channels; ix++) { | |
2042 | if (!priv->direct_tir[ix].rqt.enabled) | |
2043 | continue; | |
2044 | rqtn = priv->direct_tir[ix].rqt.rqtn; | |
2045 | mlx5e_redirect_rqt(priv, rqtn, 1, ix); | |
2046 | } | |
2047 | } | |
2048 | ||
2049 | static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv) | |
2050 | { | |
2051 | if (!priv->params.lro_en) | |
2052 | return; | |
2053 | ||
2054 | #define ROUGH_MAX_L2_L3_HDR_SZ 256 | |
2055 | ||
2056 | MLX5_SET(tirc, tirc, lro_enable_mask, | |
2057 | MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO | | |
2058 | MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO); | |
2059 | MLX5_SET(tirc, tirc, lro_max_ip_payload_size, | |
2060 | (priv->params.lro_wqe_sz - | |
2061 | ROUGH_MAX_L2_L3_HDR_SZ) >> 8); | |
2062 | MLX5_SET(tirc, tirc, lro_timeout_period_usecs, priv->params.lro_timeout); | |
2063 | } | |
2064 | ||
2065 | void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_priv *priv, void *tirc, | |
2066 | enum mlx5e_traffic_types tt) | |
2067 | { | |
2068 | void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); | |
2069 | ||
2070 | #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\ | |
2071 | MLX5_HASH_FIELD_SEL_DST_IP) | |
2072 | ||
2073 | #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\ | |
2074 | MLX5_HASH_FIELD_SEL_DST_IP |\ | |
2075 | MLX5_HASH_FIELD_SEL_L4_SPORT |\ | |
2076 | MLX5_HASH_FIELD_SEL_L4_DPORT) | |
2077 | ||
2078 | #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\ | |
2079 | MLX5_HASH_FIELD_SEL_DST_IP |\ | |
2080 | MLX5_HASH_FIELD_SEL_IPSEC_SPI) | |
2081 | ||
2082 | MLX5_SET(tirc, tirc, rx_hash_fn, | |
2083 | mlx5e_rx_hash_fn(priv->params.rss_hfunc)); | |
2084 | if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) { | |
2085 | void *rss_key = MLX5_ADDR_OF(tirc, tirc, | |
2086 | rx_hash_toeplitz_key); | |
2087 | size_t len = MLX5_FLD_SZ_BYTES(tirc, | |
2088 | rx_hash_toeplitz_key); | |
2089 | ||
2090 | MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); | |
2091 | memcpy(rss_key, priv->params.toeplitz_hash_key, len); | |
2092 | } | |
2093 | ||
2094 | switch (tt) { | |
2095 | case MLX5E_TT_IPV4_TCP: | |
2096 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2097 | MLX5_L3_PROT_TYPE_IPV4); | |
2098 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
2099 | MLX5_L4_PROT_TYPE_TCP); | |
2100 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2101 | MLX5_HASH_IP_L4PORTS); | |
2102 | break; | |
2103 | ||
2104 | case MLX5E_TT_IPV6_TCP: | |
2105 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2106 | MLX5_L3_PROT_TYPE_IPV6); | |
2107 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
2108 | MLX5_L4_PROT_TYPE_TCP); | |
2109 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2110 | MLX5_HASH_IP_L4PORTS); | |
2111 | break; | |
2112 | ||
2113 | case MLX5E_TT_IPV4_UDP: | |
2114 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2115 | MLX5_L3_PROT_TYPE_IPV4); | |
2116 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
2117 | MLX5_L4_PROT_TYPE_UDP); | |
2118 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2119 | MLX5_HASH_IP_L4PORTS); | |
2120 | break; | |
2121 | ||
2122 | case MLX5E_TT_IPV6_UDP: | |
2123 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2124 | MLX5_L3_PROT_TYPE_IPV6); | |
2125 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
2126 | MLX5_L4_PROT_TYPE_UDP); | |
2127 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2128 | MLX5_HASH_IP_L4PORTS); | |
2129 | break; | |
2130 | ||
2131 | case MLX5E_TT_IPV4_IPSEC_AH: | |
2132 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2133 | MLX5_L3_PROT_TYPE_IPV4); | |
2134 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2135 | MLX5_HASH_IP_IPSEC_SPI); | |
2136 | break; | |
2137 | ||
2138 | case MLX5E_TT_IPV6_IPSEC_AH: | |
2139 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2140 | MLX5_L3_PROT_TYPE_IPV6); | |
2141 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2142 | MLX5_HASH_IP_IPSEC_SPI); | |
2143 | break; | |
2144 | ||
2145 | case MLX5E_TT_IPV4_IPSEC_ESP: | |
2146 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2147 | MLX5_L3_PROT_TYPE_IPV4); | |
2148 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2149 | MLX5_HASH_IP_IPSEC_SPI); | |
2150 | break; | |
2151 | ||
2152 | case MLX5E_TT_IPV6_IPSEC_ESP: | |
2153 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2154 | MLX5_L3_PROT_TYPE_IPV6); | |
2155 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2156 | MLX5_HASH_IP_IPSEC_SPI); | |
2157 | break; | |
2158 | ||
2159 | case MLX5E_TT_IPV4: | |
2160 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2161 | MLX5_L3_PROT_TYPE_IPV4); | |
2162 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2163 | MLX5_HASH_IP); | |
2164 | break; | |
2165 | ||
2166 | case MLX5E_TT_IPV6: | |
2167 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2168 | MLX5_L3_PROT_TYPE_IPV6); | |
2169 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2170 | MLX5_HASH_IP); | |
2171 | break; | |
2172 | default: | |
2173 | WARN_ONCE(true, "%s: bad traffic type!\n", __func__); | |
2174 | } | |
2175 | } | |
2176 | ||
2177 | static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv) | |
2178 | { | |
2179 | struct mlx5_core_dev *mdev = priv->mdev; | |
2180 | ||
2181 | void *in; | |
2182 | void *tirc; | |
2183 | int inlen; | |
2184 | int err; | |
2185 | int tt; | |
2186 | int ix; | |
2187 | ||
2188 | inlen = MLX5_ST_SZ_BYTES(modify_tir_in); | |
2189 | in = mlx5_vzalloc(inlen); | |
2190 | if (!in) | |
2191 | return -ENOMEM; | |
2192 | ||
2193 | MLX5_SET(modify_tir_in, in, bitmask.lro, 1); | |
2194 | tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx); | |
2195 | ||
2196 | mlx5e_build_tir_ctx_lro(tirc, priv); | |
2197 | ||
2198 | for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { | |
2199 | err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, | |
2200 | inlen); | |
2201 | if (err) | |
2202 | goto free_in; | |
2203 | } | |
2204 | ||
2205 | for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) { | |
2206 | err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn, | |
2207 | in, inlen); | |
2208 | if (err) | |
2209 | goto free_in; | |
2210 | } | |
2211 | ||
2212 | free_in: | |
2213 | kvfree(in); | |
2214 | ||
2215 | return err; | |
2216 | } | |
2217 | ||
2218 | static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu) | |
2219 | { | |
2220 | struct mlx5_core_dev *mdev = priv->mdev; | |
2221 | u16 hw_mtu = MLX5E_SW2HW_MTU(mtu); | |
2222 | int err; | |
2223 | ||
2224 | err = mlx5_set_port_mtu(mdev, hw_mtu, 1); | |
2225 | if (err) | |
2226 | return err; | |
2227 | ||
2228 | /* Update vport context MTU */ | |
2229 | mlx5_modify_nic_vport_mtu(mdev, hw_mtu); | |
2230 | return 0; | |
2231 | } | |
2232 | ||
2233 | static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu) | |
2234 | { | |
2235 | struct mlx5_core_dev *mdev = priv->mdev; | |
2236 | u16 hw_mtu = 0; | |
2237 | int err; | |
2238 | ||
2239 | err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu); | |
2240 | if (err || !hw_mtu) /* fallback to port oper mtu */ | |
2241 | mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1); | |
2242 | ||
2243 | *mtu = MLX5E_HW2SW_MTU(hw_mtu); | |
2244 | } | |
2245 | ||
2246 | static int mlx5e_set_dev_port_mtu(struct net_device *netdev) | |
2247 | { | |
2248 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2249 | u16 mtu; | |
2250 | int err; | |
2251 | ||
2252 | err = mlx5e_set_mtu(priv, netdev->mtu); | |
2253 | if (err) | |
2254 | return err; | |
2255 | ||
2256 | mlx5e_query_mtu(priv, &mtu); | |
2257 | if (mtu != netdev->mtu) | |
2258 | netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n", | |
2259 | __func__, mtu, netdev->mtu); | |
2260 | ||
2261 | netdev->mtu = mtu; | |
2262 | return 0; | |
2263 | } | |
2264 | ||
2265 | static void mlx5e_netdev_set_tcs(struct net_device *netdev) | |
2266 | { | |
2267 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2268 | int nch = priv->params.num_channels; | |
2269 | int ntc = priv->params.num_tc; | |
2270 | int tc; | |
2271 | ||
2272 | netdev_reset_tc(netdev); | |
2273 | ||
2274 | if (ntc == 1) | |
2275 | return; | |
2276 | ||
2277 | netdev_set_num_tc(netdev, ntc); | |
2278 | ||
2279 | /* Map netdev TCs to offset 0 | |
2280 | * We have our own UP to TXQ mapping for QoS | |
2281 | */ | |
2282 | for (tc = 0; tc < ntc; tc++) | |
2283 | netdev_set_tc_queue(netdev, tc, nch, 0); | |
2284 | } | |
2285 | ||
2286 | int mlx5e_open_locked(struct net_device *netdev) | |
2287 | { | |
2288 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2289 | struct mlx5_core_dev *mdev = priv->mdev; | |
2290 | int num_txqs; | |
2291 | int err; | |
2292 | ||
2293 | set_bit(MLX5E_STATE_OPENED, &priv->state); | |
2294 | ||
2295 | mlx5e_netdev_set_tcs(netdev); | |
2296 | ||
2297 | num_txqs = priv->params.num_channels * priv->params.num_tc; | |
2298 | netif_set_real_num_tx_queues(netdev, num_txqs); | |
2299 | netif_set_real_num_rx_queues(netdev, priv->params.num_channels); | |
2300 | ||
2301 | err = mlx5e_open_channels(priv); | |
2302 | if (err) { | |
2303 | netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n", | |
2304 | __func__, err); | |
2305 | goto err_clear_state_opened_flag; | |
2306 | } | |
2307 | ||
2308 | err = mlx5e_refresh_tirs_self_loopback(priv->mdev, false); | |
2309 | if (err) { | |
2310 | netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n", | |
2311 | __func__, err); | |
2312 | goto err_close_channels; | |
2313 | } | |
2314 | ||
2315 | mlx5e_redirect_rqts(priv); | |
2316 | mlx5e_update_carrier(priv); | |
2317 | mlx5e_timestamp_init(priv); | |
2318 | #ifdef CONFIG_RFS_ACCEL | |
2319 | priv->netdev->rx_cpu_rmap = priv->mdev->rmap; | |
2320 | #endif | |
2321 | if (priv->profile->update_stats) | |
2322 | queue_delayed_work(priv->wq, &priv->update_stats_work, 0); | |
2323 | ||
2324 | if (MLX5_CAP_GEN(mdev, vport_group_manager)) { | |
2325 | err = mlx5e_add_sqs_fwd_rules(priv); | |
2326 | if (err) | |
2327 | goto err_close_channels; | |
2328 | } | |
2329 | return 0; | |
2330 | ||
2331 | err_close_channels: | |
2332 | mlx5e_close_channels(priv); | |
2333 | err_clear_state_opened_flag: | |
2334 | clear_bit(MLX5E_STATE_OPENED, &priv->state); | |
2335 | return err; | |
2336 | } | |
2337 | ||
2338 | int mlx5e_open(struct net_device *netdev) | |
2339 | { | |
2340 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2341 | int err; | |
2342 | ||
2343 | mutex_lock(&priv->state_lock); | |
2344 | err = mlx5e_open_locked(netdev); | |
2345 | mutex_unlock(&priv->state_lock); | |
2346 | ||
2347 | return err; | |
2348 | } | |
2349 | ||
2350 | int mlx5e_close_locked(struct net_device *netdev) | |
2351 | { | |
2352 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2353 | struct mlx5_core_dev *mdev = priv->mdev; | |
2354 | ||
2355 | /* May already be CLOSED in case a previous configuration operation | |
2356 | * (e.g RX/TX queue size change) that involves close&open failed. | |
2357 | */ | |
2358 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
2359 | return 0; | |
2360 | ||
2361 | clear_bit(MLX5E_STATE_OPENED, &priv->state); | |
2362 | ||
2363 | if (MLX5_CAP_GEN(mdev, vport_group_manager)) | |
2364 | mlx5e_remove_sqs_fwd_rules(priv); | |
2365 | ||
2366 | mlx5e_timestamp_cleanup(priv); | |
2367 | netif_carrier_off(priv->netdev); | |
2368 | mlx5e_redirect_rqts(priv); | |
2369 | mlx5e_close_channels(priv); | |
2370 | ||
2371 | return 0; | |
2372 | } | |
2373 | ||
2374 | int mlx5e_close(struct net_device *netdev) | |
2375 | { | |
2376 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2377 | int err; | |
2378 | ||
2379 | if (!netif_device_present(netdev)) | |
2380 | return -ENODEV; | |
2381 | ||
2382 | mutex_lock(&priv->state_lock); | |
2383 | err = mlx5e_close_locked(netdev); | |
2384 | mutex_unlock(&priv->state_lock); | |
2385 | ||
2386 | return err; | |
2387 | } | |
2388 | ||
2389 | static int mlx5e_create_drop_rq(struct mlx5e_priv *priv, | |
2390 | struct mlx5e_rq *rq, | |
2391 | struct mlx5e_rq_param *param) | |
2392 | { | |
2393 | struct mlx5_core_dev *mdev = priv->mdev; | |
2394 | void *rqc = param->rqc; | |
2395 | void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
2396 | int err; | |
2397 | ||
2398 | param->wq.db_numa_node = param->wq.buf_numa_node; | |
2399 | ||
2400 | err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq, | |
2401 | &rq->wq_ctrl); | |
2402 | if (err) | |
2403 | return err; | |
2404 | ||
2405 | rq->priv = priv; | |
2406 | ||
2407 | return 0; | |
2408 | } | |
2409 | ||
2410 | static int mlx5e_create_drop_cq(struct mlx5e_priv *priv, | |
2411 | struct mlx5e_cq *cq, | |
2412 | struct mlx5e_cq_param *param) | |
2413 | { | |
2414 | struct mlx5_core_dev *mdev = priv->mdev; | |
2415 | struct mlx5_core_cq *mcq = &cq->mcq; | |
2416 | int eqn_not_used; | |
2417 | unsigned int irqn; | |
2418 | int err; | |
2419 | ||
2420 | err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, | |
2421 | &cq->wq_ctrl); | |
2422 | if (err) | |
2423 | return err; | |
2424 | ||
2425 | mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn); | |
2426 | ||
2427 | mcq->cqe_sz = 64; | |
2428 | mcq->set_ci_db = cq->wq_ctrl.db.db; | |
2429 | mcq->arm_db = cq->wq_ctrl.db.db + 1; | |
2430 | *mcq->set_ci_db = 0; | |
2431 | *mcq->arm_db = 0; | |
2432 | mcq->vector = param->eq_ix; | |
2433 | mcq->comp = mlx5e_completion_event; | |
2434 | mcq->event = mlx5e_cq_error_event; | |
2435 | mcq->irqn = irqn; | |
2436 | ||
2437 | cq->priv = priv; | |
2438 | ||
2439 | return 0; | |
2440 | } | |
2441 | ||
2442 | static int mlx5e_open_drop_rq(struct mlx5e_priv *priv) | |
2443 | { | |
2444 | struct mlx5e_cq_param cq_param; | |
2445 | struct mlx5e_rq_param rq_param; | |
2446 | struct mlx5e_rq *rq = &priv->drop_rq; | |
2447 | struct mlx5e_cq *cq = &priv->drop_rq.cq; | |
2448 | int err; | |
2449 | ||
2450 | memset(&cq_param, 0, sizeof(cq_param)); | |
2451 | memset(&rq_param, 0, sizeof(rq_param)); | |
2452 | mlx5e_build_drop_rq_param(&rq_param); | |
2453 | ||
2454 | err = mlx5e_create_drop_cq(priv, cq, &cq_param); | |
2455 | if (err) | |
2456 | return err; | |
2457 | ||
2458 | err = mlx5e_enable_cq(cq, &cq_param); | |
2459 | if (err) | |
2460 | goto err_destroy_cq; | |
2461 | ||
2462 | err = mlx5e_create_drop_rq(priv, rq, &rq_param); | |
2463 | if (err) | |
2464 | goto err_disable_cq; | |
2465 | ||
2466 | err = mlx5e_enable_rq(rq, &rq_param); | |
2467 | if (err) | |
2468 | goto err_destroy_rq; | |
2469 | ||
2470 | return 0; | |
2471 | ||
2472 | err_destroy_rq: | |
2473 | mlx5e_destroy_rq(&priv->drop_rq); | |
2474 | ||
2475 | err_disable_cq: | |
2476 | mlx5e_disable_cq(&priv->drop_rq.cq); | |
2477 | ||
2478 | err_destroy_cq: | |
2479 | mlx5e_destroy_cq(&priv->drop_rq.cq); | |
2480 | ||
2481 | return err; | |
2482 | } | |
2483 | ||
2484 | static void mlx5e_close_drop_rq(struct mlx5e_priv *priv) | |
2485 | { | |
2486 | mlx5e_disable_rq(&priv->drop_rq); | |
2487 | mlx5e_destroy_rq(&priv->drop_rq); | |
2488 | mlx5e_disable_cq(&priv->drop_rq.cq); | |
2489 | mlx5e_destroy_cq(&priv->drop_rq.cq); | |
2490 | } | |
2491 | ||
2492 | static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc) | |
2493 | { | |
2494 | struct mlx5_core_dev *mdev = priv->mdev; | |
2495 | u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; | |
2496 | void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); | |
2497 | ||
2498 | MLX5_SET(tisc, tisc, prio, tc << 1); | |
2499 | MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn); | |
2500 | ||
2501 | if (mlx5_lag_is_lacp_owner(mdev)) | |
2502 | MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1); | |
2503 | ||
2504 | return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]); | |
2505 | } | |
2506 | ||
2507 | static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc) | |
2508 | { | |
2509 | mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]); | |
2510 | } | |
2511 | ||
2512 | int mlx5e_create_tises(struct mlx5e_priv *priv) | |
2513 | { | |
2514 | int err; | |
2515 | int tc; | |
2516 | ||
2517 | for (tc = 0; tc < priv->profile->max_tc; tc++) { | |
2518 | err = mlx5e_create_tis(priv, tc); | |
2519 | if (err) | |
2520 | goto err_close_tises; | |
2521 | } | |
2522 | ||
2523 | return 0; | |
2524 | ||
2525 | err_close_tises: | |
2526 | for (tc--; tc >= 0; tc--) | |
2527 | mlx5e_destroy_tis(priv, tc); | |
2528 | ||
2529 | return err; | |
2530 | } | |
2531 | ||
2532 | void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv) | |
2533 | { | |
2534 | int tc; | |
2535 | ||
2536 | for (tc = 0; tc < priv->profile->max_tc; tc++) | |
2537 | mlx5e_destroy_tis(priv, tc); | |
2538 | } | |
2539 | ||
2540 | static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, | |
2541 | enum mlx5e_traffic_types tt) | |
2542 | { | |
2543 | MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn); | |
2544 | ||
2545 | mlx5e_build_tir_ctx_lro(tirc, priv); | |
2546 | ||
2547 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); | |
2548 | MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn); | |
2549 | mlx5e_build_indir_tir_ctx_hash(priv, tirc, tt); | |
2550 | } | |
2551 | ||
2552 | static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, | |
2553 | u32 rqtn) | |
2554 | { | |
2555 | MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn); | |
2556 | ||
2557 | mlx5e_build_tir_ctx_lro(tirc, priv); | |
2558 | ||
2559 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); | |
2560 | MLX5_SET(tirc, tirc, indirect_table, rqtn); | |
2561 | MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8); | |
2562 | } | |
2563 | ||
2564 | static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv) | |
2565 | { | |
2566 | struct mlx5e_tir *tir; | |
2567 | void *tirc; | |
2568 | int inlen; | |
2569 | int err; | |
2570 | u32 *in; | |
2571 | int tt; | |
2572 | ||
2573 | inlen = MLX5_ST_SZ_BYTES(create_tir_in); | |
2574 | in = mlx5_vzalloc(inlen); | |
2575 | if (!in) | |
2576 | return -ENOMEM; | |
2577 | ||
2578 | for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { | |
2579 | memset(in, 0, inlen); | |
2580 | tir = &priv->indir_tir[tt]; | |
2581 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); | |
2582 | mlx5e_build_indir_tir_ctx(priv, tirc, tt); | |
2583 | err = mlx5e_create_tir(priv->mdev, tir, in, inlen); | |
2584 | if (err) | |
2585 | goto err_destroy_tirs; | |
2586 | } | |
2587 | ||
2588 | kvfree(in); | |
2589 | ||
2590 | return 0; | |
2591 | ||
2592 | err_destroy_tirs: | |
2593 | for (tt--; tt >= 0; tt--) | |
2594 | mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]); | |
2595 | ||
2596 | kvfree(in); | |
2597 | ||
2598 | return err; | |
2599 | } | |
2600 | ||
2601 | int mlx5e_create_direct_tirs(struct mlx5e_priv *priv) | |
2602 | { | |
2603 | int nch = priv->profile->max_nch(priv->mdev); | |
2604 | struct mlx5e_tir *tir; | |
2605 | void *tirc; | |
2606 | int inlen; | |
2607 | int err; | |
2608 | u32 *in; | |
2609 | int ix; | |
2610 | ||
2611 | inlen = MLX5_ST_SZ_BYTES(create_tir_in); | |
2612 | in = mlx5_vzalloc(inlen); | |
2613 | if (!in) | |
2614 | return -ENOMEM; | |
2615 | ||
2616 | for (ix = 0; ix < nch; ix++) { | |
2617 | memset(in, 0, inlen); | |
2618 | tir = &priv->direct_tir[ix]; | |
2619 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); | |
2620 | mlx5e_build_direct_tir_ctx(priv, tirc, | |
2621 | priv->direct_tir[ix].rqt.rqtn); | |
2622 | err = mlx5e_create_tir(priv->mdev, tir, in, inlen); | |
2623 | if (err) | |
2624 | goto err_destroy_ch_tirs; | |
2625 | } | |
2626 | ||
2627 | kvfree(in); | |
2628 | ||
2629 | return 0; | |
2630 | ||
2631 | err_destroy_ch_tirs: | |
2632 | for (ix--; ix >= 0; ix--) | |
2633 | mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]); | |
2634 | ||
2635 | kvfree(in); | |
2636 | ||
2637 | return err; | |
2638 | } | |
2639 | ||
2640 | static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv) | |
2641 | { | |
2642 | int i; | |
2643 | ||
2644 | for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) | |
2645 | mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]); | |
2646 | } | |
2647 | ||
2648 | void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv) | |
2649 | { | |
2650 | int nch = priv->profile->max_nch(priv->mdev); | |
2651 | int i; | |
2652 | ||
2653 | for (i = 0; i < nch; i++) | |
2654 | mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]); | |
2655 | } | |
2656 | ||
2657 | int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd) | |
2658 | { | |
2659 | int err = 0; | |
2660 | int i; | |
2661 | ||
2662 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
2663 | return 0; | |
2664 | ||
2665 | for (i = 0; i < priv->params.num_channels; i++) { | |
2666 | err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd); | |
2667 | if (err) | |
2668 | return err; | |
2669 | } | |
2670 | ||
2671 | return 0; | |
2672 | } | |
2673 | ||
2674 | static int mlx5e_setup_tc(struct net_device *netdev, u8 tc) | |
2675 | { | |
2676 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2677 | bool was_opened; | |
2678 | int err = 0; | |
2679 | ||
2680 | if (tc && tc != MLX5E_MAX_NUM_TC) | |
2681 | return -EINVAL; | |
2682 | ||
2683 | mutex_lock(&priv->state_lock); | |
2684 | ||
2685 | was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); | |
2686 | if (was_opened) | |
2687 | mlx5e_close_locked(priv->netdev); | |
2688 | ||
2689 | priv->params.num_tc = tc ? tc : 1; | |
2690 | ||
2691 | if (was_opened) | |
2692 | err = mlx5e_open_locked(priv->netdev); | |
2693 | ||
2694 | mutex_unlock(&priv->state_lock); | |
2695 | ||
2696 | return err; | |
2697 | } | |
2698 | ||
2699 | static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle, | |
2700 | __be16 proto, struct tc_to_netdev *tc) | |
2701 | { | |
2702 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2703 | ||
2704 | if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS)) | |
2705 | goto mqprio; | |
2706 | ||
2707 | switch (tc->type) { | |
2708 | case TC_SETUP_CLSFLOWER: | |
2709 | switch (tc->cls_flower->command) { | |
2710 | case TC_CLSFLOWER_REPLACE: | |
2711 | return mlx5e_configure_flower(priv, proto, tc->cls_flower); | |
2712 | case TC_CLSFLOWER_DESTROY: | |
2713 | return mlx5e_delete_flower(priv, tc->cls_flower); | |
2714 | case TC_CLSFLOWER_STATS: | |
2715 | return mlx5e_stats_flower(priv, tc->cls_flower); | |
2716 | } | |
2717 | default: | |
2718 | return -EOPNOTSUPP; | |
2719 | } | |
2720 | ||
2721 | mqprio: | |
2722 | if (tc->type != TC_SETUP_MQPRIO) | |
2723 | return -EINVAL; | |
2724 | ||
2725 | tc->mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; | |
2726 | ||
2727 | return mlx5e_setup_tc(dev, tc->mqprio->num_tc); | |
2728 | } | |
2729 | ||
2730 | static void | |
2731 | mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats) | |
2732 | { | |
2733 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2734 | struct mlx5e_sw_stats *sstats = &priv->stats.sw; | |
2735 | struct mlx5e_vport_stats *vstats = &priv->stats.vport; | |
2736 | struct mlx5e_pport_stats *pstats = &priv->stats.pport; | |
2737 | ||
2738 | if (mlx5e_is_uplink_rep(priv)) { | |
2739 | stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok); | |
2740 | stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok); | |
2741 | stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok); | |
2742 | stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok); | |
2743 | } else { | |
2744 | stats->rx_packets = sstats->rx_packets; | |
2745 | stats->rx_bytes = sstats->rx_bytes; | |
2746 | stats->tx_packets = sstats->tx_packets; | |
2747 | stats->tx_bytes = sstats->tx_bytes; | |
2748 | stats->tx_dropped = sstats->tx_queue_dropped; | |
2749 | } | |
2750 | ||
2751 | stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer; | |
2752 | ||
2753 | stats->rx_length_errors = | |
2754 | PPORT_802_3_GET(pstats, a_in_range_length_errors) + | |
2755 | PPORT_802_3_GET(pstats, a_out_of_range_length_field) + | |
2756 | PPORT_802_3_GET(pstats, a_frame_too_long_errors); | |
2757 | stats->rx_crc_errors = | |
2758 | PPORT_802_3_GET(pstats, a_frame_check_sequence_errors); | |
2759 | stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors); | |
2760 | stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards); | |
2761 | stats->tx_carrier_errors = | |
2762 | PPORT_802_3_GET(pstats, a_symbol_error_during_carrier); | |
2763 | stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + | |
2764 | stats->rx_frame_errors; | |
2765 | stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors; | |
2766 | ||
2767 | /* vport multicast also counts packets that are dropped due to steering | |
2768 | * or rx out of buffer | |
2769 | */ | |
2770 | stats->multicast = | |
2771 | VPORT_COUNTER_GET(vstats, received_eth_multicast.packets); | |
2772 | ||
2773 | } | |
2774 | ||
2775 | static void mlx5e_set_rx_mode(struct net_device *dev) | |
2776 | { | |
2777 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2778 | ||
2779 | queue_work(priv->wq, &priv->set_rx_mode_work); | |
2780 | } | |
2781 | ||
2782 | static int mlx5e_set_mac(struct net_device *netdev, void *addr) | |
2783 | { | |
2784 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2785 | struct sockaddr *saddr = addr; | |
2786 | ||
2787 | if (!is_valid_ether_addr(saddr->sa_data)) | |
2788 | return -EADDRNOTAVAIL; | |
2789 | ||
2790 | netif_addr_lock_bh(netdev); | |
2791 | ether_addr_copy(netdev->dev_addr, saddr->sa_data); | |
2792 | netif_addr_unlock_bh(netdev); | |
2793 | ||
2794 | queue_work(priv->wq, &priv->set_rx_mode_work); | |
2795 | ||
2796 | return 0; | |
2797 | } | |
2798 | ||
2799 | #define MLX5E_SET_FEATURE(netdev, feature, enable) \ | |
2800 | do { \ | |
2801 | if (enable) \ | |
2802 | netdev->features |= feature; \ | |
2803 | else \ | |
2804 | netdev->features &= ~feature; \ | |
2805 | } while (0) | |
2806 | ||
2807 | typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable); | |
2808 | ||
2809 | static int set_feature_lro(struct net_device *netdev, bool enable) | |
2810 | { | |
2811 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2812 | bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); | |
2813 | int err; | |
2814 | ||
2815 | mutex_lock(&priv->state_lock); | |
2816 | ||
2817 | if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST)) | |
2818 | mlx5e_close_locked(priv->netdev); | |
2819 | ||
2820 | priv->params.lro_en = enable; | |
2821 | err = mlx5e_modify_tirs_lro(priv); | |
2822 | if (err) { | |
2823 | netdev_err(netdev, "lro modify failed, %d\n", err); | |
2824 | priv->params.lro_en = !enable; | |
2825 | } | |
2826 | ||
2827 | if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST)) | |
2828 | mlx5e_open_locked(priv->netdev); | |
2829 | ||
2830 | mutex_unlock(&priv->state_lock); | |
2831 | ||
2832 | return err; | |
2833 | } | |
2834 | ||
2835 | static int set_feature_vlan_filter(struct net_device *netdev, bool enable) | |
2836 | { | |
2837 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2838 | ||
2839 | if (enable) | |
2840 | mlx5e_enable_vlan_filter(priv); | |
2841 | else | |
2842 | mlx5e_disable_vlan_filter(priv); | |
2843 | ||
2844 | return 0; | |
2845 | } | |
2846 | ||
2847 | static int set_feature_tc_num_filters(struct net_device *netdev, bool enable) | |
2848 | { | |
2849 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2850 | ||
2851 | if (!enable && mlx5e_tc_num_filters(priv)) { | |
2852 | netdev_err(netdev, | |
2853 | "Active offloaded tc filters, can't turn hw_tc_offload off\n"); | |
2854 | return -EINVAL; | |
2855 | } | |
2856 | ||
2857 | return 0; | |
2858 | } | |
2859 | ||
2860 | static int set_feature_rx_all(struct net_device *netdev, bool enable) | |
2861 | { | |
2862 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2863 | struct mlx5_core_dev *mdev = priv->mdev; | |
2864 | ||
2865 | return mlx5_set_port_fcs(mdev, !enable); | |
2866 | } | |
2867 | ||
2868 | static int set_feature_rx_vlan(struct net_device *netdev, bool enable) | |
2869 | { | |
2870 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2871 | int err; | |
2872 | ||
2873 | mutex_lock(&priv->state_lock); | |
2874 | ||
2875 | priv->params.vlan_strip_disable = !enable; | |
2876 | err = mlx5e_modify_rqs_vsd(priv, !enable); | |
2877 | if (err) | |
2878 | priv->params.vlan_strip_disable = enable; | |
2879 | ||
2880 | mutex_unlock(&priv->state_lock); | |
2881 | ||
2882 | return err; | |
2883 | } | |
2884 | ||
2885 | #ifdef CONFIG_RFS_ACCEL | |
2886 | static int set_feature_arfs(struct net_device *netdev, bool enable) | |
2887 | { | |
2888 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2889 | int err; | |
2890 | ||
2891 | if (enable) | |
2892 | err = mlx5e_arfs_enable(priv); | |
2893 | else | |
2894 | err = mlx5e_arfs_disable(priv); | |
2895 | ||
2896 | return err; | |
2897 | } | |
2898 | #endif | |
2899 | ||
2900 | static int mlx5e_handle_feature(struct net_device *netdev, | |
2901 | netdev_features_t wanted_features, | |
2902 | netdev_features_t feature, | |
2903 | mlx5e_feature_handler feature_handler) | |
2904 | { | |
2905 | netdev_features_t changes = wanted_features ^ netdev->features; | |
2906 | bool enable = !!(wanted_features & feature); | |
2907 | int err; | |
2908 | ||
2909 | if (!(changes & feature)) | |
2910 | return 0; | |
2911 | ||
2912 | err = feature_handler(netdev, enable); | |
2913 | if (err) { | |
2914 | netdev_err(netdev, "%s feature 0x%llx failed err %d\n", | |
2915 | enable ? "Enable" : "Disable", feature, err); | |
2916 | return err; | |
2917 | } | |
2918 | ||
2919 | MLX5E_SET_FEATURE(netdev, feature, enable); | |
2920 | return 0; | |
2921 | } | |
2922 | ||
2923 | static int mlx5e_set_features(struct net_device *netdev, | |
2924 | netdev_features_t features) | |
2925 | { | |
2926 | int err; | |
2927 | ||
2928 | err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO, | |
2929 | set_feature_lro); | |
2930 | err |= mlx5e_handle_feature(netdev, features, | |
2931 | NETIF_F_HW_VLAN_CTAG_FILTER, | |
2932 | set_feature_vlan_filter); | |
2933 | err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC, | |
2934 | set_feature_tc_num_filters); | |
2935 | err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL, | |
2936 | set_feature_rx_all); | |
2937 | err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX, | |
2938 | set_feature_rx_vlan); | |
2939 | #ifdef CONFIG_RFS_ACCEL | |
2940 | err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE, | |
2941 | set_feature_arfs); | |
2942 | #endif | |
2943 | ||
2944 | return err ? -EINVAL : 0; | |
2945 | } | |
2946 | ||
2947 | static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu) | |
2948 | { | |
2949 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2950 | bool was_opened; | |
2951 | int err = 0; | |
2952 | bool reset; | |
2953 | ||
2954 | mutex_lock(&priv->state_lock); | |
2955 | ||
2956 | reset = !priv->params.lro_en && | |
2957 | (priv->params.rq_wq_type != | |
2958 | MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ); | |
2959 | ||
2960 | was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); | |
2961 | if (was_opened && reset) | |
2962 | mlx5e_close_locked(netdev); | |
2963 | ||
2964 | netdev->mtu = new_mtu; | |
2965 | mlx5e_set_dev_port_mtu(netdev); | |
2966 | ||
2967 | if (was_opened && reset) | |
2968 | err = mlx5e_open_locked(netdev); | |
2969 | ||
2970 | mutex_unlock(&priv->state_lock); | |
2971 | ||
2972 | return err; | |
2973 | } | |
2974 | ||
2975 | static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
2976 | { | |
2977 | switch (cmd) { | |
2978 | case SIOCSHWTSTAMP: | |
2979 | return mlx5e_hwstamp_set(dev, ifr); | |
2980 | case SIOCGHWTSTAMP: | |
2981 | return mlx5e_hwstamp_get(dev, ifr); | |
2982 | default: | |
2983 | return -EOPNOTSUPP; | |
2984 | } | |
2985 | } | |
2986 | ||
2987 | static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac) | |
2988 | { | |
2989 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2990 | struct mlx5_core_dev *mdev = priv->mdev; | |
2991 | ||
2992 | return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac); | |
2993 | } | |
2994 | ||
2995 | static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos, | |
2996 | __be16 vlan_proto) | |
2997 | { | |
2998 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2999 | struct mlx5_core_dev *mdev = priv->mdev; | |
3000 | ||
3001 | if (vlan_proto != htons(ETH_P_8021Q)) | |
3002 | return -EPROTONOSUPPORT; | |
3003 | ||
3004 | return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1, | |
3005 | vlan, qos); | |
3006 | } | |
3007 | ||
3008 | static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting) | |
3009 | { | |
3010 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3011 | struct mlx5_core_dev *mdev = priv->mdev; | |
3012 | ||
3013 | return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting); | |
3014 | } | |
3015 | ||
3016 | static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting) | |
3017 | { | |
3018 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3019 | struct mlx5_core_dev *mdev = priv->mdev; | |
3020 | ||
3021 | return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting); | |
3022 | } | |
3023 | ||
3024 | static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, | |
3025 | int max_tx_rate) | |
3026 | { | |
3027 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3028 | struct mlx5_core_dev *mdev = priv->mdev; | |
3029 | ||
3030 | return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1, | |
3031 | max_tx_rate, min_tx_rate); | |
3032 | } | |
3033 | ||
3034 | static int mlx5_vport_link2ifla(u8 esw_link) | |
3035 | { | |
3036 | switch (esw_link) { | |
3037 | case MLX5_ESW_VPORT_ADMIN_STATE_DOWN: | |
3038 | return IFLA_VF_LINK_STATE_DISABLE; | |
3039 | case MLX5_ESW_VPORT_ADMIN_STATE_UP: | |
3040 | return IFLA_VF_LINK_STATE_ENABLE; | |
3041 | } | |
3042 | return IFLA_VF_LINK_STATE_AUTO; | |
3043 | } | |
3044 | ||
3045 | static int mlx5_ifla_link2vport(u8 ifla_link) | |
3046 | { | |
3047 | switch (ifla_link) { | |
3048 | case IFLA_VF_LINK_STATE_DISABLE: | |
3049 | return MLX5_ESW_VPORT_ADMIN_STATE_DOWN; | |
3050 | case IFLA_VF_LINK_STATE_ENABLE: | |
3051 | return MLX5_ESW_VPORT_ADMIN_STATE_UP; | |
3052 | } | |
3053 | return MLX5_ESW_VPORT_ADMIN_STATE_AUTO; | |
3054 | } | |
3055 | ||
3056 | static int mlx5e_set_vf_link_state(struct net_device *dev, int vf, | |
3057 | int link_state) | |
3058 | { | |
3059 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3060 | struct mlx5_core_dev *mdev = priv->mdev; | |
3061 | ||
3062 | return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1, | |
3063 | mlx5_ifla_link2vport(link_state)); | |
3064 | } | |
3065 | ||
3066 | static int mlx5e_get_vf_config(struct net_device *dev, | |
3067 | int vf, struct ifla_vf_info *ivi) | |
3068 | { | |
3069 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3070 | struct mlx5_core_dev *mdev = priv->mdev; | |
3071 | int err; | |
3072 | ||
3073 | err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi); | |
3074 | if (err) | |
3075 | return err; | |
3076 | ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate); | |
3077 | return 0; | |
3078 | } | |
3079 | ||
3080 | static int mlx5e_get_vf_stats(struct net_device *dev, | |
3081 | int vf, struct ifla_vf_stats *vf_stats) | |
3082 | { | |
3083 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3084 | struct mlx5_core_dev *mdev = priv->mdev; | |
3085 | ||
3086 | return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1, | |
3087 | vf_stats); | |
3088 | } | |
3089 | ||
3090 | static void mlx5e_add_vxlan_port(struct net_device *netdev, | |
3091 | struct udp_tunnel_info *ti) | |
3092 | { | |
3093 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3094 | ||
3095 | if (ti->type != UDP_TUNNEL_TYPE_VXLAN) | |
3096 | return; | |
3097 | ||
3098 | if (!mlx5e_vxlan_allowed(priv->mdev)) | |
3099 | return; | |
3100 | ||
3101 | mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1); | |
3102 | } | |
3103 | ||
3104 | static void mlx5e_del_vxlan_port(struct net_device *netdev, | |
3105 | struct udp_tunnel_info *ti) | |
3106 | { | |
3107 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3108 | ||
3109 | if (ti->type != UDP_TUNNEL_TYPE_VXLAN) | |
3110 | return; | |
3111 | ||
3112 | if (!mlx5e_vxlan_allowed(priv->mdev)) | |
3113 | return; | |
3114 | ||
3115 | mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0); | |
3116 | } | |
3117 | ||
3118 | static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv, | |
3119 | struct sk_buff *skb, | |
3120 | netdev_features_t features) | |
3121 | { | |
3122 | struct udphdr *udph; | |
3123 | u16 proto; | |
3124 | u16 port = 0; | |
3125 | ||
3126 | switch (vlan_get_protocol(skb)) { | |
3127 | case htons(ETH_P_IP): | |
3128 | proto = ip_hdr(skb)->protocol; | |
3129 | break; | |
3130 | case htons(ETH_P_IPV6): | |
3131 | proto = ipv6_hdr(skb)->nexthdr; | |
3132 | break; | |
3133 | default: | |
3134 | goto out; | |
3135 | } | |
3136 | ||
3137 | if (proto == IPPROTO_UDP) { | |
3138 | udph = udp_hdr(skb); | |
3139 | port = be16_to_cpu(udph->dest); | |
3140 | } | |
3141 | ||
3142 | /* Verify if UDP port is being offloaded by HW */ | |
3143 | if (port && mlx5e_vxlan_lookup_port(priv, port)) | |
3144 | return features; | |
3145 | ||
3146 | out: | |
3147 | /* Disable CSUM and GSO if the udp dport is not offloaded by HW */ | |
3148 | return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); | |
3149 | } | |
3150 | ||
3151 | static netdev_features_t mlx5e_features_check(struct sk_buff *skb, | |
3152 | struct net_device *netdev, | |
3153 | netdev_features_t features) | |
3154 | { | |
3155 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3156 | ||
3157 | features = vlan_features_check(skb, features); | |
3158 | features = vxlan_features_check(skb, features); | |
3159 | ||
3160 | /* Validate if the tunneled packet is being offloaded by HW */ | |
3161 | if (skb->encapsulation && | |
3162 | (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK)) | |
3163 | return mlx5e_vxlan_features_check(priv, skb, features); | |
3164 | ||
3165 | return features; | |
3166 | } | |
3167 | ||
3168 | static void mlx5e_tx_timeout(struct net_device *dev) | |
3169 | { | |
3170 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3171 | bool sched_work = false; | |
3172 | int i; | |
3173 | ||
3174 | netdev_err(dev, "TX timeout detected\n"); | |
3175 | ||
3176 | for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) { | |
3177 | struct mlx5e_sq *sq = priv->txq_to_sq_map[i]; | |
3178 | ||
3179 | if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i))) | |
3180 | continue; | |
3181 | sched_work = true; | |
3182 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); | |
3183 | netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n", | |
3184 | i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc); | |
3185 | } | |
3186 | ||
3187 | if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
3188 | schedule_work(&priv->tx_timeout_work); | |
3189 | } | |
3190 | ||
3191 | static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog) | |
3192 | { | |
3193 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3194 | struct bpf_prog *old_prog; | |
3195 | int err = 0; | |
3196 | bool reset, was_opened; | |
3197 | int i; | |
3198 | ||
3199 | mutex_lock(&priv->state_lock); | |
3200 | ||
3201 | if ((netdev->features & NETIF_F_LRO) && prog) { | |
3202 | netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n"); | |
3203 | err = -EINVAL; | |
3204 | goto unlock; | |
3205 | } | |
3206 | ||
3207 | was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); | |
3208 | /* no need for full reset when exchanging programs */ | |
3209 | reset = (!priv->xdp_prog || !prog); | |
3210 | ||
3211 | if (was_opened && reset) | |
3212 | mlx5e_close_locked(netdev); | |
3213 | if (was_opened && !reset) { | |
3214 | /* num_channels is invariant here, so we can take the | |
3215 | * batched reference right upfront. | |
3216 | */ | |
3217 | prog = bpf_prog_add(prog, priv->params.num_channels); | |
3218 | if (IS_ERR(prog)) { | |
3219 | err = PTR_ERR(prog); | |
3220 | goto unlock; | |
3221 | } | |
3222 | } | |
3223 | ||
3224 | /* exchange programs, extra prog reference we got from caller | |
3225 | * as long as we don't fail from this point onwards. | |
3226 | */ | |
3227 | old_prog = xchg(&priv->xdp_prog, prog); | |
3228 | if (old_prog) | |
3229 | bpf_prog_put(old_prog); | |
3230 | ||
3231 | if (reset) /* change RQ type according to priv->xdp_prog */ | |
3232 | mlx5e_set_rq_priv_params(priv); | |
3233 | ||
3234 | if (was_opened && reset) | |
3235 | mlx5e_open_locked(netdev); | |
3236 | ||
3237 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset) | |
3238 | goto unlock; | |
3239 | ||
3240 | /* exchanging programs w/o reset, we update ref counts on behalf | |
3241 | * of the channels RQs here. | |
3242 | */ | |
3243 | for (i = 0; i < priv->params.num_channels; i++) { | |
3244 | struct mlx5e_channel *c = priv->channel[i]; | |
3245 | ||
3246 | clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state); | |
3247 | napi_synchronize(&c->napi); | |
3248 | /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */ | |
3249 | ||
3250 | old_prog = xchg(&c->rq.xdp_prog, prog); | |
3251 | ||
3252 | set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state); | |
3253 | /* napi_schedule in case we have missed anything */ | |
3254 | set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags); | |
3255 | napi_schedule(&c->napi); | |
3256 | ||
3257 | if (old_prog) | |
3258 | bpf_prog_put(old_prog); | |
3259 | } | |
3260 | ||
3261 | unlock: | |
3262 | mutex_unlock(&priv->state_lock); | |
3263 | return err; | |
3264 | } | |
3265 | ||
3266 | static bool mlx5e_xdp_attached(struct net_device *dev) | |
3267 | { | |
3268 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3269 | ||
3270 | return !!priv->xdp_prog; | |
3271 | } | |
3272 | ||
3273 | static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp) | |
3274 | { | |
3275 | switch (xdp->command) { | |
3276 | case XDP_SETUP_PROG: | |
3277 | return mlx5e_xdp_set(dev, xdp->prog); | |
3278 | case XDP_QUERY_PROG: | |
3279 | xdp->prog_attached = mlx5e_xdp_attached(dev); | |
3280 | return 0; | |
3281 | default: | |
3282 | return -EINVAL; | |
3283 | } | |
3284 | } | |
3285 | ||
3286 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
3287 | /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without | |
3288 | * reenabling interrupts. | |
3289 | */ | |
3290 | static void mlx5e_netpoll(struct net_device *dev) | |
3291 | { | |
3292 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3293 | int i; | |
3294 | ||
3295 | for (i = 0; i < priv->params.num_channels; i++) | |
3296 | napi_schedule(&priv->channel[i]->napi); | |
3297 | } | |
3298 | #endif | |
3299 | ||
3300 | static const struct net_device_ops mlx5e_netdev_ops_basic = { | |
3301 | .ndo_open = mlx5e_open, | |
3302 | .ndo_stop = mlx5e_close, | |
3303 | .ndo_start_xmit = mlx5e_xmit, | |
3304 | .ndo_setup_tc = mlx5e_ndo_setup_tc, | |
3305 | .ndo_select_queue = mlx5e_select_queue, | |
3306 | .ndo_get_stats64 = mlx5e_get_stats, | |
3307 | .ndo_set_rx_mode = mlx5e_set_rx_mode, | |
3308 | .ndo_set_mac_address = mlx5e_set_mac, | |
3309 | .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid, | |
3310 | .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid, | |
3311 | .ndo_set_features = mlx5e_set_features, | |
3312 | .ndo_change_mtu = mlx5e_change_mtu, | |
3313 | .ndo_do_ioctl = mlx5e_ioctl, | |
3314 | .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate, | |
3315 | #ifdef CONFIG_RFS_ACCEL | |
3316 | .ndo_rx_flow_steer = mlx5e_rx_flow_steer, | |
3317 | #endif | |
3318 | .ndo_tx_timeout = mlx5e_tx_timeout, | |
3319 | .ndo_xdp = mlx5e_xdp, | |
3320 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
3321 | .ndo_poll_controller = mlx5e_netpoll, | |
3322 | #endif | |
3323 | }; | |
3324 | ||
3325 | static const struct net_device_ops mlx5e_netdev_ops_sriov = { | |
3326 | .ndo_open = mlx5e_open, | |
3327 | .ndo_stop = mlx5e_close, | |
3328 | .ndo_start_xmit = mlx5e_xmit, | |
3329 | .ndo_setup_tc = mlx5e_ndo_setup_tc, | |
3330 | .ndo_select_queue = mlx5e_select_queue, | |
3331 | .ndo_get_stats64 = mlx5e_get_stats, | |
3332 | .ndo_set_rx_mode = mlx5e_set_rx_mode, | |
3333 | .ndo_set_mac_address = mlx5e_set_mac, | |
3334 | .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid, | |
3335 | .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid, | |
3336 | .ndo_set_features = mlx5e_set_features, | |
3337 | .ndo_change_mtu = mlx5e_change_mtu, | |
3338 | .ndo_do_ioctl = mlx5e_ioctl, | |
3339 | .ndo_udp_tunnel_add = mlx5e_add_vxlan_port, | |
3340 | .ndo_udp_tunnel_del = mlx5e_del_vxlan_port, | |
3341 | .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate, | |
3342 | .ndo_features_check = mlx5e_features_check, | |
3343 | #ifdef CONFIG_RFS_ACCEL | |
3344 | .ndo_rx_flow_steer = mlx5e_rx_flow_steer, | |
3345 | #endif | |
3346 | .ndo_set_vf_mac = mlx5e_set_vf_mac, | |
3347 | .ndo_set_vf_vlan = mlx5e_set_vf_vlan, | |
3348 | .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk, | |
3349 | .ndo_set_vf_trust = mlx5e_set_vf_trust, | |
3350 | .ndo_set_vf_rate = mlx5e_set_vf_rate, | |
3351 | .ndo_get_vf_config = mlx5e_get_vf_config, | |
3352 | .ndo_set_vf_link_state = mlx5e_set_vf_link_state, | |
3353 | .ndo_get_vf_stats = mlx5e_get_vf_stats, | |
3354 | .ndo_tx_timeout = mlx5e_tx_timeout, | |
3355 | .ndo_xdp = mlx5e_xdp, | |
3356 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
3357 | .ndo_poll_controller = mlx5e_netpoll, | |
3358 | #endif | |
3359 | .ndo_has_offload_stats = mlx5e_has_offload_stats, | |
3360 | .ndo_get_offload_stats = mlx5e_get_offload_stats, | |
3361 | }; | |
3362 | ||
3363 | static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev) | |
3364 | { | |
3365 | if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) | |
3366 | return -EOPNOTSUPP; | |
3367 | if (!MLX5_CAP_GEN(mdev, eth_net_offloads) || | |
3368 | !MLX5_CAP_GEN(mdev, nic_flow_table) || | |
3369 | !MLX5_CAP_ETH(mdev, csum_cap) || | |
3370 | !MLX5_CAP_ETH(mdev, max_lso_cap) || | |
3371 | !MLX5_CAP_ETH(mdev, vlan_cap) || | |
3372 | !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) || | |
3373 | MLX5_CAP_FLOWTABLE(mdev, | |
3374 | flow_table_properties_nic_receive.max_ft_level) | |
3375 | < 3) { | |
3376 | mlx5_core_warn(mdev, | |
3377 | "Not creating net device, some required device capabilities are missing\n"); | |
3378 | return -EOPNOTSUPP; | |
3379 | } | |
3380 | if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable)) | |
3381 | mlx5_core_warn(mdev, "Self loop back prevention is not supported\n"); | |
3382 | if (!MLX5_CAP_GEN(mdev, cq_moderation)) | |
3383 | mlx5_core_warn(mdev, "CQ modiration is not supported\n"); | |
3384 | ||
3385 | return 0; | |
3386 | } | |
3387 | ||
3388 | u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev) | |
3389 | { | |
3390 | int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2; | |
3391 | ||
3392 | return bf_buf_size - | |
3393 | sizeof(struct mlx5e_tx_wqe) + | |
3394 | 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/; | |
3395 | } | |
3396 | ||
3397 | void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev, | |
3398 | u32 *indirection_rqt, int len, | |
3399 | int num_channels) | |
3400 | { | |
3401 | int node = mdev->priv.numa_node; | |
3402 | int node_num_of_cores; | |
3403 | int i; | |
3404 | ||
3405 | if (node == -1) | |
3406 | node = first_online_node; | |
3407 | ||
3408 | node_num_of_cores = cpumask_weight(cpumask_of_node(node)); | |
3409 | ||
3410 | if (node_num_of_cores) | |
3411 | num_channels = min_t(int, num_channels, node_num_of_cores); | |
3412 | ||
3413 | for (i = 0; i < len; i++) | |
3414 | indirection_rqt[i] = i % num_channels; | |
3415 | } | |
3416 | ||
3417 | static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw) | |
3418 | { | |
3419 | enum pcie_link_width width; | |
3420 | enum pci_bus_speed speed; | |
3421 | int err = 0; | |
3422 | ||
3423 | err = pcie_get_minimum_link(mdev->pdev, &speed, &width); | |
3424 | if (err) | |
3425 | return err; | |
3426 | ||
3427 | if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) | |
3428 | return -EINVAL; | |
3429 | ||
3430 | switch (speed) { | |
3431 | case PCIE_SPEED_2_5GT: | |
3432 | *pci_bw = 2500 * width; | |
3433 | break; | |
3434 | case PCIE_SPEED_5_0GT: | |
3435 | *pci_bw = 5000 * width; | |
3436 | break; | |
3437 | case PCIE_SPEED_8_0GT: | |
3438 | *pci_bw = 8000 * width; | |
3439 | break; | |
3440 | default: | |
3441 | return -EINVAL; | |
3442 | } | |
3443 | ||
3444 | return 0; | |
3445 | } | |
3446 | ||
3447 | static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw) | |
3448 | { | |
3449 | return (link_speed && pci_bw && | |
3450 | (pci_bw < 40000) && (pci_bw < link_speed)); | |
3451 | } | |
3452 | ||
3453 | void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode) | |
3454 | { | |
3455 | params->rx_cq_period_mode = cq_period_mode; | |
3456 | ||
3457 | params->rx_cq_moderation.pkts = | |
3458 | MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS; | |
3459 | params->rx_cq_moderation.usec = | |
3460 | MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC; | |
3461 | ||
3462 | if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE) | |
3463 | params->rx_cq_moderation.usec = | |
3464 | MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE; | |
3465 | } | |
3466 | ||
3467 | u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout) | |
3468 | { | |
3469 | int i; | |
3470 | ||
3471 | /* The supported periods are organized in ascending order */ | |
3472 | for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++) | |
3473 | if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout) | |
3474 | break; | |
3475 | ||
3476 | return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]); | |
3477 | } | |
3478 | ||
3479 | static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev, | |
3480 | struct net_device *netdev, | |
3481 | const struct mlx5e_profile *profile, | |
3482 | void *ppriv) | |
3483 | { | |
3484 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3485 | u32 link_speed = 0; | |
3486 | u32 pci_bw = 0; | |
3487 | u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? | |
3488 | MLX5_CQ_PERIOD_MODE_START_FROM_CQE : | |
3489 | MLX5_CQ_PERIOD_MODE_START_FROM_EQE; | |
3490 | ||
3491 | priv->mdev = mdev; | |
3492 | priv->netdev = netdev; | |
3493 | priv->params.num_channels = profile->max_nch(mdev); | |
3494 | priv->profile = profile; | |
3495 | priv->ppriv = ppriv; | |
3496 | ||
3497 | priv->params.lro_timeout = | |
3498 | mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT); | |
3499 | ||
3500 | priv->params.log_sq_size = is_kdump_kernel() ? | |
3501 | MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE : | |
3502 | MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; | |
3503 | ||
3504 | /* set CQE compression */ | |
3505 | priv->params.rx_cqe_compress_def = false; | |
3506 | if (MLX5_CAP_GEN(mdev, cqe_compression) && | |
3507 | MLX5_CAP_GEN(mdev, vport_group_manager)) { | |
3508 | mlx5e_get_max_linkspeed(mdev, &link_speed); | |
3509 | mlx5e_get_pci_bw(mdev, &pci_bw); | |
3510 | mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n", | |
3511 | link_speed, pci_bw); | |
3512 | priv->params.rx_cqe_compress_def = | |
3513 | cqe_compress_heuristic(link_speed, pci_bw); | |
3514 | } | |
3515 | ||
3516 | MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS, | |
3517 | priv->params.rx_cqe_compress_def); | |
3518 | ||
3519 | mlx5e_set_rq_priv_params(priv); | |
3520 | if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) | |
3521 | priv->params.lro_en = true; | |
3522 | ||
3523 | priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation); | |
3524 | mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode); | |
3525 | ||
3526 | priv->params.tx_cq_moderation.usec = | |
3527 | MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC; | |
3528 | priv->params.tx_cq_moderation.pkts = | |
3529 | MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS; | |
3530 | priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev); | |
3531 | mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode); | |
3532 | if (priv->params.tx_min_inline_mode == MLX5_INLINE_MODE_NONE && | |
3533 | !MLX5_CAP_ETH(mdev, wqe_vlan_insert)) | |
3534 | priv->params.tx_min_inline_mode = MLX5_INLINE_MODE_L2; | |
3535 | ||
3536 | priv->params.num_tc = 1; | |
3537 | priv->params.rss_hfunc = ETH_RSS_HASH_XOR; | |
3538 | ||
3539 | netdev_rss_key_fill(priv->params.toeplitz_hash_key, | |
3540 | sizeof(priv->params.toeplitz_hash_key)); | |
3541 | ||
3542 | mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt, | |
3543 | MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev)); | |
3544 | ||
3545 | /* Initialize pflags */ | |
3546 | MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER, | |
3547 | priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE); | |
3548 | ||
3549 | mutex_init(&priv->state_lock); | |
3550 | ||
3551 | INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work); | |
3552 | INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work); | |
3553 | INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work); | |
3554 | INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work); | |
3555 | } | |
3556 | ||
3557 | static void mlx5e_set_netdev_dev_addr(struct net_device *netdev) | |
3558 | { | |
3559 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3560 | ||
3561 | mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr); | |
3562 | if (is_zero_ether_addr(netdev->dev_addr) && | |
3563 | !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) { | |
3564 | eth_hw_addr_random(netdev); | |
3565 | mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr); | |
3566 | } | |
3567 | } | |
3568 | ||
3569 | static const struct switchdev_ops mlx5e_switchdev_ops = { | |
3570 | .switchdev_port_attr_get = mlx5e_attr_get, | |
3571 | }; | |
3572 | ||
3573 | static void mlx5e_build_nic_netdev(struct net_device *netdev) | |
3574 | { | |
3575 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3576 | struct mlx5_core_dev *mdev = priv->mdev; | |
3577 | bool fcs_supported; | |
3578 | bool fcs_enabled; | |
3579 | ||
3580 | SET_NETDEV_DEV(netdev, &mdev->pdev->dev); | |
3581 | ||
3582 | if (MLX5_CAP_GEN(mdev, vport_group_manager)) { | |
3583 | netdev->netdev_ops = &mlx5e_netdev_ops_sriov; | |
3584 | #ifdef CONFIG_MLX5_CORE_EN_DCB | |
3585 | if (MLX5_CAP_GEN(mdev, qos)) | |
3586 | netdev->dcbnl_ops = &mlx5e_dcbnl_ops; | |
3587 | #endif | |
3588 | } else { | |
3589 | netdev->netdev_ops = &mlx5e_netdev_ops_basic; | |
3590 | } | |
3591 | ||
3592 | netdev->watchdog_timeo = 15 * HZ; | |
3593 | ||
3594 | netdev->ethtool_ops = &mlx5e_ethtool_ops; | |
3595 | ||
3596 | netdev->vlan_features |= NETIF_F_SG; | |
3597 | netdev->vlan_features |= NETIF_F_IP_CSUM; | |
3598 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; | |
3599 | netdev->vlan_features |= NETIF_F_GRO; | |
3600 | netdev->vlan_features |= NETIF_F_TSO; | |
3601 | netdev->vlan_features |= NETIF_F_TSO6; | |
3602 | netdev->vlan_features |= NETIF_F_RXCSUM; | |
3603 | netdev->vlan_features |= NETIF_F_RXHASH; | |
3604 | ||
3605 | if (!!MLX5_CAP_ETH(mdev, lro_cap)) | |
3606 | netdev->vlan_features |= NETIF_F_LRO; | |
3607 | ||
3608 | netdev->hw_features = netdev->vlan_features; | |
3609 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; | |
3610 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; | |
3611 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; | |
3612 | ||
3613 | if (mlx5e_vxlan_allowed(mdev)) { | |
3614 | netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL | | |
3615 | NETIF_F_GSO_UDP_TUNNEL_CSUM | | |
3616 | NETIF_F_GSO_PARTIAL; | |
3617 | netdev->hw_enc_features |= NETIF_F_IP_CSUM; | |
3618 | netdev->hw_enc_features |= NETIF_F_IPV6_CSUM; | |
3619 | netdev->hw_enc_features |= NETIF_F_TSO; | |
3620 | netdev->hw_enc_features |= NETIF_F_TSO6; | |
3621 | netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL; | |
3622 | netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM | | |
3623 | NETIF_F_GSO_PARTIAL; | |
3624 | netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM; | |
3625 | } | |
3626 | ||
3627 | mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled); | |
3628 | ||
3629 | if (fcs_supported) | |
3630 | netdev->hw_features |= NETIF_F_RXALL; | |
3631 | ||
3632 | netdev->features = netdev->hw_features; | |
3633 | if (!priv->params.lro_en) | |
3634 | netdev->features &= ~NETIF_F_LRO; | |
3635 | ||
3636 | if (fcs_enabled) | |
3637 | netdev->features &= ~NETIF_F_RXALL; | |
3638 | ||
3639 | #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f) | |
3640 | if (FT_CAP(flow_modify_en) && | |
3641 | FT_CAP(modify_root) && | |
3642 | FT_CAP(identified_miss_table_mode) && | |
3643 | FT_CAP(flow_table_modify)) { | |
3644 | netdev->hw_features |= NETIF_F_HW_TC; | |
3645 | #ifdef CONFIG_RFS_ACCEL | |
3646 | netdev->hw_features |= NETIF_F_NTUPLE; | |
3647 | #endif | |
3648 | } | |
3649 | ||
3650 | netdev->features |= NETIF_F_HIGHDMA; | |
3651 | ||
3652 | netdev->priv_flags |= IFF_UNICAST_FLT; | |
3653 | ||
3654 | mlx5e_set_netdev_dev_addr(netdev); | |
3655 | ||
3656 | #ifdef CONFIG_NET_SWITCHDEV | |
3657 | if (MLX5_CAP_GEN(mdev, vport_group_manager)) | |
3658 | netdev->switchdev_ops = &mlx5e_switchdev_ops; | |
3659 | #endif | |
3660 | } | |
3661 | ||
3662 | static void mlx5e_create_q_counter(struct mlx5e_priv *priv) | |
3663 | { | |
3664 | struct mlx5_core_dev *mdev = priv->mdev; | |
3665 | int err; | |
3666 | ||
3667 | err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter); | |
3668 | if (err) { | |
3669 | mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err); | |
3670 | priv->q_counter = 0; | |
3671 | } | |
3672 | } | |
3673 | ||
3674 | static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv) | |
3675 | { | |
3676 | if (!priv->q_counter) | |
3677 | return; | |
3678 | ||
3679 | mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter); | |
3680 | } | |
3681 | ||
3682 | static void mlx5e_nic_init(struct mlx5_core_dev *mdev, | |
3683 | struct net_device *netdev, | |
3684 | const struct mlx5e_profile *profile, | |
3685 | void *ppriv) | |
3686 | { | |
3687 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3688 | ||
3689 | mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv); | |
3690 | mlx5e_build_nic_netdev(netdev); | |
3691 | mlx5e_vxlan_init(priv); | |
3692 | } | |
3693 | ||
3694 | static void mlx5e_nic_cleanup(struct mlx5e_priv *priv) | |
3695 | { | |
3696 | mlx5e_vxlan_cleanup(priv); | |
3697 | ||
3698 | if (priv->xdp_prog) | |
3699 | bpf_prog_put(priv->xdp_prog); | |
3700 | } | |
3701 | ||
3702 | static int mlx5e_init_nic_rx(struct mlx5e_priv *priv) | |
3703 | { | |
3704 | struct mlx5_core_dev *mdev = priv->mdev; | |
3705 | int err; | |
3706 | int i; | |
3707 | ||
3708 | err = mlx5e_create_indirect_rqts(priv); | |
3709 | if (err) { | |
3710 | mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err); | |
3711 | return err; | |
3712 | } | |
3713 | ||
3714 | err = mlx5e_create_direct_rqts(priv); | |
3715 | if (err) { | |
3716 | mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err); | |
3717 | goto err_destroy_indirect_rqts; | |
3718 | } | |
3719 | ||
3720 | err = mlx5e_create_indirect_tirs(priv); | |
3721 | if (err) { | |
3722 | mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err); | |
3723 | goto err_destroy_direct_rqts; | |
3724 | } | |
3725 | ||
3726 | err = mlx5e_create_direct_tirs(priv); | |
3727 | if (err) { | |
3728 | mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err); | |
3729 | goto err_destroy_indirect_tirs; | |
3730 | } | |
3731 | ||
3732 | err = mlx5e_create_flow_steering(priv); | |
3733 | if (err) { | |
3734 | mlx5_core_warn(mdev, "create flow steering failed, %d\n", err); | |
3735 | goto err_destroy_direct_tirs; | |
3736 | } | |
3737 | ||
3738 | err = mlx5e_tc_init(priv); | |
3739 | if (err) | |
3740 | goto err_destroy_flow_steering; | |
3741 | ||
3742 | return 0; | |
3743 | ||
3744 | err_destroy_flow_steering: | |
3745 | mlx5e_destroy_flow_steering(priv); | |
3746 | err_destroy_direct_tirs: | |
3747 | mlx5e_destroy_direct_tirs(priv); | |
3748 | err_destroy_indirect_tirs: | |
3749 | mlx5e_destroy_indirect_tirs(priv); | |
3750 | err_destroy_direct_rqts: | |
3751 | for (i = 0; i < priv->profile->max_nch(mdev); i++) | |
3752 | mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt); | |
3753 | err_destroy_indirect_rqts: | |
3754 | mlx5e_destroy_rqt(priv, &priv->indir_rqt); | |
3755 | return err; | |
3756 | } | |
3757 | ||
3758 | static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv) | |
3759 | { | |
3760 | int i; | |
3761 | ||
3762 | mlx5e_tc_cleanup(priv); | |
3763 | mlx5e_destroy_flow_steering(priv); | |
3764 | mlx5e_destroy_direct_tirs(priv); | |
3765 | mlx5e_destroy_indirect_tirs(priv); | |
3766 | for (i = 0; i < priv->profile->max_nch(priv->mdev); i++) | |
3767 | mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt); | |
3768 | mlx5e_destroy_rqt(priv, &priv->indir_rqt); | |
3769 | } | |
3770 | ||
3771 | static int mlx5e_init_nic_tx(struct mlx5e_priv *priv) | |
3772 | { | |
3773 | int err; | |
3774 | ||
3775 | err = mlx5e_create_tises(priv); | |
3776 | if (err) { | |
3777 | mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err); | |
3778 | return err; | |
3779 | } | |
3780 | ||
3781 | #ifdef CONFIG_MLX5_CORE_EN_DCB | |
3782 | mlx5e_dcbnl_initialize(priv); | |
3783 | #endif | |
3784 | return 0; | |
3785 | } | |
3786 | ||
3787 | static void mlx5e_nic_enable(struct mlx5e_priv *priv) | |
3788 | { | |
3789 | struct net_device *netdev = priv->netdev; | |
3790 | struct mlx5_core_dev *mdev = priv->mdev; | |
3791 | struct mlx5_eswitch *esw = mdev->priv.eswitch; | |
3792 | struct mlx5_eswitch_rep rep; | |
3793 | ||
3794 | mlx5_lag_add(mdev, netdev); | |
3795 | ||
3796 | mlx5e_enable_async_events(priv); | |
3797 | ||
3798 | if (MLX5_CAP_GEN(mdev, vport_group_manager)) { | |
3799 | mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id); | |
3800 | rep.load = mlx5e_nic_rep_load; | |
3801 | rep.unload = mlx5e_nic_rep_unload; | |
3802 | rep.vport = FDB_UPLINK_VPORT; | |
3803 | rep.netdev = netdev; | |
3804 | mlx5_eswitch_register_vport_rep(esw, 0, &rep); | |
3805 | } | |
3806 | ||
3807 | if (netdev->reg_state != NETREG_REGISTERED) | |
3808 | return; | |
3809 | ||
3810 | /* Device already registered: sync netdev system state */ | |
3811 | if (mlx5e_vxlan_allowed(mdev)) { | |
3812 | rtnl_lock(); | |
3813 | udp_tunnel_get_rx_info(netdev); | |
3814 | rtnl_unlock(); | |
3815 | } | |
3816 | ||
3817 | queue_work(priv->wq, &priv->set_rx_mode_work); | |
3818 | } | |
3819 | ||
3820 | static void mlx5e_nic_disable(struct mlx5e_priv *priv) | |
3821 | { | |
3822 | struct mlx5_core_dev *mdev = priv->mdev; | |
3823 | struct mlx5_eswitch *esw = mdev->priv.eswitch; | |
3824 | ||
3825 | queue_work(priv->wq, &priv->set_rx_mode_work); | |
3826 | if (MLX5_CAP_GEN(mdev, vport_group_manager)) | |
3827 | mlx5_eswitch_unregister_vport_rep(esw, 0); | |
3828 | mlx5e_disable_async_events(priv); | |
3829 | mlx5_lag_remove(mdev); | |
3830 | } | |
3831 | ||
3832 | static const struct mlx5e_profile mlx5e_nic_profile = { | |
3833 | .init = mlx5e_nic_init, | |
3834 | .cleanup = mlx5e_nic_cleanup, | |
3835 | .init_rx = mlx5e_init_nic_rx, | |
3836 | .cleanup_rx = mlx5e_cleanup_nic_rx, | |
3837 | .init_tx = mlx5e_init_nic_tx, | |
3838 | .cleanup_tx = mlx5e_cleanup_nic_tx, | |
3839 | .enable = mlx5e_nic_enable, | |
3840 | .disable = mlx5e_nic_disable, | |
3841 | .update_stats = mlx5e_update_stats, | |
3842 | .max_nch = mlx5e_get_max_num_channels, | |
3843 | .max_tc = MLX5E_MAX_NUM_TC, | |
3844 | }; | |
3845 | ||
3846 | struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev, | |
3847 | const struct mlx5e_profile *profile, | |
3848 | void *ppriv) | |
3849 | { | |
3850 | int nch = profile->max_nch(mdev); | |
3851 | struct net_device *netdev; | |
3852 | struct mlx5e_priv *priv; | |
3853 | ||
3854 | netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), | |
3855 | nch * profile->max_tc, | |
3856 | nch); | |
3857 | if (!netdev) { | |
3858 | mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n"); | |
3859 | return NULL; | |
3860 | } | |
3861 | ||
3862 | profile->init(mdev, netdev, profile, ppriv); | |
3863 | ||
3864 | netif_carrier_off(netdev); | |
3865 | ||
3866 | priv = netdev_priv(netdev); | |
3867 | ||
3868 | priv->wq = create_singlethread_workqueue("mlx5e"); | |
3869 | if (!priv->wq) | |
3870 | goto err_cleanup_nic; | |
3871 | ||
3872 | return netdev; | |
3873 | ||
3874 | err_cleanup_nic: | |
3875 | profile->cleanup(priv); | |
3876 | free_netdev(netdev); | |
3877 | ||
3878 | return NULL; | |
3879 | } | |
3880 | ||
3881 | int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev) | |
3882 | { | |
3883 | const struct mlx5e_profile *profile; | |
3884 | struct mlx5e_priv *priv; | |
3885 | u16 max_mtu; | |
3886 | int err; | |
3887 | ||
3888 | priv = netdev_priv(netdev); | |
3889 | profile = priv->profile; | |
3890 | clear_bit(MLX5E_STATE_DESTROYING, &priv->state); | |
3891 | ||
3892 | err = profile->init_tx(priv); | |
3893 | if (err) | |
3894 | goto out; | |
3895 | ||
3896 | err = mlx5e_open_drop_rq(priv); | |
3897 | if (err) { | |
3898 | mlx5_core_err(mdev, "open drop rq failed, %d\n", err); | |
3899 | goto err_cleanup_tx; | |
3900 | } | |
3901 | ||
3902 | err = profile->init_rx(priv); | |
3903 | if (err) | |
3904 | goto err_close_drop_rq; | |
3905 | ||
3906 | mlx5e_create_q_counter(priv); | |
3907 | ||
3908 | mlx5e_init_l2_addr(priv); | |
3909 | ||
3910 | /* MTU range: 68 - hw-specific max */ | |
3911 | netdev->min_mtu = ETH_MIN_MTU; | |
3912 | mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1); | |
3913 | netdev->max_mtu = MLX5E_HW2SW_MTU(max_mtu); | |
3914 | ||
3915 | mlx5e_set_dev_port_mtu(netdev); | |
3916 | ||
3917 | if (profile->enable) | |
3918 | profile->enable(priv); | |
3919 | ||
3920 | rtnl_lock(); | |
3921 | if (netif_running(netdev)) | |
3922 | mlx5e_open(netdev); | |
3923 | netif_device_attach(netdev); | |
3924 | rtnl_unlock(); | |
3925 | ||
3926 | return 0; | |
3927 | ||
3928 | err_close_drop_rq: | |
3929 | mlx5e_close_drop_rq(priv); | |
3930 | ||
3931 | err_cleanup_tx: | |
3932 | profile->cleanup_tx(priv); | |
3933 | ||
3934 | out: | |
3935 | return err; | |
3936 | } | |
3937 | ||
3938 | static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev) | |
3939 | { | |
3940 | struct mlx5_eswitch *esw = mdev->priv.eswitch; | |
3941 | int total_vfs = MLX5_TOTAL_VPORTS(mdev); | |
3942 | int vport; | |
3943 | u8 mac[ETH_ALEN]; | |
3944 | ||
3945 | if (!MLX5_CAP_GEN(mdev, vport_group_manager)) | |
3946 | return; | |
3947 | ||
3948 | mlx5_query_nic_vport_mac_address(mdev, 0, mac); | |
3949 | ||
3950 | for (vport = 1; vport < total_vfs; vport++) { | |
3951 | struct mlx5_eswitch_rep rep; | |
3952 | ||
3953 | rep.load = mlx5e_vport_rep_load; | |
3954 | rep.unload = mlx5e_vport_rep_unload; | |
3955 | rep.vport = vport; | |
3956 | ether_addr_copy(rep.hw_id, mac); | |
3957 | mlx5_eswitch_register_vport_rep(esw, vport, &rep); | |
3958 | } | |
3959 | } | |
3960 | ||
3961 | static void mlx5e_unregister_vport_rep(struct mlx5_core_dev *mdev) | |
3962 | { | |
3963 | struct mlx5_eswitch *esw = mdev->priv.eswitch; | |
3964 | int total_vfs = MLX5_TOTAL_VPORTS(mdev); | |
3965 | int vport; | |
3966 | ||
3967 | if (!MLX5_CAP_GEN(mdev, vport_group_manager)) | |
3968 | return; | |
3969 | ||
3970 | for (vport = 1; vport < total_vfs; vport++) | |
3971 | mlx5_eswitch_unregister_vport_rep(esw, vport); | |
3972 | } | |
3973 | ||
3974 | void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev) | |
3975 | { | |
3976 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3977 | const struct mlx5e_profile *profile = priv->profile; | |
3978 | ||
3979 | set_bit(MLX5E_STATE_DESTROYING, &priv->state); | |
3980 | ||
3981 | rtnl_lock(); | |
3982 | if (netif_running(netdev)) | |
3983 | mlx5e_close(netdev); | |
3984 | netif_device_detach(netdev); | |
3985 | rtnl_unlock(); | |
3986 | ||
3987 | if (profile->disable) | |
3988 | profile->disable(priv); | |
3989 | flush_workqueue(priv->wq); | |
3990 | ||
3991 | mlx5e_destroy_q_counter(priv); | |
3992 | profile->cleanup_rx(priv); | |
3993 | mlx5e_close_drop_rq(priv); | |
3994 | profile->cleanup_tx(priv); | |
3995 | cancel_delayed_work_sync(&priv->update_stats_work); | |
3996 | } | |
3997 | ||
3998 | /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying | |
3999 | * hardware contexts and to connect it to the current netdev. | |
4000 | */ | |
4001 | static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv) | |
4002 | { | |
4003 | struct mlx5e_priv *priv = vpriv; | |
4004 | struct net_device *netdev = priv->netdev; | |
4005 | int err; | |
4006 | ||
4007 | if (netif_device_present(netdev)) | |
4008 | return 0; | |
4009 | ||
4010 | err = mlx5e_create_mdev_resources(mdev); | |
4011 | if (err) | |
4012 | return err; | |
4013 | ||
4014 | err = mlx5e_attach_netdev(mdev, netdev); | |
4015 | if (err) { | |
4016 | mlx5e_destroy_mdev_resources(mdev); | |
4017 | return err; | |
4018 | } | |
4019 | ||
4020 | mlx5e_register_vport_rep(mdev); | |
4021 | return 0; | |
4022 | } | |
4023 | ||
4024 | static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv) | |
4025 | { | |
4026 | struct mlx5e_priv *priv = vpriv; | |
4027 | struct net_device *netdev = priv->netdev; | |
4028 | ||
4029 | if (!netif_device_present(netdev)) | |
4030 | return; | |
4031 | ||
4032 | mlx5e_unregister_vport_rep(mdev); | |
4033 | mlx5e_detach_netdev(mdev, netdev); | |
4034 | mlx5e_destroy_mdev_resources(mdev); | |
4035 | } | |
4036 | ||
4037 | static void *mlx5e_add(struct mlx5_core_dev *mdev) | |
4038 | { | |
4039 | struct mlx5_eswitch *esw = mdev->priv.eswitch; | |
4040 | int total_vfs = MLX5_TOTAL_VPORTS(mdev); | |
4041 | void *ppriv = NULL; | |
4042 | void *priv; | |
4043 | int vport; | |
4044 | int err; | |
4045 | struct net_device *netdev; | |
4046 | ||
4047 | err = mlx5e_check_required_hca_cap(mdev); | |
4048 | if (err) | |
4049 | return NULL; | |
4050 | ||
4051 | if (MLX5_CAP_GEN(mdev, vport_group_manager)) | |
4052 | ppriv = &esw->offloads.vport_reps[0]; | |
4053 | ||
4054 | netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv); | |
4055 | if (!netdev) { | |
4056 | mlx5_core_err(mdev, "mlx5e_create_netdev failed\n"); | |
4057 | goto err_unregister_reps; | |
4058 | } | |
4059 | ||
4060 | priv = netdev_priv(netdev); | |
4061 | ||
4062 | err = mlx5e_attach(mdev, priv); | |
4063 | if (err) { | |
4064 | mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err); | |
4065 | goto err_destroy_netdev; | |
4066 | } | |
4067 | ||
4068 | err = register_netdev(netdev); | |
4069 | if (err) { | |
4070 | mlx5_core_err(mdev, "register_netdev failed, %d\n", err); | |
4071 | goto err_detach; | |
4072 | } | |
4073 | ||
4074 | return priv; | |
4075 | ||
4076 | err_detach: | |
4077 | mlx5e_detach(mdev, priv); | |
4078 | ||
4079 | err_destroy_netdev: | |
4080 | mlx5e_destroy_netdev(mdev, priv); | |
4081 | ||
4082 | err_unregister_reps: | |
4083 | for (vport = 1; vport < total_vfs; vport++) | |
4084 | mlx5_eswitch_unregister_vport_rep(esw, vport); | |
4085 | ||
4086 | return NULL; | |
4087 | } | |
4088 | ||
4089 | void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv) | |
4090 | { | |
4091 | const struct mlx5e_profile *profile = priv->profile; | |
4092 | struct net_device *netdev = priv->netdev; | |
4093 | ||
4094 | destroy_workqueue(priv->wq); | |
4095 | if (profile->cleanup) | |
4096 | profile->cleanup(priv); | |
4097 | free_netdev(netdev); | |
4098 | } | |
4099 | ||
4100 | static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv) | |
4101 | { | |
4102 | struct mlx5e_priv *priv = vpriv; | |
4103 | ||
4104 | unregister_netdev(priv->netdev); | |
4105 | mlx5e_detach(mdev, vpriv); | |
4106 | mlx5e_destroy_netdev(mdev, priv); | |
4107 | } | |
4108 | ||
4109 | static void *mlx5e_get_netdev(void *vpriv) | |
4110 | { | |
4111 | struct mlx5e_priv *priv = vpriv; | |
4112 | ||
4113 | return priv->netdev; | |
4114 | } | |
4115 | ||
4116 | static struct mlx5_interface mlx5e_interface = { | |
4117 | .add = mlx5e_add, | |
4118 | .remove = mlx5e_remove, | |
4119 | .attach = mlx5e_attach, | |
4120 | .detach = mlx5e_detach, | |
4121 | .event = mlx5e_async_event, | |
4122 | .protocol = MLX5_INTERFACE_PROTOCOL_ETH, | |
4123 | .get_dev = mlx5e_get_netdev, | |
4124 | }; | |
4125 | ||
4126 | void mlx5e_init(void) | |
4127 | { | |
4128 | mlx5e_build_ptys2ethtool_map(); | |
4129 | mlx5_register_interface(&mlx5e_interface); | |
4130 | } | |
4131 | ||
4132 | void mlx5e_cleanup(void) | |
4133 | { | |
4134 | mlx5_unregister_interface(&mlx5e_interface); | |
4135 | } |