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1 | /* | |
2 | * QEMU PC System Emulator | |
3 | * | |
4 | * Copyright (c) 2003-2004 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | #include "hw.h" | |
25 | #include "pc.h" | |
26 | #include "fdc.h" | |
27 | #include "pci.h" | |
28 | #include "block.h" | |
29 | #include "sysemu.h" | |
30 | #include "audio/audio.h" | |
31 | #include "net.h" | |
32 | #include "smbus.h" | |
33 | #include "boards.h" | |
34 | #include "console.h" | |
35 | #include "fw_cfg.h" | |
36 | #include "virtio-blk.h" | |
37 | #include "virtio-balloon.h" | |
38 | #include "virtio-console.h" | |
39 | #include "hpet_emul.h" | |
40 | ||
41 | /* output Bochs bios info messages */ | |
42 | //#define DEBUG_BIOS | |
43 | ||
44 | #define BIOS_FILENAME "bios.bin" | |
45 | #define VGABIOS_FILENAME "vgabios.bin" | |
46 | #define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin" | |
47 | ||
48 | #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024) | |
49 | ||
50 | /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */ | |
51 | #define ACPI_DATA_SIZE 0x10000 | |
52 | #define BIOS_CFG_IOPORT 0x510 | |
53 | ||
54 | #define MAX_IDE_BUS 2 | |
55 | ||
56 | static fdctrl_t *floppy_controller; | |
57 | static RTCState *rtc_state; | |
58 | static PITState *pit; | |
59 | static IOAPICState *ioapic; | |
60 | static PCIDevice *i440fx_state; | |
61 | ||
62 | static void ioport80_write(void *opaque, uint32_t addr, uint32_t data) | |
63 | { | |
64 | } | |
65 | ||
66 | /* MSDOS compatibility mode FPU exception support */ | |
67 | static qemu_irq ferr_irq; | |
68 | /* XXX: add IGNNE support */ | |
69 | void cpu_set_ferr(CPUX86State *s) | |
70 | { | |
71 | qemu_irq_raise(ferr_irq); | |
72 | } | |
73 | ||
74 | static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data) | |
75 | { | |
76 | qemu_irq_lower(ferr_irq); | |
77 | } | |
78 | ||
79 | /* TSC handling */ | |
80 | uint64_t cpu_get_tsc(CPUX86State *env) | |
81 | { | |
82 | /* Note: when using kqemu, it is more logical to return the host TSC | |
83 | because kqemu does not trap the RDTSC instruction for | |
84 | performance reasons */ | |
85 | #ifdef USE_KQEMU | |
86 | if (env->kqemu_enabled) { | |
87 | return cpu_get_real_ticks(); | |
88 | } else | |
89 | #endif | |
90 | { | |
91 | return cpu_get_ticks(); | |
92 | } | |
93 | } | |
94 | ||
95 | /* SMM support */ | |
96 | void cpu_smm_update(CPUState *env) | |
97 | { | |
98 | if (i440fx_state && env == first_cpu) | |
99 | i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1); | |
100 | } | |
101 | ||
102 | ||
103 | /* IRQ handling */ | |
104 | int cpu_get_pic_interrupt(CPUState *env) | |
105 | { | |
106 | int intno; | |
107 | ||
108 | intno = apic_get_interrupt(env); | |
109 | if (intno >= 0) { | |
110 | /* set irq request if a PIC irq is still pending */ | |
111 | /* XXX: improve that */ | |
112 | pic_update_irq(isa_pic); | |
113 | return intno; | |
114 | } | |
115 | /* read the irq from the PIC */ | |
116 | if (!apic_accept_pic_intr(env)) | |
117 | return -1; | |
118 | ||
119 | intno = pic_read_irq(isa_pic); | |
120 | return intno; | |
121 | } | |
122 | ||
123 | static void pic_irq_request(void *opaque, int irq, int level) | |
124 | { | |
125 | CPUState *env = first_cpu; | |
126 | ||
127 | if (env->apic_state) { | |
128 | while (env) { | |
129 | if (apic_accept_pic_intr(env)) | |
130 | apic_deliver_pic_intr(env, level); | |
131 | env = env->next_cpu; | |
132 | } | |
133 | } else { | |
134 | if (level) | |
135 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
136 | else | |
137 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
138 | } | |
139 | } | |
140 | ||
141 | /* PC cmos mappings */ | |
142 | ||
143 | #define REG_EQUIPMENT_BYTE 0x14 | |
144 | ||
145 | static int cmos_get_fd_drive_type(int fd0) | |
146 | { | |
147 | int val; | |
148 | ||
149 | switch (fd0) { | |
150 | case 0: | |
151 | /* 1.44 Mb 3"5 drive */ | |
152 | val = 4; | |
153 | break; | |
154 | case 1: | |
155 | /* 2.88 Mb 3"5 drive */ | |
156 | val = 5; | |
157 | break; | |
158 | case 2: | |
159 | /* 1.2 Mb 5"5 drive */ | |
160 | val = 2; | |
161 | break; | |
162 | default: | |
163 | val = 0; | |
164 | break; | |
165 | } | |
166 | return val; | |
167 | } | |
168 | ||
169 | static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd) | |
170 | { | |
171 | RTCState *s = rtc_state; | |
172 | int cylinders, heads, sectors; | |
173 | bdrv_get_geometry_hint(hd, &cylinders, &heads, §ors); | |
174 | rtc_set_memory(s, type_ofs, 47); | |
175 | rtc_set_memory(s, info_ofs, cylinders); | |
176 | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); | |
177 | rtc_set_memory(s, info_ofs + 2, heads); | |
178 | rtc_set_memory(s, info_ofs + 3, 0xff); | |
179 | rtc_set_memory(s, info_ofs + 4, 0xff); | |
180 | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); | |
181 | rtc_set_memory(s, info_ofs + 6, cylinders); | |
182 | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); | |
183 | rtc_set_memory(s, info_ofs + 8, sectors); | |
184 | } | |
185 | ||
186 | /* convert boot_device letter to something recognizable by the bios */ | |
187 | static int boot_device2nibble(char boot_device) | |
188 | { | |
189 | switch(boot_device) { | |
190 | case 'a': | |
191 | case 'b': | |
192 | return 0x01; /* floppy boot */ | |
193 | case 'c': | |
194 | return 0x02; /* hard drive boot */ | |
195 | case 'd': | |
196 | return 0x03; /* CD-ROM boot */ | |
197 | case 'n': | |
198 | return 0x04; /* Network boot */ | |
199 | } | |
200 | return 0; | |
201 | } | |
202 | ||
203 | /* copy/pasted from cmos_init, should be made a general function | |
204 | and used there as well */ | |
205 | static int pc_boot_set(void *opaque, const char *boot_device) | |
206 | { | |
207 | #define PC_MAX_BOOT_DEVICES 3 | |
208 | RTCState *s = (RTCState *)opaque; | |
209 | int nbds, bds[3] = { 0, }; | |
210 | int i; | |
211 | ||
212 | nbds = strlen(boot_device); | |
213 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
214 | term_printf("Too many boot devices for PC\n"); | |
215 | return(1); | |
216 | } | |
217 | for (i = 0; i < nbds; i++) { | |
218 | bds[i] = boot_device2nibble(boot_device[i]); | |
219 | if (bds[i] == 0) { | |
220 | term_printf("Invalid boot device for PC: '%c'\n", | |
221 | boot_device[i]); | |
222 | return(1); | |
223 | } | |
224 | } | |
225 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
226 | rtc_set_memory(s, 0x38, (bds[2] << 4)); | |
227 | return(0); | |
228 | } | |
229 | ||
230 | /* hd_table must contain 4 block drivers */ | |
231 | static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, | |
232 | const char *boot_device, BlockDriverState **hd_table) | |
233 | { | |
234 | RTCState *s = rtc_state; | |
235 | int nbds, bds[3] = { 0, }; | |
236 | int val; | |
237 | int fd0, fd1, nb; | |
238 | int i; | |
239 | ||
240 | /* various important CMOS locations needed by PC/Bochs bios */ | |
241 | ||
242 | /* memory size */ | |
243 | val = 640; /* base memory in K */ | |
244 | rtc_set_memory(s, 0x15, val); | |
245 | rtc_set_memory(s, 0x16, val >> 8); | |
246 | ||
247 | val = (ram_size / 1024) - 1024; | |
248 | if (val > 65535) | |
249 | val = 65535; | |
250 | rtc_set_memory(s, 0x17, val); | |
251 | rtc_set_memory(s, 0x18, val >> 8); | |
252 | rtc_set_memory(s, 0x30, val); | |
253 | rtc_set_memory(s, 0x31, val >> 8); | |
254 | ||
255 | if (above_4g_mem_size) { | |
256 | rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16); | |
257 | rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24); | |
258 | rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32); | |
259 | } | |
260 | ||
261 | if (ram_size > (16 * 1024 * 1024)) | |
262 | val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536); | |
263 | else | |
264 | val = 0; | |
265 | if (val > 65535) | |
266 | val = 65535; | |
267 | rtc_set_memory(s, 0x34, val); | |
268 | rtc_set_memory(s, 0x35, val >> 8); | |
269 | ||
270 | /* set the number of CPU */ | |
271 | rtc_set_memory(s, 0x5f, smp_cpus - 1); | |
272 | ||
273 | /* set boot devices, and disable floppy signature check if requested */ | |
274 | #define PC_MAX_BOOT_DEVICES 3 | |
275 | nbds = strlen(boot_device); | |
276 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
277 | fprintf(stderr, "Too many boot devices for PC\n"); | |
278 | exit(1); | |
279 | } | |
280 | for (i = 0; i < nbds; i++) { | |
281 | bds[i] = boot_device2nibble(boot_device[i]); | |
282 | if (bds[i] == 0) { | |
283 | fprintf(stderr, "Invalid boot device for PC: '%c'\n", | |
284 | boot_device[i]); | |
285 | exit(1); | |
286 | } | |
287 | } | |
288 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
289 | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); | |
290 | ||
291 | /* floppy type */ | |
292 | ||
293 | fd0 = fdctrl_get_drive_type(floppy_controller, 0); | |
294 | fd1 = fdctrl_get_drive_type(floppy_controller, 1); | |
295 | ||
296 | val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1); | |
297 | rtc_set_memory(s, 0x10, val); | |
298 | ||
299 | val = 0; | |
300 | nb = 0; | |
301 | if (fd0 < 3) | |
302 | nb++; | |
303 | if (fd1 < 3) | |
304 | nb++; | |
305 | switch (nb) { | |
306 | case 0: | |
307 | break; | |
308 | case 1: | |
309 | val |= 0x01; /* 1 drive, ready for boot */ | |
310 | break; | |
311 | case 2: | |
312 | val |= 0x41; /* 2 drives, ready for boot */ | |
313 | break; | |
314 | } | |
315 | val |= 0x02; /* FPU is there */ | |
316 | val |= 0x04; /* PS/2 mouse installed */ | |
317 | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); | |
318 | ||
319 | /* hard drives */ | |
320 | ||
321 | rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0)); | |
322 | if (hd_table[0]) | |
323 | cmos_init_hd(0x19, 0x1b, hd_table[0]); | |
324 | if (hd_table[1]) | |
325 | cmos_init_hd(0x1a, 0x24, hd_table[1]); | |
326 | ||
327 | val = 0; | |
328 | for (i = 0; i < 4; i++) { | |
329 | if (hd_table[i]) { | |
330 | int cylinders, heads, sectors, translation; | |
331 | /* NOTE: bdrv_get_geometry_hint() returns the physical | |
332 | geometry. It is always such that: 1 <= sects <= 63, 1 | |
333 | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS | |
334 | geometry can be different if a translation is done. */ | |
335 | translation = bdrv_get_translation_hint(hd_table[i]); | |
336 | if (translation == BIOS_ATA_TRANSLATION_AUTO) { | |
337 | bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, §ors); | |
338 | if (cylinders <= 1024 && heads <= 16 && sectors <= 63) { | |
339 | /* No translation. */ | |
340 | translation = 0; | |
341 | } else { | |
342 | /* LBA translation. */ | |
343 | translation = 1; | |
344 | } | |
345 | } else { | |
346 | translation--; | |
347 | } | |
348 | val |= translation << (i * 2); | |
349 | } | |
350 | } | |
351 | rtc_set_memory(s, 0x39, val); | |
352 | } | |
353 | ||
354 | void ioport_set_a20(int enable) | |
355 | { | |
356 | /* XXX: send to all CPUs ? */ | |
357 | cpu_x86_set_a20(first_cpu, enable); | |
358 | } | |
359 | ||
360 | int ioport_get_a20(void) | |
361 | { | |
362 | return ((first_cpu->a20_mask >> 20) & 1); | |
363 | } | |
364 | ||
365 | static void ioport92_write(void *opaque, uint32_t addr, uint32_t val) | |
366 | { | |
367 | ioport_set_a20((val >> 1) & 1); | |
368 | /* XXX: bit 0 is fast reset */ | |
369 | } | |
370 | ||
371 | static uint32_t ioport92_read(void *opaque, uint32_t addr) | |
372 | { | |
373 | return ioport_get_a20() << 1; | |
374 | } | |
375 | ||
376 | /***********************************************************/ | |
377 | /* Bochs BIOS debug ports */ | |
378 | ||
379 | static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val) | |
380 | { | |
381 | static const char shutdown_str[8] = "Shutdown"; | |
382 | static int shutdown_index = 0; | |
383 | ||
384 | switch(addr) { | |
385 | /* Bochs BIOS messages */ | |
386 | case 0x400: | |
387 | case 0x401: | |
388 | fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val); | |
389 | exit(1); | |
390 | case 0x402: | |
391 | case 0x403: | |
392 | #ifdef DEBUG_BIOS | |
393 | fprintf(stderr, "%c", val); | |
394 | #endif | |
395 | break; | |
396 | case 0x8900: | |
397 | /* same as Bochs power off */ | |
398 | if (val == shutdown_str[shutdown_index]) { | |
399 | shutdown_index++; | |
400 | if (shutdown_index == 8) { | |
401 | shutdown_index = 0; | |
402 | qemu_system_shutdown_request(); | |
403 | } | |
404 | } else { | |
405 | shutdown_index = 0; | |
406 | } | |
407 | break; | |
408 | ||
409 | /* LGPL'ed VGA BIOS messages */ | |
410 | case 0x501: | |
411 | case 0x502: | |
412 | fprintf(stderr, "VGA BIOS panic, line %d\n", val); | |
413 | exit(1); | |
414 | case 0x500: | |
415 | case 0x503: | |
416 | #ifdef DEBUG_BIOS | |
417 | fprintf(stderr, "%c", val); | |
418 | #endif | |
419 | break; | |
420 | } | |
421 | } | |
422 | ||
423 | static void bochs_bios_init(void) | |
424 | { | |
425 | void *fw_cfg; | |
426 | ||
427 | register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL); | |
428 | register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL); | |
429 | register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL); | |
430 | register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL); | |
431 | register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL); | |
432 | ||
433 | register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL); | |
434 | register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL); | |
435 | register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL); | |
436 | register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL); | |
437 | ||
438 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); | |
439 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); | |
440 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); | |
441 | } | |
442 | ||
443 | /* Generate an initial boot sector which sets state and jump to | |
444 | a specified vector */ | |
445 | static void generate_bootsect(uint8_t *option_rom, | |
446 | uint32_t gpr[8], uint16_t segs[6], uint16_t ip) | |
447 | { | |
448 | uint8_t rom[512], *p, *reloc; | |
449 | uint8_t sum; | |
450 | int i; | |
451 | ||
452 | memset(rom, 0, sizeof(rom)); | |
453 | ||
454 | p = rom; | |
455 | /* Make sure we have an option rom signature */ | |
456 | *p++ = 0x55; | |
457 | *p++ = 0xaa; | |
458 | ||
459 | /* ROM size in sectors*/ | |
460 | *p++ = 1; | |
461 | ||
462 | /* Hook int19 */ | |
463 | ||
464 | *p++ = 0x50; /* push ax */ | |
465 | *p++ = 0x1e; /* push ds */ | |
466 | *p++ = 0x31; *p++ = 0xc0; /* xor ax, ax */ | |
467 | *p++ = 0x8e; *p++ = 0xd8; /* mov ax, ds */ | |
468 | ||
469 | *p++ = 0xc7; *p++ = 0x06; /* movvw _start,0x64 */ | |
470 | *p++ = 0x64; *p++ = 0x00; | |
471 | reloc = p; | |
472 | *p++ = 0x00; *p++ = 0x00; | |
473 | ||
474 | *p++ = 0x8c; *p++ = 0x0e; /* mov cs,0x66 */ | |
475 | *p++ = 0x66; *p++ = 0x00; | |
476 | ||
477 | *p++ = 0x1f; /* pop ds */ | |
478 | *p++ = 0x58; /* pop ax */ | |
479 | *p++ = 0xcb; /* lret */ | |
480 | ||
481 | /* Actual code */ | |
482 | *reloc = (p - rom); | |
483 | ||
484 | *p++ = 0xfa; /* CLI */ | |
485 | *p++ = 0xfc; /* CLD */ | |
486 | ||
487 | for (i = 0; i < 6; i++) { | |
488 | if (i == 1) /* Skip CS */ | |
489 | continue; | |
490 | ||
491 | *p++ = 0xb8; /* MOV AX,imm16 */ | |
492 | *p++ = segs[i]; | |
493 | *p++ = segs[i] >> 8; | |
494 | *p++ = 0x8e; /* MOV <seg>,AX */ | |
495 | *p++ = 0xc0 + (i << 3); | |
496 | } | |
497 | ||
498 | for (i = 0; i < 8; i++) { | |
499 | *p++ = 0x66; /* 32-bit operand size */ | |
500 | *p++ = 0xb8 + i; /* MOV <reg>,imm32 */ | |
501 | *p++ = gpr[i]; | |
502 | *p++ = gpr[i] >> 8; | |
503 | *p++ = gpr[i] >> 16; | |
504 | *p++ = gpr[i] >> 24; | |
505 | } | |
506 | ||
507 | *p++ = 0xea; /* JMP FAR */ | |
508 | *p++ = ip; /* IP */ | |
509 | *p++ = ip >> 8; | |
510 | *p++ = segs[1]; /* CS */ | |
511 | *p++ = segs[1] >> 8; | |
512 | ||
513 | /* sign rom */ | |
514 | sum = 0; | |
515 | for (i = 0; i < (sizeof(rom) - 1); i++) | |
516 | sum += rom[i]; | |
517 | rom[sizeof(rom) - 1] = -sum; | |
518 | ||
519 | memcpy(option_rom, rom, sizeof(rom)); | |
520 | } | |
521 | ||
522 | static long get_file_size(FILE *f) | |
523 | { | |
524 | long where, size; | |
525 | ||
526 | /* XXX: on Unix systems, using fstat() probably makes more sense */ | |
527 | ||
528 | where = ftell(f); | |
529 | fseek(f, 0, SEEK_END); | |
530 | size = ftell(f); | |
531 | fseek(f, where, SEEK_SET); | |
532 | ||
533 | return size; | |
534 | } | |
535 | ||
536 | static void load_linux(uint8_t *option_rom, | |
537 | const char *kernel_filename, | |
538 | const char *initrd_filename, | |
539 | const char *kernel_cmdline) | |
540 | { | |
541 | uint16_t protocol; | |
542 | uint32_t gpr[8]; | |
543 | uint16_t seg[6]; | |
544 | uint16_t real_seg; | |
545 | int setup_size, kernel_size, initrd_size, cmdline_size; | |
546 | uint32_t initrd_max; | |
547 | uint8_t header[1024]; | |
548 | target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr; | |
549 | FILE *f, *fi; | |
550 | ||
551 | /* Align to 16 bytes as a paranoia measure */ | |
552 | cmdline_size = (strlen(kernel_cmdline)+16) & ~15; | |
553 | ||
554 | /* load the kernel header */ | |
555 | f = fopen(kernel_filename, "rb"); | |
556 | if (!f || !(kernel_size = get_file_size(f)) || | |
557 | fread(header, 1, 1024, f) != 1024) { | |
558 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
559 | kernel_filename); | |
560 | exit(1); | |
561 | } | |
562 | ||
563 | /* kernel protocol version */ | |
564 | #if 0 | |
565 | fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); | |
566 | #endif | |
567 | if (ldl_p(header+0x202) == 0x53726448) | |
568 | protocol = lduw_p(header+0x206); | |
569 | else | |
570 | protocol = 0; | |
571 | ||
572 | if (protocol < 0x200 || !(header[0x211] & 0x01)) { | |
573 | /* Low kernel */ | |
574 | real_addr = 0x90000; | |
575 | cmdline_addr = 0x9a000 - cmdline_size; | |
576 | prot_addr = 0x10000; | |
577 | } else if (protocol < 0x202) { | |
578 | /* High but ancient kernel */ | |
579 | real_addr = 0x90000; | |
580 | cmdline_addr = 0x9a000 - cmdline_size; | |
581 | prot_addr = 0x100000; | |
582 | } else { | |
583 | /* High and recent kernel */ | |
584 | real_addr = 0x10000; | |
585 | cmdline_addr = 0x20000; | |
586 | prot_addr = 0x100000; | |
587 | } | |
588 | ||
589 | #if 0 | |
590 | fprintf(stderr, | |
591 | "qemu: real_addr = 0x" TARGET_FMT_plx "\n" | |
592 | "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" | |
593 | "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", | |
594 | real_addr, | |
595 | cmdline_addr, | |
596 | prot_addr); | |
597 | #endif | |
598 | ||
599 | /* highest address for loading the initrd */ | |
600 | if (protocol >= 0x203) | |
601 | initrd_max = ldl_p(header+0x22c); | |
602 | else | |
603 | initrd_max = 0x37ffffff; | |
604 | ||
605 | if (initrd_max >= ram_size-ACPI_DATA_SIZE) | |
606 | initrd_max = ram_size-ACPI_DATA_SIZE-1; | |
607 | ||
608 | /* kernel command line */ | |
609 | pstrcpy_targphys(cmdline_addr, 4096, kernel_cmdline); | |
610 | ||
611 | if (protocol >= 0x202) { | |
612 | stl_p(header+0x228, cmdline_addr); | |
613 | } else { | |
614 | stw_p(header+0x20, 0xA33F); | |
615 | stw_p(header+0x22, cmdline_addr-real_addr); | |
616 | } | |
617 | ||
618 | /* loader type */ | |
619 | /* High nybble = B reserved for Qemu; low nybble is revision number. | |
620 | If this code is substantially changed, you may want to consider | |
621 | incrementing the revision. */ | |
622 | if (protocol >= 0x200) | |
623 | header[0x210] = 0xB0; | |
624 | ||
625 | /* heap */ | |
626 | if (protocol >= 0x201) { | |
627 | header[0x211] |= 0x80; /* CAN_USE_HEAP */ | |
628 | stw_p(header+0x224, cmdline_addr-real_addr-0x200); | |
629 | } | |
630 | ||
631 | /* load initrd */ | |
632 | if (initrd_filename) { | |
633 | if (protocol < 0x200) { | |
634 | fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); | |
635 | exit(1); | |
636 | } | |
637 | ||
638 | fi = fopen(initrd_filename, "rb"); | |
639 | if (!fi) { | |
640 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
641 | initrd_filename); | |
642 | exit(1); | |
643 | } | |
644 | ||
645 | initrd_size = get_file_size(fi); | |
646 | initrd_addr = (initrd_max-initrd_size) & ~4095; | |
647 | ||
648 | fprintf(stderr, "qemu: loading initrd (%#x bytes) at 0x" TARGET_FMT_plx | |
649 | "\n", initrd_size, initrd_addr); | |
650 | ||
651 | if (!fread_targphys_ok(initrd_addr, initrd_size, fi)) { | |
652 | fprintf(stderr, "qemu: read error on initial ram disk '%s'\n", | |
653 | initrd_filename); | |
654 | exit(1); | |
655 | } | |
656 | fclose(fi); | |
657 | ||
658 | stl_p(header+0x218, initrd_addr); | |
659 | stl_p(header+0x21c, initrd_size); | |
660 | } | |
661 | ||
662 | /* store the finalized header and load the rest of the kernel */ | |
663 | cpu_physical_memory_write(real_addr, header, 1024); | |
664 | ||
665 | setup_size = header[0x1f1]; | |
666 | if (setup_size == 0) | |
667 | setup_size = 4; | |
668 | ||
669 | setup_size = (setup_size+1)*512; | |
670 | kernel_size -= setup_size; /* Size of protected-mode code */ | |
671 | ||
672 | if (!fread_targphys_ok(real_addr+1024, setup_size-1024, f) || | |
673 | !fread_targphys_ok(prot_addr, kernel_size, f)) { | |
674 | fprintf(stderr, "qemu: read error on kernel '%s'\n", | |
675 | kernel_filename); | |
676 | exit(1); | |
677 | } | |
678 | fclose(f); | |
679 | ||
680 | /* generate bootsector to set up the initial register state */ | |
681 | real_seg = real_addr >> 4; | |
682 | seg[0] = seg[2] = seg[3] = seg[4] = seg[4] = real_seg; | |
683 | seg[1] = real_seg+0x20; /* CS */ | |
684 | memset(gpr, 0, sizeof gpr); | |
685 | gpr[4] = cmdline_addr-real_addr-16; /* SP (-16 is paranoia) */ | |
686 | ||
687 | generate_bootsect(option_rom, gpr, seg, 0); | |
688 | } | |
689 | ||
690 | static void main_cpu_reset(void *opaque) | |
691 | { | |
692 | CPUState *env = opaque; | |
693 | cpu_reset(env); | |
694 | } | |
695 | ||
696 | static const int ide_iobase[2] = { 0x1f0, 0x170 }; | |
697 | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; | |
698 | static const int ide_irq[2] = { 14, 15 }; | |
699 | ||
700 | #define NE2000_NB_MAX 6 | |
701 | ||
702 | static int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; | |
703 | static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
704 | ||
705 | static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; | |
706 | static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; | |
707 | ||
708 | static int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; | |
709 | static int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; | |
710 | ||
711 | #ifdef HAS_AUDIO | |
712 | static void audio_init (PCIBus *pci_bus, qemu_irq *pic) | |
713 | { | |
714 | struct soundhw *c; | |
715 | int audio_enabled = 0; | |
716 | ||
717 | for (c = soundhw; !audio_enabled && c->name; ++c) { | |
718 | audio_enabled = c->enabled; | |
719 | } | |
720 | ||
721 | if (audio_enabled) { | |
722 | AudioState *s; | |
723 | ||
724 | s = AUD_init (); | |
725 | if (s) { | |
726 | for (c = soundhw; c->name; ++c) { | |
727 | if (c->enabled) { | |
728 | if (c->isa) { | |
729 | c->init.init_isa (s, pic); | |
730 | } | |
731 | else { | |
732 | if (pci_bus) { | |
733 | c->init.init_pci (pci_bus, s); | |
734 | } | |
735 | } | |
736 | } | |
737 | } | |
738 | } | |
739 | } | |
740 | } | |
741 | #endif | |
742 | ||
743 | static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic) | |
744 | { | |
745 | static int nb_ne2k = 0; | |
746 | ||
747 | if (nb_ne2k == NE2000_NB_MAX) | |
748 | return; | |
749 | isa_ne2000_init(ne2000_io[nb_ne2k], pic[ne2000_irq[nb_ne2k]], nd); | |
750 | nb_ne2k++; | |
751 | } | |
752 | ||
753 | /* PC hardware initialisation */ | |
754 | static void pc_init1(ram_addr_t ram_size, int vga_ram_size, | |
755 | const char *boot_device, | |
756 | const char *kernel_filename, const char *kernel_cmdline, | |
757 | const char *initrd_filename, | |
758 | int pci_enabled, const char *cpu_model) | |
759 | { | |
760 | char buf[1024]; | |
761 | int ret, linux_boot, i; | |
762 | ram_addr_t ram_addr, vga_ram_addr, bios_offset, vga_bios_offset; | |
763 | ram_addr_t below_4g_mem_size, above_4g_mem_size = 0; | |
764 | int bios_size, isa_bios_size, vga_bios_size; | |
765 | PCIBus *pci_bus; | |
766 | int piix3_devfn = -1; | |
767 | CPUState *env; | |
768 | qemu_irq *cpu_irq; | |
769 | qemu_irq *i8259; | |
770 | int index; | |
771 | BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; | |
772 | BlockDriverState *fd[MAX_FD]; | |
773 | ||
774 | if (ram_size >= 0xe0000000 ) { | |
775 | above_4g_mem_size = ram_size - 0xe0000000; | |
776 | below_4g_mem_size = 0xe0000000; | |
777 | } else { | |
778 | below_4g_mem_size = ram_size; | |
779 | } | |
780 | ||
781 | linux_boot = (kernel_filename != NULL); | |
782 | ||
783 | /* init CPUs */ | |
784 | if (cpu_model == NULL) { | |
785 | #ifdef TARGET_X86_64 | |
786 | cpu_model = "qemu64"; | |
787 | #else | |
788 | cpu_model = "qemu32"; | |
789 | #endif | |
790 | } | |
791 | ||
792 | for(i = 0; i < smp_cpus; i++) { | |
793 | env = cpu_init(cpu_model); | |
794 | if (!env) { | |
795 | fprintf(stderr, "Unable to find x86 CPU definition\n"); | |
796 | exit(1); | |
797 | } | |
798 | if (i != 0) | |
799 | env->halted = 1; | |
800 | if (smp_cpus > 1) { | |
801 | /* XXX: enable it in all cases */ | |
802 | env->cpuid_features |= CPUID_APIC; | |
803 | } | |
804 | qemu_register_reset(main_cpu_reset, env); | |
805 | if (pci_enabled) { | |
806 | apic_init(env); | |
807 | } | |
808 | } | |
809 | ||
810 | vmport_init(); | |
811 | ||
812 | /* allocate RAM */ | |
813 | ram_addr = qemu_ram_alloc(0xa0000); | |
814 | cpu_register_physical_memory(0, 0xa0000, ram_addr); | |
815 | ||
816 | /* Allocate, even though we won't register, so we don't break the | |
817 | * phys_ram_base + PA assumption. This range includes vga (0xa0000 - 0xc0000), | |
818 | * and some bios areas, which will be registered later | |
819 | */ | |
820 | ram_addr = qemu_ram_alloc(0x100000 - 0xa0000); | |
821 | ram_addr = qemu_ram_alloc(below_4g_mem_size - 0x100000); | |
822 | cpu_register_physical_memory(0x100000, | |
823 | below_4g_mem_size - 0x100000, | |
824 | ram_addr); | |
825 | ||
826 | /* above 4giga memory allocation */ | |
827 | if (above_4g_mem_size > 0) { | |
828 | ram_addr = qemu_ram_alloc(above_4g_mem_size); | |
829 | cpu_register_physical_memory(0x100000000ULL, | |
830 | above_4g_mem_size, | |
831 | ram_addr); | |
832 | } | |
833 | ||
834 | ||
835 | /* allocate VGA RAM */ | |
836 | vga_ram_addr = qemu_ram_alloc(vga_ram_size); | |
837 | ||
838 | /* BIOS load */ | |
839 | if (bios_name == NULL) | |
840 | bios_name = BIOS_FILENAME; | |
841 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); | |
842 | bios_size = get_image_size(buf); | |
843 | if (bios_size <= 0 || | |
844 | (bios_size % 65536) != 0) { | |
845 | goto bios_error; | |
846 | } | |
847 | bios_offset = qemu_ram_alloc(bios_size); | |
848 | ret = load_image(buf, phys_ram_base + bios_offset); | |
849 | if (ret != bios_size) { | |
850 | bios_error: | |
851 | fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", buf); | |
852 | exit(1); | |
853 | } | |
854 | ||
855 | if (cirrus_vga_enabled || std_vga_enabled || vmsvga_enabled) { | |
856 | /* VGA BIOS load */ | |
857 | if (cirrus_vga_enabled) { | |
858 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_CIRRUS_FILENAME); | |
859 | } else { | |
860 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME); | |
861 | } | |
862 | vga_bios_size = get_image_size(buf); | |
863 | if (vga_bios_size <= 0 || vga_bios_size > 65536) | |
864 | goto vga_bios_error; | |
865 | vga_bios_offset = qemu_ram_alloc(65536); | |
866 | ||
867 | ret = load_image(buf, phys_ram_base + vga_bios_offset); | |
868 | if (ret != vga_bios_size) { | |
869 | vga_bios_error: | |
870 | fprintf(stderr, "qemu: could not load VGA BIOS '%s'\n", buf); | |
871 | exit(1); | |
872 | } | |
873 | ||
874 | /* setup basic memory access */ | |
875 | cpu_register_physical_memory(0xc0000, 0x10000, | |
876 | vga_bios_offset | IO_MEM_ROM); | |
877 | } | |
878 | ||
879 | /* map the last 128KB of the BIOS in ISA space */ | |
880 | isa_bios_size = bios_size; | |
881 | if (isa_bios_size > (128 * 1024)) | |
882 | isa_bios_size = 128 * 1024; | |
883 | cpu_register_physical_memory(0x100000 - isa_bios_size, | |
884 | isa_bios_size, | |
885 | (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM); | |
886 | ||
887 | { | |
888 | ram_addr_t option_rom_offset; | |
889 | int size, offset; | |
890 | ||
891 | offset = 0; | |
892 | if (linux_boot) { | |
893 | option_rom_offset = qemu_ram_alloc(TARGET_PAGE_SIZE); | |
894 | load_linux(phys_ram_base + option_rom_offset, | |
895 | kernel_filename, initrd_filename, kernel_cmdline); | |
896 | cpu_register_physical_memory(0xd0000, TARGET_PAGE_SIZE, | |
897 | option_rom_offset | IO_MEM_ROM); | |
898 | offset = TARGET_PAGE_SIZE; | |
899 | } | |
900 | ||
901 | for (i = 0; i < nb_option_roms; i++) { | |
902 | size = get_image_size(option_rom[i]); | |
903 | if (size < 0) { | |
904 | fprintf(stderr, "Could not load option rom '%s'\n", | |
905 | option_rom[i]); | |
906 | exit(1); | |
907 | } | |
908 | if (size > (0x10000 - offset)) | |
909 | goto option_rom_error; | |
910 | option_rom_offset = qemu_ram_alloc(size); | |
911 | ret = load_image(option_rom[i], phys_ram_base + option_rom_offset); | |
912 | if (ret != size) { | |
913 | option_rom_error: | |
914 | fprintf(stderr, "Too many option ROMS\n"); | |
915 | exit(1); | |
916 | } | |
917 | size = (size + 4095) & ~4095; | |
918 | cpu_register_physical_memory(0xd0000 + offset, | |
919 | size, option_rom_offset | IO_MEM_ROM); | |
920 | offset += size; | |
921 | } | |
922 | } | |
923 | ||
924 | /* map all the bios at the top of memory */ | |
925 | cpu_register_physical_memory((uint32_t)(-bios_size), | |
926 | bios_size, bios_offset | IO_MEM_ROM); | |
927 | ||
928 | bochs_bios_init(); | |
929 | ||
930 | cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1); | |
931 | i8259 = i8259_init(cpu_irq[0]); | |
932 | ferr_irq = i8259[13]; | |
933 | ||
934 | if (pci_enabled) { | |
935 | pci_bus = i440fx_init(&i440fx_state, i8259); | |
936 | piix3_devfn = piix3_init(pci_bus, -1); | |
937 | } else { | |
938 | pci_bus = NULL; | |
939 | } | |
940 | ||
941 | /* init basic PC hardware */ | |
942 | register_ioport_write(0x80, 1, 1, ioport80_write, NULL); | |
943 | ||
944 | register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL); | |
945 | ||
946 | if (cirrus_vga_enabled) { | |
947 | if (pci_enabled) { | |
948 | pci_cirrus_vga_init(pci_bus, | |
949 | phys_ram_base + vga_ram_addr, | |
950 | vga_ram_addr, vga_ram_size); | |
951 | } else { | |
952 | isa_cirrus_vga_init(phys_ram_base + vga_ram_addr, | |
953 | vga_ram_addr, vga_ram_size); | |
954 | } | |
955 | } else if (vmsvga_enabled) { | |
956 | if (pci_enabled) | |
957 | pci_vmsvga_init(pci_bus, phys_ram_base + vga_ram_addr, | |
958 | vga_ram_addr, vga_ram_size); | |
959 | else | |
960 | fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__); | |
961 | } else if (std_vga_enabled) { | |
962 | if (pci_enabled) { | |
963 | pci_vga_init(pci_bus, phys_ram_base + vga_ram_addr, | |
964 | vga_ram_addr, vga_ram_size, 0, 0); | |
965 | } else { | |
966 | isa_vga_init(phys_ram_base + vga_ram_addr, | |
967 | vga_ram_addr, vga_ram_size); | |
968 | } | |
969 | } | |
970 | ||
971 | rtc_state = rtc_init(0x70, i8259[8], 2000); | |
972 | ||
973 | qemu_register_boot_set(pc_boot_set, rtc_state); | |
974 | ||
975 | register_ioport_read(0x92, 1, 1, ioport92_read, NULL); | |
976 | register_ioport_write(0x92, 1, 1, ioport92_write, NULL); | |
977 | ||
978 | if (pci_enabled) { | |
979 | ioapic = ioapic_init(); | |
980 | } | |
981 | pit = pit_init(0x40, i8259[0]); | |
982 | pcspk_init(pit); | |
983 | if (!no_hpet) { | |
984 | hpet_init(i8259); | |
985 | } | |
986 | if (pci_enabled) { | |
987 | pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic); | |
988 | } | |
989 | ||
990 | for(i = 0; i < MAX_SERIAL_PORTS; i++) { | |
991 | if (serial_hds[i]) { | |
992 | serial_init(serial_io[i], i8259[serial_irq[i]], 115200, | |
993 | serial_hds[i]); | |
994 | } | |
995 | } | |
996 | ||
997 | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { | |
998 | if (parallel_hds[i]) { | |
999 | parallel_init(parallel_io[i], i8259[parallel_irq[i]], | |
1000 | parallel_hds[i]); | |
1001 | } | |
1002 | } | |
1003 | ||
1004 | for(i = 0; i < nb_nics; i++) { | |
1005 | NICInfo *nd = &nd_table[i]; | |
1006 | ||
1007 | if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) | |
1008 | pc_init_ne2k_isa(nd, i8259); | |
1009 | else | |
1010 | pci_nic_init(pci_bus, nd, -1, "ne2k_pci"); | |
1011 | } | |
1012 | ||
1013 | qemu_system_hot_add_init(); | |
1014 | ||
1015 | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { | |
1016 | fprintf(stderr, "qemu: too many IDE bus\n"); | |
1017 | exit(1); | |
1018 | } | |
1019 | ||
1020 | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { | |
1021 | index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); | |
1022 | if (index != -1) | |
1023 | hd[i] = drives_table[index].bdrv; | |
1024 | else | |
1025 | hd[i] = NULL; | |
1026 | } | |
1027 | ||
1028 | if (pci_enabled) { | |
1029 | pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, i8259); | |
1030 | } else { | |
1031 | for(i = 0; i < MAX_IDE_BUS; i++) { | |
1032 | isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]], | |
1033 | hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]); | |
1034 | } | |
1035 | } | |
1036 | ||
1037 | i8042_init(i8259[1], i8259[12], 0x60); | |
1038 | DMA_init(0); | |
1039 | #ifdef HAS_AUDIO | |
1040 | audio_init(pci_enabled ? pci_bus : NULL, i8259); | |
1041 | #endif | |
1042 | ||
1043 | for(i = 0; i < MAX_FD; i++) { | |
1044 | index = drive_get_index(IF_FLOPPY, 0, i); | |
1045 | if (index != -1) | |
1046 | fd[i] = drives_table[index].bdrv; | |
1047 | else | |
1048 | fd[i] = NULL; | |
1049 | } | |
1050 | floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd); | |
1051 | ||
1052 | cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd); | |
1053 | ||
1054 | if (pci_enabled && usb_enabled) { | |
1055 | usb_uhci_piix3_init(pci_bus, piix3_devfn + 2); | |
1056 | } | |
1057 | ||
1058 | if (pci_enabled && acpi_enabled) { | |
1059 | uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */ | |
1060 | i2c_bus *smbus; | |
1061 | ||
1062 | /* TODO: Populate SPD eeprom data. */ | |
1063 | smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, i8259[9]); | |
1064 | for (i = 0; i < 8; i++) { | |
1065 | smbus_eeprom_device_init(smbus, 0x50 + i, eeprom_buf + (i * 256)); | |
1066 | } | |
1067 | } | |
1068 | ||
1069 | if (i440fx_state) { | |
1070 | i440fx_init_memory_mappings(i440fx_state); | |
1071 | } | |
1072 | ||
1073 | if (pci_enabled) { | |
1074 | int max_bus; | |
1075 | int bus, unit; | |
1076 | void *scsi; | |
1077 | ||
1078 | max_bus = drive_get_max_bus(IF_SCSI); | |
1079 | ||
1080 | for (bus = 0; bus <= max_bus; bus++) { | |
1081 | scsi = lsi_scsi_init(pci_bus, -1); | |
1082 | for (unit = 0; unit < LSI_MAX_DEVS; unit++) { | |
1083 | index = drive_get_index(IF_SCSI, bus, unit); | |
1084 | if (index == -1) | |
1085 | continue; | |
1086 | lsi_scsi_attach(scsi, drives_table[index].bdrv, unit); | |
1087 | } | |
1088 | } | |
1089 | } | |
1090 | ||
1091 | /* Add virtio block devices */ | |
1092 | if (pci_enabled) { | |
1093 | int index; | |
1094 | int unit_id = 0; | |
1095 | ||
1096 | while ((index = drive_get_index(IF_VIRTIO, 0, unit_id)) != -1) { | |
1097 | virtio_blk_init(pci_bus, drives_table[index].bdrv); | |
1098 | unit_id++; | |
1099 | } | |
1100 | } | |
1101 | ||
1102 | /* Add virtio balloon device */ | |
1103 | if (pci_enabled) | |
1104 | virtio_balloon_init(pci_bus); | |
1105 | ||
1106 | /* Add virtio console devices */ | |
1107 | if (pci_enabled) { | |
1108 | for(i = 0; i < MAX_VIRTIO_CONSOLES; i++) { | |
1109 | if (virtcon_hds[i]) | |
1110 | virtio_console_init(pci_bus, virtcon_hds[i]); | |
1111 | } | |
1112 | } | |
1113 | } | |
1114 | ||
1115 | static void pc_init_pci(ram_addr_t ram_size, int vga_ram_size, | |
1116 | const char *boot_device, | |
1117 | const char *kernel_filename, | |
1118 | const char *kernel_cmdline, | |
1119 | const char *initrd_filename, | |
1120 | const char *cpu_model) | |
1121 | { | |
1122 | pc_init1(ram_size, vga_ram_size, boot_device, | |
1123 | kernel_filename, kernel_cmdline, | |
1124 | initrd_filename, 1, cpu_model); | |
1125 | } | |
1126 | ||
1127 | static void pc_init_isa(ram_addr_t ram_size, int vga_ram_size, | |
1128 | const char *boot_device, | |
1129 | const char *kernel_filename, | |
1130 | const char *kernel_cmdline, | |
1131 | const char *initrd_filename, | |
1132 | const char *cpu_model) | |
1133 | { | |
1134 | pc_init1(ram_size, vga_ram_size, boot_device, | |
1135 | kernel_filename, kernel_cmdline, | |
1136 | initrd_filename, 0, cpu_model); | |
1137 | } | |
1138 | ||
1139 | /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE) | |
1140 | BIOS will read it and start S3 resume at POST Entry */ | |
1141 | void cmos_set_s3_resume(void) | |
1142 | { | |
1143 | if (rtc_state) | |
1144 | rtc_set_memory(rtc_state, 0xF, 0xFE); | |
1145 | } | |
1146 | ||
1147 | QEMUMachine pc_machine = { | |
1148 | .name = "pc", | |
1149 | .desc = "Standard PC", | |
1150 | .init = pc_init_pci, | |
1151 | .ram_require = VGA_RAM_SIZE + PC_MAX_BIOS_SIZE, | |
1152 | .max_cpus = 255, | |
1153 | }; | |
1154 | ||
1155 | QEMUMachine isapc_machine = { | |
1156 | .name = "isapc", | |
1157 | .desc = "ISA-only PC", | |
1158 | .init = pc_init_isa, | |
1159 | .ram_require = VGA_RAM_SIZE + PC_MAX_BIOS_SIZE, | |
1160 | .max_cpus = 1, | |
1161 | }; |