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1 | /* | |
2 | * QEMU PC System Emulator | |
3 | * | |
4 | * Copyright (c) 2003-2004 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | #include "hw.h" | |
25 | #include "pc.h" | |
26 | #include "fdc.h" | |
27 | #include "pci.h" | |
28 | #include "block.h" | |
29 | #include "sysemu.h" | |
30 | #include "audio/audio.h" | |
31 | #include "net.h" | |
32 | #include "smbus.h" | |
33 | #include "boards.h" | |
34 | #include "monitor.h" | |
35 | #include "fw_cfg.h" | |
36 | #include "hpet_emul.h" | |
37 | #include "watchdog.h" | |
38 | #include "smbios.h" | |
39 | #include "ide.h" | |
40 | #include "loader.h" | |
41 | #include "elf.h" | |
42 | ||
43 | /* output Bochs bios info messages */ | |
44 | //#define DEBUG_BIOS | |
45 | ||
46 | /* Show multiboot debug output */ | |
47 | //#define DEBUG_MULTIBOOT | |
48 | ||
49 | #define BIOS_FILENAME "bios.bin" | |
50 | #define VGABIOS_FILENAME "vgabios.bin" | |
51 | #define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin" | |
52 | ||
53 | #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024) | |
54 | ||
55 | /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */ | |
56 | #define ACPI_DATA_SIZE 0x10000 | |
57 | #define BIOS_CFG_IOPORT 0x510 | |
58 | #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) | |
59 | #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) | |
60 | #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) | |
61 | ||
62 | #define MAX_IDE_BUS 2 | |
63 | ||
64 | static fdctrl_t *floppy_controller; | |
65 | static RTCState *rtc_state; | |
66 | static PITState *pit; | |
67 | static PCII440FXState *i440fx_state; | |
68 | ||
69 | typedef struct isa_irq_state { | |
70 | qemu_irq *i8259; | |
71 | qemu_irq *ioapic; | |
72 | } IsaIrqState; | |
73 | ||
74 | static void isa_irq_handler(void *opaque, int n, int level) | |
75 | { | |
76 | IsaIrqState *isa = (IsaIrqState *)opaque; | |
77 | ||
78 | if (n < 16) { | |
79 | qemu_set_irq(isa->i8259[n], level); | |
80 | } | |
81 | if (isa->ioapic) | |
82 | qemu_set_irq(isa->ioapic[n], level); | |
83 | }; | |
84 | ||
85 | static void ioport80_write(void *opaque, uint32_t addr, uint32_t data) | |
86 | { | |
87 | } | |
88 | ||
89 | /* MSDOS compatibility mode FPU exception support */ | |
90 | static qemu_irq ferr_irq; | |
91 | /* XXX: add IGNNE support */ | |
92 | void cpu_set_ferr(CPUX86State *s) | |
93 | { | |
94 | qemu_irq_raise(ferr_irq); | |
95 | } | |
96 | ||
97 | static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data) | |
98 | { | |
99 | qemu_irq_lower(ferr_irq); | |
100 | } | |
101 | ||
102 | /* TSC handling */ | |
103 | uint64_t cpu_get_tsc(CPUX86State *env) | |
104 | { | |
105 | return cpu_get_ticks(); | |
106 | } | |
107 | ||
108 | /* SMM support */ | |
109 | void cpu_smm_update(CPUState *env) | |
110 | { | |
111 | if (i440fx_state && env == first_cpu) | |
112 | i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1); | |
113 | } | |
114 | ||
115 | ||
116 | /* IRQ handling */ | |
117 | int cpu_get_pic_interrupt(CPUState *env) | |
118 | { | |
119 | int intno; | |
120 | ||
121 | intno = apic_get_interrupt(env); | |
122 | if (intno >= 0) { | |
123 | /* set irq request if a PIC irq is still pending */ | |
124 | /* XXX: improve that */ | |
125 | pic_update_irq(isa_pic); | |
126 | return intno; | |
127 | } | |
128 | /* read the irq from the PIC */ | |
129 | if (!apic_accept_pic_intr(env)) | |
130 | return -1; | |
131 | ||
132 | intno = pic_read_irq(isa_pic); | |
133 | return intno; | |
134 | } | |
135 | ||
136 | static void pic_irq_request(void *opaque, int irq, int level) | |
137 | { | |
138 | CPUState *env = first_cpu; | |
139 | ||
140 | if (env->apic_state) { | |
141 | while (env) { | |
142 | if (apic_accept_pic_intr(env)) | |
143 | apic_deliver_pic_intr(env, level); | |
144 | env = env->next_cpu; | |
145 | } | |
146 | } else { | |
147 | if (level) | |
148 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
149 | else | |
150 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
151 | } | |
152 | } | |
153 | ||
154 | /* PC cmos mappings */ | |
155 | ||
156 | #define REG_EQUIPMENT_BYTE 0x14 | |
157 | ||
158 | static int cmos_get_fd_drive_type(int fd0) | |
159 | { | |
160 | int val; | |
161 | ||
162 | switch (fd0) { | |
163 | case 0: | |
164 | /* 1.44 Mb 3"5 drive */ | |
165 | val = 4; | |
166 | break; | |
167 | case 1: | |
168 | /* 2.88 Mb 3"5 drive */ | |
169 | val = 5; | |
170 | break; | |
171 | case 2: | |
172 | /* 1.2 Mb 5"5 drive */ | |
173 | val = 2; | |
174 | break; | |
175 | default: | |
176 | val = 0; | |
177 | break; | |
178 | } | |
179 | return val; | |
180 | } | |
181 | ||
182 | static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd) | |
183 | { | |
184 | RTCState *s = rtc_state; | |
185 | int cylinders, heads, sectors; | |
186 | bdrv_get_geometry_hint(hd, &cylinders, &heads, §ors); | |
187 | rtc_set_memory(s, type_ofs, 47); | |
188 | rtc_set_memory(s, info_ofs, cylinders); | |
189 | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); | |
190 | rtc_set_memory(s, info_ofs + 2, heads); | |
191 | rtc_set_memory(s, info_ofs + 3, 0xff); | |
192 | rtc_set_memory(s, info_ofs + 4, 0xff); | |
193 | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); | |
194 | rtc_set_memory(s, info_ofs + 6, cylinders); | |
195 | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); | |
196 | rtc_set_memory(s, info_ofs + 8, sectors); | |
197 | } | |
198 | ||
199 | /* convert boot_device letter to something recognizable by the bios */ | |
200 | static int boot_device2nibble(char boot_device) | |
201 | { | |
202 | switch(boot_device) { | |
203 | case 'a': | |
204 | case 'b': | |
205 | return 0x01; /* floppy boot */ | |
206 | case 'c': | |
207 | return 0x02; /* hard drive boot */ | |
208 | case 'd': | |
209 | return 0x03; /* CD-ROM boot */ | |
210 | case 'n': | |
211 | return 0x04; /* Network boot */ | |
212 | } | |
213 | return 0; | |
214 | } | |
215 | ||
216 | /* copy/pasted from cmos_init, should be made a general function | |
217 | and used there as well */ | |
218 | static int pc_boot_set(void *opaque, const char *boot_device) | |
219 | { | |
220 | Monitor *mon = cur_mon; | |
221 | #define PC_MAX_BOOT_DEVICES 3 | |
222 | RTCState *s = (RTCState *)opaque; | |
223 | int nbds, bds[3] = { 0, }; | |
224 | int i; | |
225 | ||
226 | nbds = strlen(boot_device); | |
227 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
228 | monitor_printf(mon, "Too many boot devices for PC\n"); | |
229 | return(1); | |
230 | } | |
231 | for (i = 0; i < nbds; i++) { | |
232 | bds[i] = boot_device2nibble(boot_device[i]); | |
233 | if (bds[i] == 0) { | |
234 | monitor_printf(mon, "Invalid boot device for PC: '%c'\n", | |
235 | boot_device[i]); | |
236 | return(1); | |
237 | } | |
238 | } | |
239 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
240 | rtc_set_memory(s, 0x38, (bds[2] << 4)); | |
241 | return(0); | |
242 | } | |
243 | ||
244 | /* hd_table must contain 4 block drivers */ | |
245 | static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, | |
246 | const char *boot_device, DriveInfo **hd_table) | |
247 | { | |
248 | RTCState *s = rtc_state; | |
249 | int nbds, bds[3] = { 0, }; | |
250 | int val; | |
251 | int fd0, fd1, nb; | |
252 | int i; | |
253 | ||
254 | /* various important CMOS locations needed by PC/Bochs bios */ | |
255 | ||
256 | /* memory size */ | |
257 | val = 640; /* base memory in K */ | |
258 | rtc_set_memory(s, 0x15, val); | |
259 | rtc_set_memory(s, 0x16, val >> 8); | |
260 | ||
261 | val = (ram_size / 1024) - 1024; | |
262 | if (val > 65535) | |
263 | val = 65535; | |
264 | rtc_set_memory(s, 0x17, val); | |
265 | rtc_set_memory(s, 0x18, val >> 8); | |
266 | rtc_set_memory(s, 0x30, val); | |
267 | rtc_set_memory(s, 0x31, val >> 8); | |
268 | ||
269 | if (above_4g_mem_size) { | |
270 | rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16); | |
271 | rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24); | |
272 | rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32); | |
273 | } | |
274 | ||
275 | if (ram_size > (16 * 1024 * 1024)) | |
276 | val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536); | |
277 | else | |
278 | val = 0; | |
279 | if (val > 65535) | |
280 | val = 65535; | |
281 | rtc_set_memory(s, 0x34, val); | |
282 | rtc_set_memory(s, 0x35, val >> 8); | |
283 | ||
284 | /* set the number of CPU */ | |
285 | rtc_set_memory(s, 0x5f, smp_cpus - 1); | |
286 | ||
287 | /* set boot devices, and disable floppy signature check if requested */ | |
288 | #define PC_MAX_BOOT_DEVICES 3 | |
289 | nbds = strlen(boot_device); | |
290 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
291 | fprintf(stderr, "Too many boot devices for PC\n"); | |
292 | exit(1); | |
293 | } | |
294 | for (i = 0; i < nbds; i++) { | |
295 | bds[i] = boot_device2nibble(boot_device[i]); | |
296 | if (bds[i] == 0) { | |
297 | fprintf(stderr, "Invalid boot device for PC: '%c'\n", | |
298 | boot_device[i]); | |
299 | exit(1); | |
300 | } | |
301 | } | |
302 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
303 | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); | |
304 | ||
305 | /* floppy type */ | |
306 | ||
307 | fd0 = fdctrl_get_drive_type(floppy_controller, 0); | |
308 | fd1 = fdctrl_get_drive_type(floppy_controller, 1); | |
309 | ||
310 | val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1); | |
311 | rtc_set_memory(s, 0x10, val); | |
312 | ||
313 | val = 0; | |
314 | nb = 0; | |
315 | if (fd0 < 3) | |
316 | nb++; | |
317 | if (fd1 < 3) | |
318 | nb++; | |
319 | switch (nb) { | |
320 | case 0: | |
321 | break; | |
322 | case 1: | |
323 | val |= 0x01; /* 1 drive, ready for boot */ | |
324 | break; | |
325 | case 2: | |
326 | val |= 0x41; /* 2 drives, ready for boot */ | |
327 | break; | |
328 | } | |
329 | val |= 0x02; /* FPU is there */ | |
330 | val |= 0x04; /* PS/2 mouse installed */ | |
331 | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); | |
332 | ||
333 | /* hard drives */ | |
334 | ||
335 | rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0)); | |
336 | if (hd_table[0]) | |
337 | cmos_init_hd(0x19, 0x1b, hd_table[0]->bdrv); | |
338 | if (hd_table[1]) | |
339 | cmos_init_hd(0x1a, 0x24, hd_table[1]->bdrv); | |
340 | ||
341 | val = 0; | |
342 | for (i = 0; i < 4; i++) { | |
343 | if (hd_table[i]) { | |
344 | int cylinders, heads, sectors, translation; | |
345 | /* NOTE: bdrv_get_geometry_hint() returns the physical | |
346 | geometry. It is always such that: 1 <= sects <= 63, 1 | |
347 | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS | |
348 | geometry can be different if a translation is done. */ | |
349 | translation = bdrv_get_translation_hint(hd_table[i]->bdrv); | |
350 | if (translation == BIOS_ATA_TRANSLATION_AUTO) { | |
351 | bdrv_get_geometry_hint(hd_table[i]->bdrv, &cylinders, &heads, §ors); | |
352 | if (cylinders <= 1024 && heads <= 16 && sectors <= 63) { | |
353 | /* No translation. */ | |
354 | translation = 0; | |
355 | } else { | |
356 | /* LBA translation. */ | |
357 | translation = 1; | |
358 | } | |
359 | } else { | |
360 | translation--; | |
361 | } | |
362 | val |= translation << (i * 2); | |
363 | } | |
364 | } | |
365 | rtc_set_memory(s, 0x39, val); | |
366 | } | |
367 | ||
368 | void ioport_set_a20(int enable) | |
369 | { | |
370 | /* XXX: send to all CPUs ? */ | |
371 | cpu_x86_set_a20(first_cpu, enable); | |
372 | } | |
373 | ||
374 | int ioport_get_a20(void) | |
375 | { | |
376 | return ((first_cpu->a20_mask >> 20) & 1); | |
377 | } | |
378 | ||
379 | static void ioport92_write(void *opaque, uint32_t addr, uint32_t val) | |
380 | { | |
381 | ioport_set_a20((val >> 1) & 1); | |
382 | /* XXX: bit 0 is fast reset */ | |
383 | } | |
384 | ||
385 | static uint32_t ioport92_read(void *opaque, uint32_t addr) | |
386 | { | |
387 | return ioport_get_a20() << 1; | |
388 | } | |
389 | ||
390 | /***********************************************************/ | |
391 | /* Bochs BIOS debug ports */ | |
392 | ||
393 | static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val) | |
394 | { | |
395 | static const char shutdown_str[8] = "Shutdown"; | |
396 | static int shutdown_index = 0; | |
397 | ||
398 | switch(addr) { | |
399 | /* Bochs BIOS messages */ | |
400 | case 0x400: | |
401 | case 0x401: | |
402 | fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val); | |
403 | exit(1); | |
404 | case 0x402: | |
405 | case 0x403: | |
406 | #ifdef DEBUG_BIOS | |
407 | fprintf(stderr, "%c", val); | |
408 | #endif | |
409 | break; | |
410 | case 0x8900: | |
411 | /* same as Bochs power off */ | |
412 | if (val == shutdown_str[shutdown_index]) { | |
413 | shutdown_index++; | |
414 | if (shutdown_index == 8) { | |
415 | shutdown_index = 0; | |
416 | qemu_system_shutdown_request(); | |
417 | } | |
418 | } else { | |
419 | shutdown_index = 0; | |
420 | } | |
421 | break; | |
422 | ||
423 | /* LGPL'ed VGA BIOS messages */ | |
424 | case 0x501: | |
425 | case 0x502: | |
426 | fprintf(stderr, "VGA BIOS panic, line %d\n", val); | |
427 | exit(1); | |
428 | case 0x500: | |
429 | case 0x503: | |
430 | #ifdef DEBUG_BIOS | |
431 | fprintf(stderr, "%c", val); | |
432 | #endif | |
433 | break; | |
434 | } | |
435 | } | |
436 | ||
437 | static void *bochs_bios_init(void) | |
438 | { | |
439 | void *fw_cfg; | |
440 | uint8_t *smbios_table; | |
441 | size_t smbios_len; | |
442 | uint64_t *numa_fw_cfg; | |
443 | int i, j; | |
444 | ||
445 | register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL); | |
446 | register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL); | |
447 | register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL); | |
448 | register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL); | |
449 | register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL); | |
450 | ||
451 | register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL); | |
452 | register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL); | |
453 | register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL); | |
454 | register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL); | |
455 | ||
456 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); | |
457 | ||
458 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); | |
459 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); | |
460 | fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables, | |
461 | acpi_tables_len); | |
462 | fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1); | |
463 | ||
464 | smbios_table = smbios_get_table(&smbios_len); | |
465 | if (smbios_table) | |
466 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, | |
467 | smbios_table, smbios_len); | |
468 | ||
469 | /* allocate memory for the NUMA channel: one (64bit) word for the number | |
470 | * of nodes, one word for each VCPU->node and one word for each node to | |
471 | * hold the amount of memory. | |
472 | */ | |
473 | numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8); | |
474 | numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); | |
475 | for (i = 0; i < smp_cpus; i++) { | |
476 | for (j = 0; j < nb_numa_nodes; j++) { | |
477 | if (node_cpumask[j] & (1 << i)) { | |
478 | numa_fw_cfg[i + 1] = cpu_to_le64(j); | |
479 | break; | |
480 | } | |
481 | } | |
482 | } | |
483 | for (i = 0; i < nb_numa_nodes; i++) { | |
484 | numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]); | |
485 | } | |
486 | fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg, | |
487 | (1 + smp_cpus + nb_numa_nodes) * 8); | |
488 | ||
489 | return fw_cfg; | |
490 | } | |
491 | ||
492 | /* Generate an initial boot sector which sets state and jump to | |
493 | a specified vector */ | |
494 | static void generate_bootsect(uint32_t gpr[8], uint16_t segs[6], uint16_t ip) | |
495 | { | |
496 | uint8_t rom[512], *p, *reloc; | |
497 | uint8_t sum; | |
498 | int i; | |
499 | ||
500 | memset(rom, 0, sizeof(rom)); | |
501 | ||
502 | p = rom; | |
503 | /* Make sure we have an option rom signature */ | |
504 | *p++ = 0x55; | |
505 | *p++ = 0xaa; | |
506 | ||
507 | /* ROM size in sectors*/ | |
508 | *p++ = 1; | |
509 | ||
510 | /* Hook int19 */ | |
511 | ||
512 | *p++ = 0x50; /* push ax */ | |
513 | *p++ = 0x1e; /* push ds */ | |
514 | *p++ = 0x31; *p++ = 0xc0; /* xor ax, ax */ | |
515 | *p++ = 0x8e; *p++ = 0xd8; /* mov ax, ds */ | |
516 | ||
517 | *p++ = 0xc7; *p++ = 0x06; /* movvw _start,0x64 */ | |
518 | *p++ = 0x64; *p++ = 0x00; | |
519 | reloc = p; | |
520 | *p++ = 0x00; *p++ = 0x00; | |
521 | ||
522 | *p++ = 0x8c; *p++ = 0x0e; /* mov cs,0x66 */ | |
523 | *p++ = 0x66; *p++ = 0x00; | |
524 | ||
525 | *p++ = 0x1f; /* pop ds */ | |
526 | *p++ = 0x58; /* pop ax */ | |
527 | *p++ = 0xcb; /* lret */ | |
528 | ||
529 | /* Actual code */ | |
530 | *reloc = (p - rom); | |
531 | ||
532 | *p++ = 0xfa; /* CLI */ | |
533 | *p++ = 0xfc; /* CLD */ | |
534 | ||
535 | for (i = 0; i < 6; i++) { | |
536 | if (i == 1) /* Skip CS */ | |
537 | continue; | |
538 | ||
539 | *p++ = 0xb8; /* MOV AX,imm16 */ | |
540 | *p++ = segs[i]; | |
541 | *p++ = segs[i] >> 8; | |
542 | *p++ = 0x8e; /* MOV <seg>,AX */ | |
543 | *p++ = 0xc0 + (i << 3); | |
544 | } | |
545 | ||
546 | for (i = 0; i < 8; i++) { | |
547 | *p++ = 0x66; /* 32-bit operand size */ | |
548 | *p++ = 0xb8 + i; /* MOV <reg>,imm32 */ | |
549 | *p++ = gpr[i]; | |
550 | *p++ = gpr[i] >> 8; | |
551 | *p++ = gpr[i] >> 16; | |
552 | *p++ = gpr[i] >> 24; | |
553 | } | |
554 | ||
555 | *p++ = 0xea; /* JMP FAR */ | |
556 | *p++ = ip; /* IP */ | |
557 | *p++ = ip >> 8; | |
558 | *p++ = segs[1]; /* CS */ | |
559 | *p++ = segs[1] >> 8; | |
560 | ||
561 | /* sign rom */ | |
562 | sum = 0; | |
563 | for (i = 0; i < (sizeof(rom) - 1); i++) | |
564 | sum += rom[i]; | |
565 | rom[sizeof(rom) - 1] = -sum; | |
566 | ||
567 | rom_add_blob("linux-bootsect", rom, sizeof(rom), | |
568 | PC_ROM_MIN_OPTION, PC_ROM_MAX, PC_ROM_ALIGN); | |
569 | } | |
570 | ||
571 | static long get_file_size(FILE *f) | |
572 | { | |
573 | long where, size; | |
574 | ||
575 | /* XXX: on Unix systems, using fstat() probably makes more sense */ | |
576 | ||
577 | where = ftell(f); | |
578 | fseek(f, 0, SEEK_END); | |
579 | size = ftell(f); | |
580 | fseek(f, where, SEEK_SET); | |
581 | ||
582 | return size; | |
583 | } | |
584 | ||
585 | #define MULTIBOOT_STRUCT_ADDR 0x9000 | |
586 | ||
587 | #if MULTIBOOT_STRUCT_ADDR > 0xf0000 | |
588 | #error multiboot struct needs to fit in 16 bit real mode | |
589 | #endif | |
590 | ||
591 | static int load_multiboot(void *fw_cfg, | |
592 | FILE *f, | |
593 | const char *kernel_filename, | |
594 | const char *initrd_filename, | |
595 | const char *kernel_cmdline, | |
596 | uint8_t *header) | |
597 | { | |
598 | int i, is_multiboot = 0; | |
599 | uint32_t flags = 0; | |
600 | uint32_t mh_entry_addr; | |
601 | uint32_t mh_load_addr; | |
602 | uint32_t mb_kernel_size; | |
603 | uint32_t mmap_addr = MULTIBOOT_STRUCT_ADDR; | |
604 | uint32_t mb_bootinfo = MULTIBOOT_STRUCT_ADDR + 0x500; | |
605 | uint32_t mb_mod_end; | |
606 | uint8_t bootinfo[0x500]; | |
607 | uint32_t cmdline = 0x200; | |
608 | ||
609 | /* Ok, let's see if it is a multiboot image. | |
610 | The header is 12x32bit long, so the latest entry may be 8192 - 48. */ | |
611 | for (i = 0; i < (8192 - 48); i += 4) { | |
612 | if (ldl_p(header+i) == 0x1BADB002) { | |
613 | uint32_t checksum = ldl_p(header+i+8); | |
614 | flags = ldl_p(header+i+4); | |
615 | checksum += flags; | |
616 | checksum += (uint32_t)0x1BADB002; | |
617 | if (!checksum) { | |
618 | is_multiboot = 1; | |
619 | break; | |
620 | } | |
621 | } | |
622 | } | |
623 | ||
624 | if (!is_multiboot) | |
625 | return 0; /* no multiboot */ | |
626 | ||
627 | #ifdef DEBUG_MULTIBOOT | |
628 | fprintf(stderr, "qemu: I believe we found a multiboot image!\n"); | |
629 | #endif | |
630 | memset(bootinfo, 0, sizeof(bootinfo)); | |
631 | ||
632 | if (flags & 0x00000004) { /* MULTIBOOT_HEADER_HAS_VBE */ | |
633 | fprintf(stderr, "qemu: multiboot knows VBE. we don't.\n"); | |
634 | } | |
635 | if (!(flags & 0x00010000)) { /* MULTIBOOT_HEADER_HAS_ADDR */ | |
636 | uint64_t elf_entry; | |
637 | int kernel_size; | |
638 | fclose(f); | |
639 | kernel_size = load_elf(kernel_filename, 0, &elf_entry, NULL, NULL, | |
640 | 0, ELF_MACHINE, 0); | |
641 | if (kernel_size < 0) { | |
642 | fprintf(stderr, "Error while loading elf kernel\n"); | |
643 | exit(1); | |
644 | } | |
645 | mh_load_addr = mh_entry_addr = elf_entry; | |
646 | mb_kernel_size = kernel_size; | |
647 | ||
648 | #ifdef DEBUG_MULTIBOOT | |
649 | fprintf(stderr, "qemu: loading multiboot-elf kernel (%#x bytes) with entry %#zx\n", | |
650 | mb_kernel_size, (size_t)mh_entry_addr); | |
651 | #endif | |
652 | } else { | |
653 | /* Valid if mh_flags sets MULTIBOOT_HEADER_HAS_ADDR. */ | |
654 | uint32_t mh_header_addr = ldl_p(header+i+12); | |
655 | mh_load_addr = ldl_p(header+i+16); | |
656 | #ifdef DEBUG_MULTIBOOT | |
657 | uint32_t mh_load_end_addr = ldl_p(header+i+20); | |
658 | uint32_t mh_bss_end_addr = ldl_p(header+i+24); | |
659 | #endif | |
660 | uint32_t mb_kernel_text_offset = i - (mh_header_addr - mh_load_addr); | |
661 | uint8_t *kernel; | |
662 | ||
663 | mh_entry_addr = ldl_p(header+i+28); | |
664 | mb_kernel_size = get_file_size(f) - mb_kernel_text_offset; | |
665 | ||
666 | /* Valid if mh_flags sets MULTIBOOT_HEADER_HAS_VBE. | |
667 | uint32_t mh_mode_type = ldl_p(header+i+32); | |
668 | uint32_t mh_width = ldl_p(header+i+36); | |
669 | uint32_t mh_height = ldl_p(header+i+40); | |
670 | uint32_t mh_depth = ldl_p(header+i+44); */ | |
671 | ||
672 | #ifdef DEBUG_MULTIBOOT | |
673 | fprintf(stderr, "multiboot: mh_header_addr = %#x\n", mh_header_addr); | |
674 | fprintf(stderr, "multiboot: mh_load_addr = %#x\n", mh_load_addr); | |
675 | fprintf(stderr, "multiboot: mh_load_end_addr = %#x\n", mh_load_end_addr); | |
676 | fprintf(stderr, "multiboot: mh_bss_end_addr = %#x\n", mh_bss_end_addr); | |
677 | fprintf(stderr, "qemu: loading multiboot kernel (%#x bytes) at %#x\n", | |
678 | mb_kernel_size, mh_load_addr); | |
679 | #endif | |
680 | ||
681 | kernel = qemu_malloc(mb_kernel_size); | |
682 | fseek(f, mb_kernel_text_offset, SEEK_SET); | |
683 | fread(kernel, 1, mb_kernel_size, f); | |
684 | rom_add_blob_fixed(kernel_filename, kernel, mb_kernel_size, | |
685 | mh_load_addr); | |
686 | qemu_free(kernel); | |
687 | fclose(f); | |
688 | } | |
689 | ||
690 | /* blob size is only the kernel for now */ | |
691 | mb_mod_end = mh_load_addr + mb_kernel_size; | |
692 | ||
693 | /* load modules */ | |
694 | stl_p(bootinfo + 20, 0x0); /* mods_count */ | |
695 | if (initrd_filename) { | |
696 | uint32_t mb_mod_info = 0x100; | |
697 | uint32_t mb_mod_cmdline = 0x300; | |
698 | uint32_t mb_mod_start = mh_load_addr; | |
699 | uint32_t mb_mod_length = mb_kernel_size; | |
700 | char *next_initrd; | |
701 | char *next_space; | |
702 | int mb_mod_count = 0; | |
703 | ||
704 | do { | |
705 | if (mb_mod_info + 16 > mb_mod_cmdline) { | |
706 | printf("WARNING: Too many modules loaded, aborting.\n"); | |
707 | break; | |
708 | } | |
709 | next_initrd = strchr(initrd_filename, ','); | |
710 | if (next_initrd) | |
711 | *next_initrd = '\0'; | |
712 | /* if a space comes after the module filename, treat everything | |
713 | after that as parameters */ | |
714 | pstrcpy((char*)bootinfo + mb_mod_cmdline, | |
715 | sizeof(bootinfo) - mb_mod_cmdline, | |
716 | initrd_filename); | |
717 | stl_p(bootinfo + mb_mod_info + 8, mb_bootinfo + mb_mod_cmdline); /* string */ | |
718 | mb_mod_cmdline += strlen(initrd_filename) + 1; | |
719 | if (mb_mod_cmdline > sizeof(bootinfo)) { | |
720 | mb_mod_cmdline = sizeof(bootinfo); | |
721 | printf("WARNING: Too many module cmdlines loaded, aborting.\n"); | |
722 | break; | |
723 | } | |
724 | if ((next_space = strchr(initrd_filename, ' '))) | |
725 | *next_space = '\0'; | |
726 | #ifdef DEBUG_MULTIBOOT | |
727 | printf("multiboot loading module: %s\n", initrd_filename); | |
728 | #endif | |
729 | mb_mod_start = (mb_mod_start + mb_mod_length + (TARGET_PAGE_SIZE - 1)) | |
730 | & (TARGET_PAGE_MASK); | |
731 | mb_mod_length = get_image_size(initrd_filename); | |
732 | if (mb_mod_length < 0) { | |
733 | fprintf(stderr, "failed to get %s image size\n", initrd_filename); | |
734 | exit(1); | |
735 | } | |
736 | mb_mod_end = mb_mod_start + mb_mod_length; | |
737 | rom_add_file_fixed(initrd_filename, mb_mod_start); | |
738 | ||
739 | mb_mod_count++; | |
740 | stl_p(bootinfo + mb_mod_info + 0, mb_mod_start); | |
741 | stl_p(bootinfo + mb_mod_info + 4, mb_mod_start + mb_mod_length); | |
742 | stl_p(bootinfo + mb_mod_info + 12, 0x0); /* reserved */ | |
743 | #ifdef DEBUG_MULTIBOOT | |
744 | printf("mod_start: %#x\nmod_end: %#x\n", mb_mod_start, | |
745 | mb_mod_start + mb_mod_length); | |
746 | #endif | |
747 | initrd_filename = next_initrd+1; | |
748 | mb_mod_info += 16; | |
749 | } while (next_initrd); | |
750 | stl_p(bootinfo + 20, mb_mod_count); /* mods_count */ | |
751 | stl_p(bootinfo + 24, mb_bootinfo + 0x100); /* mods_addr */ | |
752 | } | |
753 | ||
754 | /* Commandline support */ | |
755 | stl_p(bootinfo + 16, mb_bootinfo + cmdline); | |
756 | snprintf((char*)bootinfo + cmdline, 0x100, "%s %s", | |
757 | kernel_filename, kernel_cmdline); | |
758 | ||
759 | /* the kernel is where we want it to be now */ | |
760 | #define MULTIBOOT_FLAGS_MEMORY (1 << 0) | |
761 | #define MULTIBOOT_FLAGS_BOOT_DEVICE (1 << 1) | |
762 | #define MULTIBOOT_FLAGS_CMDLINE (1 << 2) | |
763 | #define MULTIBOOT_FLAGS_MODULES (1 << 3) | |
764 | #define MULTIBOOT_FLAGS_MMAP (1 << 6) | |
765 | stl_p(bootinfo, MULTIBOOT_FLAGS_MEMORY | |
766 | | MULTIBOOT_FLAGS_BOOT_DEVICE | |
767 | | MULTIBOOT_FLAGS_CMDLINE | |
768 | | MULTIBOOT_FLAGS_MODULES | |
769 | | MULTIBOOT_FLAGS_MMAP); | |
770 | stl_p(bootinfo + 4, 640); /* mem_lower */ | |
771 | stl_p(bootinfo + 8, ram_size / 1024); /* mem_upper */ | |
772 | stl_p(bootinfo + 12, 0x8001ffff); /* XXX: use the -boot switch? */ | |
773 | stl_p(bootinfo + 48, mmap_addr); /* mmap_addr */ | |
774 | ||
775 | #ifdef DEBUG_MULTIBOOT | |
776 | fprintf(stderr, "multiboot: mh_entry_addr = %#x\n", mh_entry_addr); | |
777 | #endif | |
778 | ||
779 | /* Pass variables to option rom */ | |
780 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_entry_addr); | |
781 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, mb_bootinfo); | |
782 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, mmap_addr); | |
783 | ||
784 | rom_add_blob_fixed("multiboot-info", bootinfo, sizeof(bootinfo), | |
785 | mb_bootinfo); | |
786 | ||
787 | option_rom[nb_option_roms] = "multiboot.bin"; | |
788 | nb_option_roms++; | |
789 | ||
790 | return 1; /* yes, we are multiboot */ | |
791 | } | |
792 | ||
793 | static void load_linux(void *fw_cfg, | |
794 | const char *kernel_filename, | |
795 | const char *initrd_filename, | |
796 | const char *kernel_cmdline, | |
797 | target_phys_addr_t max_ram_size) | |
798 | { | |
799 | uint16_t protocol; | |
800 | uint32_t gpr[8]; | |
801 | uint16_t seg[6]; | |
802 | uint16_t real_seg; | |
803 | int setup_size, kernel_size, initrd_size = 0, cmdline_size; | |
804 | uint32_t initrd_max; | |
805 | uint8_t header[8192], *setup, *kernel; | |
806 | target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0; | |
807 | FILE *f; | |
808 | char *vmode; | |
809 | ||
810 | /* Align to 16 bytes as a paranoia measure */ | |
811 | cmdline_size = (strlen(kernel_cmdline)+16) & ~15; | |
812 | ||
813 | /* load the kernel header */ | |
814 | f = fopen(kernel_filename, "rb"); | |
815 | if (!f || !(kernel_size = get_file_size(f)) || | |
816 | fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != | |
817 | MIN(ARRAY_SIZE(header), kernel_size)) { | |
818 | fprintf(stderr, "qemu: could not load kernel '%s': %s\n", | |
819 | kernel_filename, strerror(errno)); | |
820 | exit(1); | |
821 | } | |
822 | ||
823 | /* kernel protocol version */ | |
824 | #if 0 | |
825 | fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); | |
826 | #endif | |
827 | if (ldl_p(header+0x202) == 0x53726448) | |
828 | protocol = lduw_p(header+0x206); | |
829 | else { | |
830 | /* This looks like a multiboot kernel. If it is, let's stop | |
831 | treating it like a Linux kernel. */ | |
832 | if (load_multiboot(fw_cfg, f, kernel_filename, | |
833 | initrd_filename, kernel_cmdline, header)) | |
834 | return; | |
835 | protocol = 0; | |
836 | } | |
837 | ||
838 | if (protocol < 0x200 || !(header[0x211] & 0x01)) { | |
839 | /* Low kernel */ | |
840 | real_addr = 0x90000; | |
841 | cmdline_addr = 0x9a000 - cmdline_size; | |
842 | prot_addr = 0x10000; | |
843 | } else if (protocol < 0x202) { | |
844 | /* High but ancient kernel */ | |
845 | real_addr = 0x90000; | |
846 | cmdline_addr = 0x9a000 - cmdline_size; | |
847 | prot_addr = 0x100000; | |
848 | } else { | |
849 | /* High and recent kernel */ | |
850 | real_addr = 0x10000; | |
851 | cmdline_addr = 0x20000; | |
852 | prot_addr = 0x100000; | |
853 | } | |
854 | ||
855 | #if 0 | |
856 | fprintf(stderr, | |
857 | "qemu: real_addr = 0x" TARGET_FMT_plx "\n" | |
858 | "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" | |
859 | "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", | |
860 | real_addr, | |
861 | cmdline_addr, | |
862 | prot_addr); | |
863 | #endif | |
864 | ||
865 | /* highest address for loading the initrd */ | |
866 | if (protocol >= 0x203) | |
867 | initrd_max = ldl_p(header+0x22c); | |
868 | else | |
869 | initrd_max = 0x37ffffff; | |
870 | ||
871 | if (initrd_max >= max_ram_size-ACPI_DATA_SIZE) | |
872 | initrd_max = max_ram_size-ACPI_DATA_SIZE-1; | |
873 | ||
874 | /* kernel command line */ | |
875 | rom_add_blob_fixed("cmdline", kernel_cmdline, | |
876 | strlen(kernel_cmdline)+1, cmdline_addr); | |
877 | ||
878 | if (protocol >= 0x202) { | |
879 | stl_p(header+0x228, cmdline_addr); | |
880 | } else { | |
881 | stw_p(header+0x20, 0xA33F); | |
882 | stw_p(header+0x22, cmdline_addr-real_addr); | |
883 | } | |
884 | ||
885 | /* handle vga= parameter */ | |
886 | vmode = strstr(kernel_cmdline, "vga="); | |
887 | if (vmode) { | |
888 | unsigned int video_mode; | |
889 | /* skip "vga=" */ | |
890 | vmode += 4; | |
891 | if (!strncmp(vmode, "normal", 6)) { | |
892 | video_mode = 0xffff; | |
893 | } else if (!strncmp(vmode, "ext", 3)) { | |
894 | video_mode = 0xfffe; | |
895 | } else if (!strncmp(vmode, "ask", 3)) { | |
896 | video_mode = 0xfffd; | |
897 | } else { | |
898 | video_mode = strtol(vmode, NULL, 0); | |
899 | } | |
900 | stw_p(header+0x1fa, video_mode); | |
901 | } | |
902 | ||
903 | /* loader type */ | |
904 | /* High nybble = B reserved for Qemu; low nybble is revision number. | |
905 | If this code is substantially changed, you may want to consider | |
906 | incrementing the revision. */ | |
907 | if (protocol >= 0x200) | |
908 | header[0x210] = 0xB0; | |
909 | ||
910 | /* heap */ | |
911 | if (protocol >= 0x201) { | |
912 | header[0x211] |= 0x80; /* CAN_USE_HEAP */ | |
913 | stw_p(header+0x224, cmdline_addr-real_addr-0x200); | |
914 | } | |
915 | ||
916 | /* load initrd */ | |
917 | if (initrd_filename) { | |
918 | if (protocol < 0x200) { | |
919 | fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); | |
920 | exit(1); | |
921 | } | |
922 | ||
923 | initrd_size = get_image_size(initrd_filename); | |
924 | initrd_addr = (initrd_max-initrd_size) & ~4095; | |
925 | rom_add_file_fixed(initrd_filename, initrd_addr); | |
926 | ||
927 | stl_p(header+0x218, initrd_addr); | |
928 | stl_p(header+0x21c, initrd_size); | |
929 | } | |
930 | ||
931 | /* load kernel and setup */ | |
932 | setup_size = header[0x1f1]; | |
933 | if (setup_size == 0) | |
934 | setup_size = 4; | |
935 | setup_size = (setup_size+1)*512; | |
936 | kernel_size -= setup_size; | |
937 | ||
938 | setup = qemu_malloc(setup_size); | |
939 | kernel = qemu_malloc(kernel_size); | |
940 | fseek(f, 0, SEEK_SET); | |
941 | fread(setup, 1, setup_size, f); | |
942 | fread(kernel, 1, kernel_size, f); | |
943 | fclose(f); | |
944 | memcpy(setup, header, MIN(sizeof(header), setup_size)); | |
945 | rom_add_blob_fixed("linux-setup", setup, | |
946 | setup_size, real_addr); | |
947 | rom_add_blob_fixed(kernel_filename, kernel, | |
948 | kernel_size, prot_addr); | |
949 | qemu_free(setup); | |
950 | qemu_free(kernel); | |
951 | ||
952 | /* generate bootsector to set up the initial register state */ | |
953 | real_seg = real_addr >> 4; | |
954 | seg[0] = seg[2] = seg[3] = seg[4] = seg[4] = real_seg; | |
955 | seg[1] = real_seg+0x20; /* CS */ | |
956 | memset(gpr, 0, sizeof gpr); | |
957 | gpr[4] = cmdline_addr-real_addr-16; /* SP (-16 is paranoia) */ | |
958 | ||
959 | generate_bootsect(gpr, seg, 0); | |
960 | } | |
961 | ||
962 | static const int ide_iobase[2] = { 0x1f0, 0x170 }; | |
963 | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; | |
964 | static const int ide_irq[2] = { 14, 15 }; | |
965 | ||
966 | #define NE2000_NB_MAX 6 | |
967 | ||
968 | static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, | |
969 | 0x280, 0x380 }; | |
970 | static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
971 | ||
972 | static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; | |
973 | static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; | |
974 | ||
975 | #ifdef HAS_AUDIO | |
976 | static void audio_init (PCIBus *pci_bus, qemu_irq *pic) | |
977 | { | |
978 | struct soundhw *c; | |
979 | ||
980 | for (c = soundhw; c->name; ++c) { | |
981 | if (c->enabled) { | |
982 | if (c->isa) { | |
983 | c->init.init_isa(pic); | |
984 | } else { | |
985 | if (pci_bus) { | |
986 | c->init.init_pci(pci_bus); | |
987 | } | |
988 | } | |
989 | } | |
990 | } | |
991 | } | |
992 | #endif | |
993 | ||
994 | static void pc_init_ne2k_isa(NICInfo *nd) | |
995 | { | |
996 | static int nb_ne2k = 0; | |
997 | ||
998 | if (nb_ne2k == NE2000_NB_MAX) | |
999 | return; | |
1000 | isa_ne2000_init(ne2000_io[nb_ne2k], | |
1001 | ne2000_irq[nb_ne2k], nd); | |
1002 | nb_ne2k++; | |
1003 | } | |
1004 | ||
1005 | int cpu_is_bsp(CPUState *env) | |
1006 | { | |
1007 | return env->cpuid_apic_id == 0; | |
1008 | } | |
1009 | ||
1010 | static CPUState *pc_new_cpu(const char *cpu_model) | |
1011 | { | |
1012 | CPUState *env; | |
1013 | ||
1014 | env = cpu_init(cpu_model); | |
1015 | if (!env) { | |
1016 | fprintf(stderr, "Unable to find x86 CPU definition\n"); | |
1017 | exit(1); | |
1018 | } | |
1019 | if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) { | |
1020 | env->cpuid_apic_id = env->cpu_index; | |
1021 | /* APIC reset callback resets cpu */ | |
1022 | apic_init(env); | |
1023 | } else { | |
1024 | qemu_register_reset((QEMUResetHandler*)cpu_reset, env); | |
1025 | } | |
1026 | return env; | |
1027 | } | |
1028 | ||
1029 | /* PC hardware initialisation */ | |
1030 | static void pc_init1(ram_addr_t ram_size, | |
1031 | const char *boot_device, | |
1032 | const char *kernel_filename, | |
1033 | const char *kernel_cmdline, | |
1034 | const char *initrd_filename, | |
1035 | const char *cpu_model, | |
1036 | int pci_enabled) | |
1037 | { | |
1038 | char *filename; | |
1039 | int ret, linux_boot, i; | |
1040 | ram_addr_t ram_addr, bios_offset, option_rom_offset; | |
1041 | ram_addr_t below_4g_mem_size, above_4g_mem_size = 0; | |
1042 | int bios_size, isa_bios_size; | |
1043 | PCIBus *pci_bus; | |
1044 | ISADevice *isa_dev; | |
1045 | int piix3_devfn = -1; | |
1046 | CPUState *env; | |
1047 | qemu_irq *cpu_irq; | |
1048 | qemu_irq *isa_irq; | |
1049 | qemu_irq *i8259; | |
1050 | IsaIrqState *isa_irq_state; | |
1051 | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; | |
1052 | DriveInfo *fd[MAX_FD]; | |
1053 | int using_vga = cirrus_vga_enabled || std_vga_enabled || vmsvga_enabled; | |
1054 | void *fw_cfg; | |
1055 | ||
1056 | if (ram_size >= 0xe0000000 ) { | |
1057 | above_4g_mem_size = ram_size - 0xe0000000; | |
1058 | below_4g_mem_size = 0xe0000000; | |
1059 | } else { | |
1060 | below_4g_mem_size = ram_size; | |
1061 | } | |
1062 | ||
1063 | linux_boot = (kernel_filename != NULL); | |
1064 | ||
1065 | /* init CPUs */ | |
1066 | if (cpu_model == NULL) { | |
1067 | #ifdef TARGET_X86_64 | |
1068 | cpu_model = "qemu64"; | |
1069 | #else | |
1070 | cpu_model = "qemu32"; | |
1071 | #endif | |
1072 | } | |
1073 | ||
1074 | for (i = 0; i < smp_cpus; i++) { | |
1075 | env = pc_new_cpu(cpu_model); | |
1076 | } | |
1077 | ||
1078 | vmport_init(); | |
1079 | ||
1080 | /* allocate RAM */ | |
1081 | ram_addr = qemu_ram_alloc(0xa0000); | |
1082 | cpu_register_physical_memory(0, 0xa0000, ram_addr); | |
1083 | ||
1084 | /* Allocate, even though we won't register, so we don't break the | |
1085 | * phys_ram_base + PA assumption. This range includes vga (0xa0000 - 0xc0000), | |
1086 | * and some bios areas, which will be registered later | |
1087 | */ | |
1088 | ram_addr = qemu_ram_alloc(0x100000 - 0xa0000); | |
1089 | ram_addr = qemu_ram_alloc(below_4g_mem_size - 0x100000); | |
1090 | cpu_register_physical_memory(0x100000, | |
1091 | below_4g_mem_size - 0x100000, | |
1092 | ram_addr); | |
1093 | ||
1094 | /* above 4giga memory allocation */ | |
1095 | if (above_4g_mem_size > 0) { | |
1096 | #if TARGET_PHYS_ADDR_BITS == 32 | |
1097 | hw_error("To much RAM for 32-bit physical address"); | |
1098 | #else | |
1099 | ram_addr = qemu_ram_alloc(above_4g_mem_size); | |
1100 | cpu_register_physical_memory(0x100000000ULL, | |
1101 | above_4g_mem_size, | |
1102 | ram_addr); | |
1103 | #endif | |
1104 | } | |
1105 | ||
1106 | ||
1107 | /* BIOS load */ | |
1108 | if (bios_name == NULL) | |
1109 | bios_name = BIOS_FILENAME; | |
1110 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
1111 | if (filename) { | |
1112 | bios_size = get_image_size(filename); | |
1113 | } else { | |
1114 | bios_size = -1; | |
1115 | } | |
1116 | if (bios_size <= 0 || | |
1117 | (bios_size % 65536) != 0) { | |
1118 | goto bios_error; | |
1119 | } | |
1120 | bios_offset = qemu_ram_alloc(bios_size); | |
1121 | ret = load_image(filename, qemu_get_ram_ptr(bios_offset)); | |
1122 | if (ret != bios_size) { | |
1123 | bios_error: | |
1124 | fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name); | |
1125 | exit(1); | |
1126 | } | |
1127 | if (filename) { | |
1128 | qemu_free(filename); | |
1129 | } | |
1130 | /* map the last 128KB of the BIOS in ISA space */ | |
1131 | isa_bios_size = bios_size; | |
1132 | if (isa_bios_size > (128 * 1024)) | |
1133 | isa_bios_size = 128 * 1024; | |
1134 | cpu_register_physical_memory(0x100000 - isa_bios_size, | |
1135 | isa_bios_size, | |
1136 | (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM); | |
1137 | ||
1138 | ||
1139 | ||
1140 | option_rom_offset = qemu_ram_alloc(PC_ROM_SIZE); | |
1141 | cpu_register_physical_memory(PC_ROM_MIN_VGA, PC_ROM_SIZE, option_rom_offset); | |
1142 | ||
1143 | if (using_vga) { | |
1144 | /* VGA BIOS load */ | |
1145 | if (cirrus_vga_enabled) { | |
1146 | rom_add_vga(VGABIOS_CIRRUS_FILENAME); | |
1147 | } else { | |
1148 | rom_add_vga(VGABIOS_FILENAME); | |
1149 | } | |
1150 | } | |
1151 | ||
1152 | /* map all the bios at the top of memory */ | |
1153 | cpu_register_physical_memory((uint32_t)(-bios_size), | |
1154 | bios_size, bios_offset | IO_MEM_ROM); | |
1155 | ||
1156 | fw_cfg = bochs_bios_init(); | |
1157 | ||
1158 | if (linux_boot) { | |
1159 | load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size); | |
1160 | } | |
1161 | ||
1162 | for (i = 0; i < nb_option_roms; i++) { | |
1163 | rom_add_option(option_rom[i]); | |
1164 | } | |
1165 | ||
1166 | for (i = 0; i < nb_nics; i++) { | |
1167 | char nic_oprom[1024]; | |
1168 | const char *model = nd_table[i].model; | |
1169 | ||
1170 | if (!nd_table[i].bootable) | |
1171 | continue; | |
1172 | ||
1173 | if (model == NULL) | |
1174 | model = "e1000"; | |
1175 | snprintf(nic_oprom, sizeof(nic_oprom), "pxe-%s.bin", model); | |
1176 | ||
1177 | rom_add_option(nic_oprom); | |
1178 | } | |
1179 | ||
1180 | cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1); | |
1181 | i8259 = i8259_init(cpu_irq[0]); | |
1182 | isa_irq_state = qemu_mallocz(sizeof(*isa_irq_state)); | |
1183 | isa_irq_state->i8259 = i8259; | |
1184 | isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24); | |
1185 | ||
1186 | if (pci_enabled) { | |
1187 | pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, isa_irq); | |
1188 | } else { | |
1189 | pci_bus = NULL; | |
1190 | isa_bus_new(NULL); | |
1191 | } | |
1192 | isa_bus_irqs(isa_irq); | |
1193 | ||
1194 | ferr_irq = isa_reserve_irq(13); | |
1195 | ||
1196 | /* init basic PC hardware */ | |
1197 | register_ioport_write(0x80, 1, 1, ioport80_write, NULL); | |
1198 | ||
1199 | register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL); | |
1200 | ||
1201 | if (cirrus_vga_enabled) { | |
1202 | if (pci_enabled) { | |
1203 | pci_cirrus_vga_init(pci_bus); | |
1204 | } else { | |
1205 | isa_cirrus_vga_init(); | |
1206 | } | |
1207 | } else if (vmsvga_enabled) { | |
1208 | if (pci_enabled) | |
1209 | pci_vmsvga_init(pci_bus); | |
1210 | else | |
1211 | fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__); | |
1212 | } else if (std_vga_enabled) { | |
1213 | if (pci_enabled) { | |
1214 | pci_vga_init(pci_bus, 0, 0); | |
1215 | } else { | |
1216 | isa_vga_init(); | |
1217 | } | |
1218 | } | |
1219 | ||
1220 | rtc_state = rtc_init(2000); | |
1221 | ||
1222 | qemu_register_boot_set(pc_boot_set, rtc_state); | |
1223 | ||
1224 | register_ioport_read(0x92, 1, 1, ioport92_read, NULL); | |
1225 | register_ioport_write(0x92, 1, 1, ioport92_write, NULL); | |
1226 | ||
1227 | if (pci_enabled) { | |
1228 | isa_irq_state->ioapic = ioapic_init(); | |
1229 | } | |
1230 | pit = pit_init(0x40, isa_reserve_irq(0)); | |
1231 | pcspk_init(pit); | |
1232 | if (!no_hpet) { | |
1233 | hpet_init(isa_irq); | |
1234 | } | |
1235 | ||
1236 | for(i = 0; i < MAX_SERIAL_PORTS; i++) { | |
1237 | if (serial_hds[i]) { | |
1238 | serial_isa_init(i, serial_hds[i]); | |
1239 | } | |
1240 | } | |
1241 | ||
1242 | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { | |
1243 | if (parallel_hds[i]) { | |
1244 | parallel_init(i, parallel_hds[i]); | |
1245 | } | |
1246 | } | |
1247 | ||
1248 | for(i = 0; i < nb_nics; i++) { | |
1249 | NICInfo *nd = &nd_table[i]; | |
1250 | ||
1251 | if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) | |
1252 | pc_init_ne2k_isa(nd); | |
1253 | else | |
1254 | pci_nic_init_nofail(nd, "e1000", NULL); | |
1255 | } | |
1256 | ||
1257 | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { | |
1258 | fprintf(stderr, "qemu: too many IDE bus\n"); | |
1259 | exit(1); | |
1260 | } | |
1261 | ||
1262 | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { | |
1263 | hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); | |
1264 | } | |
1265 | ||
1266 | if (pci_enabled) { | |
1267 | pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1); | |
1268 | } else { | |
1269 | for(i = 0; i < MAX_IDE_BUS; i++) { | |
1270 | isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i], | |
1271 | hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]); | |
1272 | } | |
1273 | } | |
1274 | ||
1275 | isa_dev = isa_create_simple("i8042"); | |
1276 | DMA_init(0); | |
1277 | #ifdef HAS_AUDIO | |
1278 | audio_init(pci_enabled ? pci_bus : NULL, isa_irq); | |
1279 | #endif | |
1280 | ||
1281 | for(i = 0; i < MAX_FD; i++) { | |
1282 | fd[i] = drive_get(IF_FLOPPY, 0, i); | |
1283 | } | |
1284 | floppy_controller = fdctrl_init_isa(fd); | |
1285 | ||
1286 | cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd); | |
1287 | ||
1288 | if (pci_enabled && usb_enabled) { | |
1289 | usb_uhci_piix3_init(pci_bus, piix3_devfn + 2); | |
1290 | } | |
1291 | ||
1292 | if (pci_enabled && acpi_enabled) { | |
1293 | uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */ | |
1294 | i2c_bus *smbus; | |
1295 | ||
1296 | /* TODO: Populate SPD eeprom data. */ | |
1297 | smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, | |
1298 | isa_reserve_irq(9)); | |
1299 | for (i = 0; i < 8; i++) { | |
1300 | DeviceState *eeprom; | |
1301 | eeprom = qdev_create((BusState *)smbus, "smbus-eeprom"); | |
1302 | qdev_prop_set_uint8(eeprom, "address", 0x50 + i); | |
1303 | qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256)); | |
1304 | qdev_init_nofail(eeprom); | |
1305 | } | |
1306 | piix4_acpi_system_hot_add_init(pci_bus); | |
1307 | } | |
1308 | ||
1309 | if (i440fx_state) { | |
1310 | i440fx_init_memory_mappings(i440fx_state); | |
1311 | } | |
1312 | ||
1313 | if (pci_enabled) { | |
1314 | int max_bus; | |
1315 | int bus; | |
1316 | ||
1317 | max_bus = drive_get_max_bus(IF_SCSI); | |
1318 | for (bus = 0; bus <= max_bus; bus++) { | |
1319 | pci_create_simple(pci_bus, -1, "lsi53c895a"); | |
1320 | } | |
1321 | } | |
1322 | ||
1323 | /* Add virtio console devices */ | |
1324 | if (pci_enabled) { | |
1325 | for(i = 0; i < MAX_VIRTIO_CONSOLES; i++) { | |
1326 | if (virtcon_hds[i]) { | |
1327 | pci_create_simple(pci_bus, -1, "virtio-console-pci"); | |
1328 | } | |
1329 | } | |
1330 | } | |
1331 | } | |
1332 | ||
1333 | static void pc_init_pci(ram_addr_t ram_size, | |
1334 | const char *boot_device, | |
1335 | const char *kernel_filename, | |
1336 | const char *kernel_cmdline, | |
1337 | const char *initrd_filename, | |
1338 | const char *cpu_model) | |
1339 | { | |
1340 | pc_init1(ram_size, boot_device, | |
1341 | kernel_filename, kernel_cmdline, | |
1342 | initrd_filename, cpu_model, 1); | |
1343 | } | |
1344 | ||
1345 | static void pc_init_isa(ram_addr_t ram_size, | |
1346 | const char *boot_device, | |
1347 | const char *kernel_filename, | |
1348 | const char *kernel_cmdline, | |
1349 | const char *initrd_filename, | |
1350 | const char *cpu_model) | |
1351 | { | |
1352 | if (cpu_model == NULL) | |
1353 | cpu_model = "486"; | |
1354 | pc_init1(ram_size, boot_device, | |
1355 | kernel_filename, kernel_cmdline, | |
1356 | initrd_filename, cpu_model, 0); | |
1357 | } | |
1358 | ||
1359 | /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE) | |
1360 | BIOS will read it and start S3 resume at POST Entry */ | |
1361 | void cmos_set_s3_resume(void) | |
1362 | { | |
1363 | if (rtc_state) | |
1364 | rtc_set_memory(rtc_state, 0xF, 0xFE); | |
1365 | } | |
1366 | ||
1367 | static QEMUMachine pc_machine = { | |
1368 | .name = "pc-0.11", | |
1369 | .alias = "pc", | |
1370 | .desc = "Standard PC", | |
1371 | .init = pc_init_pci, | |
1372 | .max_cpus = 255, | |
1373 | .is_default = 1, | |
1374 | }; | |
1375 | ||
1376 | static QEMUMachine pc_machine_v0_10 = { | |
1377 | .name = "pc-0.10", | |
1378 | .desc = "Standard PC, qemu 0.10", | |
1379 | .init = pc_init_pci, | |
1380 | .max_cpus = 255, | |
1381 | .compat_props = (CompatProperty[]) { | |
1382 | { | |
1383 | .driver = "virtio-blk-pci", | |
1384 | .property = "class", | |
1385 | .value = stringify(PCI_CLASS_STORAGE_OTHER), | |
1386 | },{ | |
1387 | .driver = "virtio-console-pci", | |
1388 | .property = "class", | |
1389 | .value = stringify(PCI_CLASS_DISPLAY_OTHER), | |
1390 | },{ | |
1391 | .driver = "virtio-net-pci", | |
1392 | .property = "vectors", | |
1393 | .value = stringify(0), | |
1394 | },{ | |
1395 | .driver = "virtio-blk-pci", | |
1396 | .property = "vectors", | |
1397 | .value = stringify(0), | |
1398 | }, | |
1399 | { /* end of list */ } | |
1400 | }, | |
1401 | }; | |
1402 | ||
1403 | static QEMUMachine isapc_machine = { | |
1404 | .name = "isapc", | |
1405 | .desc = "ISA-only PC", | |
1406 | .init = pc_init_isa, | |
1407 | .max_cpus = 1, | |
1408 | }; | |
1409 | ||
1410 | static void pc_machine_init(void) | |
1411 | { | |
1412 | qemu_register_machine(&pc_machine); | |
1413 | qemu_register_machine(&pc_machine_v0_10); | |
1414 | qemu_register_machine(&isapc_machine); | |
1415 | } | |
1416 | ||
1417 | machine_init(pc_machine_init); |