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1 | /* | |
2 | * QEMU PowerPC E500 embedded processors pci controller emulation | |
3 | * | |
4 | * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. | |
5 | * | |
6 | * Author: Yu Liu, <yu.liu@freescale.com> | |
7 | * | |
8 | * This file is derived from hw/ppc4xx_pci.c, | |
9 | * the copyright for that material belongs to the original owners. | |
10 | * | |
11 | * This is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | */ | |
16 | ||
17 | #include "hw.h" | |
18 | #include "pci.h" | |
19 | #include "pci_host.h" | |
20 | #include "bswap.h" | |
21 | ||
22 | #ifdef DEBUG_PCI | |
23 | #define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__) | |
24 | #else | |
25 | #define pci_debug(fmt, ...) | |
26 | #endif | |
27 | ||
28 | #define PCIE500_CFGADDR 0x0 | |
29 | #define PCIE500_CFGDATA 0x4 | |
30 | #define PCIE500_REG_BASE 0xC00 | |
31 | #define PCIE500_ALL_SIZE 0x1000 | |
32 | #define PCIE500_REG_SIZE (PCIE500_ALL_SIZE - PCIE500_REG_BASE) | |
33 | ||
34 | #define PPCE500_PCI_CONFIG_ADDR 0x0 | |
35 | #define PPCE500_PCI_CONFIG_DATA 0x4 | |
36 | #define PPCE500_PCI_INTACK 0x8 | |
37 | ||
38 | #define PPCE500_PCI_OW1 (0xC20 - PCIE500_REG_BASE) | |
39 | #define PPCE500_PCI_OW2 (0xC40 - PCIE500_REG_BASE) | |
40 | #define PPCE500_PCI_OW3 (0xC60 - PCIE500_REG_BASE) | |
41 | #define PPCE500_PCI_OW4 (0xC80 - PCIE500_REG_BASE) | |
42 | #define PPCE500_PCI_IW3 (0xDA0 - PCIE500_REG_BASE) | |
43 | #define PPCE500_PCI_IW2 (0xDC0 - PCIE500_REG_BASE) | |
44 | #define PPCE500_PCI_IW1 (0xDE0 - PCIE500_REG_BASE) | |
45 | ||
46 | #define PPCE500_PCI_GASKET_TIMR (0xE20 - PCIE500_REG_BASE) | |
47 | ||
48 | #define PCI_POTAR 0x0 | |
49 | #define PCI_POTEAR 0x4 | |
50 | #define PCI_POWBAR 0x8 | |
51 | #define PCI_POWAR 0x10 | |
52 | ||
53 | #define PCI_PITAR 0x0 | |
54 | #define PCI_PIWBAR 0x8 | |
55 | #define PCI_PIWBEAR 0xC | |
56 | #define PCI_PIWAR 0x10 | |
57 | ||
58 | #define PPCE500_PCI_NR_POBS 5 | |
59 | #define PPCE500_PCI_NR_PIBS 3 | |
60 | ||
61 | struct pci_outbound { | |
62 | uint32_t potar; | |
63 | uint32_t potear; | |
64 | uint32_t powbar; | |
65 | uint32_t powar; | |
66 | }; | |
67 | ||
68 | struct pci_inbound { | |
69 | uint32_t pitar; | |
70 | uint32_t piwbar; | |
71 | uint32_t piwbear; | |
72 | uint32_t piwar; | |
73 | }; | |
74 | ||
75 | struct PPCE500PCIState { | |
76 | PCIHostState pci_state; | |
77 | struct pci_outbound pob[PPCE500_PCI_NR_POBS]; | |
78 | struct pci_inbound pib[PPCE500_PCI_NR_PIBS]; | |
79 | uint32_t gasket_time; | |
80 | qemu_irq irq[4]; | |
81 | /* mmio maps */ | |
82 | int reg; | |
83 | }; | |
84 | ||
85 | typedef struct PPCE500PCIState PPCE500PCIState; | |
86 | ||
87 | static uint32_t pci_reg_read4(void *opaque, target_phys_addr_t addr) | |
88 | { | |
89 | PPCE500PCIState *pci = opaque; | |
90 | unsigned long win; | |
91 | uint32_t value = 0; | |
92 | ||
93 | win = addr & 0xfe0; | |
94 | ||
95 | switch (win) { | |
96 | case PPCE500_PCI_OW1: | |
97 | case PPCE500_PCI_OW2: | |
98 | case PPCE500_PCI_OW3: | |
99 | case PPCE500_PCI_OW4: | |
100 | switch (addr & 0xC) { | |
101 | case PCI_POTAR: | |
102 | value = pci->pob[(addr >> 5) & 0x7].potar; | |
103 | break; | |
104 | case PCI_POTEAR: | |
105 | value = pci->pob[(addr >> 5) & 0x7].potear; | |
106 | break; | |
107 | case PCI_POWBAR: | |
108 | value = pci->pob[(addr >> 5) & 0x7].powbar; | |
109 | break; | |
110 | case PCI_POWAR: | |
111 | value = pci->pob[(addr >> 5) & 0x7].powar; | |
112 | break; | |
113 | default: | |
114 | break; | |
115 | } | |
116 | break; | |
117 | ||
118 | case PPCE500_PCI_IW3: | |
119 | case PPCE500_PCI_IW2: | |
120 | case PPCE500_PCI_IW1: | |
121 | switch (addr & 0xC) { | |
122 | case PCI_PITAR: | |
123 | value = pci->pib[(addr >> 5) & 0x3].pitar; | |
124 | break; | |
125 | case PCI_PIWBAR: | |
126 | value = pci->pib[(addr >> 5) & 0x3].piwbar; | |
127 | break; | |
128 | case PCI_PIWBEAR: | |
129 | value = pci->pib[(addr >> 5) & 0x3].piwbear; | |
130 | break; | |
131 | case PCI_PIWAR: | |
132 | value = pci->pib[(addr >> 5) & 0x3].piwar; | |
133 | break; | |
134 | default: | |
135 | break; | |
136 | }; | |
137 | break; | |
138 | ||
139 | case PPCE500_PCI_GASKET_TIMR: | |
140 | value = pci->gasket_time; | |
141 | break; | |
142 | ||
143 | default: | |
144 | break; | |
145 | } | |
146 | ||
147 | pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__, | |
148 | win, addr, value); | |
149 | return value; | |
150 | } | |
151 | ||
152 | static CPUReadMemoryFunc * const e500_pci_reg_read[] = { | |
153 | &pci_reg_read4, | |
154 | &pci_reg_read4, | |
155 | &pci_reg_read4, | |
156 | }; | |
157 | ||
158 | static void pci_reg_write4(void *opaque, target_phys_addr_t addr, | |
159 | uint32_t value) | |
160 | { | |
161 | PPCE500PCIState *pci = opaque; | |
162 | unsigned long win; | |
163 | ||
164 | win = addr & 0xfe0; | |
165 | ||
166 | pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n", | |
167 | __func__, value, win, addr); | |
168 | ||
169 | switch (win) { | |
170 | case PPCE500_PCI_OW1: | |
171 | case PPCE500_PCI_OW2: | |
172 | case PPCE500_PCI_OW3: | |
173 | case PPCE500_PCI_OW4: | |
174 | switch (addr & 0xC) { | |
175 | case PCI_POTAR: | |
176 | pci->pob[(addr >> 5) & 0x7].potar = value; | |
177 | break; | |
178 | case PCI_POTEAR: | |
179 | pci->pob[(addr >> 5) & 0x7].potear = value; | |
180 | break; | |
181 | case PCI_POWBAR: | |
182 | pci->pob[(addr >> 5) & 0x7].powbar = value; | |
183 | break; | |
184 | case PCI_POWAR: | |
185 | pci->pob[(addr >> 5) & 0x7].powar = value; | |
186 | break; | |
187 | default: | |
188 | break; | |
189 | }; | |
190 | break; | |
191 | ||
192 | case PPCE500_PCI_IW3: | |
193 | case PPCE500_PCI_IW2: | |
194 | case PPCE500_PCI_IW1: | |
195 | switch (addr & 0xC) { | |
196 | case PCI_PITAR: | |
197 | pci->pib[(addr >> 5) & 0x3].pitar = value; | |
198 | break; | |
199 | case PCI_PIWBAR: | |
200 | pci->pib[(addr >> 5) & 0x3].piwbar = value; | |
201 | break; | |
202 | case PCI_PIWBEAR: | |
203 | pci->pib[(addr >> 5) & 0x3].piwbear = value; | |
204 | break; | |
205 | case PCI_PIWAR: | |
206 | pci->pib[(addr >> 5) & 0x3].piwar = value; | |
207 | break; | |
208 | default: | |
209 | break; | |
210 | }; | |
211 | break; | |
212 | ||
213 | case PPCE500_PCI_GASKET_TIMR: | |
214 | pci->gasket_time = value; | |
215 | break; | |
216 | ||
217 | default: | |
218 | break; | |
219 | }; | |
220 | } | |
221 | ||
222 | static CPUWriteMemoryFunc * const e500_pci_reg_write[] = { | |
223 | &pci_reg_write4, | |
224 | &pci_reg_write4, | |
225 | &pci_reg_write4, | |
226 | }; | |
227 | ||
228 | static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num) | |
229 | { | |
230 | int devno = pci_dev->devfn >> 3, ret = 0; | |
231 | ||
232 | switch (devno) { | |
233 | /* Two PCI slot */ | |
234 | case 0x11: | |
235 | case 0x12: | |
236 | ret = (irq_num + devno - 0x10) % 4; | |
237 | break; | |
238 | default: | |
239 | printf("Error:%s:unknown dev number\n", __func__); | |
240 | } | |
241 | ||
242 | pci_debug("%s: devfn %x irq %d -> %d devno:%x\n", __func__, | |
243 | pci_dev->devfn, irq_num, ret, devno); | |
244 | ||
245 | return ret; | |
246 | } | |
247 | ||
248 | static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level) | |
249 | { | |
250 | qemu_irq *pic = opaque; | |
251 | ||
252 | pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level); | |
253 | ||
254 | qemu_set_irq(pic[irq_num], level); | |
255 | } | |
256 | ||
257 | static const VMStateDescription vmstate_pci_outbound = { | |
258 | .name = "pci_outbound", | |
259 | .version_id = 0, | |
260 | .minimum_version_id = 0, | |
261 | .minimum_version_id_old = 0, | |
262 | .fields = (VMStateField[]) { | |
263 | VMSTATE_UINT32(potar, struct pci_outbound), | |
264 | VMSTATE_UINT32(potear, struct pci_outbound), | |
265 | VMSTATE_UINT32(powbar, struct pci_outbound), | |
266 | VMSTATE_UINT32(powar, struct pci_outbound), | |
267 | VMSTATE_END_OF_LIST() | |
268 | } | |
269 | }; | |
270 | ||
271 | static const VMStateDescription vmstate_pci_inbound = { | |
272 | .name = "pci_inbound", | |
273 | .version_id = 0, | |
274 | .minimum_version_id = 0, | |
275 | .minimum_version_id_old = 0, | |
276 | .fields = (VMStateField[]) { | |
277 | VMSTATE_UINT32(pitar, struct pci_inbound), | |
278 | VMSTATE_UINT32(piwbar, struct pci_inbound), | |
279 | VMSTATE_UINT32(piwbear, struct pci_inbound), | |
280 | VMSTATE_UINT32(piwar, struct pci_inbound), | |
281 | VMSTATE_END_OF_LIST() | |
282 | } | |
283 | }; | |
284 | ||
285 | static const VMStateDescription vmstate_ppce500_pci = { | |
286 | .name = "ppce500_pci", | |
287 | .version_id = 1, | |
288 | .minimum_version_id = 1, | |
289 | .minimum_version_id_old = 1, | |
290 | .fields = (VMStateField[]) { | |
291 | VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1, | |
292 | vmstate_pci_outbound, struct pci_outbound), | |
293 | VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1, | |
294 | vmstate_pci_outbound, struct pci_inbound), | |
295 | VMSTATE_UINT32(gasket_time, PPCE500PCIState), | |
296 | VMSTATE_END_OF_LIST() | |
297 | } | |
298 | }; | |
299 | ||
300 | static void e500_pci_map(SysBusDevice *dev, target_phys_addr_t base) | |
301 | { | |
302 | PCIHostState *h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev)); | |
303 | PPCE500PCIState *s = DO_UPCAST(PPCE500PCIState, pci_state, h); | |
304 | ||
305 | sysbus_add_memory(dev, base + PCIE500_CFGADDR, &h->conf_mem); | |
306 | sysbus_add_memory(dev, base + PCIE500_CFGDATA, &h->data_mem); | |
307 | cpu_register_physical_memory(base + PCIE500_REG_BASE, PCIE500_REG_SIZE, | |
308 | s->reg); | |
309 | } | |
310 | ||
311 | static void e500_pci_unmap(SysBusDevice *dev, target_phys_addr_t base) | |
312 | { | |
313 | PCIHostState *h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev)); | |
314 | ||
315 | sysbus_del_memory(dev, &h->conf_mem); | |
316 | sysbus_del_memory(dev, &h->data_mem); | |
317 | cpu_register_physical_memory(base + PCIE500_REG_BASE, PCIE500_REG_SIZE, | |
318 | IO_MEM_UNASSIGNED); | |
319 | } | |
320 | ||
321 | #include "exec-memory.h" | |
322 | ||
323 | static int e500_pcihost_initfn(SysBusDevice *dev) | |
324 | { | |
325 | PCIHostState *h; | |
326 | PPCE500PCIState *s; | |
327 | PCIBus *b; | |
328 | int i; | |
329 | MemoryRegion *address_space_mem = get_system_memory(); | |
330 | MemoryRegion *address_space_io = get_system_io(); | |
331 | ||
332 | h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev)); | |
333 | s = DO_UPCAST(PPCE500PCIState, pci_state, h); | |
334 | ||
335 | for (i = 0; i < ARRAY_SIZE(s->irq); i++) { | |
336 | sysbus_init_irq(dev, &s->irq[i]); | |
337 | } | |
338 | ||
339 | b = pci_register_bus(&s->pci_state.busdev.qdev, NULL, mpc85xx_pci_set_irq, | |
340 | mpc85xx_pci_map_irq, s->irq, address_space_mem, | |
341 | address_space_io, PCI_DEVFN(0x11, 0), 4); | |
342 | s->pci_state.bus = b; | |
343 | ||
344 | pci_create_simple(b, 0, "e500-host-bridge"); | |
345 | ||
346 | memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, h, | |
347 | "pci-conf-idx", 4); | |
348 | memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h, | |
349 | "pci-conf-data", 4); | |
350 | s->reg = cpu_register_io_memory(e500_pci_reg_read, e500_pci_reg_write, s, | |
351 | DEVICE_BIG_ENDIAN); | |
352 | sysbus_init_mmio_cb2(dev, e500_pci_map, e500_pci_unmap); | |
353 | ||
354 | return 0; | |
355 | } | |
356 | ||
357 | static PCIDeviceInfo e500_host_bridge_info = { | |
358 | .qdev.name = "e500-host-bridge", | |
359 | .qdev.desc = "Host bridge", | |
360 | .qdev.size = sizeof(PCIDevice), | |
361 | .vendor_id = PCI_VENDOR_ID_FREESCALE, | |
362 | .device_id = PCI_DEVICE_ID_MPC8533E, | |
363 | .class_id = PCI_CLASS_PROCESSOR_POWERPC, | |
364 | }; | |
365 | ||
366 | static SysBusDeviceInfo e500_pcihost_info = { | |
367 | .init = e500_pcihost_initfn, | |
368 | .qdev.name = "e500-pcihost", | |
369 | .qdev.size = sizeof(PPCE500PCIState), | |
370 | .qdev.vmsd = &vmstate_ppce500_pci, | |
371 | }; | |
372 | ||
373 | static void e500_pci_register(void) | |
374 | { | |
375 | sysbus_register_withprop(&e500_pcihost_info); | |
376 | pci_qdev_register(&e500_host_bridge_info); | |
377 | } | |
378 | device_init(e500_pci_register); |