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1 | /* | |
2 | * QEMU ARM CPU -- internal functions and types | |
3 | * | |
4 | * Copyright (c) 2014 Linaro Ltd | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | * | |
20 | * This header defines functions, types, etc which need to be shared | |
21 | * between different source files within target/arm/ but which are | |
22 | * private to it and not required by the rest of QEMU. | |
23 | */ | |
24 | ||
25 | #ifndef TARGET_ARM_INTERNALS_H | |
26 | #define TARGET_ARM_INTERNALS_H | |
27 | ||
28 | #include "hw/registerfields.h" | |
29 | ||
30 | /* register banks for CPU modes */ | |
31 | #define BANK_USRSYS 0 | |
32 | #define BANK_SVC 1 | |
33 | #define BANK_ABT 2 | |
34 | #define BANK_UND 3 | |
35 | #define BANK_IRQ 4 | |
36 | #define BANK_FIQ 5 | |
37 | #define BANK_HYP 6 | |
38 | #define BANK_MON 7 | |
39 | ||
40 | static inline bool excp_is_internal(int excp) | |
41 | { | |
42 | /* Return true if this exception number represents a QEMU-internal | |
43 | * exception that will not be passed to the guest. | |
44 | */ | |
45 | return excp == EXCP_INTERRUPT | |
46 | || excp == EXCP_HLT | |
47 | || excp == EXCP_DEBUG | |
48 | || excp == EXCP_HALTED | |
49 | || excp == EXCP_EXCEPTION_EXIT | |
50 | || excp == EXCP_KERNEL_TRAP | |
51 | || excp == EXCP_SEMIHOST; | |
52 | } | |
53 | ||
54 | /* Scale factor for generic timers, ie number of ns per tick. | |
55 | * This gives a 62.5MHz timer. | |
56 | */ | |
57 | #define GTIMER_SCALE 16 | |
58 | ||
59 | /* Bit definitions for the v7M CONTROL register */ | |
60 | FIELD(V7M_CONTROL, NPRIV, 0, 1) | |
61 | FIELD(V7M_CONTROL, SPSEL, 1, 1) | |
62 | FIELD(V7M_CONTROL, FPCA, 2, 1) | |
63 | ||
64 | /* Bit definitions for v7M exception return payload */ | |
65 | FIELD(V7M_EXCRET, ES, 0, 1) | |
66 | FIELD(V7M_EXCRET, RES0, 1, 1) | |
67 | FIELD(V7M_EXCRET, SPSEL, 2, 1) | |
68 | FIELD(V7M_EXCRET, MODE, 3, 1) | |
69 | FIELD(V7M_EXCRET, FTYPE, 4, 1) | |
70 | FIELD(V7M_EXCRET, DCRS, 5, 1) | |
71 | FIELD(V7M_EXCRET, S, 6, 1) | |
72 | FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */ | |
73 | ||
74 | /* | |
75 | * For AArch64, map a given EL to an index in the banked_spsr array. | |
76 | * Note that this mapping and the AArch32 mapping defined in bank_number() | |
77 | * must agree such that the AArch64<->AArch32 SPSRs have the architecturally | |
78 | * mandated mapping between each other. | |
79 | */ | |
80 | static inline unsigned int aarch64_banked_spsr_index(unsigned int el) | |
81 | { | |
82 | static const unsigned int map[4] = { | |
83 | [1] = BANK_SVC, /* EL1. */ | |
84 | [2] = BANK_HYP, /* EL2. */ | |
85 | [3] = BANK_MON, /* EL3. */ | |
86 | }; | |
87 | assert(el >= 1 && el <= 3); | |
88 | return map[el]; | |
89 | } | |
90 | ||
91 | /* Map CPU modes onto saved register banks. */ | |
92 | static inline int bank_number(int mode) | |
93 | { | |
94 | switch (mode) { | |
95 | case ARM_CPU_MODE_USR: | |
96 | case ARM_CPU_MODE_SYS: | |
97 | return BANK_USRSYS; | |
98 | case ARM_CPU_MODE_SVC: | |
99 | return BANK_SVC; | |
100 | case ARM_CPU_MODE_ABT: | |
101 | return BANK_ABT; | |
102 | case ARM_CPU_MODE_UND: | |
103 | return BANK_UND; | |
104 | case ARM_CPU_MODE_IRQ: | |
105 | return BANK_IRQ; | |
106 | case ARM_CPU_MODE_FIQ: | |
107 | return BANK_FIQ; | |
108 | case ARM_CPU_MODE_HYP: | |
109 | return BANK_HYP; | |
110 | case ARM_CPU_MODE_MON: | |
111 | return BANK_MON; | |
112 | } | |
113 | g_assert_not_reached(); | |
114 | } | |
115 | ||
116 | void switch_mode(CPUARMState *, int); | |
117 | void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); | |
118 | void arm_translate_init(void); | |
119 | ||
120 | enum arm_fprounding { | |
121 | FPROUNDING_TIEEVEN, | |
122 | FPROUNDING_POSINF, | |
123 | FPROUNDING_NEGINF, | |
124 | FPROUNDING_ZERO, | |
125 | FPROUNDING_TIEAWAY, | |
126 | FPROUNDING_ODD | |
127 | }; | |
128 | ||
129 | int arm_rmode_to_sf(int rmode); | |
130 | ||
131 | static inline void aarch64_save_sp(CPUARMState *env, int el) | |
132 | { | |
133 | if (env->pstate & PSTATE_SP) { | |
134 | env->sp_el[el] = env->xregs[31]; | |
135 | } else { | |
136 | env->sp_el[0] = env->xregs[31]; | |
137 | } | |
138 | } | |
139 | ||
140 | static inline void aarch64_restore_sp(CPUARMState *env, int el) | |
141 | { | |
142 | if (env->pstate & PSTATE_SP) { | |
143 | env->xregs[31] = env->sp_el[el]; | |
144 | } else { | |
145 | env->xregs[31] = env->sp_el[0]; | |
146 | } | |
147 | } | |
148 | ||
149 | static inline void update_spsel(CPUARMState *env, uint32_t imm) | |
150 | { | |
151 | unsigned int cur_el = arm_current_el(env); | |
152 | /* Update PSTATE SPSel bit; this requires us to update the | |
153 | * working stack pointer in xregs[31]. | |
154 | */ | |
155 | if (!((imm ^ env->pstate) & PSTATE_SP)) { | |
156 | return; | |
157 | } | |
158 | aarch64_save_sp(env, cur_el); | |
159 | env->pstate = deposit32(env->pstate, 0, 1, imm); | |
160 | ||
161 | /* We rely on illegal updates to SPsel from EL0 to get trapped | |
162 | * at translation time. | |
163 | */ | |
164 | assert(cur_el >= 1 && cur_el <= 3); | |
165 | aarch64_restore_sp(env, cur_el); | |
166 | } | |
167 | ||
168 | /* | |
169 | * arm_pamax | |
170 | * @cpu: ARMCPU | |
171 | * | |
172 | * Returns the implementation defined bit-width of physical addresses. | |
173 | * The ARMv8 reference manuals refer to this as PAMax(). | |
174 | */ | |
175 | static inline unsigned int arm_pamax(ARMCPU *cpu) | |
176 | { | |
177 | static const unsigned int pamax_map[] = { | |
178 | [0] = 32, | |
179 | [1] = 36, | |
180 | [2] = 40, | |
181 | [3] = 42, | |
182 | [4] = 44, | |
183 | [5] = 48, | |
184 | }; | |
185 | unsigned int parange = extract32(cpu->id_aa64mmfr0, 0, 4); | |
186 | ||
187 | /* id_aa64mmfr0 is a read-only register so values outside of the | |
188 | * supported mappings can be considered an implementation error. */ | |
189 | assert(parange < ARRAY_SIZE(pamax_map)); | |
190 | return pamax_map[parange]; | |
191 | } | |
192 | ||
193 | /* Return true if extended addresses are enabled. | |
194 | * This is always the case if our translation regime is 64 bit, | |
195 | * but depends on TTBCR.EAE for 32 bit. | |
196 | */ | |
197 | static inline bool extended_addresses_enabled(CPUARMState *env) | |
198 | { | |
199 | TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; | |
200 | return arm_el_is_aa64(env, 1) || | |
201 | (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE)); | |
202 | } | |
203 | ||
204 | /* Valid Syndrome Register EC field values */ | |
205 | enum arm_exception_class { | |
206 | EC_UNCATEGORIZED = 0x00, | |
207 | EC_WFX_TRAP = 0x01, | |
208 | EC_CP15RTTRAP = 0x03, | |
209 | EC_CP15RRTTRAP = 0x04, | |
210 | EC_CP14RTTRAP = 0x05, | |
211 | EC_CP14DTTRAP = 0x06, | |
212 | EC_ADVSIMDFPACCESSTRAP = 0x07, | |
213 | EC_FPIDTRAP = 0x08, | |
214 | EC_CP14RRTTRAP = 0x0c, | |
215 | EC_ILLEGALSTATE = 0x0e, | |
216 | EC_AA32_SVC = 0x11, | |
217 | EC_AA32_HVC = 0x12, | |
218 | EC_AA32_SMC = 0x13, | |
219 | EC_AA64_SVC = 0x15, | |
220 | EC_AA64_HVC = 0x16, | |
221 | EC_AA64_SMC = 0x17, | |
222 | EC_SYSTEMREGISTERTRAP = 0x18, | |
223 | EC_INSNABORT = 0x20, | |
224 | EC_INSNABORT_SAME_EL = 0x21, | |
225 | EC_PCALIGNMENT = 0x22, | |
226 | EC_DATAABORT = 0x24, | |
227 | EC_DATAABORT_SAME_EL = 0x25, | |
228 | EC_SPALIGNMENT = 0x26, | |
229 | EC_AA32_FPTRAP = 0x28, | |
230 | EC_AA64_FPTRAP = 0x2c, | |
231 | EC_SERROR = 0x2f, | |
232 | EC_BREAKPOINT = 0x30, | |
233 | EC_BREAKPOINT_SAME_EL = 0x31, | |
234 | EC_SOFTWARESTEP = 0x32, | |
235 | EC_SOFTWARESTEP_SAME_EL = 0x33, | |
236 | EC_WATCHPOINT = 0x34, | |
237 | EC_WATCHPOINT_SAME_EL = 0x35, | |
238 | EC_AA32_BKPT = 0x38, | |
239 | EC_VECTORCATCH = 0x3a, | |
240 | EC_AA64_BKPT = 0x3c, | |
241 | }; | |
242 | ||
243 | #define ARM_EL_EC_SHIFT 26 | |
244 | #define ARM_EL_IL_SHIFT 25 | |
245 | #define ARM_EL_ISV_SHIFT 24 | |
246 | #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) | |
247 | #define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) | |
248 | ||
249 | /* Utility functions for constructing various kinds of syndrome value. | |
250 | * Note that in general we follow the AArch64 syndrome values; in a | |
251 | * few cases the value in HSR for exceptions taken to AArch32 Hyp | |
252 | * mode differs slightly, so if we ever implemented Hyp mode then the | |
253 | * syndrome value would need some massaging on exception entry. | |
254 | * (One example of this is that AArch64 defaults to IL bit set for | |
255 | * exceptions which don't specifically indicate information about the | |
256 | * trapping instruction, whereas AArch32 defaults to IL bit clear.) | |
257 | */ | |
258 | static inline uint32_t syn_uncategorized(void) | |
259 | { | |
260 | return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL; | |
261 | } | |
262 | ||
263 | static inline uint32_t syn_aa64_svc(uint32_t imm16) | |
264 | { | |
265 | return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); | |
266 | } | |
267 | ||
268 | static inline uint32_t syn_aa64_hvc(uint32_t imm16) | |
269 | { | |
270 | return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); | |
271 | } | |
272 | ||
273 | static inline uint32_t syn_aa64_smc(uint32_t imm16) | |
274 | { | |
275 | return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); | |
276 | } | |
277 | ||
278 | static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) | |
279 | { | |
280 | return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) | |
281 | | (is_16bit ? 0 : ARM_EL_IL); | |
282 | } | |
283 | ||
284 | static inline uint32_t syn_aa32_hvc(uint32_t imm16) | |
285 | { | |
286 | return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); | |
287 | } | |
288 | ||
289 | static inline uint32_t syn_aa32_smc(void) | |
290 | { | |
291 | return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL; | |
292 | } | |
293 | ||
294 | static inline uint32_t syn_aa64_bkpt(uint32_t imm16) | |
295 | { | |
296 | return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); | |
297 | } | |
298 | ||
299 | static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) | |
300 | { | |
301 | return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) | |
302 | | (is_16bit ? 0 : ARM_EL_IL); | |
303 | } | |
304 | ||
305 | static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, | |
306 | int crn, int crm, int rt, | |
307 | int isread) | |
308 | { | |
309 | return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | |
310 | | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5) | |
311 | | (crm << 1) | isread; | |
312 | } | |
313 | ||
314 | static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2, | |
315 | int crn, int crm, int rt, int isread, | |
316 | bool is_16bit) | |
317 | { | |
318 | return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT) | |
319 | | (is_16bit ? 0 : ARM_EL_IL) | |
320 | | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) | |
321 | | (crn << 10) | (rt << 5) | (crm << 1) | isread; | |
322 | } | |
323 | ||
324 | static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2, | |
325 | int crn, int crm, int rt, int isread, | |
326 | bool is_16bit) | |
327 | { | |
328 | return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT) | |
329 | | (is_16bit ? 0 : ARM_EL_IL) | |
330 | | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) | |
331 | | (crn << 10) | (rt << 5) | (crm << 1) | isread; | |
332 | } | |
333 | ||
334 | static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm, | |
335 | int rt, int rt2, int isread, | |
336 | bool is_16bit) | |
337 | { | |
338 | return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT) | |
339 | | (is_16bit ? 0 : ARM_EL_IL) | |
340 | | (cv << 24) | (cond << 20) | (opc1 << 16) | |
341 | | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; | |
342 | } | |
343 | ||
344 | static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, | |
345 | int rt, int rt2, int isread, | |
346 | bool is_16bit) | |
347 | { | |
348 | return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT) | |
349 | | (is_16bit ? 0 : ARM_EL_IL) | |
350 | | (cv << 24) | (cond << 20) | (opc1 << 16) | |
351 | | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; | |
352 | } | |
353 | ||
354 | static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit) | |
355 | { | |
356 | return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) | |
357 | | (is_16bit ? 0 : ARM_EL_IL) | |
358 | | (cv << 24) | (cond << 20); | |
359 | } | |
360 | ||
361 | static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) | |
362 | { | |
363 | return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) | |
364 | | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc; | |
365 | } | |
366 | ||
367 | static inline uint32_t syn_data_abort_no_iss(int same_el, | |
368 | int ea, int cm, int s1ptw, | |
369 | int wnr, int fsc) | |
370 | { | |
371 | return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) | |
372 | | ARM_EL_IL | |
373 | | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; | |
374 | } | |
375 | ||
376 | static inline uint32_t syn_data_abort_with_iss(int same_el, | |
377 | int sas, int sse, int srt, | |
378 | int sf, int ar, | |
379 | int ea, int cm, int s1ptw, | |
380 | int wnr, int fsc, | |
381 | bool is_16bit) | |
382 | { | |
383 | return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) | |
384 | | (is_16bit ? 0 : ARM_EL_IL) | |
385 | | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16) | |
386 | | (sf << 15) | (ar << 14) | |
387 | | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; | |
388 | } | |
389 | ||
390 | static inline uint32_t syn_swstep(int same_el, int isv, int ex) | |
391 | { | |
392 | return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) | |
393 | | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22; | |
394 | } | |
395 | ||
396 | static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr) | |
397 | { | |
398 | return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) | |
399 | | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22; | |
400 | } | |
401 | ||
402 | static inline uint32_t syn_breakpoint(int same_el) | |
403 | { | |
404 | return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) | |
405 | | ARM_EL_IL | 0x22; | |
406 | } | |
407 | ||
408 | static inline uint32_t syn_wfx(int cv, int cond, int ti) | |
409 | { | |
410 | return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | | |
411 | (cv << 24) | (cond << 20) | ti; | |
412 | } | |
413 | ||
414 | /* Update a QEMU watchpoint based on the information the guest has set in the | |
415 | * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers. | |
416 | */ | |
417 | void hw_watchpoint_update(ARMCPU *cpu, int n); | |
418 | /* Update the QEMU watchpoints for every guest watchpoint. This does a | |
419 | * complete delete-and-reinstate of the QEMU watchpoint list and so is | |
420 | * suitable for use after migration or on reset. | |
421 | */ | |
422 | void hw_watchpoint_update_all(ARMCPU *cpu); | |
423 | /* Update a QEMU breakpoint based on the information the guest has set in the | |
424 | * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers. | |
425 | */ | |
426 | void hw_breakpoint_update(ARMCPU *cpu, int n); | |
427 | /* Update the QEMU breakpoints for every guest breakpoint. This does a | |
428 | * complete delete-and-reinstate of the QEMU breakpoint list and so is | |
429 | * suitable for use after migration or on reset. | |
430 | */ | |
431 | void hw_breakpoint_update_all(ARMCPU *cpu); | |
432 | ||
433 | /* Callback function for checking if a watchpoint should trigger. */ | |
434 | bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); | |
435 | ||
436 | /* Adjust addresses (in BE32 mode) before testing against watchpoint | |
437 | * addresses. | |
438 | */ | |
439 | vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len); | |
440 | ||
441 | /* Callback function for when a watchpoint or breakpoint triggers. */ | |
442 | void arm_debug_excp_handler(CPUState *cs); | |
443 | ||
444 | #ifdef CONFIG_USER_ONLY | |
445 | static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type) | |
446 | { | |
447 | return false; | |
448 | } | |
449 | #else | |
450 | /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */ | |
451 | bool arm_is_psci_call(ARMCPU *cpu, int excp_type); | |
452 | /* Actually handle a PSCI call */ | |
453 | void arm_handle_psci_call(ARMCPU *cpu); | |
454 | #endif | |
455 | ||
456 | /** | |
457 | * arm_clear_exclusive: clear the exclusive monitor | |
458 | * @env: CPU env | |
459 | * Clear the CPU's exclusive monitor, like the guest CLREX instruction. | |
460 | */ | |
461 | static inline void arm_clear_exclusive(CPUARMState *env) | |
462 | { | |
463 | env->exclusive_addr = -1; | |
464 | } | |
465 | ||
466 | /** | |
467 | * ARMMMUFaultInfo: Information describing an ARM MMU Fault | |
468 | * @s2addr: Address that caused a fault at stage 2 | |
469 | * @stage2: True if we faulted at stage 2 | |
470 | * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk | |
471 | * @ea: True if we should set the EA (external abort type) bit in syndrome | |
472 | */ | |
473 | typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; | |
474 | struct ARMMMUFaultInfo { | |
475 | target_ulong s2addr; | |
476 | bool stage2; | |
477 | bool s1ptw; | |
478 | bool ea; | |
479 | }; | |
480 | ||
481 | /* Do a page table walk and add page to TLB if possible */ | |
482 | bool arm_tlb_fill(CPUState *cpu, vaddr address, | |
483 | MMUAccessType access_type, int mmu_idx, | |
484 | uint32_t *fsr, ARMMMUFaultInfo *fi); | |
485 | ||
486 | /* Return true if the stage 1 translation regime is using LPAE format page | |
487 | * tables */ | |
488 | bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); | |
489 | ||
490 | /* Raise a data fault alignment exception for the specified virtual address */ | |
491 | void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, | |
492 | MMUAccessType access_type, | |
493 | int mmu_idx, uintptr_t retaddr); | |
494 | ||
495 | /* arm_cpu_do_transaction_failed: handle a memory system error response | |
496 | * (eg "no device/memory present at address") by raising an external abort | |
497 | * exception | |
498 | */ | |
499 | void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, | |
500 | vaddr addr, unsigned size, | |
501 | MMUAccessType access_type, | |
502 | int mmu_idx, MemTxAttrs attrs, | |
503 | MemTxResult response, uintptr_t retaddr); | |
504 | ||
505 | /* Call the EL change hook if one has been registered */ | |
506 | static inline void arm_call_el_change_hook(ARMCPU *cpu) | |
507 | { | |
508 | if (cpu->el_change_hook) { | |
509 | cpu->el_change_hook(cpu, cpu->el_change_hook_opaque); | |
510 | } | |
511 | } | |
512 | ||
513 | /* Return true if this address translation regime is secure */ | |
514 | static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) | |
515 | { | |
516 | switch (mmu_idx) { | |
517 | case ARMMMUIdx_S12NSE0: | |
518 | case ARMMMUIdx_S12NSE1: | |
519 | case ARMMMUIdx_S1NSE0: | |
520 | case ARMMMUIdx_S1NSE1: | |
521 | case ARMMMUIdx_S1E2: | |
522 | case ARMMMUIdx_S2NS: | |
523 | case ARMMMUIdx_MPriv: | |
524 | case ARMMMUIdx_MNegPri: | |
525 | case ARMMMUIdx_MUser: | |
526 | return false; | |
527 | case ARMMMUIdx_S1E3: | |
528 | case ARMMMUIdx_S1SE0: | |
529 | case ARMMMUIdx_S1SE1: | |
530 | case ARMMMUIdx_MSPriv: | |
531 | case ARMMMUIdx_MSNegPri: | |
532 | case ARMMMUIdx_MSUser: | |
533 | return true; | |
534 | default: | |
535 | g_assert_not_reached(); | |
536 | } | |
537 | } | |
538 | ||
539 | #endif |