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1 | /* | |
2 | * QEMU KVM support | |
3 | * | |
4 | * Copyright (C) 2006-2008 Qumranet Technologies | |
5 | * Copyright IBM, Corp. 2008 | |
6 | * | |
7 | * Authors: | |
8 | * Anthony Liguori <aliguori@us.ibm.com> | |
9 | * | |
10 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
11 | * See the COPYING file in the top-level directory. | |
12 | * | |
13 | */ | |
14 | ||
15 | #include "qemu/osdep.h" | |
16 | #include <sys/ioctl.h> | |
17 | #include <sys/mman.h> | |
18 | #include <sys/utsname.h> | |
19 | ||
20 | #include <linux/kvm.h> | |
21 | #include <linux/kvm_para.h> | |
22 | ||
23 | #include "qemu-common.h" | |
24 | #include "sysemu/sysemu.h" | |
25 | #include "sysemu/kvm_int.h" | |
26 | #include "kvm_i386.h" | |
27 | #include "cpu.h" | |
28 | #include "hyperv.h" | |
29 | ||
30 | #include "exec/gdbstub.h" | |
31 | #include "qemu/host-utils.h" | |
32 | #include "qemu/config-file.h" | |
33 | #include "qemu/error-report.h" | |
34 | #include "hw/i386/pc.h" | |
35 | #include "hw/i386/apic.h" | |
36 | #include "hw/i386/apic_internal.h" | |
37 | #include "hw/i386/apic-msidef.h" | |
38 | ||
39 | #include "exec/ioport.h" | |
40 | #include "standard-headers/asm-x86/hyperv.h" | |
41 | #include "hw/pci/pci.h" | |
42 | #include "hw/pci/msi.h" | |
43 | #include "migration/migration.h" | |
44 | #include "exec/memattrs.h" | |
45 | ||
46 | //#define DEBUG_KVM | |
47 | ||
48 | #ifdef DEBUG_KVM | |
49 | #define DPRINTF(fmt, ...) \ | |
50 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) | |
51 | #else | |
52 | #define DPRINTF(fmt, ...) \ | |
53 | do { } while (0) | |
54 | #endif | |
55 | ||
56 | #define MSR_KVM_WALL_CLOCK 0x11 | |
57 | #define MSR_KVM_SYSTEM_TIME 0x12 | |
58 | ||
59 | #ifndef BUS_MCEERR_AR | |
60 | #define BUS_MCEERR_AR 4 | |
61 | #endif | |
62 | #ifndef BUS_MCEERR_AO | |
63 | #define BUS_MCEERR_AO 5 | |
64 | #endif | |
65 | ||
66 | const KVMCapabilityInfo kvm_arch_required_capabilities[] = { | |
67 | KVM_CAP_INFO(SET_TSS_ADDR), | |
68 | KVM_CAP_INFO(EXT_CPUID), | |
69 | KVM_CAP_INFO(MP_STATE), | |
70 | KVM_CAP_LAST_INFO | |
71 | }; | |
72 | ||
73 | static bool has_msr_star; | |
74 | static bool has_msr_hsave_pa; | |
75 | static bool has_msr_tsc_aux; | |
76 | static bool has_msr_tsc_adjust; | |
77 | static bool has_msr_tsc_deadline; | |
78 | static bool has_msr_feature_control; | |
79 | static bool has_msr_async_pf_en; | |
80 | static bool has_msr_pv_eoi_en; | |
81 | static bool has_msr_misc_enable; | |
82 | static bool has_msr_smbase; | |
83 | static bool has_msr_bndcfgs; | |
84 | static bool has_msr_kvm_steal_time; | |
85 | static int lm_capable_kernel; | |
86 | static bool has_msr_hv_hypercall; | |
87 | static bool has_msr_hv_vapic; | |
88 | static bool has_msr_hv_tsc; | |
89 | static bool has_msr_hv_crash; | |
90 | static bool has_msr_hv_reset; | |
91 | static bool has_msr_hv_vpindex; | |
92 | static bool has_msr_hv_runtime; | |
93 | static bool has_msr_hv_synic; | |
94 | static bool has_msr_hv_stimer; | |
95 | static bool has_msr_mtrr; | |
96 | static bool has_msr_xss; | |
97 | ||
98 | static bool has_msr_architectural_pmu; | |
99 | static uint32_t num_architectural_pmu_counters; | |
100 | ||
101 | static int has_xsave; | |
102 | static int has_xcrs; | |
103 | static int has_pit_state2; | |
104 | ||
105 | int kvm_has_pit_state2(void) | |
106 | { | |
107 | return has_pit_state2; | |
108 | } | |
109 | ||
110 | bool kvm_has_smm(void) | |
111 | { | |
112 | return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM); | |
113 | } | |
114 | ||
115 | bool kvm_allows_irq0_override(void) | |
116 | { | |
117 | return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing(); | |
118 | } | |
119 | ||
120 | static int kvm_get_tsc(CPUState *cs) | |
121 | { | |
122 | X86CPU *cpu = X86_CPU(cs); | |
123 | CPUX86State *env = &cpu->env; | |
124 | struct { | |
125 | struct kvm_msrs info; | |
126 | struct kvm_msr_entry entries[1]; | |
127 | } msr_data; | |
128 | int ret; | |
129 | ||
130 | if (env->tsc_valid) { | |
131 | return 0; | |
132 | } | |
133 | ||
134 | msr_data.info.nmsrs = 1; | |
135 | msr_data.entries[0].index = MSR_IA32_TSC; | |
136 | env->tsc_valid = !runstate_is_running(); | |
137 | ||
138 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data); | |
139 | if (ret < 0) { | |
140 | return ret; | |
141 | } | |
142 | ||
143 | env->tsc = msr_data.entries[0].data; | |
144 | return 0; | |
145 | } | |
146 | ||
147 | static inline void do_kvm_synchronize_tsc(void *arg) | |
148 | { | |
149 | CPUState *cpu = arg; | |
150 | ||
151 | kvm_get_tsc(cpu); | |
152 | } | |
153 | ||
154 | void kvm_synchronize_all_tsc(void) | |
155 | { | |
156 | CPUState *cpu; | |
157 | ||
158 | if (kvm_enabled()) { | |
159 | CPU_FOREACH(cpu) { | |
160 | run_on_cpu(cpu, do_kvm_synchronize_tsc, cpu); | |
161 | } | |
162 | } | |
163 | } | |
164 | ||
165 | static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max) | |
166 | { | |
167 | struct kvm_cpuid2 *cpuid; | |
168 | int r, size; | |
169 | ||
170 | size = sizeof(*cpuid) + max * sizeof(*cpuid->entries); | |
171 | cpuid = g_malloc0(size); | |
172 | cpuid->nent = max; | |
173 | r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid); | |
174 | if (r == 0 && cpuid->nent >= max) { | |
175 | r = -E2BIG; | |
176 | } | |
177 | if (r < 0) { | |
178 | if (r == -E2BIG) { | |
179 | g_free(cpuid); | |
180 | return NULL; | |
181 | } else { | |
182 | fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n", | |
183 | strerror(-r)); | |
184 | exit(1); | |
185 | } | |
186 | } | |
187 | return cpuid; | |
188 | } | |
189 | ||
190 | /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough | |
191 | * for all entries. | |
192 | */ | |
193 | static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s) | |
194 | { | |
195 | struct kvm_cpuid2 *cpuid; | |
196 | int max = 1; | |
197 | while ((cpuid = try_get_cpuid(s, max)) == NULL) { | |
198 | max *= 2; | |
199 | } | |
200 | return cpuid; | |
201 | } | |
202 | ||
203 | static const struct kvm_para_features { | |
204 | int cap; | |
205 | int feature; | |
206 | } para_features[] = { | |
207 | { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE }, | |
208 | { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY }, | |
209 | { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP }, | |
210 | { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF }, | |
211 | }; | |
212 | ||
213 | static int get_para_features(KVMState *s) | |
214 | { | |
215 | int i, features = 0; | |
216 | ||
217 | for (i = 0; i < ARRAY_SIZE(para_features); i++) { | |
218 | if (kvm_check_extension(s, para_features[i].cap)) { | |
219 | features |= (1 << para_features[i].feature); | |
220 | } | |
221 | } | |
222 | ||
223 | return features; | |
224 | } | |
225 | ||
226 | ||
227 | /* Returns the value for a specific register on the cpuid entry | |
228 | */ | |
229 | static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg) | |
230 | { | |
231 | uint32_t ret = 0; | |
232 | switch (reg) { | |
233 | case R_EAX: | |
234 | ret = entry->eax; | |
235 | break; | |
236 | case R_EBX: | |
237 | ret = entry->ebx; | |
238 | break; | |
239 | case R_ECX: | |
240 | ret = entry->ecx; | |
241 | break; | |
242 | case R_EDX: | |
243 | ret = entry->edx; | |
244 | break; | |
245 | } | |
246 | return ret; | |
247 | } | |
248 | ||
249 | /* Find matching entry for function/index on kvm_cpuid2 struct | |
250 | */ | |
251 | static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid, | |
252 | uint32_t function, | |
253 | uint32_t index) | |
254 | { | |
255 | int i; | |
256 | for (i = 0; i < cpuid->nent; ++i) { | |
257 | if (cpuid->entries[i].function == function && | |
258 | cpuid->entries[i].index == index) { | |
259 | return &cpuid->entries[i]; | |
260 | } | |
261 | } | |
262 | /* not found: */ | |
263 | return NULL; | |
264 | } | |
265 | ||
266 | uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, | |
267 | uint32_t index, int reg) | |
268 | { | |
269 | struct kvm_cpuid2 *cpuid; | |
270 | uint32_t ret = 0; | |
271 | uint32_t cpuid_1_edx; | |
272 | bool found = false; | |
273 | ||
274 | cpuid = get_supported_cpuid(s); | |
275 | ||
276 | struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index); | |
277 | if (entry) { | |
278 | found = true; | |
279 | ret = cpuid_entry_get_reg(entry, reg); | |
280 | } | |
281 | ||
282 | /* Fixups for the data returned by KVM, below */ | |
283 | ||
284 | if (function == 1 && reg == R_EDX) { | |
285 | /* KVM before 2.6.30 misreports the following features */ | |
286 | ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA; | |
287 | } else if (function == 1 && reg == R_ECX) { | |
288 | /* We can set the hypervisor flag, even if KVM does not return it on | |
289 | * GET_SUPPORTED_CPUID | |
290 | */ | |
291 | ret |= CPUID_EXT_HYPERVISOR; | |
292 | /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it | |
293 | * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER, | |
294 | * and the irqchip is in the kernel. | |
295 | */ | |
296 | if (kvm_irqchip_in_kernel() && | |
297 | kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) { | |
298 | ret |= CPUID_EXT_TSC_DEADLINE_TIMER; | |
299 | } | |
300 | ||
301 | /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled | |
302 | * without the in-kernel irqchip | |
303 | */ | |
304 | if (!kvm_irqchip_in_kernel()) { | |
305 | ret &= ~CPUID_EXT_X2APIC; | |
306 | } | |
307 | } else if (function == 6 && reg == R_EAX) { | |
308 | ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */ | |
309 | } else if (function == 0x80000001 && reg == R_EDX) { | |
310 | /* On Intel, kvm returns cpuid according to the Intel spec, | |
311 | * so add missing bits according to the AMD spec: | |
312 | */ | |
313 | cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); | |
314 | ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES; | |
315 | } | |
316 | ||
317 | g_free(cpuid); | |
318 | ||
319 | /* fallback for older kernels */ | |
320 | if ((function == KVM_CPUID_FEATURES) && !found) { | |
321 | ret = get_para_features(s); | |
322 | } | |
323 | ||
324 | return ret; | |
325 | } | |
326 | ||
327 | typedef struct HWPoisonPage { | |
328 | ram_addr_t ram_addr; | |
329 | QLIST_ENTRY(HWPoisonPage) list; | |
330 | } HWPoisonPage; | |
331 | ||
332 | static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list = | |
333 | QLIST_HEAD_INITIALIZER(hwpoison_page_list); | |
334 | ||
335 | static void kvm_unpoison_all(void *param) | |
336 | { | |
337 | HWPoisonPage *page, *next_page; | |
338 | ||
339 | QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) { | |
340 | QLIST_REMOVE(page, list); | |
341 | qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE); | |
342 | g_free(page); | |
343 | } | |
344 | } | |
345 | ||
346 | static void kvm_hwpoison_page_add(ram_addr_t ram_addr) | |
347 | { | |
348 | HWPoisonPage *page; | |
349 | ||
350 | QLIST_FOREACH(page, &hwpoison_page_list, list) { | |
351 | if (page->ram_addr == ram_addr) { | |
352 | return; | |
353 | } | |
354 | } | |
355 | page = g_new(HWPoisonPage, 1); | |
356 | page->ram_addr = ram_addr; | |
357 | QLIST_INSERT_HEAD(&hwpoison_page_list, page, list); | |
358 | } | |
359 | ||
360 | static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap, | |
361 | int *max_banks) | |
362 | { | |
363 | int r; | |
364 | ||
365 | r = kvm_check_extension(s, KVM_CAP_MCE); | |
366 | if (r > 0) { | |
367 | *max_banks = r; | |
368 | return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap); | |
369 | } | |
370 | return -ENOSYS; | |
371 | } | |
372 | ||
373 | static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code) | |
374 | { | |
375 | CPUX86State *env = &cpu->env; | |
376 | uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | | |
377 | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S; | |
378 | uint64_t mcg_status = MCG_STATUS_MCIP; | |
379 | ||
380 | if (code == BUS_MCEERR_AR) { | |
381 | status |= MCI_STATUS_AR | 0x134; | |
382 | mcg_status |= MCG_STATUS_EIPV; | |
383 | } else { | |
384 | status |= 0xc0; | |
385 | mcg_status |= MCG_STATUS_RIPV; | |
386 | } | |
387 | cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr, | |
388 | (MCM_ADDR_PHYS << 6) | 0xc, | |
389 | cpu_x86_support_mca_broadcast(env) ? | |
390 | MCE_INJECT_BROADCAST : 0); | |
391 | } | |
392 | ||
393 | static void hardware_memory_error(void) | |
394 | { | |
395 | fprintf(stderr, "Hardware memory error!\n"); | |
396 | exit(1); | |
397 | } | |
398 | ||
399 | int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) | |
400 | { | |
401 | X86CPU *cpu = X86_CPU(c); | |
402 | CPUX86State *env = &cpu->env; | |
403 | ram_addr_t ram_addr; | |
404 | hwaddr paddr; | |
405 | ||
406 | if ((env->mcg_cap & MCG_SER_P) && addr | |
407 | && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) { | |
408 | if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL || | |
409 | !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) { | |
410 | fprintf(stderr, "Hardware memory error for memory used by " | |
411 | "QEMU itself instead of guest system!\n"); | |
412 | /* Hope we are lucky for AO MCE */ | |
413 | if (code == BUS_MCEERR_AO) { | |
414 | return 0; | |
415 | } else { | |
416 | hardware_memory_error(); | |
417 | } | |
418 | } | |
419 | kvm_hwpoison_page_add(ram_addr); | |
420 | kvm_mce_inject(cpu, paddr, code); | |
421 | } else { | |
422 | if (code == BUS_MCEERR_AO) { | |
423 | return 0; | |
424 | } else if (code == BUS_MCEERR_AR) { | |
425 | hardware_memory_error(); | |
426 | } else { | |
427 | return 1; | |
428 | } | |
429 | } | |
430 | return 0; | |
431 | } | |
432 | ||
433 | int kvm_arch_on_sigbus(int code, void *addr) | |
434 | { | |
435 | X86CPU *cpu = X86_CPU(first_cpu); | |
436 | ||
437 | if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) { | |
438 | ram_addr_t ram_addr; | |
439 | hwaddr paddr; | |
440 | ||
441 | /* Hope we are lucky for AO MCE */ | |
442 | if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL || | |
443 | !kvm_physical_memory_addr_from_host(first_cpu->kvm_state, | |
444 | addr, &paddr)) { | |
445 | fprintf(stderr, "Hardware memory error for memory used by " | |
446 | "QEMU itself instead of guest system!: %p\n", addr); | |
447 | return 0; | |
448 | } | |
449 | kvm_hwpoison_page_add(ram_addr); | |
450 | kvm_mce_inject(X86_CPU(first_cpu), paddr, code); | |
451 | } else { | |
452 | if (code == BUS_MCEERR_AO) { | |
453 | return 0; | |
454 | } else if (code == BUS_MCEERR_AR) { | |
455 | hardware_memory_error(); | |
456 | } else { | |
457 | return 1; | |
458 | } | |
459 | } | |
460 | return 0; | |
461 | } | |
462 | ||
463 | static int kvm_inject_mce_oldstyle(X86CPU *cpu) | |
464 | { | |
465 | CPUX86State *env = &cpu->env; | |
466 | ||
467 | if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) { | |
468 | unsigned int bank, bank_num = env->mcg_cap & 0xff; | |
469 | struct kvm_x86_mce mce; | |
470 | ||
471 | env->exception_injected = -1; | |
472 | ||
473 | /* | |
474 | * There must be at least one bank in use if an MCE is pending. | |
475 | * Find it and use its values for the event injection. | |
476 | */ | |
477 | for (bank = 0; bank < bank_num; bank++) { | |
478 | if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) { | |
479 | break; | |
480 | } | |
481 | } | |
482 | assert(bank < bank_num); | |
483 | ||
484 | mce.bank = bank; | |
485 | mce.status = env->mce_banks[bank * 4 + 1]; | |
486 | mce.mcg_status = env->mcg_status; | |
487 | mce.addr = env->mce_banks[bank * 4 + 2]; | |
488 | mce.misc = env->mce_banks[bank * 4 + 3]; | |
489 | ||
490 | return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce); | |
491 | } | |
492 | return 0; | |
493 | } | |
494 | ||
495 | static void cpu_update_state(void *opaque, int running, RunState state) | |
496 | { | |
497 | CPUX86State *env = opaque; | |
498 | ||
499 | if (running) { | |
500 | env->tsc_valid = false; | |
501 | } | |
502 | } | |
503 | ||
504 | unsigned long kvm_arch_vcpu_id(CPUState *cs) | |
505 | { | |
506 | X86CPU *cpu = X86_CPU(cs); | |
507 | return cpu->apic_id; | |
508 | } | |
509 | ||
510 | #ifndef KVM_CPUID_SIGNATURE_NEXT | |
511 | #define KVM_CPUID_SIGNATURE_NEXT 0x40000100 | |
512 | #endif | |
513 | ||
514 | static bool hyperv_hypercall_available(X86CPU *cpu) | |
515 | { | |
516 | return cpu->hyperv_vapic || | |
517 | (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY); | |
518 | } | |
519 | ||
520 | static bool hyperv_enabled(X86CPU *cpu) | |
521 | { | |
522 | CPUState *cs = CPU(cpu); | |
523 | return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 && | |
524 | (hyperv_hypercall_available(cpu) || | |
525 | cpu->hyperv_time || | |
526 | cpu->hyperv_relaxed_timing || | |
527 | cpu->hyperv_crash || | |
528 | cpu->hyperv_reset || | |
529 | cpu->hyperv_vpindex || | |
530 | cpu->hyperv_runtime || | |
531 | cpu->hyperv_synic || | |
532 | cpu->hyperv_stimer); | |
533 | } | |
534 | ||
535 | static int kvm_arch_set_tsc_khz(CPUState *cs) | |
536 | { | |
537 | X86CPU *cpu = X86_CPU(cs); | |
538 | CPUX86State *env = &cpu->env; | |
539 | int r; | |
540 | ||
541 | if (!env->tsc_khz) { | |
542 | return 0; | |
543 | } | |
544 | ||
545 | r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ? | |
546 | kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) : | |
547 | -ENOTSUP; | |
548 | if (r < 0) { | |
549 | /* When KVM_SET_TSC_KHZ fails, it's an error only if the current | |
550 | * TSC frequency doesn't match the one we want. | |
551 | */ | |
552 | int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ? | |
553 | kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : | |
554 | -ENOTSUP; | |
555 | if (cur_freq <= 0 || cur_freq != env->tsc_khz) { | |
556 | error_report("warning: TSC frequency mismatch between " | |
557 | "VM and host, and TSC scaling unavailable"); | |
558 | return r; | |
559 | } | |
560 | } | |
561 | ||
562 | return 0; | |
563 | } | |
564 | ||
565 | static Error *invtsc_mig_blocker; | |
566 | ||
567 | #define KVM_MAX_CPUID_ENTRIES 100 | |
568 | ||
569 | int kvm_arch_init_vcpu(CPUState *cs) | |
570 | { | |
571 | struct { | |
572 | struct kvm_cpuid2 cpuid; | |
573 | struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES]; | |
574 | } QEMU_PACKED cpuid_data; | |
575 | X86CPU *cpu = X86_CPU(cs); | |
576 | CPUX86State *env = &cpu->env; | |
577 | uint32_t limit, i, j, cpuid_i; | |
578 | uint32_t unused; | |
579 | struct kvm_cpuid_entry2 *c; | |
580 | uint32_t signature[3]; | |
581 | int kvm_base = KVM_CPUID_SIGNATURE; | |
582 | int r; | |
583 | ||
584 | memset(&cpuid_data, 0, sizeof(cpuid_data)); | |
585 | ||
586 | cpuid_i = 0; | |
587 | ||
588 | /* Paravirtualization CPUIDs */ | |
589 | if (hyperv_enabled(cpu)) { | |
590 | c = &cpuid_data.entries[cpuid_i++]; | |
591 | c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS; | |
592 | if (!cpu->hyperv_vendor_id) { | |
593 | memcpy(signature, "Microsoft Hv", 12); | |
594 | } else { | |
595 | size_t len = strlen(cpu->hyperv_vendor_id); | |
596 | ||
597 | if (len > 12) { | |
598 | error_report("hv-vendor-id truncated to 12 characters"); | |
599 | len = 12; | |
600 | } | |
601 | memset(signature, 0, 12); | |
602 | memcpy(signature, cpu->hyperv_vendor_id, len); | |
603 | } | |
604 | c->eax = HYPERV_CPUID_MIN; | |
605 | c->ebx = signature[0]; | |
606 | c->ecx = signature[1]; | |
607 | c->edx = signature[2]; | |
608 | ||
609 | c = &cpuid_data.entries[cpuid_i++]; | |
610 | c->function = HYPERV_CPUID_INTERFACE; | |
611 | memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12); | |
612 | c->eax = signature[0]; | |
613 | c->ebx = 0; | |
614 | c->ecx = 0; | |
615 | c->edx = 0; | |
616 | ||
617 | c = &cpuid_data.entries[cpuid_i++]; | |
618 | c->function = HYPERV_CPUID_VERSION; | |
619 | c->eax = 0x00001bbc; | |
620 | c->ebx = 0x00060001; | |
621 | ||
622 | c = &cpuid_data.entries[cpuid_i++]; | |
623 | c->function = HYPERV_CPUID_FEATURES; | |
624 | if (cpu->hyperv_relaxed_timing) { | |
625 | c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE; | |
626 | } | |
627 | if (cpu->hyperv_vapic) { | |
628 | c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE; | |
629 | c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE; | |
630 | has_msr_hv_vapic = true; | |
631 | } | |
632 | if (cpu->hyperv_time && | |
633 | kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) { | |
634 | c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE; | |
635 | c->eax |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE; | |
636 | c->eax |= 0x200; | |
637 | has_msr_hv_tsc = true; | |
638 | } | |
639 | if (cpu->hyperv_crash && has_msr_hv_crash) { | |
640 | c->edx |= HV_X64_GUEST_CRASH_MSR_AVAILABLE; | |
641 | } | |
642 | if (cpu->hyperv_reset && has_msr_hv_reset) { | |
643 | c->eax |= HV_X64_MSR_RESET_AVAILABLE; | |
644 | } | |
645 | if (cpu->hyperv_vpindex && has_msr_hv_vpindex) { | |
646 | c->eax |= HV_X64_MSR_VP_INDEX_AVAILABLE; | |
647 | } | |
648 | if (cpu->hyperv_runtime && has_msr_hv_runtime) { | |
649 | c->eax |= HV_X64_MSR_VP_RUNTIME_AVAILABLE; | |
650 | } | |
651 | if (cpu->hyperv_synic) { | |
652 | int sint; | |
653 | ||
654 | if (!has_msr_hv_synic || | |
655 | kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) { | |
656 | fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n"); | |
657 | return -ENOSYS; | |
658 | } | |
659 | ||
660 | c->eax |= HV_X64_MSR_SYNIC_AVAILABLE; | |
661 | env->msr_hv_synic_version = HV_SYNIC_VERSION_1; | |
662 | for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) { | |
663 | env->msr_hv_synic_sint[sint] = HV_SYNIC_SINT_MASKED; | |
664 | } | |
665 | } | |
666 | if (cpu->hyperv_stimer) { | |
667 | if (!has_msr_hv_stimer) { | |
668 | fprintf(stderr, "Hyper-V timers aren't supported by kernel\n"); | |
669 | return -ENOSYS; | |
670 | } | |
671 | c->eax |= HV_X64_MSR_SYNTIMER_AVAILABLE; | |
672 | } | |
673 | c = &cpuid_data.entries[cpuid_i++]; | |
674 | c->function = HYPERV_CPUID_ENLIGHTMENT_INFO; | |
675 | if (cpu->hyperv_relaxed_timing) { | |
676 | c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED; | |
677 | } | |
678 | if (has_msr_hv_vapic) { | |
679 | c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED; | |
680 | } | |
681 | c->ebx = cpu->hyperv_spinlock_attempts; | |
682 | ||
683 | c = &cpuid_data.entries[cpuid_i++]; | |
684 | c->function = HYPERV_CPUID_IMPLEMENT_LIMITS; | |
685 | c->eax = 0x40; | |
686 | c->ebx = 0x40; | |
687 | ||
688 | kvm_base = KVM_CPUID_SIGNATURE_NEXT; | |
689 | has_msr_hv_hypercall = true; | |
690 | } | |
691 | ||
692 | if (cpu->expose_kvm) { | |
693 | memcpy(signature, "KVMKVMKVM\0\0\0", 12); | |
694 | c = &cpuid_data.entries[cpuid_i++]; | |
695 | c->function = KVM_CPUID_SIGNATURE | kvm_base; | |
696 | c->eax = KVM_CPUID_FEATURES | kvm_base; | |
697 | c->ebx = signature[0]; | |
698 | c->ecx = signature[1]; | |
699 | c->edx = signature[2]; | |
700 | ||
701 | c = &cpuid_data.entries[cpuid_i++]; | |
702 | c->function = KVM_CPUID_FEATURES | kvm_base; | |
703 | c->eax = env->features[FEAT_KVM]; | |
704 | ||
705 | has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF); | |
706 | ||
707 | has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI); | |
708 | ||
709 | has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME); | |
710 | } | |
711 | ||
712 | cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused); | |
713 | ||
714 | for (i = 0; i <= limit; i++) { | |
715 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { | |
716 | fprintf(stderr, "unsupported level value: 0x%x\n", limit); | |
717 | abort(); | |
718 | } | |
719 | c = &cpuid_data.entries[cpuid_i++]; | |
720 | ||
721 | switch (i) { | |
722 | case 2: { | |
723 | /* Keep reading function 2 till all the input is received */ | |
724 | int times; | |
725 | ||
726 | c->function = i; | |
727 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC | | |
728 | KVM_CPUID_FLAG_STATE_READ_NEXT; | |
729 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
730 | times = c->eax & 0xff; | |
731 | ||
732 | for (j = 1; j < times; ++j) { | |
733 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { | |
734 | fprintf(stderr, "cpuid_data is full, no space for " | |
735 | "cpuid(eax:2):eax & 0xf = 0x%x\n", times); | |
736 | abort(); | |
737 | } | |
738 | c = &cpuid_data.entries[cpuid_i++]; | |
739 | c->function = i; | |
740 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC; | |
741 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
742 | } | |
743 | break; | |
744 | } | |
745 | case 4: | |
746 | case 0xb: | |
747 | case 0xd: | |
748 | for (j = 0; ; j++) { | |
749 | if (i == 0xd && j == 64) { | |
750 | break; | |
751 | } | |
752 | c->function = i; | |
753 | c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
754 | c->index = j; | |
755 | cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
756 | ||
757 | if (i == 4 && c->eax == 0) { | |
758 | break; | |
759 | } | |
760 | if (i == 0xb && !(c->ecx & 0xff00)) { | |
761 | break; | |
762 | } | |
763 | if (i == 0xd && c->eax == 0) { | |
764 | continue; | |
765 | } | |
766 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { | |
767 | fprintf(stderr, "cpuid_data is full, no space for " | |
768 | "cpuid(eax:0x%x,ecx:0x%x)\n", i, j); | |
769 | abort(); | |
770 | } | |
771 | c = &cpuid_data.entries[cpuid_i++]; | |
772 | } | |
773 | break; | |
774 | default: | |
775 | c->function = i; | |
776 | c->flags = 0; | |
777 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
778 | break; | |
779 | } | |
780 | } | |
781 | ||
782 | if (limit >= 0x0a) { | |
783 | uint32_t ver; | |
784 | ||
785 | cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused); | |
786 | if ((ver & 0xff) > 0) { | |
787 | has_msr_architectural_pmu = true; | |
788 | num_architectural_pmu_counters = (ver & 0xff00) >> 8; | |
789 | ||
790 | /* Shouldn't be more than 32, since that's the number of bits | |
791 | * available in EBX to tell us _which_ counters are available. | |
792 | * Play it safe. | |
793 | */ | |
794 | if (num_architectural_pmu_counters > MAX_GP_COUNTERS) { | |
795 | num_architectural_pmu_counters = MAX_GP_COUNTERS; | |
796 | } | |
797 | } | |
798 | } | |
799 | ||
800 | cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused); | |
801 | ||
802 | for (i = 0x80000000; i <= limit; i++) { | |
803 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { | |
804 | fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit); | |
805 | abort(); | |
806 | } | |
807 | c = &cpuid_data.entries[cpuid_i++]; | |
808 | ||
809 | c->function = i; | |
810 | c->flags = 0; | |
811 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
812 | } | |
813 | ||
814 | /* Call Centaur's CPUID instructions they are supported. */ | |
815 | if (env->cpuid_xlevel2 > 0) { | |
816 | cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused); | |
817 | ||
818 | for (i = 0xC0000000; i <= limit; i++) { | |
819 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { | |
820 | fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit); | |
821 | abort(); | |
822 | } | |
823 | c = &cpuid_data.entries[cpuid_i++]; | |
824 | ||
825 | c->function = i; | |
826 | c->flags = 0; | |
827 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
828 | } | |
829 | } | |
830 | ||
831 | cpuid_data.cpuid.nent = cpuid_i; | |
832 | ||
833 | if (((env->cpuid_version >> 8)&0xF) >= 6 | |
834 | && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == | |
835 | (CPUID_MCE | CPUID_MCA) | |
836 | && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) { | |
837 | uint64_t mcg_cap, unsupported_caps; | |
838 | int banks; | |
839 | int ret; | |
840 | ||
841 | ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks); | |
842 | if (ret < 0) { | |
843 | fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret)); | |
844 | return ret; | |
845 | } | |
846 | ||
847 | if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) { | |
848 | error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)", | |
849 | (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks); | |
850 | return -ENOTSUP; | |
851 | } | |
852 | ||
853 | unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK); | |
854 | if (unsupported_caps) { | |
855 | error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64, | |
856 | unsupported_caps); | |
857 | } | |
858 | ||
859 | env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK; | |
860 | ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap); | |
861 | if (ret < 0) { | |
862 | fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret)); | |
863 | return ret; | |
864 | } | |
865 | } | |
866 | ||
867 | qemu_add_vm_change_state_handler(cpu_update_state, env); | |
868 | ||
869 | c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0); | |
870 | if (c) { | |
871 | has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) || | |
872 | !!(c->ecx & CPUID_EXT_SMX); | |
873 | } | |
874 | ||
875 | c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0); | |
876 | if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) { | |
877 | /* for migration */ | |
878 | error_setg(&invtsc_mig_blocker, | |
879 | "State blocked by non-migratable CPU device" | |
880 | " (invtsc flag)"); | |
881 | migrate_add_blocker(invtsc_mig_blocker); | |
882 | /* for savevm */ | |
883 | vmstate_x86_cpu.unmigratable = 1; | |
884 | } | |
885 | ||
886 | cpuid_data.cpuid.padding = 0; | |
887 | r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data); | |
888 | if (r) { | |
889 | return r; | |
890 | } | |
891 | ||
892 | r = kvm_arch_set_tsc_khz(cs); | |
893 | if (r < 0) { | |
894 | return r; | |
895 | } | |
896 | ||
897 | /* vcpu's TSC frequency is either specified by user, or following | |
898 | * the value used by KVM if the former is not present. In the | |
899 | * latter case, we query it from KVM and record in env->tsc_khz, | |
900 | * so that vcpu's TSC frequency can be migrated later via this field. | |
901 | */ | |
902 | if (!env->tsc_khz) { | |
903 | r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ? | |
904 | kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : | |
905 | -ENOTSUP; | |
906 | if (r > 0) { | |
907 | env->tsc_khz = r; | |
908 | } | |
909 | } | |
910 | ||
911 | if (has_xsave) { | |
912 | env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave)); | |
913 | } | |
914 | ||
915 | if (env->features[FEAT_1_EDX] & CPUID_MTRR) { | |
916 | has_msr_mtrr = true; | |
917 | } | |
918 | ||
919 | return 0; | |
920 | } | |
921 | ||
922 | void kvm_arch_reset_vcpu(X86CPU *cpu) | |
923 | { | |
924 | CPUX86State *env = &cpu->env; | |
925 | ||
926 | env->exception_injected = -1; | |
927 | env->interrupt_injected = -1; | |
928 | env->xcr0 = 1; | |
929 | if (kvm_irqchip_in_kernel()) { | |
930 | env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE : | |
931 | KVM_MP_STATE_UNINITIALIZED; | |
932 | } else { | |
933 | env->mp_state = KVM_MP_STATE_RUNNABLE; | |
934 | } | |
935 | } | |
936 | ||
937 | void kvm_arch_do_init_vcpu(X86CPU *cpu) | |
938 | { | |
939 | CPUX86State *env = &cpu->env; | |
940 | ||
941 | /* APs get directly into wait-for-SIPI state. */ | |
942 | if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) { | |
943 | env->mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
944 | } | |
945 | } | |
946 | ||
947 | static int kvm_get_supported_msrs(KVMState *s) | |
948 | { | |
949 | static int kvm_supported_msrs; | |
950 | int ret = 0; | |
951 | ||
952 | /* first time */ | |
953 | if (kvm_supported_msrs == 0) { | |
954 | struct kvm_msr_list msr_list, *kvm_msr_list; | |
955 | ||
956 | kvm_supported_msrs = -1; | |
957 | ||
958 | /* Obtain MSR list from KVM. These are the MSRs that we must | |
959 | * save/restore */ | |
960 | msr_list.nmsrs = 0; | |
961 | ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list); | |
962 | if (ret < 0 && ret != -E2BIG) { | |
963 | return ret; | |
964 | } | |
965 | /* Old kernel modules had a bug and could write beyond the provided | |
966 | memory. Allocate at least a safe amount of 1K. */ | |
967 | kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) + | |
968 | msr_list.nmsrs * | |
969 | sizeof(msr_list.indices[0]))); | |
970 | ||
971 | kvm_msr_list->nmsrs = msr_list.nmsrs; | |
972 | ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list); | |
973 | if (ret >= 0) { | |
974 | int i; | |
975 | ||
976 | for (i = 0; i < kvm_msr_list->nmsrs; i++) { | |
977 | if (kvm_msr_list->indices[i] == MSR_STAR) { | |
978 | has_msr_star = true; | |
979 | continue; | |
980 | } | |
981 | if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) { | |
982 | has_msr_hsave_pa = true; | |
983 | continue; | |
984 | } | |
985 | if (kvm_msr_list->indices[i] == MSR_TSC_AUX) { | |
986 | has_msr_tsc_aux = true; | |
987 | continue; | |
988 | } | |
989 | if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) { | |
990 | has_msr_tsc_adjust = true; | |
991 | continue; | |
992 | } | |
993 | if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) { | |
994 | has_msr_tsc_deadline = true; | |
995 | continue; | |
996 | } | |
997 | if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) { | |
998 | has_msr_smbase = true; | |
999 | continue; | |
1000 | } | |
1001 | if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) { | |
1002 | has_msr_misc_enable = true; | |
1003 | continue; | |
1004 | } | |
1005 | if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) { | |
1006 | has_msr_bndcfgs = true; | |
1007 | continue; | |
1008 | } | |
1009 | if (kvm_msr_list->indices[i] == MSR_IA32_XSS) { | |
1010 | has_msr_xss = true; | |
1011 | continue; | |
1012 | } | |
1013 | if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) { | |
1014 | has_msr_hv_crash = true; | |
1015 | continue; | |
1016 | } | |
1017 | if (kvm_msr_list->indices[i] == HV_X64_MSR_RESET) { | |
1018 | has_msr_hv_reset = true; | |
1019 | continue; | |
1020 | } | |
1021 | if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_INDEX) { | |
1022 | has_msr_hv_vpindex = true; | |
1023 | continue; | |
1024 | } | |
1025 | if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_RUNTIME) { | |
1026 | has_msr_hv_runtime = true; | |
1027 | continue; | |
1028 | } | |
1029 | if (kvm_msr_list->indices[i] == HV_X64_MSR_SCONTROL) { | |
1030 | has_msr_hv_synic = true; | |
1031 | continue; | |
1032 | } | |
1033 | if (kvm_msr_list->indices[i] == HV_X64_MSR_STIMER0_CONFIG) { | |
1034 | has_msr_hv_stimer = true; | |
1035 | continue; | |
1036 | } | |
1037 | } | |
1038 | } | |
1039 | ||
1040 | g_free(kvm_msr_list); | |
1041 | } | |
1042 | ||
1043 | return ret; | |
1044 | } | |
1045 | ||
1046 | static Notifier smram_machine_done; | |
1047 | static KVMMemoryListener smram_listener; | |
1048 | static AddressSpace smram_address_space; | |
1049 | static MemoryRegion smram_as_root; | |
1050 | static MemoryRegion smram_as_mem; | |
1051 | ||
1052 | static void register_smram_listener(Notifier *n, void *unused) | |
1053 | { | |
1054 | MemoryRegion *smram = | |
1055 | (MemoryRegion *) object_resolve_path("/machine/smram", NULL); | |
1056 | ||
1057 | /* Outer container... */ | |
1058 | memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull); | |
1059 | memory_region_set_enabled(&smram_as_root, true); | |
1060 | ||
1061 | /* ... with two regions inside: normal system memory with low | |
1062 | * priority, and... | |
1063 | */ | |
1064 | memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram", | |
1065 | get_system_memory(), 0, ~0ull); | |
1066 | memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0); | |
1067 | memory_region_set_enabled(&smram_as_mem, true); | |
1068 | ||
1069 | if (smram) { | |
1070 | /* ... SMRAM with higher priority */ | |
1071 | memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10); | |
1072 | memory_region_set_enabled(smram, true); | |
1073 | } | |
1074 | ||
1075 | address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM"); | |
1076 | kvm_memory_listener_register(kvm_state, &smram_listener, | |
1077 | &smram_address_space, 1); | |
1078 | } | |
1079 | ||
1080 | int kvm_arch_init(MachineState *ms, KVMState *s) | |
1081 | { | |
1082 | uint64_t identity_base = 0xfffbc000; | |
1083 | uint64_t shadow_mem; | |
1084 | int ret; | |
1085 | struct utsname utsname; | |
1086 | ||
1087 | #ifdef KVM_CAP_XSAVE | |
1088 | has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE); | |
1089 | #endif | |
1090 | ||
1091 | #ifdef KVM_CAP_XCRS | |
1092 | has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS); | |
1093 | #endif | |
1094 | ||
1095 | #ifdef KVM_CAP_PIT_STATE2 | |
1096 | has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2); | |
1097 | #endif | |
1098 | ||
1099 | ret = kvm_get_supported_msrs(s); | |
1100 | if (ret < 0) { | |
1101 | return ret; | |
1102 | } | |
1103 | ||
1104 | uname(&utsname); | |
1105 | lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0; | |
1106 | ||
1107 | /* | |
1108 | * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly. | |
1109 | * In order to use vm86 mode, an EPT identity map and a TSS are needed. | |
1110 | * Since these must be part of guest physical memory, we need to allocate | |
1111 | * them, both by setting their start addresses in the kernel and by | |
1112 | * creating a corresponding e820 entry. We need 4 pages before the BIOS. | |
1113 | * | |
1114 | * Older KVM versions may not support setting the identity map base. In | |
1115 | * that case we need to stick with the default, i.e. a 256K maximum BIOS | |
1116 | * size. | |
1117 | */ | |
1118 | if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) { | |
1119 | /* Allows up to 16M BIOSes. */ | |
1120 | identity_base = 0xfeffc000; | |
1121 | ||
1122 | ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base); | |
1123 | if (ret < 0) { | |
1124 | return ret; | |
1125 | } | |
1126 | } | |
1127 | ||
1128 | /* Set TSS base one page after EPT identity map. */ | |
1129 | ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000); | |
1130 | if (ret < 0) { | |
1131 | return ret; | |
1132 | } | |
1133 | ||
1134 | /* Tell fw_cfg to notify the BIOS to reserve the range. */ | |
1135 | ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED); | |
1136 | if (ret < 0) { | |
1137 | fprintf(stderr, "e820_add_entry() table is full\n"); | |
1138 | return ret; | |
1139 | } | |
1140 | qemu_register_reset(kvm_unpoison_all, NULL); | |
1141 | ||
1142 | shadow_mem = machine_kvm_shadow_mem(ms); | |
1143 | if (shadow_mem != -1) { | |
1144 | shadow_mem /= 4096; | |
1145 | ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem); | |
1146 | if (ret < 0) { | |
1147 | return ret; | |
1148 | } | |
1149 | } | |
1150 | ||
1151 | if (kvm_check_extension(s, KVM_CAP_X86_SMM)) { | |
1152 | smram_machine_done.notify = register_smram_listener; | |
1153 | qemu_add_machine_init_done_notifier(&smram_machine_done); | |
1154 | } | |
1155 | return 0; | |
1156 | } | |
1157 | ||
1158 | static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs) | |
1159 | { | |
1160 | lhs->selector = rhs->selector; | |
1161 | lhs->base = rhs->base; | |
1162 | lhs->limit = rhs->limit; | |
1163 | lhs->type = 3; | |
1164 | lhs->present = 1; | |
1165 | lhs->dpl = 3; | |
1166 | lhs->db = 0; | |
1167 | lhs->s = 1; | |
1168 | lhs->l = 0; | |
1169 | lhs->g = 0; | |
1170 | lhs->avl = 0; | |
1171 | lhs->unusable = 0; | |
1172 | } | |
1173 | ||
1174 | static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs) | |
1175 | { | |
1176 | unsigned flags = rhs->flags; | |
1177 | lhs->selector = rhs->selector; | |
1178 | lhs->base = rhs->base; | |
1179 | lhs->limit = rhs->limit; | |
1180 | lhs->type = (flags >> DESC_TYPE_SHIFT) & 15; | |
1181 | lhs->present = (flags & DESC_P_MASK) != 0; | |
1182 | lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3; | |
1183 | lhs->db = (flags >> DESC_B_SHIFT) & 1; | |
1184 | lhs->s = (flags & DESC_S_MASK) != 0; | |
1185 | lhs->l = (flags >> DESC_L_SHIFT) & 1; | |
1186 | lhs->g = (flags & DESC_G_MASK) != 0; | |
1187 | lhs->avl = (flags & DESC_AVL_MASK) != 0; | |
1188 | lhs->unusable = !lhs->present; | |
1189 | lhs->padding = 0; | |
1190 | } | |
1191 | ||
1192 | static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs) | |
1193 | { | |
1194 | lhs->selector = rhs->selector; | |
1195 | lhs->base = rhs->base; | |
1196 | lhs->limit = rhs->limit; | |
1197 | if (rhs->unusable) { | |
1198 | lhs->flags = 0; | |
1199 | } else { | |
1200 | lhs->flags = (rhs->type << DESC_TYPE_SHIFT) | | |
1201 | (rhs->present * DESC_P_MASK) | | |
1202 | (rhs->dpl << DESC_DPL_SHIFT) | | |
1203 | (rhs->db << DESC_B_SHIFT) | | |
1204 | (rhs->s * DESC_S_MASK) | | |
1205 | (rhs->l << DESC_L_SHIFT) | | |
1206 | (rhs->g * DESC_G_MASK) | | |
1207 | (rhs->avl * DESC_AVL_MASK); | |
1208 | } | |
1209 | } | |
1210 | ||
1211 | static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set) | |
1212 | { | |
1213 | if (set) { | |
1214 | *kvm_reg = *qemu_reg; | |
1215 | } else { | |
1216 | *qemu_reg = *kvm_reg; | |
1217 | } | |
1218 | } | |
1219 | ||
1220 | static int kvm_getput_regs(X86CPU *cpu, int set) | |
1221 | { | |
1222 | CPUX86State *env = &cpu->env; | |
1223 | struct kvm_regs regs; | |
1224 | int ret = 0; | |
1225 | ||
1226 | if (!set) { | |
1227 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, ®s); | |
1228 | if (ret < 0) { | |
1229 | return ret; | |
1230 | } | |
1231 | } | |
1232 | ||
1233 | kvm_getput_reg(®s.rax, &env->regs[R_EAX], set); | |
1234 | kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set); | |
1235 | kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set); | |
1236 | kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set); | |
1237 | kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set); | |
1238 | kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set); | |
1239 | kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set); | |
1240 | kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set); | |
1241 | #ifdef TARGET_X86_64 | |
1242 | kvm_getput_reg(®s.r8, &env->regs[8], set); | |
1243 | kvm_getput_reg(®s.r9, &env->regs[9], set); | |
1244 | kvm_getput_reg(®s.r10, &env->regs[10], set); | |
1245 | kvm_getput_reg(®s.r11, &env->regs[11], set); | |
1246 | kvm_getput_reg(®s.r12, &env->regs[12], set); | |
1247 | kvm_getput_reg(®s.r13, &env->regs[13], set); | |
1248 | kvm_getput_reg(®s.r14, &env->regs[14], set); | |
1249 | kvm_getput_reg(®s.r15, &env->regs[15], set); | |
1250 | #endif | |
1251 | ||
1252 | kvm_getput_reg(®s.rflags, &env->eflags, set); | |
1253 | kvm_getput_reg(®s.rip, &env->eip, set); | |
1254 | ||
1255 | if (set) { | |
1256 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, ®s); | |
1257 | } | |
1258 | ||
1259 | return ret; | |
1260 | } | |
1261 | ||
1262 | static int kvm_put_fpu(X86CPU *cpu) | |
1263 | { | |
1264 | CPUX86State *env = &cpu->env; | |
1265 | struct kvm_fpu fpu; | |
1266 | int i; | |
1267 | ||
1268 | memset(&fpu, 0, sizeof fpu); | |
1269 | fpu.fsw = env->fpus & ~(7 << 11); | |
1270 | fpu.fsw |= (env->fpstt & 7) << 11; | |
1271 | fpu.fcw = env->fpuc; | |
1272 | fpu.last_opcode = env->fpop; | |
1273 | fpu.last_ip = env->fpip; | |
1274 | fpu.last_dp = env->fpdp; | |
1275 | for (i = 0; i < 8; ++i) { | |
1276 | fpu.ftwx |= (!env->fptags[i]) << i; | |
1277 | } | |
1278 | memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs); | |
1279 | for (i = 0; i < CPU_NB_REGS; i++) { | |
1280 | stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0)); | |
1281 | stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1)); | |
1282 | } | |
1283 | fpu.mxcsr = env->mxcsr; | |
1284 | ||
1285 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu); | |
1286 | } | |
1287 | ||
1288 | #define XSAVE_FCW_FSW 0 | |
1289 | #define XSAVE_FTW_FOP 1 | |
1290 | #define XSAVE_CWD_RIP 2 | |
1291 | #define XSAVE_CWD_RDP 4 | |
1292 | #define XSAVE_MXCSR 6 | |
1293 | #define XSAVE_ST_SPACE 8 | |
1294 | #define XSAVE_XMM_SPACE 40 | |
1295 | #define XSAVE_XSTATE_BV 128 | |
1296 | #define XSAVE_YMMH_SPACE 144 | |
1297 | #define XSAVE_BNDREGS 240 | |
1298 | #define XSAVE_BNDCSR 256 | |
1299 | #define XSAVE_OPMASK 272 | |
1300 | #define XSAVE_ZMM_Hi256 288 | |
1301 | #define XSAVE_Hi16_ZMM 416 | |
1302 | #define XSAVE_PKRU 672 | |
1303 | ||
1304 | static int kvm_put_xsave(X86CPU *cpu) | |
1305 | { | |
1306 | CPUX86State *env = &cpu->env; | |
1307 | struct kvm_xsave* xsave = env->kvm_xsave_buf; | |
1308 | uint16_t cwd, swd, twd; | |
1309 | uint8_t *xmm, *ymmh, *zmmh; | |
1310 | int i, r; | |
1311 | ||
1312 | if (!has_xsave) { | |
1313 | return kvm_put_fpu(cpu); | |
1314 | } | |
1315 | ||
1316 | memset(xsave, 0, sizeof(struct kvm_xsave)); | |
1317 | twd = 0; | |
1318 | swd = env->fpus & ~(7 << 11); | |
1319 | swd |= (env->fpstt & 7) << 11; | |
1320 | cwd = env->fpuc; | |
1321 | for (i = 0; i < 8; ++i) { | |
1322 | twd |= (!env->fptags[i]) << i; | |
1323 | } | |
1324 | xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd; | |
1325 | xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd; | |
1326 | memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip)); | |
1327 | memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp)); | |
1328 | memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs, | |
1329 | sizeof env->fpregs); | |
1330 | xsave->region[XSAVE_MXCSR] = env->mxcsr; | |
1331 | *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv; | |
1332 | memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs, | |
1333 | sizeof env->bnd_regs); | |
1334 | memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs, | |
1335 | sizeof(env->bndcs_regs)); | |
1336 | memcpy(&xsave->region[XSAVE_OPMASK], env->opmask_regs, | |
1337 | sizeof env->opmask_regs); | |
1338 | ||
1339 | xmm = (uint8_t *)&xsave->region[XSAVE_XMM_SPACE]; | |
1340 | ymmh = (uint8_t *)&xsave->region[XSAVE_YMMH_SPACE]; | |
1341 | zmmh = (uint8_t *)&xsave->region[XSAVE_ZMM_Hi256]; | |
1342 | for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) { | |
1343 | stq_p(xmm, env->xmm_regs[i].ZMM_Q(0)); | |
1344 | stq_p(xmm+8, env->xmm_regs[i].ZMM_Q(1)); | |
1345 | stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2)); | |
1346 | stq_p(ymmh+8, env->xmm_regs[i].ZMM_Q(3)); | |
1347 | stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4)); | |
1348 | stq_p(zmmh+8, env->xmm_regs[i].ZMM_Q(5)); | |
1349 | stq_p(zmmh+16, env->xmm_regs[i].ZMM_Q(6)); | |
1350 | stq_p(zmmh+24, env->xmm_regs[i].ZMM_Q(7)); | |
1351 | } | |
1352 | ||
1353 | #ifdef TARGET_X86_64 | |
1354 | memcpy(&xsave->region[XSAVE_Hi16_ZMM], &env->xmm_regs[16], | |
1355 | 16 * sizeof env->xmm_regs[16]); | |
1356 | memcpy(&xsave->region[XSAVE_PKRU], &env->pkru, sizeof env->pkru); | |
1357 | #endif | |
1358 | r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave); | |
1359 | return r; | |
1360 | } | |
1361 | ||
1362 | static int kvm_put_xcrs(X86CPU *cpu) | |
1363 | { | |
1364 | CPUX86State *env = &cpu->env; | |
1365 | struct kvm_xcrs xcrs = {}; | |
1366 | ||
1367 | if (!has_xcrs) { | |
1368 | return 0; | |
1369 | } | |
1370 | ||
1371 | xcrs.nr_xcrs = 1; | |
1372 | xcrs.flags = 0; | |
1373 | xcrs.xcrs[0].xcr = 0; | |
1374 | xcrs.xcrs[0].value = env->xcr0; | |
1375 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs); | |
1376 | } | |
1377 | ||
1378 | static int kvm_put_sregs(X86CPU *cpu) | |
1379 | { | |
1380 | CPUX86State *env = &cpu->env; | |
1381 | struct kvm_sregs sregs; | |
1382 | ||
1383 | memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap)); | |
1384 | if (env->interrupt_injected >= 0) { | |
1385 | sregs.interrupt_bitmap[env->interrupt_injected / 64] |= | |
1386 | (uint64_t)1 << (env->interrupt_injected % 64); | |
1387 | } | |
1388 | ||
1389 | if ((env->eflags & VM_MASK)) { | |
1390 | set_v8086_seg(&sregs.cs, &env->segs[R_CS]); | |
1391 | set_v8086_seg(&sregs.ds, &env->segs[R_DS]); | |
1392 | set_v8086_seg(&sregs.es, &env->segs[R_ES]); | |
1393 | set_v8086_seg(&sregs.fs, &env->segs[R_FS]); | |
1394 | set_v8086_seg(&sregs.gs, &env->segs[R_GS]); | |
1395 | set_v8086_seg(&sregs.ss, &env->segs[R_SS]); | |
1396 | } else { | |
1397 | set_seg(&sregs.cs, &env->segs[R_CS]); | |
1398 | set_seg(&sregs.ds, &env->segs[R_DS]); | |
1399 | set_seg(&sregs.es, &env->segs[R_ES]); | |
1400 | set_seg(&sregs.fs, &env->segs[R_FS]); | |
1401 | set_seg(&sregs.gs, &env->segs[R_GS]); | |
1402 | set_seg(&sregs.ss, &env->segs[R_SS]); | |
1403 | } | |
1404 | ||
1405 | set_seg(&sregs.tr, &env->tr); | |
1406 | set_seg(&sregs.ldt, &env->ldt); | |
1407 | ||
1408 | sregs.idt.limit = env->idt.limit; | |
1409 | sregs.idt.base = env->idt.base; | |
1410 | memset(sregs.idt.padding, 0, sizeof sregs.idt.padding); | |
1411 | sregs.gdt.limit = env->gdt.limit; | |
1412 | sregs.gdt.base = env->gdt.base; | |
1413 | memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding); | |
1414 | ||
1415 | sregs.cr0 = env->cr[0]; | |
1416 | sregs.cr2 = env->cr[2]; | |
1417 | sregs.cr3 = env->cr[3]; | |
1418 | sregs.cr4 = env->cr[4]; | |
1419 | ||
1420 | sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state); | |
1421 | sregs.apic_base = cpu_get_apic_base(cpu->apic_state); | |
1422 | ||
1423 | sregs.efer = env->efer; | |
1424 | ||
1425 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs); | |
1426 | } | |
1427 | ||
1428 | static void kvm_msr_entry_set(struct kvm_msr_entry *entry, | |
1429 | uint32_t index, uint64_t value) | |
1430 | { | |
1431 | entry->index = index; | |
1432 | entry->reserved = 0; | |
1433 | entry->data = value; | |
1434 | } | |
1435 | ||
1436 | static int kvm_put_tscdeadline_msr(X86CPU *cpu) | |
1437 | { | |
1438 | CPUX86State *env = &cpu->env; | |
1439 | struct { | |
1440 | struct kvm_msrs info; | |
1441 | struct kvm_msr_entry entries[1]; | |
1442 | } msr_data; | |
1443 | struct kvm_msr_entry *msrs = msr_data.entries; | |
1444 | ||
1445 | if (!has_msr_tsc_deadline) { | |
1446 | return 0; | |
1447 | } | |
1448 | ||
1449 | kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline); | |
1450 | ||
1451 | msr_data.info = (struct kvm_msrs) { | |
1452 | .nmsrs = 1, | |
1453 | }; | |
1454 | ||
1455 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data); | |
1456 | } | |
1457 | ||
1458 | /* | |
1459 | * Provide a separate write service for the feature control MSR in order to | |
1460 | * kick the VCPU out of VMXON or even guest mode on reset. This has to be done | |
1461 | * before writing any other state because forcibly leaving nested mode | |
1462 | * invalidates the VCPU state. | |
1463 | */ | |
1464 | static int kvm_put_msr_feature_control(X86CPU *cpu) | |
1465 | { | |
1466 | struct { | |
1467 | struct kvm_msrs info; | |
1468 | struct kvm_msr_entry entry; | |
1469 | } msr_data; | |
1470 | ||
1471 | kvm_msr_entry_set(&msr_data.entry, MSR_IA32_FEATURE_CONTROL, | |
1472 | cpu->env.msr_ia32_feature_control); | |
1473 | ||
1474 | msr_data.info = (struct kvm_msrs) { | |
1475 | .nmsrs = 1, | |
1476 | }; | |
1477 | ||
1478 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data); | |
1479 | } | |
1480 | ||
1481 | static int kvm_put_msrs(X86CPU *cpu, int level) | |
1482 | { | |
1483 | CPUX86State *env = &cpu->env; | |
1484 | struct { | |
1485 | struct kvm_msrs info; | |
1486 | struct kvm_msr_entry entries[150]; | |
1487 | } msr_data; | |
1488 | struct kvm_msr_entry *msrs = msr_data.entries; | |
1489 | int n = 0, i; | |
1490 | ||
1491 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs); | |
1492 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp); | |
1493 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip); | |
1494 | kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat); | |
1495 | if (has_msr_star) { | |
1496 | kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star); | |
1497 | } | |
1498 | if (has_msr_hsave_pa) { | |
1499 | kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave); | |
1500 | } | |
1501 | if (has_msr_tsc_aux) { | |
1502 | kvm_msr_entry_set(&msrs[n++], MSR_TSC_AUX, env->tsc_aux); | |
1503 | } | |
1504 | if (has_msr_tsc_adjust) { | |
1505 | kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust); | |
1506 | } | |
1507 | if (has_msr_misc_enable) { | |
1508 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE, | |
1509 | env->msr_ia32_misc_enable); | |
1510 | } | |
1511 | if (has_msr_smbase) { | |
1512 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SMBASE, env->smbase); | |
1513 | } | |
1514 | if (has_msr_bndcfgs) { | |
1515 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs); | |
1516 | } | |
1517 | if (has_msr_xss) { | |
1518 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_XSS, env->xss); | |
1519 | } | |
1520 | #ifdef TARGET_X86_64 | |
1521 | if (lm_capable_kernel) { | |
1522 | kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar); | |
1523 | kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase); | |
1524 | kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask); | |
1525 | kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar); | |
1526 | } | |
1527 | #endif | |
1528 | /* | |
1529 | * The following MSRs have side effects on the guest or are too heavy | |
1530 | * for normal writeback. Limit them to reset or full state updates. | |
1531 | */ | |
1532 | if (level >= KVM_PUT_RESET_STATE) { | |
1533 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc); | |
1534 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME, | |
1535 | env->system_time_msr); | |
1536 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr); | |
1537 | if (has_msr_async_pf_en) { | |
1538 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN, | |
1539 | env->async_pf_en_msr); | |
1540 | } | |
1541 | if (has_msr_pv_eoi_en) { | |
1542 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN, | |
1543 | env->pv_eoi_en_msr); | |
1544 | } | |
1545 | if (has_msr_kvm_steal_time) { | |
1546 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME, | |
1547 | env->steal_time_msr); | |
1548 | } | |
1549 | if (has_msr_architectural_pmu) { | |
1550 | /* Stop the counter. */ | |
1551 | kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0); | |
1552 | kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0); | |
1553 | ||
1554 | /* Set the counter values. */ | |
1555 | for (i = 0; i < MAX_FIXED_COUNTERS; i++) { | |
1556 | kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i, | |
1557 | env->msr_fixed_counters[i]); | |
1558 | } | |
1559 | for (i = 0; i < num_architectural_pmu_counters; i++) { | |
1560 | kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i, | |
1561 | env->msr_gp_counters[i]); | |
1562 | kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i, | |
1563 | env->msr_gp_evtsel[i]); | |
1564 | } | |
1565 | kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS, | |
1566 | env->msr_global_status); | |
1567 | kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL, | |
1568 | env->msr_global_ovf_ctrl); | |
1569 | ||
1570 | /* Now start the PMU. */ | |
1571 | kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, | |
1572 | env->msr_fixed_ctr_ctrl); | |
1573 | kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, | |
1574 | env->msr_global_ctrl); | |
1575 | } | |
1576 | if (has_msr_hv_hypercall) { | |
1577 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID, | |
1578 | env->msr_hv_guest_os_id); | |
1579 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL, | |
1580 | env->msr_hv_hypercall); | |
1581 | } | |
1582 | if (has_msr_hv_vapic) { | |
1583 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, | |
1584 | env->msr_hv_vapic); | |
1585 | } | |
1586 | if (has_msr_hv_tsc) { | |
1587 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_REFERENCE_TSC, | |
1588 | env->msr_hv_tsc); | |
1589 | } | |
1590 | if (has_msr_hv_crash) { | |
1591 | int j; | |
1592 | ||
1593 | for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) | |
1594 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_CRASH_P0 + j, | |
1595 | env->msr_hv_crash_params[j]); | |
1596 | ||
1597 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_CRASH_CTL, | |
1598 | HV_X64_MSR_CRASH_CTL_NOTIFY); | |
1599 | } | |
1600 | if (has_msr_hv_runtime) { | |
1601 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_VP_RUNTIME, | |
1602 | env->msr_hv_runtime); | |
1603 | } | |
1604 | if (cpu->hyperv_synic) { | |
1605 | int j; | |
1606 | ||
1607 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SCONTROL, | |
1608 | env->msr_hv_synic_control); | |
1609 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SVERSION, | |
1610 | env->msr_hv_synic_version); | |
1611 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SIEFP, | |
1612 | env->msr_hv_synic_evt_page); | |
1613 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SIMP, | |
1614 | env->msr_hv_synic_msg_page); | |
1615 | ||
1616 | for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) { | |
1617 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SINT0 + j, | |
1618 | env->msr_hv_synic_sint[j]); | |
1619 | } | |
1620 | } | |
1621 | if (has_msr_hv_stimer) { | |
1622 | int j; | |
1623 | ||
1624 | for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) { | |
1625 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_STIMER0_CONFIG + j*2, | |
1626 | env->msr_hv_stimer_config[j]); | |
1627 | } | |
1628 | ||
1629 | for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) { | |
1630 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_STIMER0_COUNT + j*2, | |
1631 | env->msr_hv_stimer_count[j]); | |
1632 | } | |
1633 | } | |
1634 | if (has_msr_mtrr) { | |
1635 | kvm_msr_entry_set(&msrs[n++], MSR_MTRRdefType, env->mtrr_deftype); | |
1636 | kvm_msr_entry_set(&msrs[n++], | |
1637 | MSR_MTRRfix64K_00000, env->mtrr_fixed[0]); | |
1638 | kvm_msr_entry_set(&msrs[n++], | |
1639 | MSR_MTRRfix16K_80000, env->mtrr_fixed[1]); | |
1640 | kvm_msr_entry_set(&msrs[n++], | |
1641 | MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]); | |
1642 | kvm_msr_entry_set(&msrs[n++], | |
1643 | MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]); | |
1644 | kvm_msr_entry_set(&msrs[n++], | |
1645 | MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]); | |
1646 | kvm_msr_entry_set(&msrs[n++], | |
1647 | MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]); | |
1648 | kvm_msr_entry_set(&msrs[n++], | |
1649 | MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]); | |
1650 | kvm_msr_entry_set(&msrs[n++], | |
1651 | MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]); | |
1652 | kvm_msr_entry_set(&msrs[n++], | |
1653 | MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]); | |
1654 | kvm_msr_entry_set(&msrs[n++], | |
1655 | MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]); | |
1656 | kvm_msr_entry_set(&msrs[n++], | |
1657 | MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]); | |
1658 | for (i = 0; i < MSR_MTRRcap_VCNT; i++) { | |
1659 | kvm_msr_entry_set(&msrs[n++], | |
1660 | MSR_MTRRphysBase(i), env->mtrr_var[i].base); | |
1661 | kvm_msr_entry_set(&msrs[n++], | |
1662 | MSR_MTRRphysMask(i), env->mtrr_var[i].mask); | |
1663 | } | |
1664 | } | |
1665 | ||
1666 | /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see | |
1667 | * kvm_put_msr_feature_control. */ | |
1668 | } | |
1669 | if (env->mcg_cap) { | |
1670 | int i; | |
1671 | ||
1672 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status); | |
1673 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl); | |
1674 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { | |
1675 | kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]); | |
1676 | } | |
1677 | } | |
1678 | ||
1679 | msr_data.info = (struct kvm_msrs) { | |
1680 | .nmsrs = n, | |
1681 | }; | |
1682 | ||
1683 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data); | |
1684 | ||
1685 | } | |
1686 | ||
1687 | ||
1688 | static int kvm_get_fpu(X86CPU *cpu) | |
1689 | { | |
1690 | CPUX86State *env = &cpu->env; | |
1691 | struct kvm_fpu fpu; | |
1692 | int i, ret; | |
1693 | ||
1694 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu); | |
1695 | if (ret < 0) { | |
1696 | return ret; | |
1697 | } | |
1698 | ||
1699 | env->fpstt = (fpu.fsw >> 11) & 7; | |
1700 | env->fpus = fpu.fsw; | |
1701 | env->fpuc = fpu.fcw; | |
1702 | env->fpop = fpu.last_opcode; | |
1703 | env->fpip = fpu.last_ip; | |
1704 | env->fpdp = fpu.last_dp; | |
1705 | for (i = 0; i < 8; ++i) { | |
1706 | env->fptags[i] = !((fpu.ftwx >> i) & 1); | |
1707 | } | |
1708 | memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs); | |
1709 | for (i = 0; i < CPU_NB_REGS; i++) { | |
1710 | env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]); | |
1711 | env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]); | |
1712 | } | |
1713 | env->mxcsr = fpu.mxcsr; | |
1714 | ||
1715 | return 0; | |
1716 | } | |
1717 | ||
1718 | static int kvm_get_xsave(X86CPU *cpu) | |
1719 | { | |
1720 | CPUX86State *env = &cpu->env; | |
1721 | struct kvm_xsave* xsave = env->kvm_xsave_buf; | |
1722 | int ret, i; | |
1723 | const uint8_t *xmm, *ymmh, *zmmh; | |
1724 | uint16_t cwd, swd, twd; | |
1725 | ||
1726 | if (!has_xsave) { | |
1727 | return kvm_get_fpu(cpu); | |
1728 | } | |
1729 | ||
1730 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave); | |
1731 | if (ret < 0) { | |
1732 | return ret; | |
1733 | } | |
1734 | ||
1735 | cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW]; | |
1736 | swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16); | |
1737 | twd = (uint16_t)xsave->region[XSAVE_FTW_FOP]; | |
1738 | env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16); | |
1739 | env->fpstt = (swd >> 11) & 7; | |
1740 | env->fpus = swd; | |
1741 | env->fpuc = cwd; | |
1742 | for (i = 0; i < 8; ++i) { | |
1743 | env->fptags[i] = !((twd >> i) & 1); | |
1744 | } | |
1745 | memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip)); | |
1746 | memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp)); | |
1747 | env->mxcsr = xsave->region[XSAVE_MXCSR]; | |
1748 | memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE], | |
1749 | sizeof env->fpregs); | |
1750 | env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV]; | |
1751 | memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS], | |
1752 | sizeof env->bnd_regs); | |
1753 | memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR], | |
1754 | sizeof(env->bndcs_regs)); | |
1755 | memcpy(env->opmask_regs, &xsave->region[XSAVE_OPMASK], | |
1756 | sizeof env->opmask_regs); | |
1757 | ||
1758 | xmm = (const uint8_t *)&xsave->region[XSAVE_XMM_SPACE]; | |
1759 | ymmh = (const uint8_t *)&xsave->region[XSAVE_YMMH_SPACE]; | |
1760 | zmmh = (const uint8_t *)&xsave->region[XSAVE_ZMM_Hi256]; | |
1761 | for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) { | |
1762 | env->xmm_regs[i].ZMM_Q(0) = ldq_p(xmm); | |
1763 | env->xmm_regs[i].ZMM_Q(1) = ldq_p(xmm+8); | |
1764 | env->xmm_regs[i].ZMM_Q(2) = ldq_p(ymmh); | |
1765 | env->xmm_regs[i].ZMM_Q(3) = ldq_p(ymmh+8); | |
1766 | env->xmm_regs[i].ZMM_Q(4) = ldq_p(zmmh); | |
1767 | env->xmm_regs[i].ZMM_Q(5) = ldq_p(zmmh+8); | |
1768 | env->xmm_regs[i].ZMM_Q(6) = ldq_p(zmmh+16); | |
1769 | env->xmm_regs[i].ZMM_Q(7) = ldq_p(zmmh+24); | |
1770 | } | |
1771 | ||
1772 | #ifdef TARGET_X86_64 | |
1773 | memcpy(&env->xmm_regs[16], &xsave->region[XSAVE_Hi16_ZMM], | |
1774 | 16 * sizeof env->xmm_regs[16]); | |
1775 | memcpy(&env->pkru, &xsave->region[XSAVE_PKRU], sizeof env->pkru); | |
1776 | #endif | |
1777 | return 0; | |
1778 | } | |
1779 | ||
1780 | static int kvm_get_xcrs(X86CPU *cpu) | |
1781 | { | |
1782 | CPUX86State *env = &cpu->env; | |
1783 | int i, ret; | |
1784 | struct kvm_xcrs xcrs; | |
1785 | ||
1786 | if (!has_xcrs) { | |
1787 | return 0; | |
1788 | } | |
1789 | ||
1790 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs); | |
1791 | if (ret < 0) { | |
1792 | return ret; | |
1793 | } | |
1794 | ||
1795 | for (i = 0; i < xcrs.nr_xcrs; i++) { | |
1796 | /* Only support xcr0 now */ | |
1797 | if (xcrs.xcrs[i].xcr == 0) { | |
1798 | env->xcr0 = xcrs.xcrs[i].value; | |
1799 | break; | |
1800 | } | |
1801 | } | |
1802 | return 0; | |
1803 | } | |
1804 | ||
1805 | static int kvm_get_sregs(X86CPU *cpu) | |
1806 | { | |
1807 | CPUX86State *env = &cpu->env; | |
1808 | struct kvm_sregs sregs; | |
1809 | uint32_t hflags; | |
1810 | int bit, i, ret; | |
1811 | ||
1812 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs); | |
1813 | if (ret < 0) { | |
1814 | return ret; | |
1815 | } | |
1816 | ||
1817 | /* There can only be one pending IRQ set in the bitmap at a time, so try | |
1818 | to find it and save its number instead (-1 for none). */ | |
1819 | env->interrupt_injected = -1; | |
1820 | for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) { | |
1821 | if (sregs.interrupt_bitmap[i]) { | |
1822 | bit = ctz64(sregs.interrupt_bitmap[i]); | |
1823 | env->interrupt_injected = i * 64 + bit; | |
1824 | break; | |
1825 | } | |
1826 | } | |
1827 | ||
1828 | get_seg(&env->segs[R_CS], &sregs.cs); | |
1829 | get_seg(&env->segs[R_DS], &sregs.ds); | |
1830 | get_seg(&env->segs[R_ES], &sregs.es); | |
1831 | get_seg(&env->segs[R_FS], &sregs.fs); | |
1832 | get_seg(&env->segs[R_GS], &sregs.gs); | |
1833 | get_seg(&env->segs[R_SS], &sregs.ss); | |
1834 | ||
1835 | get_seg(&env->tr, &sregs.tr); | |
1836 | get_seg(&env->ldt, &sregs.ldt); | |
1837 | ||
1838 | env->idt.limit = sregs.idt.limit; | |
1839 | env->idt.base = sregs.idt.base; | |
1840 | env->gdt.limit = sregs.gdt.limit; | |
1841 | env->gdt.base = sregs.gdt.base; | |
1842 | ||
1843 | env->cr[0] = sregs.cr0; | |
1844 | env->cr[2] = sregs.cr2; | |
1845 | env->cr[3] = sregs.cr3; | |
1846 | env->cr[4] = sregs.cr4; | |
1847 | ||
1848 | env->efer = sregs.efer; | |
1849 | ||
1850 | /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */ | |
1851 | ||
1852 | #define HFLAG_COPY_MASK \ | |
1853 | ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ | |
1854 | HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ | |
1855 | HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ | |
1856 | HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) | |
1857 | ||
1858 | hflags = env->hflags & HFLAG_COPY_MASK; | |
1859 | hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; | |
1860 | hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); | |
1861 | hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & | |
1862 | (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); | |
1863 | hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); | |
1864 | ||
1865 | if (env->cr[4] & CR4_OSFXSR_MASK) { | |
1866 | hflags |= HF_OSFXSR_MASK; | |
1867 | } | |
1868 | ||
1869 | if (env->efer & MSR_EFER_LMA) { | |
1870 | hflags |= HF_LMA_MASK; | |
1871 | } | |
1872 | ||
1873 | if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { | |
1874 | hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; | |
1875 | } else { | |
1876 | hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> | |
1877 | (DESC_B_SHIFT - HF_CS32_SHIFT); | |
1878 | hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> | |
1879 | (DESC_B_SHIFT - HF_SS32_SHIFT); | |
1880 | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || | |
1881 | !(hflags & HF_CS32_MASK)) { | |
1882 | hflags |= HF_ADDSEG_MASK; | |
1883 | } else { | |
1884 | hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | | |
1885 | env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; | |
1886 | } | |
1887 | } | |
1888 | env->hflags = hflags; | |
1889 | ||
1890 | return 0; | |
1891 | } | |
1892 | ||
1893 | static int kvm_get_msrs(X86CPU *cpu) | |
1894 | { | |
1895 | CPUX86State *env = &cpu->env; | |
1896 | struct { | |
1897 | struct kvm_msrs info; | |
1898 | struct kvm_msr_entry entries[150]; | |
1899 | } msr_data; | |
1900 | struct kvm_msr_entry *msrs = msr_data.entries; | |
1901 | int ret, i, n; | |
1902 | ||
1903 | n = 0; | |
1904 | msrs[n++].index = MSR_IA32_SYSENTER_CS; | |
1905 | msrs[n++].index = MSR_IA32_SYSENTER_ESP; | |
1906 | msrs[n++].index = MSR_IA32_SYSENTER_EIP; | |
1907 | msrs[n++].index = MSR_PAT; | |
1908 | if (has_msr_star) { | |
1909 | msrs[n++].index = MSR_STAR; | |
1910 | } | |
1911 | if (has_msr_hsave_pa) { | |
1912 | msrs[n++].index = MSR_VM_HSAVE_PA; | |
1913 | } | |
1914 | if (has_msr_tsc_aux) { | |
1915 | msrs[n++].index = MSR_TSC_AUX; | |
1916 | } | |
1917 | if (has_msr_tsc_adjust) { | |
1918 | msrs[n++].index = MSR_TSC_ADJUST; | |
1919 | } | |
1920 | if (has_msr_tsc_deadline) { | |
1921 | msrs[n++].index = MSR_IA32_TSCDEADLINE; | |
1922 | } | |
1923 | if (has_msr_misc_enable) { | |
1924 | msrs[n++].index = MSR_IA32_MISC_ENABLE; | |
1925 | } | |
1926 | if (has_msr_smbase) { | |
1927 | msrs[n++].index = MSR_IA32_SMBASE; | |
1928 | } | |
1929 | if (has_msr_feature_control) { | |
1930 | msrs[n++].index = MSR_IA32_FEATURE_CONTROL; | |
1931 | } | |
1932 | if (has_msr_bndcfgs) { | |
1933 | msrs[n++].index = MSR_IA32_BNDCFGS; | |
1934 | } | |
1935 | if (has_msr_xss) { | |
1936 | msrs[n++].index = MSR_IA32_XSS; | |
1937 | } | |
1938 | ||
1939 | ||
1940 | if (!env->tsc_valid) { | |
1941 | msrs[n++].index = MSR_IA32_TSC; | |
1942 | env->tsc_valid = !runstate_is_running(); | |
1943 | } | |
1944 | ||
1945 | #ifdef TARGET_X86_64 | |
1946 | if (lm_capable_kernel) { | |
1947 | msrs[n++].index = MSR_CSTAR; | |
1948 | msrs[n++].index = MSR_KERNELGSBASE; | |
1949 | msrs[n++].index = MSR_FMASK; | |
1950 | msrs[n++].index = MSR_LSTAR; | |
1951 | } | |
1952 | #endif | |
1953 | msrs[n++].index = MSR_KVM_SYSTEM_TIME; | |
1954 | msrs[n++].index = MSR_KVM_WALL_CLOCK; | |
1955 | if (has_msr_async_pf_en) { | |
1956 | msrs[n++].index = MSR_KVM_ASYNC_PF_EN; | |
1957 | } | |
1958 | if (has_msr_pv_eoi_en) { | |
1959 | msrs[n++].index = MSR_KVM_PV_EOI_EN; | |
1960 | } | |
1961 | if (has_msr_kvm_steal_time) { | |
1962 | msrs[n++].index = MSR_KVM_STEAL_TIME; | |
1963 | } | |
1964 | if (has_msr_architectural_pmu) { | |
1965 | msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL; | |
1966 | msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL; | |
1967 | msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS; | |
1968 | msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL; | |
1969 | for (i = 0; i < MAX_FIXED_COUNTERS; i++) { | |
1970 | msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i; | |
1971 | } | |
1972 | for (i = 0; i < num_architectural_pmu_counters; i++) { | |
1973 | msrs[n++].index = MSR_P6_PERFCTR0 + i; | |
1974 | msrs[n++].index = MSR_P6_EVNTSEL0 + i; | |
1975 | } | |
1976 | } | |
1977 | ||
1978 | if (env->mcg_cap) { | |
1979 | msrs[n++].index = MSR_MCG_STATUS; | |
1980 | msrs[n++].index = MSR_MCG_CTL; | |
1981 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { | |
1982 | msrs[n++].index = MSR_MC0_CTL + i; | |
1983 | } | |
1984 | } | |
1985 | ||
1986 | if (has_msr_hv_hypercall) { | |
1987 | msrs[n++].index = HV_X64_MSR_HYPERCALL; | |
1988 | msrs[n++].index = HV_X64_MSR_GUEST_OS_ID; | |
1989 | } | |
1990 | if (has_msr_hv_vapic) { | |
1991 | msrs[n++].index = HV_X64_MSR_APIC_ASSIST_PAGE; | |
1992 | } | |
1993 | if (has_msr_hv_tsc) { | |
1994 | msrs[n++].index = HV_X64_MSR_REFERENCE_TSC; | |
1995 | } | |
1996 | if (has_msr_hv_crash) { | |
1997 | int j; | |
1998 | ||
1999 | for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) { | |
2000 | msrs[n++].index = HV_X64_MSR_CRASH_P0 + j; | |
2001 | } | |
2002 | } | |
2003 | if (has_msr_hv_runtime) { | |
2004 | msrs[n++].index = HV_X64_MSR_VP_RUNTIME; | |
2005 | } | |
2006 | if (cpu->hyperv_synic) { | |
2007 | uint32_t msr; | |
2008 | ||
2009 | msrs[n++].index = HV_X64_MSR_SCONTROL; | |
2010 | msrs[n++].index = HV_X64_MSR_SVERSION; | |
2011 | msrs[n++].index = HV_X64_MSR_SIEFP; | |
2012 | msrs[n++].index = HV_X64_MSR_SIMP; | |
2013 | for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) { | |
2014 | msrs[n++].index = msr; | |
2015 | } | |
2016 | } | |
2017 | if (has_msr_hv_stimer) { | |
2018 | uint32_t msr; | |
2019 | ||
2020 | for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT; | |
2021 | msr++) { | |
2022 | msrs[n++].index = msr; | |
2023 | } | |
2024 | } | |
2025 | if (has_msr_mtrr) { | |
2026 | msrs[n++].index = MSR_MTRRdefType; | |
2027 | msrs[n++].index = MSR_MTRRfix64K_00000; | |
2028 | msrs[n++].index = MSR_MTRRfix16K_80000; | |
2029 | msrs[n++].index = MSR_MTRRfix16K_A0000; | |
2030 | msrs[n++].index = MSR_MTRRfix4K_C0000; | |
2031 | msrs[n++].index = MSR_MTRRfix4K_C8000; | |
2032 | msrs[n++].index = MSR_MTRRfix4K_D0000; | |
2033 | msrs[n++].index = MSR_MTRRfix4K_D8000; | |
2034 | msrs[n++].index = MSR_MTRRfix4K_E0000; | |
2035 | msrs[n++].index = MSR_MTRRfix4K_E8000; | |
2036 | msrs[n++].index = MSR_MTRRfix4K_F0000; | |
2037 | msrs[n++].index = MSR_MTRRfix4K_F8000; | |
2038 | for (i = 0; i < MSR_MTRRcap_VCNT; i++) { | |
2039 | msrs[n++].index = MSR_MTRRphysBase(i); | |
2040 | msrs[n++].index = MSR_MTRRphysMask(i); | |
2041 | } | |
2042 | } | |
2043 | ||
2044 | msr_data.info = (struct kvm_msrs) { | |
2045 | .nmsrs = n, | |
2046 | }; | |
2047 | ||
2048 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data); | |
2049 | if (ret < 0) { | |
2050 | return ret; | |
2051 | } | |
2052 | ||
2053 | for (i = 0; i < ret; i++) { | |
2054 | uint32_t index = msrs[i].index; | |
2055 | switch (index) { | |
2056 | case MSR_IA32_SYSENTER_CS: | |
2057 | env->sysenter_cs = msrs[i].data; | |
2058 | break; | |
2059 | case MSR_IA32_SYSENTER_ESP: | |
2060 | env->sysenter_esp = msrs[i].data; | |
2061 | break; | |
2062 | case MSR_IA32_SYSENTER_EIP: | |
2063 | env->sysenter_eip = msrs[i].data; | |
2064 | break; | |
2065 | case MSR_PAT: | |
2066 | env->pat = msrs[i].data; | |
2067 | break; | |
2068 | case MSR_STAR: | |
2069 | env->star = msrs[i].data; | |
2070 | break; | |
2071 | #ifdef TARGET_X86_64 | |
2072 | case MSR_CSTAR: | |
2073 | env->cstar = msrs[i].data; | |
2074 | break; | |
2075 | case MSR_KERNELGSBASE: | |
2076 | env->kernelgsbase = msrs[i].data; | |
2077 | break; | |
2078 | case MSR_FMASK: | |
2079 | env->fmask = msrs[i].data; | |
2080 | break; | |
2081 | case MSR_LSTAR: | |
2082 | env->lstar = msrs[i].data; | |
2083 | break; | |
2084 | #endif | |
2085 | case MSR_IA32_TSC: | |
2086 | env->tsc = msrs[i].data; | |
2087 | break; | |
2088 | case MSR_TSC_AUX: | |
2089 | env->tsc_aux = msrs[i].data; | |
2090 | break; | |
2091 | case MSR_TSC_ADJUST: | |
2092 | env->tsc_adjust = msrs[i].data; | |
2093 | break; | |
2094 | case MSR_IA32_TSCDEADLINE: | |
2095 | env->tsc_deadline = msrs[i].data; | |
2096 | break; | |
2097 | case MSR_VM_HSAVE_PA: | |
2098 | env->vm_hsave = msrs[i].data; | |
2099 | break; | |
2100 | case MSR_KVM_SYSTEM_TIME: | |
2101 | env->system_time_msr = msrs[i].data; | |
2102 | break; | |
2103 | case MSR_KVM_WALL_CLOCK: | |
2104 | env->wall_clock_msr = msrs[i].data; | |
2105 | break; | |
2106 | case MSR_MCG_STATUS: | |
2107 | env->mcg_status = msrs[i].data; | |
2108 | break; | |
2109 | case MSR_MCG_CTL: | |
2110 | env->mcg_ctl = msrs[i].data; | |
2111 | break; | |
2112 | case MSR_IA32_MISC_ENABLE: | |
2113 | env->msr_ia32_misc_enable = msrs[i].data; | |
2114 | break; | |
2115 | case MSR_IA32_SMBASE: | |
2116 | env->smbase = msrs[i].data; | |
2117 | break; | |
2118 | case MSR_IA32_FEATURE_CONTROL: | |
2119 | env->msr_ia32_feature_control = msrs[i].data; | |
2120 | break; | |
2121 | case MSR_IA32_BNDCFGS: | |
2122 | env->msr_bndcfgs = msrs[i].data; | |
2123 | break; | |
2124 | case MSR_IA32_XSS: | |
2125 | env->xss = msrs[i].data; | |
2126 | break; | |
2127 | default: | |
2128 | if (msrs[i].index >= MSR_MC0_CTL && | |
2129 | msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) { | |
2130 | env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data; | |
2131 | } | |
2132 | break; | |
2133 | case MSR_KVM_ASYNC_PF_EN: | |
2134 | env->async_pf_en_msr = msrs[i].data; | |
2135 | break; | |
2136 | case MSR_KVM_PV_EOI_EN: | |
2137 | env->pv_eoi_en_msr = msrs[i].data; | |
2138 | break; | |
2139 | case MSR_KVM_STEAL_TIME: | |
2140 | env->steal_time_msr = msrs[i].data; | |
2141 | break; | |
2142 | case MSR_CORE_PERF_FIXED_CTR_CTRL: | |
2143 | env->msr_fixed_ctr_ctrl = msrs[i].data; | |
2144 | break; | |
2145 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
2146 | env->msr_global_ctrl = msrs[i].data; | |
2147 | break; | |
2148 | case MSR_CORE_PERF_GLOBAL_STATUS: | |
2149 | env->msr_global_status = msrs[i].data; | |
2150 | break; | |
2151 | case MSR_CORE_PERF_GLOBAL_OVF_CTRL: | |
2152 | env->msr_global_ovf_ctrl = msrs[i].data; | |
2153 | break; | |
2154 | case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1: | |
2155 | env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data; | |
2156 | break; | |
2157 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1: | |
2158 | env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data; | |
2159 | break; | |
2160 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1: | |
2161 | env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data; | |
2162 | break; | |
2163 | case HV_X64_MSR_HYPERCALL: | |
2164 | env->msr_hv_hypercall = msrs[i].data; | |
2165 | break; | |
2166 | case HV_X64_MSR_GUEST_OS_ID: | |
2167 | env->msr_hv_guest_os_id = msrs[i].data; | |
2168 | break; | |
2169 | case HV_X64_MSR_APIC_ASSIST_PAGE: | |
2170 | env->msr_hv_vapic = msrs[i].data; | |
2171 | break; | |
2172 | case HV_X64_MSR_REFERENCE_TSC: | |
2173 | env->msr_hv_tsc = msrs[i].data; | |
2174 | break; | |
2175 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: | |
2176 | env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data; | |
2177 | break; | |
2178 | case HV_X64_MSR_VP_RUNTIME: | |
2179 | env->msr_hv_runtime = msrs[i].data; | |
2180 | break; | |
2181 | case HV_X64_MSR_SCONTROL: | |
2182 | env->msr_hv_synic_control = msrs[i].data; | |
2183 | break; | |
2184 | case HV_X64_MSR_SVERSION: | |
2185 | env->msr_hv_synic_version = msrs[i].data; | |
2186 | break; | |
2187 | case HV_X64_MSR_SIEFP: | |
2188 | env->msr_hv_synic_evt_page = msrs[i].data; | |
2189 | break; | |
2190 | case HV_X64_MSR_SIMP: | |
2191 | env->msr_hv_synic_msg_page = msrs[i].data; | |
2192 | break; | |
2193 | case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15: | |
2194 | env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data; | |
2195 | break; | |
2196 | case HV_X64_MSR_STIMER0_CONFIG: | |
2197 | case HV_X64_MSR_STIMER1_CONFIG: | |
2198 | case HV_X64_MSR_STIMER2_CONFIG: | |
2199 | case HV_X64_MSR_STIMER3_CONFIG: | |
2200 | env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] = | |
2201 | msrs[i].data; | |
2202 | break; | |
2203 | case HV_X64_MSR_STIMER0_COUNT: | |
2204 | case HV_X64_MSR_STIMER1_COUNT: | |
2205 | case HV_X64_MSR_STIMER2_COUNT: | |
2206 | case HV_X64_MSR_STIMER3_COUNT: | |
2207 | env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] = | |
2208 | msrs[i].data; | |
2209 | break; | |
2210 | case MSR_MTRRdefType: | |
2211 | env->mtrr_deftype = msrs[i].data; | |
2212 | break; | |
2213 | case MSR_MTRRfix64K_00000: | |
2214 | env->mtrr_fixed[0] = msrs[i].data; | |
2215 | break; | |
2216 | case MSR_MTRRfix16K_80000: | |
2217 | env->mtrr_fixed[1] = msrs[i].data; | |
2218 | break; | |
2219 | case MSR_MTRRfix16K_A0000: | |
2220 | env->mtrr_fixed[2] = msrs[i].data; | |
2221 | break; | |
2222 | case MSR_MTRRfix4K_C0000: | |
2223 | env->mtrr_fixed[3] = msrs[i].data; | |
2224 | break; | |
2225 | case MSR_MTRRfix4K_C8000: | |
2226 | env->mtrr_fixed[4] = msrs[i].data; | |
2227 | break; | |
2228 | case MSR_MTRRfix4K_D0000: | |
2229 | env->mtrr_fixed[5] = msrs[i].data; | |
2230 | break; | |
2231 | case MSR_MTRRfix4K_D8000: | |
2232 | env->mtrr_fixed[6] = msrs[i].data; | |
2233 | break; | |
2234 | case MSR_MTRRfix4K_E0000: | |
2235 | env->mtrr_fixed[7] = msrs[i].data; | |
2236 | break; | |
2237 | case MSR_MTRRfix4K_E8000: | |
2238 | env->mtrr_fixed[8] = msrs[i].data; | |
2239 | break; | |
2240 | case MSR_MTRRfix4K_F0000: | |
2241 | env->mtrr_fixed[9] = msrs[i].data; | |
2242 | break; | |
2243 | case MSR_MTRRfix4K_F8000: | |
2244 | env->mtrr_fixed[10] = msrs[i].data; | |
2245 | break; | |
2246 | case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1): | |
2247 | if (index & 1) { | |
2248 | env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data; | |
2249 | } else { | |
2250 | env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data; | |
2251 | } | |
2252 | break; | |
2253 | } | |
2254 | } | |
2255 | ||
2256 | return 0; | |
2257 | } | |
2258 | ||
2259 | static int kvm_put_mp_state(X86CPU *cpu) | |
2260 | { | |
2261 | struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state }; | |
2262 | ||
2263 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); | |
2264 | } | |
2265 | ||
2266 | static int kvm_get_mp_state(X86CPU *cpu) | |
2267 | { | |
2268 | CPUState *cs = CPU(cpu); | |
2269 | CPUX86State *env = &cpu->env; | |
2270 | struct kvm_mp_state mp_state; | |
2271 | int ret; | |
2272 | ||
2273 | ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state); | |
2274 | if (ret < 0) { | |
2275 | return ret; | |
2276 | } | |
2277 | env->mp_state = mp_state.mp_state; | |
2278 | if (kvm_irqchip_in_kernel()) { | |
2279 | cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED); | |
2280 | } | |
2281 | return 0; | |
2282 | } | |
2283 | ||
2284 | static int kvm_get_apic(X86CPU *cpu) | |
2285 | { | |
2286 | DeviceState *apic = cpu->apic_state; | |
2287 | struct kvm_lapic_state kapic; | |
2288 | int ret; | |
2289 | ||
2290 | if (apic && kvm_irqchip_in_kernel()) { | |
2291 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic); | |
2292 | if (ret < 0) { | |
2293 | return ret; | |
2294 | } | |
2295 | ||
2296 | kvm_get_apic_state(apic, &kapic); | |
2297 | } | |
2298 | return 0; | |
2299 | } | |
2300 | ||
2301 | static int kvm_put_apic(X86CPU *cpu) | |
2302 | { | |
2303 | DeviceState *apic = cpu->apic_state; | |
2304 | struct kvm_lapic_state kapic; | |
2305 | ||
2306 | if (apic && kvm_irqchip_in_kernel()) { | |
2307 | kvm_put_apic_state(apic, &kapic); | |
2308 | ||
2309 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic); | |
2310 | } | |
2311 | return 0; | |
2312 | } | |
2313 | ||
2314 | static int kvm_put_vcpu_events(X86CPU *cpu, int level) | |
2315 | { | |
2316 | CPUState *cs = CPU(cpu); | |
2317 | CPUX86State *env = &cpu->env; | |
2318 | struct kvm_vcpu_events events = {}; | |
2319 | ||
2320 | if (!kvm_has_vcpu_events()) { | |
2321 | return 0; | |
2322 | } | |
2323 | ||
2324 | events.exception.injected = (env->exception_injected >= 0); | |
2325 | events.exception.nr = env->exception_injected; | |
2326 | events.exception.has_error_code = env->has_error_code; | |
2327 | events.exception.error_code = env->error_code; | |
2328 | events.exception.pad = 0; | |
2329 | ||
2330 | events.interrupt.injected = (env->interrupt_injected >= 0); | |
2331 | events.interrupt.nr = env->interrupt_injected; | |
2332 | events.interrupt.soft = env->soft_interrupt; | |
2333 | ||
2334 | events.nmi.injected = env->nmi_injected; | |
2335 | events.nmi.pending = env->nmi_pending; | |
2336 | events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK); | |
2337 | events.nmi.pad = 0; | |
2338 | ||
2339 | events.sipi_vector = env->sipi_vector; | |
2340 | ||
2341 | if (has_msr_smbase) { | |
2342 | events.smi.smm = !!(env->hflags & HF_SMM_MASK); | |
2343 | events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK); | |
2344 | if (kvm_irqchip_in_kernel()) { | |
2345 | /* As soon as these are moved to the kernel, remove them | |
2346 | * from cs->interrupt_request. | |
2347 | */ | |
2348 | events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI; | |
2349 | events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT; | |
2350 | cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI); | |
2351 | } else { | |
2352 | /* Keep these in cs->interrupt_request. */ | |
2353 | events.smi.pending = 0; | |
2354 | events.smi.latched_init = 0; | |
2355 | } | |
2356 | events.flags |= KVM_VCPUEVENT_VALID_SMM; | |
2357 | } | |
2358 | ||
2359 | events.flags = 0; | |
2360 | if (level >= KVM_PUT_RESET_STATE) { | |
2361 | events.flags |= | |
2362 | KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR; | |
2363 | } | |
2364 | ||
2365 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events); | |
2366 | } | |
2367 | ||
2368 | static int kvm_get_vcpu_events(X86CPU *cpu) | |
2369 | { | |
2370 | CPUX86State *env = &cpu->env; | |
2371 | struct kvm_vcpu_events events; | |
2372 | int ret; | |
2373 | ||
2374 | if (!kvm_has_vcpu_events()) { | |
2375 | return 0; | |
2376 | } | |
2377 | ||
2378 | memset(&events, 0, sizeof(events)); | |
2379 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events); | |
2380 | if (ret < 0) { | |
2381 | return ret; | |
2382 | } | |
2383 | env->exception_injected = | |
2384 | events.exception.injected ? events.exception.nr : -1; | |
2385 | env->has_error_code = events.exception.has_error_code; | |
2386 | env->error_code = events.exception.error_code; | |
2387 | ||
2388 | env->interrupt_injected = | |
2389 | events.interrupt.injected ? events.interrupt.nr : -1; | |
2390 | env->soft_interrupt = events.interrupt.soft; | |
2391 | ||
2392 | env->nmi_injected = events.nmi.injected; | |
2393 | env->nmi_pending = events.nmi.pending; | |
2394 | if (events.nmi.masked) { | |
2395 | env->hflags2 |= HF2_NMI_MASK; | |
2396 | } else { | |
2397 | env->hflags2 &= ~HF2_NMI_MASK; | |
2398 | } | |
2399 | ||
2400 | if (events.flags & KVM_VCPUEVENT_VALID_SMM) { | |
2401 | if (events.smi.smm) { | |
2402 | env->hflags |= HF_SMM_MASK; | |
2403 | } else { | |
2404 | env->hflags &= ~HF_SMM_MASK; | |
2405 | } | |
2406 | if (events.smi.pending) { | |
2407 | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); | |
2408 | } else { | |
2409 | cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); | |
2410 | } | |
2411 | if (events.smi.smm_inside_nmi) { | |
2412 | env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK; | |
2413 | } else { | |
2414 | env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK; | |
2415 | } | |
2416 | if (events.smi.latched_init) { | |
2417 | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT); | |
2418 | } else { | |
2419 | cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT); | |
2420 | } | |
2421 | } | |
2422 | ||
2423 | env->sipi_vector = events.sipi_vector; | |
2424 | ||
2425 | return 0; | |
2426 | } | |
2427 | ||
2428 | static int kvm_guest_debug_workarounds(X86CPU *cpu) | |
2429 | { | |
2430 | CPUState *cs = CPU(cpu); | |
2431 | CPUX86State *env = &cpu->env; | |
2432 | int ret = 0; | |
2433 | unsigned long reinject_trap = 0; | |
2434 | ||
2435 | if (!kvm_has_vcpu_events()) { | |
2436 | if (env->exception_injected == 1) { | |
2437 | reinject_trap = KVM_GUESTDBG_INJECT_DB; | |
2438 | } else if (env->exception_injected == 3) { | |
2439 | reinject_trap = KVM_GUESTDBG_INJECT_BP; | |
2440 | } | |
2441 | env->exception_injected = -1; | |
2442 | } | |
2443 | ||
2444 | /* | |
2445 | * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF | |
2446 | * injected via SET_GUEST_DEBUG while updating GP regs. Work around this | |
2447 | * by updating the debug state once again if single-stepping is on. | |
2448 | * Another reason to call kvm_update_guest_debug here is a pending debug | |
2449 | * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to | |
2450 | * reinject them via SET_GUEST_DEBUG. | |
2451 | */ | |
2452 | if (reinject_trap || | |
2453 | (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) { | |
2454 | ret = kvm_update_guest_debug(cs, reinject_trap); | |
2455 | } | |
2456 | return ret; | |
2457 | } | |
2458 | ||
2459 | static int kvm_put_debugregs(X86CPU *cpu) | |
2460 | { | |
2461 | CPUX86State *env = &cpu->env; | |
2462 | struct kvm_debugregs dbgregs; | |
2463 | int i; | |
2464 | ||
2465 | if (!kvm_has_debugregs()) { | |
2466 | return 0; | |
2467 | } | |
2468 | ||
2469 | for (i = 0; i < 4; i++) { | |
2470 | dbgregs.db[i] = env->dr[i]; | |
2471 | } | |
2472 | dbgregs.dr6 = env->dr[6]; | |
2473 | dbgregs.dr7 = env->dr[7]; | |
2474 | dbgregs.flags = 0; | |
2475 | ||
2476 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs); | |
2477 | } | |
2478 | ||
2479 | static int kvm_get_debugregs(X86CPU *cpu) | |
2480 | { | |
2481 | CPUX86State *env = &cpu->env; | |
2482 | struct kvm_debugregs dbgregs; | |
2483 | int i, ret; | |
2484 | ||
2485 | if (!kvm_has_debugregs()) { | |
2486 | return 0; | |
2487 | } | |
2488 | ||
2489 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs); | |
2490 | if (ret < 0) { | |
2491 | return ret; | |
2492 | } | |
2493 | for (i = 0; i < 4; i++) { | |
2494 | env->dr[i] = dbgregs.db[i]; | |
2495 | } | |
2496 | env->dr[4] = env->dr[6] = dbgregs.dr6; | |
2497 | env->dr[5] = env->dr[7] = dbgregs.dr7; | |
2498 | ||
2499 | return 0; | |
2500 | } | |
2501 | ||
2502 | int kvm_arch_put_registers(CPUState *cpu, int level) | |
2503 | { | |
2504 | X86CPU *x86_cpu = X86_CPU(cpu); | |
2505 | int ret; | |
2506 | ||
2507 | assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu)); | |
2508 | ||
2509 | if (level >= KVM_PUT_RESET_STATE && has_msr_feature_control) { | |
2510 | ret = kvm_put_msr_feature_control(x86_cpu); | |
2511 | if (ret < 0) { | |
2512 | return ret; | |
2513 | } | |
2514 | } | |
2515 | ||
2516 | if (level == KVM_PUT_FULL_STATE) { | |
2517 | /* We don't check for kvm_arch_set_tsc_khz() errors here, | |
2518 | * because TSC frequency mismatch shouldn't abort migration, | |
2519 | * unless the user explicitly asked for a more strict TSC | |
2520 | * setting (e.g. using an explicit "tsc-freq" option). | |
2521 | */ | |
2522 | kvm_arch_set_tsc_khz(cpu); | |
2523 | } | |
2524 | ||
2525 | ret = kvm_getput_regs(x86_cpu, 1); | |
2526 | if (ret < 0) { | |
2527 | return ret; | |
2528 | } | |
2529 | ret = kvm_put_xsave(x86_cpu); | |
2530 | if (ret < 0) { | |
2531 | return ret; | |
2532 | } | |
2533 | ret = kvm_put_xcrs(x86_cpu); | |
2534 | if (ret < 0) { | |
2535 | return ret; | |
2536 | } | |
2537 | ret = kvm_put_sregs(x86_cpu); | |
2538 | if (ret < 0) { | |
2539 | return ret; | |
2540 | } | |
2541 | /* must be before kvm_put_msrs */ | |
2542 | ret = kvm_inject_mce_oldstyle(x86_cpu); | |
2543 | if (ret < 0) { | |
2544 | return ret; | |
2545 | } | |
2546 | ret = kvm_put_msrs(x86_cpu, level); | |
2547 | if (ret < 0) { | |
2548 | return ret; | |
2549 | } | |
2550 | if (level >= KVM_PUT_RESET_STATE) { | |
2551 | ret = kvm_put_mp_state(x86_cpu); | |
2552 | if (ret < 0) { | |
2553 | return ret; | |
2554 | } | |
2555 | ret = kvm_put_apic(x86_cpu); | |
2556 | if (ret < 0) { | |
2557 | return ret; | |
2558 | } | |
2559 | } | |
2560 | ||
2561 | ret = kvm_put_tscdeadline_msr(x86_cpu); | |
2562 | if (ret < 0) { | |
2563 | return ret; | |
2564 | } | |
2565 | ||
2566 | ret = kvm_put_vcpu_events(x86_cpu, level); | |
2567 | if (ret < 0) { | |
2568 | return ret; | |
2569 | } | |
2570 | ret = kvm_put_debugregs(x86_cpu); | |
2571 | if (ret < 0) { | |
2572 | return ret; | |
2573 | } | |
2574 | /* must be last */ | |
2575 | ret = kvm_guest_debug_workarounds(x86_cpu); | |
2576 | if (ret < 0) { | |
2577 | return ret; | |
2578 | } | |
2579 | return 0; | |
2580 | } | |
2581 | ||
2582 | int kvm_arch_get_registers(CPUState *cs) | |
2583 | { | |
2584 | X86CPU *cpu = X86_CPU(cs); | |
2585 | int ret; | |
2586 | ||
2587 | assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs)); | |
2588 | ||
2589 | ret = kvm_getput_regs(cpu, 0); | |
2590 | if (ret < 0) { | |
2591 | return ret; | |
2592 | } | |
2593 | ret = kvm_get_xsave(cpu); | |
2594 | if (ret < 0) { | |
2595 | return ret; | |
2596 | } | |
2597 | ret = kvm_get_xcrs(cpu); | |
2598 | if (ret < 0) { | |
2599 | return ret; | |
2600 | } | |
2601 | ret = kvm_get_sregs(cpu); | |
2602 | if (ret < 0) { | |
2603 | return ret; | |
2604 | } | |
2605 | ret = kvm_get_msrs(cpu); | |
2606 | if (ret < 0) { | |
2607 | return ret; | |
2608 | } | |
2609 | ret = kvm_get_mp_state(cpu); | |
2610 | if (ret < 0) { | |
2611 | return ret; | |
2612 | } | |
2613 | ret = kvm_get_apic(cpu); | |
2614 | if (ret < 0) { | |
2615 | return ret; | |
2616 | } | |
2617 | ret = kvm_get_vcpu_events(cpu); | |
2618 | if (ret < 0) { | |
2619 | return ret; | |
2620 | } | |
2621 | ret = kvm_get_debugregs(cpu); | |
2622 | if (ret < 0) { | |
2623 | return ret; | |
2624 | } | |
2625 | return 0; | |
2626 | } | |
2627 | ||
2628 | void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run) | |
2629 | { | |
2630 | X86CPU *x86_cpu = X86_CPU(cpu); | |
2631 | CPUX86State *env = &x86_cpu->env; | |
2632 | int ret; | |
2633 | ||
2634 | /* Inject NMI */ | |
2635 | if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) { | |
2636 | if (cpu->interrupt_request & CPU_INTERRUPT_NMI) { | |
2637 | qemu_mutex_lock_iothread(); | |
2638 | cpu->interrupt_request &= ~CPU_INTERRUPT_NMI; | |
2639 | qemu_mutex_unlock_iothread(); | |
2640 | DPRINTF("injected NMI\n"); | |
2641 | ret = kvm_vcpu_ioctl(cpu, KVM_NMI); | |
2642 | if (ret < 0) { | |
2643 | fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n", | |
2644 | strerror(-ret)); | |
2645 | } | |
2646 | } | |
2647 | if (cpu->interrupt_request & CPU_INTERRUPT_SMI) { | |
2648 | qemu_mutex_lock_iothread(); | |
2649 | cpu->interrupt_request &= ~CPU_INTERRUPT_SMI; | |
2650 | qemu_mutex_unlock_iothread(); | |
2651 | DPRINTF("injected SMI\n"); | |
2652 | ret = kvm_vcpu_ioctl(cpu, KVM_SMI); | |
2653 | if (ret < 0) { | |
2654 | fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n", | |
2655 | strerror(-ret)); | |
2656 | } | |
2657 | } | |
2658 | } | |
2659 | ||
2660 | if (!kvm_pic_in_kernel()) { | |
2661 | qemu_mutex_lock_iothread(); | |
2662 | } | |
2663 | ||
2664 | /* Force the VCPU out of its inner loop to process any INIT requests | |
2665 | * or (for userspace APIC, but it is cheap to combine the checks here) | |
2666 | * pending TPR access reports. | |
2667 | */ | |
2668 | if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) { | |
2669 | if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) && | |
2670 | !(env->hflags & HF_SMM_MASK)) { | |
2671 | cpu->exit_request = 1; | |
2672 | } | |
2673 | if (cpu->interrupt_request & CPU_INTERRUPT_TPR) { | |
2674 | cpu->exit_request = 1; | |
2675 | } | |
2676 | } | |
2677 | ||
2678 | if (!kvm_pic_in_kernel()) { | |
2679 | /* Try to inject an interrupt if the guest can accept it */ | |
2680 | if (run->ready_for_interrupt_injection && | |
2681 | (cpu->interrupt_request & CPU_INTERRUPT_HARD) && | |
2682 | (env->eflags & IF_MASK)) { | |
2683 | int irq; | |
2684 | ||
2685 | cpu->interrupt_request &= ~CPU_INTERRUPT_HARD; | |
2686 | irq = cpu_get_pic_interrupt(env); | |
2687 | if (irq >= 0) { | |
2688 | struct kvm_interrupt intr; | |
2689 | ||
2690 | intr.irq = irq; | |
2691 | DPRINTF("injected interrupt %d\n", irq); | |
2692 | ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr); | |
2693 | if (ret < 0) { | |
2694 | fprintf(stderr, | |
2695 | "KVM: injection failed, interrupt lost (%s)\n", | |
2696 | strerror(-ret)); | |
2697 | } | |
2698 | } | |
2699 | } | |
2700 | ||
2701 | /* If we have an interrupt but the guest is not ready to receive an | |
2702 | * interrupt, request an interrupt window exit. This will | |
2703 | * cause a return to userspace as soon as the guest is ready to | |
2704 | * receive interrupts. */ | |
2705 | if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) { | |
2706 | run->request_interrupt_window = 1; | |
2707 | } else { | |
2708 | run->request_interrupt_window = 0; | |
2709 | } | |
2710 | ||
2711 | DPRINTF("setting tpr\n"); | |
2712 | run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state); | |
2713 | ||
2714 | qemu_mutex_unlock_iothread(); | |
2715 | } | |
2716 | } | |
2717 | ||
2718 | MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run) | |
2719 | { | |
2720 | X86CPU *x86_cpu = X86_CPU(cpu); | |
2721 | CPUX86State *env = &x86_cpu->env; | |
2722 | ||
2723 | if (run->flags & KVM_RUN_X86_SMM) { | |
2724 | env->hflags |= HF_SMM_MASK; | |
2725 | } else { | |
2726 | env->hflags &= HF_SMM_MASK; | |
2727 | } | |
2728 | if (run->if_flag) { | |
2729 | env->eflags |= IF_MASK; | |
2730 | } else { | |
2731 | env->eflags &= ~IF_MASK; | |
2732 | } | |
2733 | ||
2734 | /* We need to protect the apic state against concurrent accesses from | |
2735 | * different threads in case the userspace irqchip is used. */ | |
2736 | if (!kvm_irqchip_in_kernel()) { | |
2737 | qemu_mutex_lock_iothread(); | |
2738 | } | |
2739 | cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8); | |
2740 | cpu_set_apic_base(x86_cpu->apic_state, run->apic_base); | |
2741 | if (!kvm_irqchip_in_kernel()) { | |
2742 | qemu_mutex_unlock_iothread(); | |
2743 | } | |
2744 | return cpu_get_mem_attrs(env); | |
2745 | } | |
2746 | ||
2747 | int kvm_arch_process_async_events(CPUState *cs) | |
2748 | { | |
2749 | X86CPU *cpu = X86_CPU(cs); | |
2750 | CPUX86State *env = &cpu->env; | |
2751 | ||
2752 | if (cs->interrupt_request & CPU_INTERRUPT_MCE) { | |
2753 | /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */ | |
2754 | assert(env->mcg_cap); | |
2755 | ||
2756 | cs->interrupt_request &= ~CPU_INTERRUPT_MCE; | |
2757 | ||
2758 | kvm_cpu_synchronize_state(cs); | |
2759 | ||
2760 | if (env->exception_injected == EXCP08_DBLE) { | |
2761 | /* this means triple fault */ | |
2762 | qemu_system_reset_request(); | |
2763 | cs->exit_request = 1; | |
2764 | return 0; | |
2765 | } | |
2766 | env->exception_injected = EXCP12_MCHK; | |
2767 | env->has_error_code = 0; | |
2768 | ||
2769 | cs->halted = 0; | |
2770 | if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) { | |
2771 | env->mp_state = KVM_MP_STATE_RUNNABLE; | |
2772 | } | |
2773 | } | |
2774 | ||
2775 | if ((cs->interrupt_request & CPU_INTERRUPT_INIT) && | |
2776 | !(env->hflags & HF_SMM_MASK)) { | |
2777 | kvm_cpu_synchronize_state(cs); | |
2778 | do_cpu_init(cpu); | |
2779 | } | |
2780 | ||
2781 | if (kvm_irqchip_in_kernel()) { | |
2782 | return 0; | |
2783 | } | |
2784 | ||
2785 | if (cs->interrupt_request & CPU_INTERRUPT_POLL) { | |
2786 | cs->interrupt_request &= ~CPU_INTERRUPT_POLL; | |
2787 | apic_poll_irq(cpu->apic_state); | |
2788 | } | |
2789 | if (((cs->interrupt_request & CPU_INTERRUPT_HARD) && | |
2790 | (env->eflags & IF_MASK)) || | |
2791 | (cs->interrupt_request & CPU_INTERRUPT_NMI)) { | |
2792 | cs->halted = 0; | |
2793 | } | |
2794 | if (cs->interrupt_request & CPU_INTERRUPT_SIPI) { | |
2795 | kvm_cpu_synchronize_state(cs); | |
2796 | do_cpu_sipi(cpu); | |
2797 | } | |
2798 | if (cs->interrupt_request & CPU_INTERRUPT_TPR) { | |
2799 | cs->interrupt_request &= ~CPU_INTERRUPT_TPR; | |
2800 | kvm_cpu_synchronize_state(cs); | |
2801 | apic_handle_tpr_access_report(cpu->apic_state, env->eip, | |
2802 | env->tpr_access_type); | |
2803 | } | |
2804 | ||
2805 | return cs->halted; | |
2806 | } | |
2807 | ||
2808 | static int kvm_handle_halt(X86CPU *cpu) | |
2809 | { | |
2810 | CPUState *cs = CPU(cpu); | |
2811 | CPUX86State *env = &cpu->env; | |
2812 | ||
2813 | if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) && | |
2814 | (env->eflags & IF_MASK)) && | |
2815 | !(cs->interrupt_request & CPU_INTERRUPT_NMI)) { | |
2816 | cs->halted = 1; | |
2817 | return EXCP_HLT; | |
2818 | } | |
2819 | ||
2820 | return 0; | |
2821 | } | |
2822 | ||
2823 | static int kvm_handle_tpr_access(X86CPU *cpu) | |
2824 | { | |
2825 | CPUState *cs = CPU(cpu); | |
2826 | struct kvm_run *run = cs->kvm_run; | |
2827 | ||
2828 | apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip, | |
2829 | run->tpr_access.is_write ? TPR_ACCESS_WRITE | |
2830 | : TPR_ACCESS_READ); | |
2831 | return 1; | |
2832 | } | |
2833 | ||
2834 | int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) | |
2835 | { | |
2836 | static const uint8_t int3 = 0xcc; | |
2837 | ||
2838 | if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) || | |
2839 | cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) { | |
2840 | return -EINVAL; | |
2841 | } | |
2842 | return 0; | |
2843 | } | |
2844 | ||
2845 | int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) | |
2846 | { | |
2847 | uint8_t int3; | |
2848 | ||
2849 | if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc || | |
2850 | cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) { | |
2851 | return -EINVAL; | |
2852 | } | |
2853 | return 0; | |
2854 | } | |
2855 | ||
2856 | static struct { | |
2857 | target_ulong addr; | |
2858 | int len; | |
2859 | int type; | |
2860 | } hw_breakpoint[4]; | |
2861 | ||
2862 | static int nb_hw_breakpoint; | |
2863 | ||
2864 | static int find_hw_breakpoint(target_ulong addr, int len, int type) | |
2865 | { | |
2866 | int n; | |
2867 | ||
2868 | for (n = 0; n < nb_hw_breakpoint; n++) { | |
2869 | if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type && | |
2870 | (hw_breakpoint[n].len == len || len == -1)) { | |
2871 | return n; | |
2872 | } | |
2873 | } | |
2874 | return -1; | |
2875 | } | |
2876 | ||
2877 | int kvm_arch_insert_hw_breakpoint(target_ulong addr, | |
2878 | target_ulong len, int type) | |
2879 | { | |
2880 | switch (type) { | |
2881 | case GDB_BREAKPOINT_HW: | |
2882 | len = 1; | |
2883 | break; | |
2884 | case GDB_WATCHPOINT_WRITE: | |
2885 | case GDB_WATCHPOINT_ACCESS: | |
2886 | switch (len) { | |
2887 | case 1: | |
2888 | break; | |
2889 | case 2: | |
2890 | case 4: | |
2891 | case 8: | |
2892 | if (addr & (len - 1)) { | |
2893 | return -EINVAL; | |
2894 | } | |
2895 | break; | |
2896 | default: | |
2897 | return -EINVAL; | |
2898 | } | |
2899 | break; | |
2900 | default: | |
2901 | return -ENOSYS; | |
2902 | } | |
2903 | ||
2904 | if (nb_hw_breakpoint == 4) { | |
2905 | return -ENOBUFS; | |
2906 | } | |
2907 | if (find_hw_breakpoint(addr, len, type) >= 0) { | |
2908 | return -EEXIST; | |
2909 | } | |
2910 | hw_breakpoint[nb_hw_breakpoint].addr = addr; | |
2911 | hw_breakpoint[nb_hw_breakpoint].len = len; | |
2912 | hw_breakpoint[nb_hw_breakpoint].type = type; | |
2913 | nb_hw_breakpoint++; | |
2914 | ||
2915 | return 0; | |
2916 | } | |
2917 | ||
2918 | int kvm_arch_remove_hw_breakpoint(target_ulong addr, | |
2919 | target_ulong len, int type) | |
2920 | { | |
2921 | int n; | |
2922 | ||
2923 | n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type); | |
2924 | if (n < 0) { | |
2925 | return -ENOENT; | |
2926 | } | |
2927 | nb_hw_breakpoint--; | |
2928 | hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint]; | |
2929 | ||
2930 | return 0; | |
2931 | } | |
2932 | ||
2933 | void kvm_arch_remove_all_hw_breakpoints(void) | |
2934 | { | |
2935 | nb_hw_breakpoint = 0; | |
2936 | } | |
2937 | ||
2938 | static CPUWatchpoint hw_watchpoint; | |
2939 | ||
2940 | static int kvm_handle_debug(X86CPU *cpu, | |
2941 | struct kvm_debug_exit_arch *arch_info) | |
2942 | { | |
2943 | CPUState *cs = CPU(cpu); | |
2944 | CPUX86State *env = &cpu->env; | |
2945 | int ret = 0; | |
2946 | int n; | |
2947 | ||
2948 | if (arch_info->exception == 1) { | |
2949 | if (arch_info->dr6 & (1 << 14)) { | |
2950 | if (cs->singlestep_enabled) { | |
2951 | ret = EXCP_DEBUG; | |
2952 | } | |
2953 | } else { | |
2954 | for (n = 0; n < 4; n++) { | |
2955 | if (arch_info->dr6 & (1 << n)) { | |
2956 | switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) { | |
2957 | case 0x0: | |
2958 | ret = EXCP_DEBUG; | |
2959 | break; | |
2960 | case 0x1: | |
2961 | ret = EXCP_DEBUG; | |
2962 | cs->watchpoint_hit = &hw_watchpoint; | |
2963 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; | |
2964 | hw_watchpoint.flags = BP_MEM_WRITE; | |
2965 | break; | |
2966 | case 0x3: | |
2967 | ret = EXCP_DEBUG; | |
2968 | cs->watchpoint_hit = &hw_watchpoint; | |
2969 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; | |
2970 | hw_watchpoint.flags = BP_MEM_ACCESS; | |
2971 | break; | |
2972 | } | |
2973 | } | |
2974 | } | |
2975 | } | |
2976 | } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) { | |
2977 | ret = EXCP_DEBUG; | |
2978 | } | |
2979 | if (ret == 0) { | |
2980 | cpu_synchronize_state(cs); | |
2981 | assert(env->exception_injected == -1); | |
2982 | ||
2983 | /* pass to guest */ | |
2984 | env->exception_injected = arch_info->exception; | |
2985 | env->has_error_code = 0; | |
2986 | } | |
2987 | ||
2988 | return ret; | |
2989 | } | |
2990 | ||
2991 | void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg) | |
2992 | { | |
2993 | const uint8_t type_code[] = { | |
2994 | [GDB_BREAKPOINT_HW] = 0x0, | |
2995 | [GDB_WATCHPOINT_WRITE] = 0x1, | |
2996 | [GDB_WATCHPOINT_ACCESS] = 0x3 | |
2997 | }; | |
2998 | const uint8_t len_code[] = { | |
2999 | [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2 | |
3000 | }; | |
3001 | int n; | |
3002 | ||
3003 | if (kvm_sw_breakpoints_active(cpu)) { | |
3004 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; | |
3005 | } | |
3006 | if (nb_hw_breakpoint > 0) { | |
3007 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; | |
3008 | dbg->arch.debugreg[7] = 0x0600; | |
3009 | for (n = 0; n < nb_hw_breakpoint; n++) { | |
3010 | dbg->arch.debugreg[n] = hw_breakpoint[n].addr; | |
3011 | dbg->arch.debugreg[7] |= (2 << (n * 2)) | | |
3012 | (type_code[hw_breakpoint[n].type] << (16 + n*4)) | | |
3013 | ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4)); | |
3014 | } | |
3015 | } | |
3016 | } | |
3017 | ||
3018 | static bool host_supports_vmx(void) | |
3019 | { | |
3020 | uint32_t ecx, unused; | |
3021 | ||
3022 | host_cpuid(1, 0, &unused, &unused, &ecx, &unused); | |
3023 | return ecx & CPUID_EXT_VMX; | |
3024 | } | |
3025 | ||
3026 | #define VMX_INVALID_GUEST_STATE 0x80000021 | |
3027 | ||
3028 | int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) | |
3029 | { | |
3030 | X86CPU *cpu = X86_CPU(cs); | |
3031 | uint64_t code; | |
3032 | int ret; | |
3033 | ||
3034 | switch (run->exit_reason) { | |
3035 | case KVM_EXIT_HLT: | |
3036 | DPRINTF("handle_hlt\n"); | |
3037 | qemu_mutex_lock_iothread(); | |
3038 | ret = kvm_handle_halt(cpu); | |
3039 | qemu_mutex_unlock_iothread(); | |
3040 | break; | |
3041 | case KVM_EXIT_SET_TPR: | |
3042 | ret = 0; | |
3043 | break; | |
3044 | case KVM_EXIT_TPR_ACCESS: | |
3045 | qemu_mutex_lock_iothread(); | |
3046 | ret = kvm_handle_tpr_access(cpu); | |
3047 | qemu_mutex_unlock_iothread(); | |
3048 | break; | |
3049 | case KVM_EXIT_FAIL_ENTRY: | |
3050 | code = run->fail_entry.hardware_entry_failure_reason; | |
3051 | fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n", | |
3052 | code); | |
3053 | if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) { | |
3054 | fprintf(stderr, | |
3055 | "\nIf you're running a guest on an Intel machine without " | |
3056 | "unrestricted mode\n" | |
3057 | "support, the failure can be most likely due to the guest " | |
3058 | "entering an invalid\n" | |
3059 | "state for Intel VT. For example, the guest maybe running " | |
3060 | "in big real mode\n" | |
3061 | "which is not supported on less recent Intel processors." | |
3062 | "\n\n"); | |
3063 | } | |
3064 | ret = -1; | |
3065 | break; | |
3066 | case KVM_EXIT_EXCEPTION: | |
3067 | fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n", | |
3068 | run->ex.exception, run->ex.error_code); | |
3069 | ret = -1; | |
3070 | break; | |
3071 | case KVM_EXIT_DEBUG: | |
3072 | DPRINTF("kvm_exit_debug\n"); | |
3073 | qemu_mutex_lock_iothread(); | |
3074 | ret = kvm_handle_debug(cpu, &run->debug.arch); | |
3075 | qemu_mutex_unlock_iothread(); | |
3076 | break; | |
3077 | case KVM_EXIT_HYPERV: | |
3078 | ret = kvm_hv_handle_exit(cpu, &run->hyperv); | |
3079 | break; | |
3080 | case KVM_EXIT_IOAPIC_EOI: | |
3081 | ioapic_eoi_broadcast(run->eoi.vector); | |
3082 | ret = 0; | |
3083 | break; | |
3084 | default: | |
3085 | fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); | |
3086 | ret = -1; | |
3087 | break; | |
3088 | } | |
3089 | ||
3090 | return ret; | |
3091 | } | |
3092 | ||
3093 | bool kvm_arch_stop_on_emulation_error(CPUState *cs) | |
3094 | { | |
3095 | X86CPU *cpu = X86_CPU(cs); | |
3096 | CPUX86State *env = &cpu->env; | |
3097 | ||
3098 | kvm_cpu_synchronize_state(cs); | |
3099 | return !(env->cr[0] & CR0_PE_MASK) || | |
3100 | ((env->segs[R_CS].selector & 3) != 3); | |
3101 | } | |
3102 | ||
3103 | void kvm_arch_init_irq_routing(KVMState *s) | |
3104 | { | |
3105 | if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) { | |
3106 | /* If kernel can't do irq routing, interrupt source | |
3107 | * override 0->2 cannot be set up as required by HPET. | |
3108 | * So we have to disable it. | |
3109 | */ | |
3110 | no_hpet = 1; | |
3111 | } | |
3112 | /* We know at this point that we're using the in-kernel | |
3113 | * irqchip, so we can use irqfds, and on x86 we know | |
3114 | * we can use msi via irqfd and GSI routing. | |
3115 | */ | |
3116 | kvm_msi_via_irqfd_allowed = true; | |
3117 | kvm_gsi_routing_allowed = true; | |
3118 | ||
3119 | if (kvm_irqchip_is_split()) { | |
3120 | int i; | |
3121 | ||
3122 | /* If the ioapic is in QEMU and the lapics are in KVM, reserve | |
3123 | MSI routes for signaling interrupts to the local apics. */ | |
3124 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
3125 | struct MSIMessage msg = { 0x0, 0x0 }; | |
3126 | if (kvm_irqchip_add_msi_route(s, msg, NULL) < 0) { | |
3127 | error_report("Could not enable split IRQ mode."); | |
3128 | exit(1); | |
3129 | } | |
3130 | } | |
3131 | } | |
3132 | } | |
3133 | ||
3134 | int kvm_arch_irqchip_create(MachineState *ms, KVMState *s) | |
3135 | { | |
3136 | int ret; | |
3137 | if (machine_kernel_irqchip_split(ms)) { | |
3138 | ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24); | |
3139 | if (ret) { | |
3140 | error_report("Could not enable split irqchip mode: %s\n", | |
3141 | strerror(-ret)); | |
3142 | exit(1); | |
3143 | } else { | |
3144 | DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n"); | |
3145 | kvm_split_irqchip = true; | |
3146 | return 1; | |
3147 | } | |
3148 | } else { | |
3149 | return 0; | |
3150 | } | |
3151 | } | |
3152 | ||
3153 | /* Classic KVM device assignment interface. Will remain x86 only. */ | |
3154 | int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr, | |
3155 | uint32_t flags, uint32_t *dev_id) | |
3156 | { | |
3157 | struct kvm_assigned_pci_dev dev_data = { | |
3158 | .segnr = dev_addr->domain, | |
3159 | .busnr = dev_addr->bus, | |
3160 | .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function), | |
3161 | .flags = flags, | |
3162 | }; | |
3163 | int ret; | |
3164 | ||
3165 | dev_data.assigned_dev_id = | |
3166 | (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn; | |
3167 | ||
3168 | ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data); | |
3169 | if (ret < 0) { | |
3170 | return ret; | |
3171 | } | |
3172 | ||
3173 | *dev_id = dev_data.assigned_dev_id; | |
3174 | ||
3175 | return 0; | |
3176 | } | |
3177 | ||
3178 | int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id) | |
3179 | { | |
3180 | struct kvm_assigned_pci_dev dev_data = { | |
3181 | .assigned_dev_id = dev_id, | |
3182 | }; | |
3183 | ||
3184 | return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data); | |
3185 | } | |
3186 | ||
3187 | static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id, | |
3188 | uint32_t irq_type, uint32_t guest_irq) | |
3189 | { | |
3190 | struct kvm_assigned_irq assigned_irq = { | |
3191 | .assigned_dev_id = dev_id, | |
3192 | .guest_irq = guest_irq, | |
3193 | .flags = irq_type, | |
3194 | }; | |
3195 | ||
3196 | if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) { | |
3197 | return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq); | |
3198 | } else { | |
3199 | return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq); | |
3200 | } | |
3201 | } | |
3202 | ||
3203 | int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi, | |
3204 | uint32_t guest_irq) | |
3205 | { | |
3206 | uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX | | |
3207 | (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX); | |
3208 | ||
3209 | return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq); | |
3210 | } | |
3211 | ||
3212 | int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked) | |
3213 | { | |
3214 | struct kvm_assigned_pci_dev dev_data = { | |
3215 | .assigned_dev_id = dev_id, | |
3216 | .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0, | |
3217 | }; | |
3218 | ||
3219 | return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data); | |
3220 | } | |
3221 | ||
3222 | static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id, | |
3223 | uint32_t type) | |
3224 | { | |
3225 | struct kvm_assigned_irq assigned_irq = { | |
3226 | .assigned_dev_id = dev_id, | |
3227 | .flags = type, | |
3228 | }; | |
3229 | ||
3230 | return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq); | |
3231 | } | |
3232 | ||
3233 | int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi) | |
3234 | { | |
3235 | return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX | | |
3236 | (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX)); | |
3237 | } | |
3238 | ||
3239 | int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq) | |
3240 | { | |
3241 | return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI | | |
3242 | KVM_DEV_IRQ_GUEST_MSI, virq); | |
3243 | } | |
3244 | ||
3245 | int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id) | |
3246 | { | |
3247 | return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI | | |
3248 | KVM_DEV_IRQ_HOST_MSI); | |
3249 | } | |
3250 | ||
3251 | bool kvm_device_msix_supported(KVMState *s) | |
3252 | { | |
3253 | /* The kernel lacks a corresponding KVM_CAP, so we probe by calling | |
3254 | * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */ | |
3255 | return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT; | |
3256 | } | |
3257 | ||
3258 | int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id, | |
3259 | uint32_t nr_vectors) | |
3260 | { | |
3261 | struct kvm_assigned_msix_nr msix_nr = { | |
3262 | .assigned_dev_id = dev_id, | |
3263 | .entry_nr = nr_vectors, | |
3264 | }; | |
3265 | ||
3266 | return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr); | |
3267 | } | |
3268 | ||
3269 | int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector, | |
3270 | int virq) | |
3271 | { | |
3272 | struct kvm_assigned_msix_entry msix_entry = { | |
3273 | .assigned_dev_id = dev_id, | |
3274 | .gsi = virq, | |
3275 | .entry = vector, | |
3276 | }; | |
3277 | ||
3278 | return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry); | |
3279 | } | |
3280 | ||
3281 | int kvm_device_msix_assign(KVMState *s, uint32_t dev_id) | |
3282 | { | |
3283 | return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX | | |
3284 | KVM_DEV_IRQ_GUEST_MSIX, 0); | |
3285 | } | |
3286 | ||
3287 | int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id) | |
3288 | { | |
3289 | return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX | | |
3290 | KVM_DEV_IRQ_HOST_MSIX); | |
3291 | } | |
3292 | ||
3293 | int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, | |
3294 | uint64_t address, uint32_t data, PCIDevice *dev) | |
3295 | { | |
3296 | return 0; | |
3297 | } | |
3298 | ||
3299 | int kvm_arch_msi_data_to_gsi(uint32_t data) | |
3300 | { | |
3301 | abort(); | |
3302 | } |