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1 | /* | |
2 | * QEMU OpenRISC CPU | |
3 | * | |
4 | * Copyright (c) 2012 Jia Liu <proljc@gmail.com> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "cpu.h" | |
21 | #include "qemu-common.h" | |
22 | ||
23 | /* CPUClass::reset() */ | |
24 | static void openrisc_cpu_reset(CPUState *s) | |
25 | { | |
26 | OpenRISCCPU *cpu = OPENRISC_CPU(s); | |
27 | OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu); | |
28 | ||
29 | if (qemu_loglevel_mask(CPU_LOG_RESET)) { | |
30 | qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); | |
31 | log_cpu_state(s, 0); | |
32 | } | |
33 | ||
34 | occ->parent_reset(s); | |
35 | ||
36 | memset(&cpu->env, 0, offsetof(CPUOpenRISCState, breakpoints)); | |
37 | ||
38 | tlb_flush(&cpu->env, 1); | |
39 | /*tb_flush(&cpu->env); FIXME: Do we need it? */ | |
40 | ||
41 | cpu->env.pc = 0x100; | |
42 | cpu->env.sr = SR_FO | SR_SM; | |
43 | cpu->env.exception_index = -1; | |
44 | ||
45 | cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP; | |
46 | cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S; | |
47 | cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2)); | |
48 | cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2)); | |
49 | ||
50 | #ifndef CONFIG_USER_ONLY | |
51 | cpu->env.picmr = 0x00000000; | |
52 | cpu->env.picsr = 0x00000000; | |
53 | ||
54 | cpu->env.ttmr = 0x00000000; | |
55 | cpu->env.ttcr = 0x00000000; | |
56 | #endif | |
57 | } | |
58 | ||
59 | static inline void set_feature(OpenRISCCPU *cpu, int feature) | |
60 | { | |
61 | cpu->feature |= feature; | |
62 | cpu->env.cpucfgr = cpu->feature; | |
63 | } | |
64 | ||
65 | static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) | |
66 | { | |
67 | OpenRISCCPU *cpu = OPENRISC_CPU(dev); | |
68 | OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev); | |
69 | ||
70 | cpu_reset(CPU(cpu)); | |
71 | ||
72 | occ->parent_realize(dev, errp); | |
73 | } | |
74 | ||
75 | static void openrisc_cpu_initfn(Object *obj) | |
76 | { | |
77 | CPUState *cs = CPU(obj); | |
78 | OpenRISCCPU *cpu = OPENRISC_CPU(obj); | |
79 | static int inited; | |
80 | ||
81 | cs->env_ptr = &cpu->env; | |
82 | cpu_exec_init(&cpu->env); | |
83 | ||
84 | #ifndef CONFIG_USER_ONLY | |
85 | cpu_openrisc_mmu_init(cpu); | |
86 | #endif | |
87 | ||
88 | if (tcg_enabled() && !inited) { | |
89 | inited = 1; | |
90 | openrisc_translate_init(); | |
91 | } | |
92 | } | |
93 | ||
94 | /* CPU models */ | |
95 | ||
96 | static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model) | |
97 | { | |
98 | ObjectClass *oc; | |
99 | char *typename; | |
100 | ||
101 | if (cpu_model == NULL) { | |
102 | return NULL; | |
103 | } | |
104 | ||
105 | typename = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, cpu_model); | |
106 | oc = object_class_by_name(typename); | |
107 | if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) || | |
108 | object_class_is_abstract(oc))) { | |
109 | return NULL; | |
110 | } | |
111 | return oc; | |
112 | } | |
113 | ||
114 | static void or1200_initfn(Object *obj) | |
115 | { | |
116 | OpenRISCCPU *cpu = OPENRISC_CPU(obj); | |
117 | ||
118 | set_feature(cpu, OPENRISC_FEATURE_OB32S); | |
119 | set_feature(cpu, OPENRISC_FEATURE_OF32S); | |
120 | } | |
121 | ||
122 | static void openrisc_any_initfn(Object *obj) | |
123 | { | |
124 | OpenRISCCPU *cpu = OPENRISC_CPU(obj); | |
125 | ||
126 | set_feature(cpu, OPENRISC_FEATURE_OB32S); | |
127 | } | |
128 | ||
129 | typedef struct OpenRISCCPUInfo { | |
130 | const char *name; | |
131 | void (*initfn)(Object *obj); | |
132 | } OpenRISCCPUInfo; | |
133 | ||
134 | static const OpenRISCCPUInfo openrisc_cpus[] = { | |
135 | { .name = "or1200", .initfn = or1200_initfn }, | |
136 | { .name = "any", .initfn = openrisc_any_initfn }, | |
137 | }; | |
138 | ||
139 | static void openrisc_cpu_class_init(ObjectClass *oc, void *data) | |
140 | { | |
141 | OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc); | |
142 | CPUClass *cc = CPU_CLASS(occ); | |
143 | DeviceClass *dc = DEVICE_CLASS(oc); | |
144 | ||
145 | occ->parent_realize = dc->realize; | |
146 | dc->realize = openrisc_cpu_realizefn; | |
147 | ||
148 | occ->parent_reset = cc->reset; | |
149 | cc->reset = openrisc_cpu_reset; | |
150 | ||
151 | cc->class_by_name = openrisc_cpu_class_by_name; | |
152 | cc->do_interrupt = openrisc_cpu_do_interrupt; | |
153 | cc->dump_state = openrisc_cpu_dump_state; | |
154 | device_class_set_vmsd(dc, &vmstate_openrisc_cpu); | |
155 | } | |
156 | ||
157 | static void cpu_register(const OpenRISCCPUInfo *info) | |
158 | { | |
159 | TypeInfo type_info = { | |
160 | .parent = TYPE_OPENRISC_CPU, | |
161 | .instance_size = sizeof(OpenRISCCPU), | |
162 | .instance_init = info->initfn, | |
163 | .class_size = sizeof(OpenRISCCPUClass), | |
164 | }; | |
165 | ||
166 | type_info.name = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, info->name); | |
167 | type_register(&type_info); | |
168 | g_free((void *)type_info.name); | |
169 | } | |
170 | ||
171 | static const TypeInfo openrisc_cpu_type_info = { | |
172 | .name = TYPE_OPENRISC_CPU, | |
173 | .parent = TYPE_CPU, | |
174 | .instance_size = sizeof(OpenRISCCPU), | |
175 | .instance_init = openrisc_cpu_initfn, | |
176 | .abstract = true, | |
177 | .class_size = sizeof(OpenRISCCPUClass), | |
178 | .class_init = openrisc_cpu_class_init, | |
179 | }; | |
180 | ||
181 | static void openrisc_cpu_register_types(void) | |
182 | { | |
183 | int i; | |
184 | ||
185 | type_register_static(&openrisc_cpu_type_info); | |
186 | for (i = 0; i < ARRAY_SIZE(openrisc_cpus); i++) { | |
187 | cpu_register(&openrisc_cpus[i]); | |
188 | } | |
189 | } | |
190 | ||
191 | OpenRISCCPU *cpu_openrisc_init(const char *cpu_model) | |
192 | { | |
193 | OpenRISCCPU *cpu; | |
194 | ObjectClass *oc; | |
195 | ||
196 | oc = openrisc_cpu_class_by_name(cpu_model); | |
197 | if (oc == NULL) { | |
198 | return NULL; | |
199 | } | |
200 | cpu = OPENRISC_CPU(object_new(object_class_get_name(oc))); | |
201 | cpu->env.cpu_model_str = cpu_model; | |
202 | ||
203 | object_property_set_bool(OBJECT(cpu), true, "realized", NULL); | |
204 | ||
205 | return cpu; | |
206 | } | |
207 | ||
208 | /* Sort alphabetically by type name, except for "any". */ | |
209 | static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b) | |
210 | { | |
211 | ObjectClass *class_a = (ObjectClass *)a; | |
212 | ObjectClass *class_b = (ObjectClass *)b; | |
213 | const char *name_a, *name_b; | |
214 | ||
215 | name_a = object_class_get_name(class_a); | |
216 | name_b = object_class_get_name(class_b); | |
217 | if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) { | |
218 | return 1; | |
219 | } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) { | |
220 | return -1; | |
221 | } else { | |
222 | return strcmp(name_a, name_b); | |
223 | } | |
224 | } | |
225 | ||
226 | static void openrisc_cpu_list_entry(gpointer data, gpointer user_data) | |
227 | { | |
228 | ObjectClass *oc = data; | |
229 | CPUListState *s = user_data; | |
230 | const char *typename; | |
231 | char *name; | |
232 | ||
233 | typename = object_class_get_name(oc); | |
234 | name = g_strndup(typename, | |
235 | strlen(typename) - strlen("-" TYPE_OPENRISC_CPU)); | |
236 | (*s->cpu_fprintf)(s->file, " %s\n", | |
237 | name); | |
238 | g_free(name); | |
239 | } | |
240 | ||
241 | void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf) | |
242 | { | |
243 | CPUListState s = { | |
244 | .file = f, | |
245 | .cpu_fprintf = cpu_fprintf, | |
246 | }; | |
247 | GSList *list; | |
248 | ||
249 | list = object_class_get_list(TYPE_OPENRISC_CPU, false); | |
250 | list = g_slist_sort(list, openrisc_cpu_list_compare); | |
251 | (*cpu_fprintf)(f, "Available CPUs:\n"); | |
252 | g_slist_foreach(list, openrisc_cpu_list_entry, &s); | |
253 | g_slist_free(list); | |
254 | } | |
255 | ||
256 | type_init(openrisc_cpu_register_types) |