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1 | /* | |
2 | * PowerPC emulation for qemu: main translation routines. | |
3 | * | |
4 | * Copyright (c) 2003-2007 Jocelyn Mayer | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | #include <stdarg.h> | |
21 | #include <stdlib.h> | |
22 | #include <stdio.h> | |
23 | #include <string.h> | |
24 | #include <inttypes.h> | |
25 | ||
26 | #include "cpu.h" | |
27 | #include "exec-all.h" | |
28 | #include "disas.h" | |
29 | #include "tcg-op.h" | |
30 | #include "qemu-common.h" | |
31 | ||
32 | #include "helper.h" | |
33 | #define GEN_HELPER 1 | |
34 | #include "helper.h" | |
35 | ||
36 | #define CPU_SINGLE_STEP 0x1 | |
37 | #define CPU_BRANCH_STEP 0x2 | |
38 | #define GDBSTUB_SINGLE_STEP 0x4 | |
39 | ||
40 | /* Include definitions for instructions classes and implementations flags */ | |
41 | //#define DO_SINGLE_STEP | |
42 | //#define PPC_DEBUG_DISAS | |
43 | //#define DO_PPC_STATISTICS | |
44 | //#define OPTIMIZE_FPRF_UPDATE | |
45 | ||
46 | /*****************************************************************************/ | |
47 | /* Code translation helpers */ | |
48 | ||
49 | /* global register indexes */ | |
50 | static TCGv_ptr cpu_env; | |
51 | static char cpu_reg_names[10*3 + 22*4 /* GPR */ | |
52 | #if !defined(TARGET_PPC64) | |
53 | + 10*4 + 22*5 /* SPE GPRh */ | |
54 | #endif | |
55 | + 10*4 + 22*5 /* FPR */ | |
56 | + 2*(10*6 + 22*7) /* AVRh, AVRl */ | |
57 | + 8*5 /* CRF */]; | |
58 | static TCGv cpu_gpr[32]; | |
59 | #if !defined(TARGET_PPC64) | |
60 | static TCGv cpu_gprh[32]; | |
61 | #endif | |
62 | static TCGv_i64 cpu_fpr[32]; | |
63 | static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; | |
64 | static TCGv_i32 cpu_crf[8]; | |
65 | static TCGv cpu_nip; | |
66 | static TCGv cpu_ctr; | |
67 | static TCGv cpu_lr; | |
68 | static TCGv cpu_xer; | |
69 | static TCGv_i32 cpu_fpscr; | |
70 | static TCGv_i32 cpu_access_type; | |
71 | ||
72 | /* dyngen register indexes */ | |
73 | static TCGv cpu_T[3]; | |
74 | ||
75 | #include "gen-icount.h" | |
76 | ||
77 | void ppc_translate_init(void) | |
78 | { | |
79 | int i; | |
80 | char* p; | |
81 | static int done_init = 0; | |
82 | ||
83 | if (done_init) | |
84 | return; | |
85 | ||
86 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); | |
87 | #if TARGET_LONG_BITS > HOST_LONG_BITS | |
88 | cpu_T[0] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t0), "T0"); | |
89 | cpu_T[1] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t1), "T1"); | |
90 | cpu_T[2] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t2), "T2"); | |
91 | #else | |
92 | cpu_T[0] = tcg_global_reg_new(TCG_AREG1, "T0"); | |
93 | cpu_T[1] = tcg_global_reg_new(TCG_AREG2, "T1"); | |
94 | #ifdef HOST_I386 | |
95 | /* XXX: This is a temporary workaround for i386. | |
96 | * On i386 qemu_st32 runs out of registers. | |
97 | * The proper fix is to remove cpu_T. | |
98 | */ | |
99 | cpu_T[2] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t2), "T2"); | |
100 | #else | |
101 | cpu_T[2] = tcg_global_reg_new(TCG_AREG3, "T2"); | |
102 | #endif | |
103 | #endif | |
104 | ||
105 | p = cpu_reg_names; | |
106 | ||
107 | for (i = 0; i < 8; i++) { | |
108 | sprintf(p, "crf%d", i); | |
109 | cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0, | |
110 | offsetof(CPUState, crf[i]), p); | |
111 | p += 5; | |
112 | } | |
113 | ||
114 | for (i = 0; i < 32; i++) { | |
115 | sprintf(p, "r%d", i); | |
116 | cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0, | |
117 | offsetof(CPUState, gpr[i]), p); | |
118 | p += (i < 10) ? 3 : 4; | |
119 | #if !defined(TARGET_PPC64) | |
120 | sprintf(p, "r%dH", i); | |
121 | cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0, | |
122 | offsetof(CPUState, gprh[i]), p); | |
123 | p += (i < 10) ? 4 : 5; | |
124 | #endif | |
125 | ||
126 | sprintf(p, "fp%d", i); | |
127 | cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0, | |
128 | offsetof(CPUState, fpr[i]), p); | |
129 | p += (i < 10) ? 4 : 5; | |
130 | ||
131 | sprintf(p, "avr%dH", i); | |
132 | #ifdef WORDS_BIGENDIAN | |
133 | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, | |
134 | offsetof(CPUState, avr[i].u64[0]), p); | |
135 | #else | |
136 | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, | |
137 | offsetof(CPUState, avr[i].u64[1]), p); | |
138 | #endif | |
139 | p += (i < 10) ? 6 : 7; | |
140 | ||
141 | sprintf(p, "avr%dL", i); | |
142 | #ifdef WORDS_BIGENDIAN | |
143 | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, | |
144 | offsetof(CPUState, avr[i].u64[1]), p); | |
145 | #else | |
146 | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, | |
147 | offsetof(CPUState, avr[i].u64[0]), p); | |
148 | #endif | |
149 | p += (i < 10) ? 6 : 7; | |
150 | } | |
151 | ||
152 | cpu_nip = tcg_global_mem_new(TCG_AREG0, | |
153 | offsetof(CPUState, nip), "nip"); | |
154 | ||
155 | cpu_ctr = tcg_global_mem_new(TCG_AREG0, | |
156 | offsetof(CPUState, ctr), "ctr"); | |
157 | ||
158 | cpu_lr = tcg_global_mem_new(TCG_AREG0, | |
159 | offsetof(CPUState, lr), "lr"); | |
160 | ||
161 | cpu_xer = tcg_global_mem_new(TCG_AREG0, | |
162 | offsetof(CPUState, xer), "xer"); | |
163 | ||
164 | cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0, | |
165 | offsetof(CPUState, fpscr), "fpscr"); | |
166 | ||
167 | cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0, | |
168 | offsetof(CPUState, access_type), "access_type"); | |
169 | ||
170 | /* register helpers */ | |
171 | #define GEN_HELPER 2 | |
172 | #include "helper.h" | |
173 | ||
174 | done_init = 1; | |
175 | } | |
176 | ||
177 | #if defined(OPTIMIZE_FPRF_UPDATE) | |
178 | static uint16_t *gen_fprf_buf[OPC_BUF_SIZE]; | |
179 | static uint16_t **gen_fprf_ptr; | |
180 | #endif | |
181 | ||
182 | /* internal defines */ | |
183 | typedef struct DisasContext { | |
184 | struct TranslationBlock *tb; | |
185 | target_ulong nip; | |
186 | uint32_t opcode; | |
187 | uint32_t exception; | |
188 | /* Routine used to access memory */ | |
189 | int mem_idx; | |
190 | /* Translation flags */ | |
191 | #if !defined(CONFIG_USER_ONLY) | |
192 | int supervisor; | |
193 | #endif | |
194 | #if defined(TARGET_PPC64) | |
195 | int sf_mode; | |
196 | #endif | |
197 | int fpu_enabled; | |
198 | int altivec_enabled; | |
199 | int spe_enabled; | |
200 | ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ | |
201 | int singlestep_enabled; | |
202 | } DisasContext; | |
203 | ||
204 | struct opc_handler_t { | |
205 | /* invalid bits */ | |
206 | uint32_t inval; | |
207 | /* instruction type */ | |
208 | uint64_t type; | |
209 | /* handler */ | |
210 | void (*handler)(DisasContext *ctx); | |
211 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) | |
212 | const char *oname; | |
213 | #endif | |
214 | #if defined(DO_PPC_STATISTICS) | |
215 | uint64_t count; | |
216 | #endif | |
217 | }; | |
218 | ||
219 | static always_inline void gen_reset_fpstatus (void) | |
220 | { | |
221 | #ifdef CONFIG_SOFTFLOAT | |
222 | gen_op_reset_fpstatus(); | |
223 | #endif | |
224 | } | |
225 | ||
226 | static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc) | |
227 | { | |
228 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
229 | ||
230 | if (set_fprf != 0) { | |
231 | /* This case might be optimized later */ | |
232 | #if defined(OPTIMIZE_FPRF_UPDATE) | |
233 | *gen_fprf_ptr++ = gen_opc_ptr; | |
234 | #endif | |
235 | tcg_gen_movi_i32(t0, 1); | |
236 | gen_helper_compute_fprf(t0, arg, t0); | |
237 | if (unlikely(set_rc)) { | |
238 | tcg_gen_mov_i32(cpu_crf[1], t0); | |
239 | } | |
240 | gen_helper_float_check_status(); | |
241 | } else if (unlikely(set_rc)) { | |
242 | /* We always need to compute fpcc */ | |
243 | tcg_gen_movi_i32(t0, 0); | |
244 | gen_helper_compute_fprf(t0, arg, t0); | |
245 | tcg_gen_mov_i32(cpu_crf[1], t0); | |
246 | if (set_fprf) | |
247 | gen_helper_float_check_status(); | |
248 | } | |
249 | ||
250 | tcg_temp_free_i32(t0); | |
251 | } | |
252 | ||
253 | static always_inline void gen_optimize_fprf (void) | |
254 | { | |
255 | #if defined(OPTIMIZE_FPRF_UPDATE) | |
256 | uint16_t **ptr; | |
257 | ||
258 | for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++) | |
259 | *ptr = INDEX_op_nop1; | |
260 | gen_fprf_ptr = gen_fprf_buf; | |
261 | #endif | |
262 | } | |
263 | ||
264 | static always_inline void gen_set_access_type(int access_type) | |
265 | { | |
266 | tcg_gen_movi_i32(cpu_access_type, access_type); | |
267 | } | |
268 | ||
269 | static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip) | |
270 | { | |
271 | #if defined(TARGET_PPC64) | |
272 | if (ctx->sf_mode) | |
273 | tcg_gen_movi_tl(cpu_nip, nip); | |
274 | else | |
275 | #endif | |
276 | tcg_gen_movi_tl(cpu_nip, (uint32_t)nip); | |
277 | } | |
278 | ||
279 | #define GEN_EXCP(ctx, excp, error) \ | |
280 | do { \ | |
281 | TCGv_i32 t0 = tcg_const_i32(excp); \ | |
282 | TCGv_i32 t1 = tcg_const_i32(error); \ | |
283 | if ((ctx)->exception == POWERPC_EXCP_NONE) { \ | |
284 | gen_update_nip(ctx, (ctx)->nip); \ | |
285 | } \ | |
286 | gen_helper_raise_exception_err(t0, t1); \ | |
287 | tcg_temp_free_i32(t0); \ | |
288 | tcg_temp_free_i32(t1); \ | |
289 | ctx->exception = (excp); \ | |
290 | } while (0) | |
291 | ||
292 | #define GEN_EXCP_INVAL(ctx) \ | |
293 | GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \ | |
294 | POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL) | |
295 | ||
296 | #define GEN_EXCP_PRIVOPC(ctx) \ | |
297 | GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \ | |
298 | POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC) | |
299 | ||
300 | #define GEN_EXCP_PRIVREG(ctx) \ | |
301 | GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \ | |
302 | POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG) | |
303 | ||
304 | #define GEN_EXCP_NO_FP(ctx) \ | |
305 | GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0) | |
306 | ||
307 | #define GEN_EXCP_NO_AP(ctx) \ | |
308 | GEN_EXCP(ctx, POWERPC_EXCP_APU, 0) | |
309 | ||
310 | #define GEN_EXCP_NO_VR(ctx) \ | |
311 | GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0) | |
312 | ||
313 | /* Stop translation */ | |
314 | static always_inline void GEN_STOP (DisasContext *ctx) | |
315 | { | |
316 | gen_update_nip(ctx, ctx->nip); | |
317 | ctx->exception = POWERPC_EXCP_STOP; | |
318 | } | |
319 | ||
320 | /* No need to update nip here, as execution flow will change */ | |
321 | static always_inline void GEN_SYNC (DisasContext *ctx) | |
322 | { | |
323 | ctx->exception = POWERPC_EXCP_SYNC; | |
324 | } | |
325 | ||
326 | #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ | |
327 | static void gen_##name (DisasContext *ctx); \ | |
328 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \ | |
329 | static void gen_##name (DisasContext *ctx) | |
330 | ||
331 | #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ | |
332 | static void gen_##name (DisasContext *ctx); \ | |
333 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \ | |
334 | static void gen_##name (DisasContext *ctx) | |
335 | ||
336 | typedef struct opcode_t { | |
337 | unsigned char opc1, opc2, opc3; | |
338 | #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ | |
339 | unsigned char pad[5]; | |
340 | #else | |
341 | unsigned char pad[1]; | |
342 | #endif | |
343 | opc_handler_t handler; | |
344 | const char *oname; | |
345 | } opcode_t; | |
346 | ||
347 | /*****************************************************************************/ | |
348 | /*** Instruction decoding ***/ | |
349 | #define EXTRACT_HELPER(name, shift, nb) \ | |
350 | static always_inline uint32_t name (uint32_t opcode) \ | |
351 | { \ | |
352 | return (opcode >> (shift)) & ((1 << (nb)) - 1); \ | |
353 | } | |
354 | ||
355 | #define EXTRACT_SHELPER(name, shift, nb) \ | |
356 | static always_inline int32_t name (uint32_t opcode) \ | |
357 | { \ | |
358 | return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \ | |
359 | } | |
360 | ||
361 | /* Opcode part 1 */ | |
362 | EXTRACT_HELPER(opc1, 26, 6); | |
363 | /* Opcode part 2 */ | |
364 | EXTRACT_HELPER(opc2, 1, 5); | |
365 | /* Opcode part 3 */ | |
366 | EXTRACT_HELPER(opc3, 6, 5); | |
367 | /* Update Cr0 flags */ | |
368 | EXTRACT_HELPER(Rc, 0, 1); | |
369 | /* Destination */ | |
370 | EXTRACT_HELPER(rD, 21, 5); | |
371 | /* Source */ | |
372 | EXTRACT_HELPER(rS, 21, 5); | |
373 | /* First operand */ | |
374 | EXTRACT_HELPER(rA, 16, 5); | |
375 | /* Second operand */ | |
376 | EXTRACT_HELPER(rB, 11, 5); | |
377 | /* Third operand */ | |
378 | EXTRACT_HELPER(rC, 6, 5); | |
379 | /*** Get CRn ***/ | |
380 | EXTRACT_HELPER(crfD, 23, 3); | |
381 | EXTRACT_HELPER(crfS, 18, 3); | |
382 | EXTRACT_HELPER(crbD, 21, 5); | |
383 | EXTRACT_HELPER(crbA, 16, 5); | |
384 | EXTRACT_HELPER(crbB, 11, 5); | |
385 | /* SPR / TBL */ | |
386 | EXTRACT_HELPER(_SPR, 11, 10); | |
387 | static always_inline uint32_t SPR (uint32_t opcode) | |
388 | { | |
389 | uint32_t sprn = _SPR(opcode); | |
390 | ||
391 | return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); | |
392 | } | |
393 | /*** Get constants ***/ | |
394 | EXTRACT_HELPER(IMM, 12, 8); | |
395 | /* 16 bits signed immediate value */ | |
396 | EXTRACT_SHELPER(SIMM, 0, 16); | |
397 | /* 16 bits unsigned immediate value */ | |
398 | EXTRACT_HELPER(UIMM, 0, 16); | |
399 | /* Bit count */ | |
400 | EXTRACT_HELPER(NB, 11, 5); | |
401 | /* Shift count */ | |
402 | EXTRACT_HELPER(SH, 11, 5); | |
403 | /* Mask start */ | |
404 | EXTRACT_HELPER(MB, 6, 5); | |
405 | /* Mask end */ | |
406 | EXTRACT_HELPER(ME, 1, 5); | |
407 | /* Trap operand */ | |
408 | EXTRACT_HELPER(TO, 21, 5); | |
409 | ||
410 | EXTRACT_HELPER(CRM, 12, 8); | |
411 | EXTRACT_HELPER(FM, 17, 8); | |
412 | EXTRACT_HELPER(SR, 16, 4); | |
413 | EXTRACT_HELPER(FPIMM, 12, 4); | |
414 | ||
415 | /*** Jump target decoding ***/ | |
416 | /* Displacement */ | |
417 | EXTRACT_SHELPER(d, 0, 16); | |
418 | /* Immediate address */ | |
419 | static always_inline target_ulong LI (uint32_t opcode) | |
420 | { | |
421 | return (opcode >> 0) & 0x03FFFFFC; | |
422 | } | |
423 | ||
424 | static always_inline uint32_t BD (uint32_t opcode) | |
425 | { | |
426 | return (opcode >> 0) & 0xFFFC; | |
427 | } | |
428 | ||
429 | EXTRACT_HELPER(BO, 21, 5); | |
430 | EXTRACT_HELPER(BI, 16, 5); | |
431 | /* Absolute/relative address */ | |
432 | EXTRACT_HELPER(AA, 1, 1); | |
433 | /* Link */ | |
434 | EXTRACT_HELPER(LK, 0, 1); | |
435 | ||
436 | /* Create a mask between <start> and <end> bits */ | |
437 | static always_inline target_ulong MASK (uint32_t start, uint32_t end) | |
438 | { | |
439 | target_ulong ret; | |
440 | ||
441 | #if defined(TARGET_PPC64) | |
442 | if (likely(start == 0)) { | |
443 | ret = UINT64_MAX << (63 - end); | |
444 | } else if (likely(end == 63)) { | |
445 | ret = UINT64_MAX >> start; | |
446 | } | |
447 | #else | |
448 | if (likely(start == 0)) { | |
449 | ret = UINT32_MAX << (31 - end); | |
450 | } else if (likely(end == 31)) { | |
451 | ret = UINT32_MAX >> start; | |
452 | } | |
453 | #endif | |
454 | else { | |
455 | ret = (((target_ulong)(-1ULL)) >> (start)) ^ | |
456 | (((target_ulong)(-1ULL) >> (end)) >> 1); | |
457 | if (unlikely(start > end)) | |
458 | return ~ret; | |
459 | } | |
460 | ||
461 | return ret; | |
462 | } | |
463 | ||
464 | /*****************************************************************************/ | |
465 | /* PowerPC Instructions types definitions */ | |
466 | enum { | |
467 | PPC_NONE = 0x0000000000000000ULL, | |
468 | /* PowerPC base instructions set */ | |
469 | PPC_INSNS_BASE = 0x0000000000000001ULL, | |
470 | /* integer operations instructions */ | |
471 | #define PPC_INTEGER PPC_INSNS_BASE | |
472 | /* flow control instructions */ | |
473 | #define PPC_FLOW PPC_INSNS_BASE | |
474 | /* virtual memory instructions */ | |
475 | #define PPC_MEM PPC_INSNS_BASE | |
476 | /* ld/st with reservation instructions */ | |
477 | #define PPC_RES PPC_INSNS_BASE | |
478 | /* spr/msr access instructions */ | |
479 | #define PPC_MISC PPC_INSNS_BASE | |
480 | /* Deprecated instruction sets */ | |
481 | /* Original POWER instruction set */ | |
482 | PPC_POWER = 0x0000000000000002ULL, | |
483 | /* POWER2 instruction set extension */ | |
484 | PPC_POWER2 = 0x0000000000000004ULL, | |
485 | /* Power RTC support */ | |
486 | PPC_POWER_RTC = 0x0000000000000008ULL, | |
487 | /* Power-to-PowerPC bridge (601) */ | |
488 | PPC_POWER_BR = 0x0000000000000010ULL, | |
489 | /* 64 bits PowerPC instruction set */ | |
490 | PPC_64B = 0x0000000000000020ULL, | |
491 | /* New 64 bits extensions (PowerPC 2.0x) */ | |
492 | PPC_64BX = 0x0000000000000040ULL, | |
493 | /* 64 bits hypervisor extensions */ | |
494 | PPC_64H = 0x0000000000000080ULL, | |
495 | /* New wait instruction (PowerPC 2.0x) */ | |
496 | PPC_WAIT = 0x0000000000000100ULL, | |
497 | /* Time base mftb instruction */ | |
498 | PPC_MFTB = 0x0000000000000200ULL, | |
499 | ||
500 | /* Fixed-point unit extensions */ | |
501 | /* PowerPC 602 specific */ | |
502 | PPC_602_SPEC = 0x0000000000000400ULL, | |
503 | /* isel instruction */ | |
504 | PPC_ISEL = 0x0000000000000800ULL, | |
505 | /* popcntb instruction */ | |
506 | PPC_POPCNTB = 0x0000000000001000ULL, | |
507 | /* string load / store */ | |
508 | PPC_STRING = 0x0000000000002000ULL, | |
509 | ||
510 | /* Floating-point unit extensions */ | |
511 | /* Optional floating point instructions */ | |
512 | PPC_FLOAT = 0x0000000000010000ULL, | |
513 | /* New floating-point extensions (PowerPC 2.0x) */ | |
514 | PPC_FLOAT_EXT = 0x0000000000020000ULL, | |
515 | PPC_FLOAT_FSQRT = 0x0000000000040000ULL, | |
516 | PPC_FLOAT_FRES = 0x0000000000080000ULL, | |
517 | PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL, | |
518 | PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL, | |
519 | PPC_FLOAT_FSEL = 0x0000000000400000ULL, | |
520 | PPC_FLOAT_STFIWX = 0x0000000000800000ULL, | |
521 | ||
522 | /* Vector/SIMD extensions */ | |
523 | /* Altivec support */ | |
524 | PPC_ALTIVEC = 0x0000000001000000ULL, | |
525 | /* PowerPC 2.03 SPE extension */ | |
526 | PPC_SPE = 0x0000000002000000ULL, | |
527 | /* PowerPC 2.03 SPE floating-point extension */ | |
528 | PPC_SPEFPU = 0x0000000004000000ULL, | |
529 | ||
530 | /* Optional memory control instructions */ | |
531 | PPC_MEM_TLBIA = 0x0000000010000000ULL, | |
532 | PPC_MEM_TLBIE = 0x0000000020000000ULL, | |
533 | PPC_MEM_TLBSYNC = 0x0000000040000000ULL, | |
534 | /* sync instruction */ | |
535 | PPC_MEM_SYNC = 0x0000000080000000ULL, | |
536 | /* eieio instruction */ | |
537 | PPC_MEM_EIEIO = 0x0000000100000000ULL, | |
538 | ||
539 | /* Cache control instructions */ | |
540 | PPC_CACHE = 0x0000000200000000ULL, | |
541 | /* icbi instruction */ | |
542 | PPC_CACHE_ICBI = 0x0000000400000000ULL, | |
543 | /* dcbz instruction with fixed cache line size */ | |
544 | PPC_CACHE_DCBZ = 0x0000000800000000ULL, | |
545 | /* dcbz instruction with tunable cache line size */ | |
546 | PPC_CACHE_DCBZT = 0x0000001000000000ULL, | |
547 | /* dcba instruction */ | |
548 | PPC_CACHE_DCBA = 0x0000002000000000ULL, | |
549 | /* Freescale cache locking instructions */ | |
550 | PPC_CACHE_LOCK = 0x0000004000000000ULL, | |
551 | ||
552 | /* MMU related extensions */ | |
553 | /* external control instructions */ | |
554 | PPC_EXTERN = 0x0000010000000000ULL, | |
555 | /* segment register access instructions */ | |
556 | PPC_SEGMENT = 0x0000020000000000ULL, | |
557 | /* PowerPC 6xx TLB management instructions */ | |
558 | PPC_6xx_TLB = 0x0000040000000000ULL, | |
559 | /* PowerPC 74xx TLB management instructions */ | |
560 | PPC_74xx_TLB = 0x0000080000000000ULL, | |
561 | /* PowerPC 40x TLB management instructions */ | |
562 | PPC_40x_TLB = 0x0000100000000000ULL, | |
563 | /* segment register access instructions for PowerPC 64 "bridge" */ | |
564 | PPC_SEGMENT_64B = 0x0000200000000000ULL, | |
565 | /* SLB management */ | |
566 | PPC_SLBI = 0x0000400000000000ULL, | |
567 | ||
568 | /* Embedded PowerPC dedicated instructions */ | |
569 | PPC_WRTEE = 0x0001000000000000ULL, | |
570 | /* PowerPC 40x exception model */ | |
571 | PPC_40x_EXCP = 0x0002000000000000ULL, | |
572 | /* PowerPC 405 Mac instructions */ | |
573 | PPC_405_MAC = 0x0004000000000000ULL, | |
574 | /* PowerPC 440 specific instructions */ | |
575 | PPC_440_SPEC = 0x0008000000000000ULL, | |
576 | /* BookE (embedded) PowerPC specification */ | |
577 | PPC_BOOKE = 0x0010000000000000ULL, | |
578 | /* mfapidi instruction */ | |
579 | PPC_MFAPIDI = 0x0020000000000000ULL, | |
580 | /* tlbiva instruction */ | |
581 | PPC_TLBIVA = 0x0040000000000000ULL, | |
582 | /* tlbivax instruction */ | |
583 | PPC_TLBIVAX = 0x0080000000000000ULL, | |
584 | /* PowerPC 4xx dedicated instructions */ | |
585 | PPC_4xx_COMMON = 0x0100000000000000ULL, | |
586 | /* PowerPC 40x ibct instructions */ | |
587 | PPC_40x_ICBT = 0x0200000000000000ULL, | |
588 | /* rfmci is not implemented in all BookE PowerPC */ | |
589 | PPC_RFMCI = 0x0400000000000000ULL, | |
590 | /* rfdi instruction */ | |
591 | PPC_RFDI = 0x0800000000000000ULL, | |
592 | /* DCR accesses */ | |
593 | PPC_DCR = 0x1000000000000000ULL, | |
594 | /* DCR extended accesse */ | |
595 | PPC_DCRX = 0x2000000000000000ULL, | |
596 | /* user-mode DCR access, implemented in PowerPC 460 */ | |
597 | PPC_DCRUX = 0x4000000000000000ULL, | |
598 | }; | |
599 | ||
600 | /*****************************************************************************/ | |
601 | /* PowerPC instructions table */ | |
602 | #if HOST_LONG_BITS == 64 | |
603 | #define OPC_ALIGN 8 | |
604 | #else | |
605 | #define OPC_ALIGN 4 | |
606 | #endif | |
607 | #if defined(__APPLE__) | |
608 | #define OPCODES_SECTION \ | |
609 | __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) )) | |
610 | #else | |
611 | #define OPCODES_SECTION \ | |
612 | __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) )) | |
613 | #endif | |
614 | ||
615 | #if defined(DO_PPC_STATISTICS) | |
616 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \ | |
617 | OPCODES_SECTION opcode_t opc_##name = { \ | |
618 | .opc1 = op1, \ | |
619 | .opc2 = op2, \ | |
620 | .opc3 = op3, \ | |
621 | .pad = { 0, }, \ | |
622 | .handler = { \ | |
623 | .inval = invl, \ | |
624 | .type = _typ, \ | |
625 | .handler = &gen_##name, \ | |
626 | .oname = stringify(name), \ | |
627 | }, \ | |
628 | .oname = stringify(name), \ | |
629 | } | |
630 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \ | |
631 | OPCODES_SECTION opcode_t opc_##name = { \ | |
632 | .opc1 = op1, \ | |
633 | .opc2 = op2, \ | |
634 | .opc3 = op3, \ | |
635 | .pad = { 0, }, \ | |
636 | .handler = { \ | |
637 | .inval = invl, \ | |
638 | .type = _typ, \ | |
639 | .handler = &gen_##name, \ | |
640 | .oname = onam, \ | |
641 | }, \ | |
642 | .oname = onam, \ | |
643 | } | |
644 | #else | |
645 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \ | |
646 | OPCODES_SECTION opcode_t opc_##name = { \ | |
647 | .opc1 = op1, \ | |
648 | .opc2 = op2, \ | |
649 | .opc3 = op3, \ | |
650 | .pad = { 0, }, \ | |
651 | .handler = { \ | |
652 | .inval = invl, \ | |
653 | .type = _typ, \ | |
654 | .handler = &gen_##name, \ | |
655 | }, \ | |
656 | .oname = stringify(name), \ | |
657 | } | |
658 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \ | |
659 | OPCODES_SECTION opcode_t opc_##name = { \ | |
660 | .opc1 = op1, \ | |
661 | .opc2 = op2, \ | |
662 | .opc3 = op3, \ | |
663 | .pad = { 0, }, \ | |
664 | .handler = { \ | |
665 | .inval = invl, \ | |
666 | .type = _typ, \ | |
667 | .handler = &gen_##name, \ | |
668 | }, \ | |
669 | .oname = onam, \ | |
670 | } | |
671 | #endif | |
672 | ||
673 | #define GEN_OPCODE_MARK(name) \ | |
674 | OPCODES_SECTION opcode_t opc_##name = { \ | |
675 | .opc1 = 0xFF, \ | |
676 | .opc2 = 0xFF, \ | |
677 | .opc3 = 0xFF, \ | |
678 | .pad = { 0, }, \ | |
679 | .handler = { \ | |
680 | .inval = 0x00000000, \ | |
681 | .type = 0x00, \ | |
682 | .handler = NULL, \ | |
683 | }, \ | |
684 | .oname = stringify(name), \ | |
685 | } | |
686 | ||
687 | /* Start opcode list */ | |
688 | GEN_OPCODE_MARK(start); | |
689 | ||
690 | /* Invalid instruction */ | |
691 | GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE) | |
692 | { | |
693 | GEN_EXCP_INVAL(ctx); | |
694 | } | |
695 | ||
696 | static opc_handler_t invalid_handler = { | |
697 | .inval = 0xFFFFFFFF, | |
698 | .type = PPC_NONE, | |
699 | .handler = gen_invalid, | |
700 | }; | |
701 | ||
702 | /*** Integer comparison ***/ | |
703 | ||
704 | static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) | |
705 | { | |
706 | int l1, l2, l3; | |
707 | ||
708 | tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer); | |
709 | tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO); | |
710 | tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1); | |
711 | ||
712 | l1 = gen_new_label(); | |
713 | l2 = gen_new_label(); | |
714 | l3 = gen_new_label(); | |
715 | if (s) { | |
716 | tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1); | |
717 | tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2); | |
718 | } else { | |
719 | tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1); | |
720 | tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2); | |
721 | } | |
722 | tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ); | |
723 | tcg_gen_br(l3); | |
724 | gen_set_label(l1); | |
725 | tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT); | |
726 | tcg_gen_br(l3); | |
727 | gen_set_label(l2); | |
728 | tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT); | |
729 | gen_set_label(l3); | |
730 | } | |
731 | ||
732 | static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) | |
733 | { | |
734 | TCGv t0 = tcg_const_local_tl(arg1); | |
735 | gen_op_cmp(arg0, t0, s, crf); | |
736 | tcg_temp_free(t0); | |
737 | } | |
738 | ||
739 | #if defined(TARGET_PPC64) | |
740 | static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) | |
741 | { | |
742 | TCGv t0, t1; | |
743 | t0 = tcg_temp_local_new(); | |
744 | t1 = tcg_temp_local_new(); | |
745 | if (s) { | |
746 | tcg_gen_ext32s_tl(t0, arg0); | |
747 | tcg_gen_ext32s_tl(t1, arg1); | |
748 | } else { | |
749 | tcg_gen_ext32u_tl(t0, arg0); | |
750 | tcg_gen_ext32u_tl(t1, arg1); | |
751 | } | |
752 | gen_op_cmp(t0, t1, s, crf); | |
753 | tcg_temp_free(t1); | |
754 | tcg_temp_free(t0); | |
755 | } | |
756 | ||
757 | static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) | |
758 | { | |
759 | TCGv t0 = tcg_const_local_tl(arg1); | |
760 | gen_op_cmp32(arg0, t0, s, crf); | |
761 | tcg_temp_free(t0); | |
762 | } | |
763 | #endif | |
764 | ||
765 | static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg) | |
766 | { | |
767 | #if defined(TARGET_PPC64) | |
768 | if (!(ctx->sf_mode)) | |
769 | gen_op_cmpi32(reg, 0, 1, 0); | |
770 | else | |
771 | #endif | |
772 | gen_op_cmpi(reg, 0, 1, 0); | |
773 | } | |
774 | ||
775 | /* cmp */ | |
776 | GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER) | |
777 | { | |
778 | #if defined(TARGET_PPC64) | |
779 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) | |
780 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
781 | 1, crfD(ctx->opcode)); | |
782 | else | |
783 | #endif | |
784 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
785 | 1, crfD(ctx->opcode)); | |
786 | } | |
787 | ||
788 | /* cmpi */ | |
789 | GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER) | |
790 | { | |
791 | #if defined(TARGET_PPC64) | |
792 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) | |
793 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), | |
794 | 1, crfD(ctx->opcode)); | |
795 | else | |
796 | #endif | |
797 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), | |
798 | 1, crfD(ctx->opcode)); | |
799 | } | |
800 | ||
801 | /* cmpl */ | |
802 | GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER) | |
803 | { | |
804 | #if defined(TARGET_PPC64) | |
805 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) | |
806 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
807 | 0, crfD(ctx->opcode)); | |
808 | else | |
809 | #endif | |
810 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
811 | 0, crfD(ctx->opcode)); | |
812 | } | |
813 | ||
814 | /* cmpli */ | |
815 | GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER) | |
816 | { | |
817 | #if defined(TARGET_PPC64) | |
818 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) | |
819 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), | |
820 | 0, crfD(ctx->opcode)); | |
821 | else | |
822 | #endif | |
823 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), | |
824 | 0, crfD(ctx->opcode)); | |
825 | } | |
826 | ||
827 | /* isel (PowerPC 2.03 specification) */ | |
828 | GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL) | |
829 | { | |
830 | int l1, l2; | |
831 | uint32_t bi = rC(ctx->opcode); | |
832 | uint32_t mask; | |
833 | TCGv_i32 t0; | |
834 | ||
835 | l1 = gen_new_label(); | |
836 | l2 = gen_new_label(); | |
837 | ||
838 | mask = 1 << (3 - (bi & 0x03)); | |
839 | t0 = tcg_temp_new_i32(); | |
840 | tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask); | |
841 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); | |
842 | if (rA(ctx->opcode) == 0) | |
843 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
844 | else | |
845 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
846 | tcg_gen_br(l2); | |
847 | gen_set_label(l1); | |
848 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
849 | gen_set_label(l2); | |
850 | tcg_temp_free_i32(t0); | |
851 | } | |
852 | ||
853 | /*** Integer arithmetic ***/ | |
854 | ||
855 | static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub) | |
856 | { | |
857 | int l1; | |
858 | TCGv t0; | |
859 | ||
860 | l1 = gen_new_label(); | |
861 | /* Start with XER OV disabled, the most likely case */ | |
862 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
863 | t0 = tcg_temp_local_new(); | |
864 | tcg_gen_xor_tl(t0, arg0, arg1); | |
865 | #if defined(TARGET_PPC64) | |
866 | if (!ctx->sf_mode) | |
867 | tcg_gen_ext32s_tl(t0, t0); | |
868 | #endif | |
869 | if (sub) | |
870 | tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1); | |
871 | else | |
872 | tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1); | |
873 | tcg_gen_xor_tl(t0, arg1, arg2); | |
874 | #if defined(TARGET_PPC64) | |
875 | if (!ctx->sf_mode) | |
876 | tcg_gen_ext32s_tl(t0, t0); | |
877 | #endif | |
878 | if (sub) | |
879 | tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1); | |
880 | else | |
881 | tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1); | |
882 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
883 | gen_set_label(l1); | |
884 | tcg_temp_free(t0); | |
885 | } | |
886 | ||
887 | static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub) | |
888 | { | |
889 | int l1 = gen_new_label(); | |
890 | ||
891 | #if defined(TARGET_PPC64) | |
892 | if (!(ctx->sf_mode)) { | |
893 | TCGv t0, t1; | |
894 | t0 = tcg_temp_new(); | |
895 | t1 = tcg_temp_new(); | |
896 | ||
897 | tcg_gen_ext32u_tl(t0, arg1); | |
898 | tcg_gen_ext32u_tl(t1, arg2); | |
899 | if (sub) { | |
900 | tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1); | |
901 | } else { | |
902 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); | |
903 | } | |
904 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA); | |
905 | gen_set_label(l1); | |
906 | tcg_temp_free(t0); | |
907 | tcg_temp_free(t1); | |
908 | } else | |
909 | #endif | |
910 | { | |
911 | if (sub) { | |
912 | tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1); | |
913 | } else { | |
914 | tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1); | |
915 | } | |
916 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA); | |
917 | gen_set_label(l1); | |
918 | } | |
919 | } | |
920 | ||
921 | /* Common add function */ | |
922 | static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2, | |
923 | int add_ca, int compute_ca, int compute_ov) | |
924 | { | |
925 | TCGv t0, t1; | |
926 | ||
927 | if ((!compute_ca && !compute_ov) || | |
928 | (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) { | |
929 | t0 = ret; | |
930 | } else { | |
931 | t0 = tcg_temp_local_new(); | |
932 | } | |
933 | ||
934 | if (add_ca) { | |
935 | t1 = tcg_temp_local_new(); | |
936 | tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA)); | |
937 | tcg_gen_shri_tl(t1, t1, XER_CA); | |
938 | } | |
939 | ||
940 | if (compute_ca && compute_ov) { | |
941 | /* Start with XER CA and OV disabled, the most likely case */ | |
942 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV))); | |
943 | } else if (compute_ca) { | |
944 | /* Start with XER CA disabled, the most likely case */ | |
945 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); | |
946 | } else if (compute_ov) { | |
947 | /* Start with XER OV disabled, the most likely case */ | |
948 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
949 | } | |
950 | ||
951 | tcg_gen_add_tl(t0, arg1, arg2); | |
952 | ||
953 | if (compute_ca) { | |
954 | gen_op_arith_compute_ca(ctx, t0, arg1, 0); | |
955 | } | |
956 | if (add_ca) { | |
957 | tcg_gen_add_tl(t0, t0, t1); | |
958 | gen_op_arith_compute_ca(ctx, t0, t1, 0); | |
959 | tcg_temp_free(t1); | |
960 | } | |
961 | if (compute_ov) { | |
962 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); | |
963 | } | |
964 | ||
965 | if (unlikely(Rc(ctx->opcode) != 0)) | |
966 | gen_set_Rc0(ctx, t0); | |
967 | ||
968 | if (!TCGV_EQUAL(t0, ret)) { | |
969 | tcg_gen_mov_tl(ret, t0); | |
970 | tcg_temp_free(t0); | |
971 | } | |
972 | } | |
973 | /* Add functions with two operands */ | |
974 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
975 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \ | |
976 | { \ | |
977 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
978 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
979 | add_ca, compute_ca, compute_ov); \ | |
980 | } | |
981 | /* Add functions with one operand and one immediate */ | |
982 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
983 | add_ca, compute_ca, compute_ov) \ | |
984 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \ | |
985 | { \ | |
986 | TCGv t0 = tcg_const_local_tl(const_val); \ | |
987 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
988 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
989 | add_ca, compute_ca, compute_ov); \ | |
990 | tcg_temp_free(t0); \ | |
991 | } | |
992 | ||
993 | /* add add. addo addo. */ | |
994 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
995 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
996 | /* addc addc. addco addco. */ | |
997 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
998 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
999 | /* adde adde. addeo addeo. */ | |
1000 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
1001 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
1002 | /* addme addme. addmeo addmeo. */ | |
1003 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
1004 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
1005 | /* addze addze. addzeo addzeo.*/ | |
1006 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) | |
1007 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
1008 | /* addi */ | |
1009 | GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) | |
1010 | { | |
1011 | target_long simm = SIMM(ctx->opcode); | |
1012 | ||
1013 | if (rA(ctx->opcode) == 0) { | |
1014 | /* li case */ | |
1015 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); | |
1016 | } else { | |
1017 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm); | |
1018 | } | |
1019 | } | |
1020 | /* addic addic.*/ | |
1021 | static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1, | |
1022 | int compute_Rc0) | |
1023 | { | |
1024 | target_long simm = SIMM(ctx->opcode); | |
1025 | ||
1026 | /* Start with XER CA and OV disabled, the most likely case */ | |
1027 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); | |
1028 | ||
1029 | if (likely(simm != 0)) { | |
1030 | TCGv t0 = tcg_temp_local_new(); | |
1031 | tcg_gen_addi_tl(t0, arg1, simm); | |
1032 | gen_op_arith_compute_ca(ctx, t0, arg1, 0); | |
1033 | tcg_gen_mov_tl(ret, t0); | |
1034 | tcg_temp_free(t0); | |
1035 | } else { | |
1036 | tcg_gen_mov_tl(ret, arg1); | |
1037 | } | |
1038 | if (compute_Rc0) { | |
1039 | gen_set_Rc0(ctx, ret); | |
1040 | } | |
1041 | } | |
1042 | GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) | |
1043 | { | |
1044 | gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0); | |
1045 | } | |
1046 | GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) | |
1047 | { | |
1048 | gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1); | |
1049 | } | |
1050 | /* addis */ | |
1051 | GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) | |
1052 | { | |
1053 | target_long simm = SIMM(ctx->opcode); | |
1054 | ||
1055 | if (rA(ctx->opcode) == 0) { | |
1056 | /* lis case */ | |
1057 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); | |
1058 | } else { | |
1059 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16); | |
1060 | } | |
1061 | } | |
1062 | ||
1063 | static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2, | |
1064 | int sign, int compute_ov) | |
1065 | { | |
1066 | int l1 = gen_new_label(); | |
1067 | int l2 = gen_new_label(); | |
1068 | TCGv_i32 t0 = tcg_temp_local_new_i32(); | |
1069 | TCGv_i32 t1 = tcg_temp_local_new_i32(); | |
1070 | ||
1071 | tcg_gen_trunc_tl_i32(t0, arg1); | |
1072 | tcg_gen_trunc_tl_i32(t1, arg2); | |
1073 | tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1); | |
1074 | if (sign) { | |
1075 | int l3 = gen_new_label(); | |
1076 | tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3); | |
1077 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1); | |
1078 | gen_set_label(l3); | |
1079 | tcg_gen_div_i32(t0, t0, t1); | |
1080 | } else { | |
1081 | tcg_gen_divu_i32(t0, t0, t1); | |
1082 | } | |
1083 | if (compute_ov) { | |
1084 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
1085 | } | |
1086 | tcg_gen_br(l2); | |
1087 | gen_set_label(l1); | |
1088 | if (sign) { | |
1089 | tcg_gen_sari_i32(t0, t0, 31); | |
1090 | } else { | |
1091 | tcg_gen_movi_i32(t0, 0); | |
1092 | } | |
1093 | if (compute_ov) { | |
1094 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
1095 | } | |
1096 | gen_set_label(l2); | |
1097 | tcg_gen_extu_i32_tl(ret, t0); | |
1098 | tcg_temp_free_i32(t0); | |
1099 | tcg_temp_free_i32(t1); | |
1100 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1101 | gen_set_Rc0(ctx, ret); | |
1102 | } | |
1103 | /* Div functions */ | |
1104 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
1105 | GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \ | |
1106 | { \ | |
1107 | gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1108 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1109 | sign, compute_ov); \ | |
1110 | } | |
1111 | /* divwu divwu. divwuo divwuo. */ | |
1112 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); | |
1113 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); | |
1114 | /* divw divw. divwo divwo. */ | |
1115 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); | |
1116 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); | |
1117 | #if defined(TARGET_PPC64) | |
1118 | static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2, | |
1119 | int sign, int compute_ov) | |
1120 | { | |
1121 | int l1 = gen_new_label(); | |
1122 | int l2 = gen_new_label(); | |
1123 | ||
1124 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1); | |
1125 | if (sign) { | |
1126 | int l3 = gen_new_label(); | |
1127 | tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3); | |
1128 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1); | |
1129 | gen_set_label(l3); | |
1130 | tcg_gen_div_i64(ret, arg1, arg2); | |
1131 | } else { | |
1132 | tcg_gen_divu_i64(ret, arg1, arg2); | |
1133 | } | |
1134 | if (compute_ov) { | |
1135 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
1136 | } | |
1137 | tcg_gen_br(l2); | |
1138 | gen_set_label(l1); | |
1139 | if (sign) { | |
1140 | tcg_gen_sari_i64(ret, arg1, 63); | |
1141 | } else { | |
1142 | tcg_gen_movi_i64(ret, 0); | |
1143 | } | |
1144 | if (compute_ov) { | |
1145 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
1146 | } | |
1147 | gen_set_label(l2); | |
1148 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1149 | gen_set_Rc0(ctx, ret); | |
1150 | } | |
1151 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ | |
1152 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \ | |
1153 | { \ | |
1154 | gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1155 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1156 | sign, compute_ov); \ | |
1157 | } | |
1158 | /* divwu divwu. divwuo divwuo. */ | |
1159 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); | |
1160 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); | |
1161 | /* divw divw. divwo divwo. */ | |
1162 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); | |
1163 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); | |
1164 | #endif | |
1165 | ||
1166 | /* mulhw mulhw. */ | |
1167 | GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER) | |
1168 | { | |
1169 | TCGv_i64 t0, t1; | |
1170 | ||
1171 | t0 = tcg_temp_new_i64(); | |
1172 | t1 = tcg_temp_new_i64(); | |
1173 | #if defined(TARGET_PPC64) | |
1174 | tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); | |
1175 | tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); | |
1176 | tcg_gen_mul_i64(t0, t0, t1); | |
1177 | tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32); | |
1178 | #else | |
1179 | tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
1180 | tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
1181 | tcg_gen_mul_i64(t0, t0, t1); | |
1182 | tcg_gen_shri_i64(t0, t0, 32); | |
1183 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
1184 | #endif | |
1185 | tcg_temp_free_i64(t0); | |
1186 | tcg_temp_free_i64(t1); | |
1187 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1188 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1189 | } | |
1190 | /* mulhwu mulhwu. */ | |
1191 | GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER) | |
1192 | { | |
1193 | TCGv_i64 t0, t1; | |
1194 | ||
1195 | t0 = tcg_temp_new_i64(); | |
1196 | t1 = tcg_temp_new_i64(); | |
1197 | #if defined(TARGET_PPC64) | |
1198 | tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
1199 | tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
1200 | tcg_gen_mul_i64(t0, t0, t1); | |
1201 | tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32); | |
1202 | #else | |
1203 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
1204 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
1205 | tcg_gen_mul_i64(t0, t0, t1); | |
1206 | tcg_gen_shri_i64(t0, t0, 32); | |
1207 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
1208 | #endif | |
1209 | tcg_temp_free_i64(t0); | |
1210 | tcg_temp_free_i64(t1); | |
1211 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1212 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1213 | } | |
1214 | /* mullw mullw. */ | |
1215 | GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER) | |
1216 | { | |
1217 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1218 | cpu_gpr[rB(ctx->opcode)]); | |
1219 | tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]); | |
1220 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1221 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1222 | } | |
1223 | /* mullwo mullwo. */ | |
1224 | GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER) | |
1225 | { | |
1226 | int l1; | |
1227 | TCGv_i64 t0, t1; | |
1228 | ||
1229 | t0 = tcg_temp_new_i64(); | |
1230 | t1 = tcg_temp_new_i64(); | |
1231 | l1 = gen_new_label(); | |
1232 | /* Start with XER OV disabled, the most likely case */ | |
1233 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
1234 | #if defined(TARGET_PPC64) | |
1235 | tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
1236 | tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
1237 | #else | |
1238 | tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
1239 | tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
1240 | #endif | |
1241 | tcg_gen_mul_i64(t0, t0, t1); | |
1242 | #if defined(TARGET_PPC64) | |
1243 | tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0); | |
1244 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1); | |
1245 | #else | |
1246 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
1247 | tcg_gen_ext32s_i64(t1, t0); | |
1248 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); | |
1249 | #endif | |
1250 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
1251 | gen_set_label(l1); | |
1252 | tcg_temp_free_i64(t0); | |
1253 | tcg_temp_free_i64(t1); | |
1254 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1255 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1256 | } | |
1257 | /* mulli */ | |
1258 | GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) | |
1259 | { | |
1260 | tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1261 | SIMM(ctx->opcode)); | |
1262 | } | |
1263 | #if defined(TARGET_PPC64) | |
1264 | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ | |
1265 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \ | |
1266 | { \ | |
1267 | gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \ | |
1268 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ | |
1269 | if (unlikely(Rc(ctx->opcode) != 0)) \ | |
1270 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ | |
1271 | } | |
1272 | /* mulhd mulhd. */ | |
1273 | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00); | |
1274 | /* mulhdu mulhdu. */ | |
1275 | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02); | |
1276 | /* mulld mulld. */ | |
1277 | GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B) | |
1278 | { | |
1279 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1280 | cpu_gpr[rB(ctx->opcode)]); | |
1281 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1282 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1283 | } | |
1284 | /* mulldo mulldo. */ | |
1285 | GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17); | |
1286 | #endif | |
1287 | ||
1288 | /* neg neg. nego nego. */ | |
1289 | static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check) | |
1290 | { | |
1291 | int l1 = gen_new_label(); | |
1292 | int l2 = gen_new_label(); | |
1293 | TCGv t0 = tcg_temp_local_new(); | |
1294 | #if defined(TARGET_PPC64) | |
1295 | if (ctx->sf_mode) { | |
1296 | tcg_gen_mov_tl(t0, arg1); | |
1297 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1); | |
1298 | } else | |
1299 | #endif | |
1300 | { | |
1301 | tcg_gen_ext32s_tl(t0, arg1); | |
1302 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1); | |
1303 | } | |
1304 | tcg_gen_neg_tl(ret, arg1); | |
1305 | if (ov_check) { | |
1306 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
1307 | } | |
1308 | tcg_gen_br(l2); | |
1309 | gen_set_label(l1); | |
1310 | tcg_gen_mov_tl(ret, t0); | |
1311 | if (ov_check) { | |
1312 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
1313 | } | |
1314 | gen_set_label(l2); | |
1315 | tcg_temp_free(t0); | |
1316 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1317 | gen_set_Rc0(ctx, ret); | |
1318 | } | |
1319 | GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER) | |
1320 | { | |
1321 | gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0); | |
1322 | } | |
1323 | GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER) | |
1324 | { | |
1325 | gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1); | |
1326 | } | |
1327 | ||
1328 | /* Common subf function */ | |
1329 | static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2, | |
1330 | int add_ca, int compute_ca, int compute_ov) | |
1331 | { | |
1332 | TCGv t0, t1; | |
1333 | ||
1334 | if ((!compute_ca && !compute_ov) || | |
1335 | (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) { | |
1336 | t0 = ret; | |
1337 | } else { | |
1338 | t0 = tcg_temp_local_new(); | |
1339 | } | |
1340 | ||
1341 | if (add_ca) { | |
1342 | t1 = tcg_temp_local_new(); | |
1343 | tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA)); | |
1344 | tcg_gen_shri_tl(t1, t1, XER_CA); | |
1345 | } | |
1346 | ||
1347 | if (compute_ca && compute_ov) { | |
1348 | /* Start with XER CA and OV disabled, the most likely case */ | |
1349 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV))); | |
1350 | } else if (compute_ca) { | |
1351 | /* Start with XER CA disabled, the most likely case */ | |
1352 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); | |
1353 | } else if (compute_ov) { | |
1354 | /* Start with XER OV disabled, the most likely case */ | |
1355 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
1356 | } | |
1357 | ||
1358 | if (add_ca) { | |
1359 | tcg_gen_not_tl(t0, arg1); | |
1360 | tcg_gen_add_tl(t0, t0, arg2); | |
1361 | gen_op_arith_compute_ca(ctx, t0, arg2, 0); | |
1362 | tcg_gen_add_tl(t0, t0, t1); | |
1363 | gen_op_arith_compute_ca(ctx, t0, t1, 0); | |
1364 | tcg_temp_free(t1); | |
1365 | } else { | |
1366 | tcg_gen_sub_tl(t0, arg2, arg1); | |
1367 | if (compute_ca) { | |
1368 | gen_op_arith_compute_ca(ctx, t0, arg2, 1); | |
1369 | } | |
1370 | } | |
1371 | if (compute_ov) { | |
1372 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); | |
1373 | } | |
1374 | ||
1375 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1376 | gen_set_Rc0(ctx, t0); | |
1377 | ||
1378 | if (!TCGV_EQUAL(t0, ret)) { | |
1379 | tcg_gen_mov_tl(ret, t0); | |
1380 | tcg_temp_free(t0); | |
1381 | } | |
1382 | } | |
1383 | /* Sub functions with Two operands functions */ | |
1384 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
1385 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \ | |
1386 | { \ | |
1387 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1388 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1389 | add_ca, compute_ca, compute_ov); \ | |
1390 | } | |
1391 | /* Sub functions with one operand and one immediate */ | |
1392 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
1393 | add_ca, compute_ca, compute_ov) \ | |
1394 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \ | |
1395 | { \ | |
1396 | TCGv t0 = tcg_const_local_tl(const_val); \ | |
1397 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1398 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
1399 | add_ca, compute_ca, compute_ov); \ | |
1400 | tcg_temp_free(t0); \ | |
1401 | } | |
1402 | /* subf subf. subfo subfo. */ | |
1403 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
1404 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
1405 | /* subfc subfc. subfco subfco. */ | |
1406 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
1407 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
1408 | /* subfe subfe. subfeo subfo. */ | |
1409 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
1410 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
1411 | /* subfme subfme. subfmeo subfmeo. */ | |
1412 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
1413 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
1414 | /* subfze subfze. subfzeo subfzeo.*/ | |
1415 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
1416 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
1417 | /* subfic */ | |
1418 | GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) | |
1419 | { | |
1420 | /* Start with XER CA and OV disabled, the most likely case */ | |
1421 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); | |
1422 | TCGv t0 = tcg_temp_local_new(); | |
1423 | TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode)); | |
1424 | tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]); | |
1425 | gen_op_arith_compute_ca(ctx, t0, t1, 1); | |
1426 | tcg_temp_free(t1); | |
1427 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
1428 | tcg_temp_free(t0); | |
1429 | } | |
1430 | ||
1431 | /*** Integer logical ***/ | |
1432 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ | |
1433 | GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \ | |
1434 | { \ | |
1435 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ | |
1436 | cpu_gpr[rB(ctx->opcode)]); \ | |
1437 | if (unlikely(Rc(ctx->opcode) != 0)) \ | |
1438 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ | |
1439 | } | |
1440 | ||
1441 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ | |
1442 | GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \ | |
1443 | { \ | |
1444 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ | |
1445 | if (unlikely(Rc(ctx->opcode) != 0)) \ | |
1446 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ | |
1447 | } | |
1448 | ||
1449 | /* and & and. */ | |
1450 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); | |
1451 | /* andc & andc. */ | |
1452 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); | |
1453 | /* andi. */ | |
1454 | GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) | |
1455 | { | |
1456 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); | |
1457 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1458 | } | |
1459 | /* andis. */ | |
1460 | GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) | |
1461 | { | |
1462 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16); | |
1463 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1464 | } | |
1465 | /* cntlzw */ | |
1466 | GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER) | |
1467 | { | |
1468 | gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1469 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1470 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1471 | } | |
1472 | /* eqv & eqv. */ | |
1473 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); | |
1474 | /* extsb & extsb. */ | |
1475 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); | |
1476 | /* extsh & extsh. */ | |
1477 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); | |
1478 | /* nand & nand. */ | |
1479 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); | |
1480 | /* nor & nor. */ | |
1481 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); | |
1482 | /* or & or. */ | |
1483 | GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER) | |
1484 | { | |
1485 | int rs, ra, rb; | |
1486 | ||
1487 | rs = rS(ctx->opcode); | |
1488 | ra = rA(ctx->opcode); | |
1489 | rb = rB(ctx->opcode); | |
1490 | /* Optimisation for mr. ri case */ | |
1491 | if (rs != ra || rs != rb) { | |
1492 | if (rs != rb) | |
1493 | tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); | |
1494 | else | |
1495 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); | |
1496 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1497 | gen_set_Rc0(ctx, cpu_gpr[ra]); | |
1498 | } else if (unlikely(Rc(ctx->opcode) != 0)) { | |
1499 | gen_set_Rc0(ctx, cpu_gpr[rs]); | |
1500 | #if defined(TARGET_PPC64) | |
1501 | } else { | |
1502 | int prio = 0; | |
1503 | ||
1504 | switch (rs) { | |
1505 | case 1: | |
1506 | /* Set process priority to low */ | |
1507 | prio = 2; | |
1508 | break; | |
1509 | case 6: | |
1510 | /* Set process priority to medium-low */ | |
1511 | prio = 3; | |
1512 | break; | |
1513 | case 2: | |
1514 | /* Set process priority to normal */ | |
1515 | prio = 4; | |
1516 | break; | |
1517 | #if !defined(CONFIG_USER_ONLY) | |
1518 | case 31: | |
1519 | if (ctx->supervisor > 0) { | |
1520 | /* Set process priority to very low */ | |
1521 | prio = 1; | |
1522 | } | |
1523 | break; | |
1524 | case 5: | |
1525 | if (ctx->supervisor > 0) { | |
1526 | /* Set process priority to medium-hight */ | |
1527 | prio = 5; | |
1528 | } | |
1529 | break; | |
1530 | case 3: | |
1531 | if (ctx->supervisor > 0) { | |
1532 | /* Set process priority to high */ | |
1533 | prio = 6; | |
1534 | } | |
1535 | break; | |
1536 | case 7: | |
1537 | if (ctx->supervisor > 1) { | |
1538 | /* Set process priority to very high */ | |
1539 | prio = 7; | |
1540 | } | |
1541 | break; | |
1542 | #endif | |
1543 | default: | |
1544 | /* nop */ | |
1545 | break; | |
1546 | } | |
1547 | if (prio) { | |
1548 | TCGv t0 = tcg_temp_new(); | |
1549 | tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR])); | |
1550 | tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); | |
1551 | tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); | |
1552 | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR])); | |
1553 | tcg_temp_free(t0); | |
1554 | } | |
1555 | #endif | |
1556 | } | |
1557 | } | |
1558 | /* orc & orc. */ | |
1559 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); | |
1560 | /* xor & xor. */ | |
1561 | GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER) | |
1562 | { | |
1563 | /* Optimisation for "set to zero" case */ | |
1564 | if (rS(ctx->opcode) != rB(ctx->opcode)) | |
1565 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1566 | else | |
1567 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
1568 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1569 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1570 | } | |
1571 | /* ori */ | |
1572 | GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) | |
1573 | { | |
1574 | target_ulong uimm = UIMM(ctx->opcode); | |
1575 | ||
1576 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1577 | /* NOP */ | |
1578 | /* XXX: should handle special NOPs for POWER series */ | |
1579 | return; | |
1580 | } | |
1581 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); | |
1582 | } | |
1583 | /* oris */ | |
1584 | GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) | |
1585 | { | |
1586 | target_ulong uimm = UIMM(ctx->opcode); | |
1587 | ||
1588 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1589 | /* NOP */ | |
1590 | return; | |
1591 | } | |
1592 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); | |
1593 | } | |
1594 | /* xori */ | |
1595 | GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) | |
1596 | { | |
1597 | target_ulong uimm = UIMM(ctx->opcode); | |
1598 | ||
1599 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1600 | /* NOP */ | |
1601 | return; | |
1602 | } | |
1603 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); | |
1604 | } | |
1605 | /* xoris */ | |
1606 | GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) | |
1607 | { | |
1608 | target_ulong uimm = UIMM(ctx->opcode); | |
1609 | ||
1610 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1611 | /* NOP */ | |
1612 | return; | |
1613 | } | |
1614 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); | |
1615 | } | |
1616 | /* popcntb : PowerPC 2.03 specification */ | |
1617 | GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB) | |
1618 | { | |
1619 | #if defined(TARGET_PPC64) | |
1620 | if (ctx->sf_mode) | |
1621 | gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1622 | else | |
1623 | #endif | |
1624 | gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1625 | } | |
1626 | ||
1627 | #if defined(TARGET_PPC64) | |
1628 | /* extsw & extsw. */ | |
1629 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); | |
1630 | /* cntlzd */ | |
1631 | GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B) | |
1632 | { | |
1633 | gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1634 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1635 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1636 | } | |
1637 | #endif | |
1638 | ||
1639 | /*** Integer rotate ***/ | |
1640 | /* rlwimi & rlwimi. */ | |
1641 | GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) | |
1642 | { | |
1643 | uint32_t mb, me, sh; | |
1644 | ||
1645 | mb = MB(ctx->opcode); | |
1646 | me = ME(ctx->opcode); | |
1647 | sh = SH(ctx->opcode); | |
1648 | if (likely(sh == 0 && mb == 0 && me == 31)) { | |
1649 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1650 | } else { | |
1651 | target_ulong mask; | |
1652 | TCGv t1; | |
1653 | TCGv t0 = tcg_temp_new(); | |
1654 | #if defined(TARGET_PPC64) | |
1655 | TCGv_i32 t2 = tcg_temp_new_i32(); | |
1656 | tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]); | |
1657 | tcg_gen_rotli_i32(t2, t2, sh); | |
1658 | tcg_gen_extu_i32_i64(t0, t2); | |
1659 | tcg_temp_free_i32(t2); | |
1660 | #else | |
1661 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
1662 | #endif | |
1663 | #if defined(TARGET_PPC64) | |
1664 | mb += 32; | |
1665 | me += 32; | |
1666 | #endif | |
1667 | mask = MASK(mb, me); | |
1668 | t1 = tcg_temp_new(); | |
1669 | tcg_gen_andi_tl(t0, t0, mask); | |
1670 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); | |
1671 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1672 | tcg_temp_free(t0); | |
1673 | tcg_temp_free(t1); | |
1674 | } | |
1675 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1676 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1677 | } | |
1678 | /* rlwinm & rlwinm. */ | |
1679 | GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) | |
1680 | { | |
1681 | uint32_t mb, me, sh; | |
1682 | ||
1683 | sh = SH(ctx->opcode); | |
1684 | mb = MB(ctx->opcode); | |
1685 | me = ME(ctx->opcode); | |
1686 | ||
1687 | if (likely(mb == 0 && me == (31 - sh))) { | |
1688 | if (likely(sh == 0)) { | |
1689 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1690 | } else { | |
1691 | TCGv t0 = tcg_temp_new(); | |
1692 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); | |
1693 | tcg_gen_shli_tl(t0, t0, sh); | |
1694 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1695 | tcg_temp_free(t0); | |
1696 | } | |
1697 | } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) { | |
1698 | TCGv t0 = tcg_temp_new(); | |
1699 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); | |
1700 | tcg_gen_shri_tl(t0, t0, mb); | |
1701 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1702 | tcg_temp_free(t0); | |
1703 | } else { | |
1704 | TCGv t0 = tcg_temp_new(); | |
1705 | #if defined(TARGET_PPC64) | |
1706 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
1707 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); | |
1708 | tcg_gen_rotli_i32(t1, t1, sh); | |
1709 | tcg_gen_extu_i32_i64(t0, t1); | |
1710 | tcg_temp_free_i32(t1); | |
1711 | #else | |
1712 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
1713 | #endif | |
1714 | #if defined(TARGET_PPC64) | |
1715 | mb += 32; | |
1716 | me += 32; | |
1717 | #endif | |
1718 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); | |
1719 | tcg_temp_free(t0); | |
1720 | } | |
1721 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1722 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1723 | } | |
1724 | /* rlwnm & rlwnm. */ | |
1725 | GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) | |
1726 | { | |
1727 | uint32_t mb, me; | |
1728 | TCGv t0; | |
1729 | #if defined(TARGET_PPC64) | |
1730 | TCGv_i32 t1, t2; | |
1731 | #endif | |
1732 | ||
1733 | mb = MB(ctx->opcode); | |
1734 | me = ME(ctx->opcode); | |
1735 | t0 = tcg_temp_new(); | |
1736 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f); | |
1737 | #if defined(TARGET_PPC64) | |
1738 | t1 = tcg_temp_new_i32(); | |
1739 | t2 = tcg_temp_new_i32(); | |
1740 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); | |
1741 | tcg_gen_trunc_i64_i32(t2, t0); | |
1742 | tcg_gen_rotl_i32(t1, t1, t2); | |
1743 | tcg_gen_extu_i32_i64(t0, t1); | |
1744 | tcg_temp_free_i32(t1); | |
1745 | tcg_temp_free_i32(t2); | |
1746 | #else | |
1747 | tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1748 | #endif | |
1749 | if (unlikely(mb != 0 || me != 31)) { | |
1750 | #if defined(TARGET_PPC64) | |
1751 | mb += 32; | |
1752 | me += 32; | |
1753 | #endif | |
1754 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); | |
1755 | } else { | |
1756 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1757 | } | |
1758 | tcg_temp_free(t0); | |
1759 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1760 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1761 | } | |
1762 | ||
1763 | #if defined(TARGET_PPC64) | |
1764 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
1765 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \ | |
1766 | { \ | |
1767 | gen_##name(ctx, 0); \ | |
1768 | } \ | |
1769 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
1770 | PPC_64B) \ | |
1771 | { \ | |
1772 | gen_##name(ctx, 1); \ | |
1773 | } | |
1774 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
1775 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \ | |
1776 | { \ | |
1777 | gen_##name(ctx, 0, 0); \ | |
1778 | } \ | |
1779 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ | |
1780 | PPC_64B) \ | |
1781 | { \ | |
1782 | gen_##name(ctx, 0, 1); \ | |
1783 | } \ | |
1784 | GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
1785 | PPC_64B) \ | |
1786 | { \ | |
1787 | gen_##name(ctx, 1, 0); \ | |
1788 | } \ | |
1789 | GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ | |
1790 | PPC_64B) \ | |
1791 | { \ | |
1792 | gen_##name(ctx, 1, 1); \ | |
1793 | } | |
1794 | ||
1795 | static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb, | |
1796 | uint32_t me, uint32_t sh) | |
1797 | { | |
1798 | if (likely(sh != 0 && mb == 0 && me == (63 - sh))) { | |
1799 | tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); | |
1800 | } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) { | |
1801 | tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb); | |
1802 | } else { | |
1803 | TCGv t0 = tcg_temp_new(); | |
1804 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
1805 | if (likely(mb == 0 && me == 63)) { | |
1806 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1807 | } else { | |
1808 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); | |
1809 | } | |
1810 | tcg_temp_free(t0); | |
1811 | } | |
1812 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1813 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1814 | } | |
1815 | /* rldicl - rldicl. */ | |
1816 | static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn) | |
1817 | { | |
1818 | uint32_t sh, mb; | |
1819 | ||
1820 | sh = SH(ctx->opcode) | (shn << 5); | |
1821 | mb = MB(ctx->opcode) | (mbn << 5); | |
1822 | gen_rldinm(ctx, mb, 63, sh); | |
1823 | } | |
1824 | GEN_PPC64_R4(rldicl, 0x1E, 0x00); | |
1825 | /* rldicr - rldicr. */ | |
1826 | static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn) | |
1827 | { | |
1828 | uint32_t sh, me; | |
1829 | ||
1830 | sh = SH(ctx->opcode) | (shn << 5); | |
1831 | me = MB(ctx->opcode) | (men << 5); | |
1832 | gen_rldinm(ctx, 0, me, sh); | |
1833 | } | |
1834 | GEN_PPC64_R4(rldicr, 0x1E, 0x02); | |
1835 | /* rldic - rldic. */ | |
1836 | static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn) | |
1837 | { | |
1838 | uint32_t sh, mb; | |
1839 | ||
1840 | sh = SH(ctx->opcode) | (shn << 5); | |
1841 | mb = MB(ctx->opcode) | (mbn << 5); | |
1842 | gen_rldinm(ctx, mb, 63 - sh, sh); | |
1843 | } | |
1844 | GEN_PPC64_R4(rldic, 0x1E, 0x04); | |
1845 | ||
1846 | static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb, | |
1847 | uint32_t me) | |
1848 | { | |
1849 | TCGv t0; | |
1850 | ||
1851 | mb = MB(ctx->opcode); | |
1852 | me = ME(ctx->opcode); | |
1853 | t0 = tcg_temp_new(); | |
1854 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
1855 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1856 | if (unlikely(mb != 0 || me != 63)) { | |
1857 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); | |
1858 | } else { | |
1859 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1860 | } | |
1861 | tcg_temp_free(t0); | |
1862 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1863 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1864 | } | |
1865 | ||
1866 | /* rldcl - rldcl. */ | |
1867 | static always_inline void gen_rldcl (DisasContext *ctx, int mbn) | |
1868 | { | |
1869 | uint32_t mb; | |
1870 | ||
1871 | mb = MB(ctx->opcode) | (mbn << 5); | |
1872 | gen_rldnm(ctx, mb, 63); | |
1873 | } | |
1874 | GEN_PPC64_R2(rldcl, 0x1E, 0x08); | |
1875 | /* rldcr - rldcr. */ | |
1876 | static always_inline void gen_rldcr (DisasContext *ctx, int men) | |
1877 | { | |
1878 | uint32_t me; | |
1879 | ||
1880 | me = MB(ctx->opcode) | (men << 5); | |
1881 | gen_rldnm(ctx, 0, me); | |
1882 | } | |
1883 | GEN_PPC64_R2(rldcr, 0x1E, 0x09); | |
1884 | /* rldimi - rldimi. */ | |
1885 | static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn) | |
1886 | { | |
1887 | uint32_t sh, mb, me; | |
1888 | ||
1889 | sh = SH(ctx->opcode) | (shn << 5); | |
1890 | mb = MB(ctx->opcode) | (mbn << 5); | |
1891 | me = 63 - sh; | |
1892 | if (unlikely(sh == 0 && mb == 0)) { | |
1893 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1894 | } else { | |
1895 | TCGv t0, t1; | |
1896 | target_ulong mask; | |
1897 | ||
1898 | t0 = tcg_temp_new(); | |
1899 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
1900 | t1 = tcg_temp_new(); | |
1901 | mask = MASK(mb, me); | |
1902 | tcg_gen_andi_tl(t0, t0, mask); | |
1903 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); | |
1904 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1905 | tcg_temp_free(t0); | |
1906 | tcg_temp_free(t1); | |
1907 | } | |
1908 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1909 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1910 | } | |
1911 | GEN_PPC64_R4(rldimi, 0x1E, 0x06); | |
1912 | #endif | |
1913 | ||
1914 | /*** Integer shift ***/ | |
1915 | /* slw & slw. */ | |
1916 | GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER) | |
1917 | { | |
1918 | TCGv t0; | |
1919 | int l1, l2; | |
1920 | l1 = gen_new_label(); | |
1921 | l2 = gen_new_label(); | |
1922 | ||
1923 | t0 = tcg_temp_local_new(); | |
1924 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
1925 | tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1); | |
1926 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
1927 | tcg_gen_br(l2); | |
1928 | gen_set_label(l1); | |
1929 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0); | |
1930 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
1931 | gen_set_label(l2); | |
1932 | tcg_temp_free(t0); | |
1933 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1934 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1935 | } | |
1936 | /* sraw & sraw. */ | |
1937 | GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER) | |
1938 | { | |
1939 | gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], | |
1940 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1941 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1942 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1943 | } | |
1944 | /* srawi & srawi. */ | |
1945 | GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER) | |
1946 | { | |
1947 | int sh = SH(ctx->opcode); | |
1948 | if (sh != 0) { | |
1949 | int l1, l2; | |
1950 | TCGv t0; | |
1951 | l1 = gen_new_label(); | |
1952 | l2 = gen_new_label(); | |
1953 | t0 = tcg_temp_local_new(); | |
1954 | tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]); | |
1955 | tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1); | |
1956 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1); | |
1957 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
1958 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA); | |
1959 | tcg_gen_br(l2); | |
1960 | gen_set_label(l1); | |
1961 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); | |
1962 | gen_set_label(l2); | |
1963 | tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]); | |
1964 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh); | |
1965 | tcg_temp_free(t0); | |
1966 | } else { | |
1967 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1968 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); | |
1969 | } | |
1970 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1971 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1972 | } | |
1973 | /* srw & srw. */ | |
1974 | GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER) | |
1975 | { | |
1976 | TCGv t0, t1; | |
1977 | int l1, l2; | |
1978 | l1 = gen_new_label(); | |
1979 | l2 = gen_new_label(); | |
1980 | ||
1981 | t0 = tcg_temp_local_new(); | |
1982 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
1983 | tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1); | |
1984 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
1985 | tcg_gen_br(l2); | |
1986 | gen_set_label(l1); | |
1987 | t1 = tcg_temp_new(); | |
1988 | tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]); | |
1989 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0); | |
1990 | tcg_temp_free(t1); | |
1991 | gen_set_label(l2); | |
1992 | tcg_temp_free(t0); | |
1993 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1994 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1995 | } | |
1996 | #if defined(TARGET_PPC64) | |
1997 | /* sld & sld. */ | |
1998 | GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B) | |
1999 | { | |
2000 | TCGv t0; | |
2001 | int l1, l2; | |
2002 | l1 = gen_new_label(); | |
2003 | l2 = gen_new_label(); | |
2004 | ||
2005 | t0 = tcg_temp_local_new(); | |
2006 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f); | |
2007 | tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1); | |
2008 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
2009 | tcg_gen_br(l2); | |
2010 | gen_set_label(l1); | |
2011 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0); | |
2012 | gen_set_label(l2); | |
2013 | tcg_temp_free(t0); | |
2014 | if (unlikely(Rc(ctx->opcode) != 0)) | |
2015 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2016 | } | |
2017 | /* srad & srad. */ | |
2018 | GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B) | |
2019 | { | |
2020 | gen_helper_srad(cpu_gpr[rA(ctx->opcode)], | |
2021 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
2022 | if (unlikely(Rc(ctx->opcode) != 0)) | |
2023 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2024 | } | |
2025 | /* sradi & sradi. */ | |
2026 | static always_inline void gen_sradi (DisasContext *ctx, int n) | |
2027 | { | |
2028 | int sh = SH(ctx->opcode) + (n << 5); | |
2029 | if (sh != 0) { | |
2030 | int l1, l2; | |
2031 | TCGv t0; | |
2032 | l1 = gen_new_label(); | |
2033 | l2 = gen_new_label(); | |
2034 | t0 = tcg_temp_local_new(); | |
2035 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); | |
2036 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1); | |
2037 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
2038 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA); | |
2039 | tcg_gen_br(l2); | |
2040 | gen_set_label(l1); | |
2041 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); | |
2042 | gen_set_label(l2); | |
2043 | tcg_temp_free(t0); | |
2044 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); | |
2045 | } else { | |
2046 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
2047 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); | |
2048 | } | |
2049 | if (unlikely(Rc(ctx->opcode) != 0)) | |
2050 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2051 | } | |
2052 | GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B) | |
2053 | { | |
2054 | gen_sradi(ctx, 0); | |
2055 | } | |
2056 | GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B) | |
2057 | { | |
2058 | gen_sradi(ctx, 1); | |
2059 | } | |
2060 | /* srd & srd. */ | |
2061 | GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B) | |
2062 | { | |
2063 | TCGv t0; | |
2064 | int l1, l2; | |
2065 | l1 = gen_new_label(); | |
2066 | l2 = gen_new_label(); | |
2067 | ||
2068 | t0 = tcg_temp_local_new(); | |
2069 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f); | |
2070 | tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1); | |
2071 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
2072 | tcg_gen_br(l2); | |
2073 | gen_set_label(l1); | |
2074 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0); | |
2075 | gen_set_label(l2); | |
2076 | tcg_temp_free(t0); | |
2077 | if (unlikely(Rc(ctx->opcode) != 0)) | |
2078 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2079 | } | |
2080 | #endif | |
2081 | ||
2082 | /*** Floating-Point arithmetic ***/ | |
2083 | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ | |
2084 | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \ | |
2085 | { \ | |
2086 | if (unlikely(!ctx->fpu_enabled)) { \ | |
2087 | GEN_EXCP_NO_FP(ctx); \ | |
2088 | return; \ | |
2089 | } \ | |
2090 | gen_reset_fpstatus(); \ | |
2091 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \ | |
2092 | cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ | |
2093 | if (isfloat) { \ | |
2094 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \ | |
2095 | } \ | |
2096 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \ | |
2097 | Rc(ctx->opcode) != 0); \ | |
2098 | } | |
2099 | ||
2100 | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ | |
2101 | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \ | |
2102 | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type); | |
2103 | ||
2104 | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ | |
2105 | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \ | |
2106 | { \ | |
2107 | if (unlikely(!ctx->fpu_enabled)) { \ | |
2108 | GEN_EXCP_NO_FP(ctx); \ | |
2109 | return; \ | |
2110 | } \ | |
2111 | gen_reset_fpstatus(); \ | |
2112 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \ | |
2113 | cpu_fpr[rB(ctx->opcode)]); \ | |
2114 | if (isfloat) { \ | |
2115 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \ | |
2116 | } \ | |
2117 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ | |
2118 | set_fprf, Rc(ctx->opcode) != 0); \ | |
2119 | } | |
2120 | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ | |
2121 | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ | |
2122 | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); | |
2123 | ||
2124 | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ | |
2125 | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \ | |
2126 | { \ | |
2127 | if (unlikely(!ctx->fpu_enabled)) { \ | |
2128 | GEN_EXCP_NO_FP(ctx); \ | |
2129 | return; \ | |
2130 | } \ | |
2131 | gen_reset_fpstatus(); \ | |
2132 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \ | |
2133 | cpu_fpr[rC(ctx->opcode)]); \ | |
2134 | if (isfloat) { \ | |
2135 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \ | |
2136 | } \ | |
2137 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ | |
2138 | set_fprf, Rc(ctx->opcode) != 0); \ | |
2139 | } | |
2140 | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ | |
2141 | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ | |
2142 | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); | |
2143 | ||
2144 | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ | |
2145 | GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \ | |
2146 | { \ | |
2147 | if (unlikely(!ctx->fpu_enabled)) { \ | |
2148 | GEN_EXCP_NO_FP(ctx); \ | |
2149 | return; \ | |
2150 | } \ | |
2151 | gen_reset_fpstatus(); \ | |
2152 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ | |
2153 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ | |
2154 | set_fprf, Rc(ctx->opcode) != 0); \ | |
2155 | } | |
2156 | ||
2157 | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ | |
2158 | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \ | |
2159 | { \ | |
2160 | if (unlikely(!ctx->fpu_enabled)) { \ | |
2161 | GEN_EXCP_NO_FP(ctx); \ | |
2162 | return; \ | |
2163 | } \ | |
2164 | gen_reset_fpstatus(); \ | |
2165 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ | |
2166 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ | |
2167 | set_fprf, Rc(ctx->opcode) != 0); \ | |
2168 | } | |
2169 | ||
2170 | /* fadd - fadds */ | |
2171 | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT); | |
2172 | /* fdiv - fdivs */ | |
2173 | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT); | |
2174 | /* fmul - fmuls */ | |
2175 | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT); | |
2176 | ||
2177 | /* fre */ | |
2178 | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT); | |
2179 | ||
2180 | /* fres */ | |
2181 | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES); | |
2182 | ||
2183 | /* frsqrte */ | |
2184 | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE); | |
2185 | ||
2186 | /* frsqrtes */ | |
2187 | GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES) | |
2188 | { | |
2189 | if (unlikely(!ctx->fpu_enabled)) { | |
2190 | GEN_EXCP_NO_FP(ctx); | |
2191 | return; | |
2192 | } | |
2193 | gen_reset_fpstatus(); | |
2194 | gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); | |
2195 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); | |
2196 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); | |
2197 | } | |
2198 | ||
2199 | /* fsel */ | |
2200 | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL); | |
2201 | /* fsub - fsubs */ | |
2202 | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT); | |
2203 | /* Optional: */ | |
2204 | /* fsqrt */ | |
2205 | GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT) | |
2206 | { | |
2207 | if (unlikely(!ctx->fpu_enabled)) { | |
2208 | GEN_EXCP_NO_FP(ctx); | |
2209 | return; | |
2210 | } | |
2211 | gen_reset_fpstatus(); | |
2212 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); | |
2213 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); | |
2214 | } | |
2215 | ||
2216 | GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT) | |
2217 | { | |
2218 | if (unlikely(!ctx->fpu_enabled)) { | |
2219 | GEN_EXCP_NO_FP(ctx); | |
2220 | return; | |
2221 | } | |
2222 | gen_reset_fpstatus(); | |
2223 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); | |
2224 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); | |
2225 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); | |
2226 | } | |
2227 | ||
2228 | /*** Floating-Point multiply-and-add ***/ | |
2229 | /* fmadd - fmadds */ | |
2230 | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT); | |
2231 | /* fmsub - fmsubs */ | |
2232 | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT); | |
2233 | /* fnmadd - fnmadds */ | |
2234 | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT); | |
2235 | /* fnmsub - fnmsubs */ | |
2236 | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT); | |
2237 | ||
2238 | /*** Floating-Point round & convert ***/ | |
2239 | /* fctiw */ | |
2240 | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT); | |
2241 | /* fctiwz */ | |
2242 | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT); | |
2243 | /* frsp */ | |
2244 | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT); | |
2245 | #if defined(TARGET_PPC64) | |
2246 | /* fcfid */ | |
2247 | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B); | |
2248 | /* fctid */ | |
2249 | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B); | |
2250 | /* fctidz */ | |
2251 | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B); | |
2252 | #endif | |
2253 | ||
2254 | /* frin */ | |
2255 | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT); | |
2256 | /* friz */ | |
2257 | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT); | |
2258 | /* frip */ | |
2259 | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT); | |
2260 | /* frim */ | |
2261 | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT); | |
2262 | ||
2263 | /*** Floating-Point compare ***/ | |
2264 | /* fcmpo */ | |
2265 | GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT) | |
2266 | { | |
2267 | if (unlikely(!ctx->fpu_enabled)) { | |
2268 | GEN_EXCP_NO_FP(ctx); | |
2269 | return; | |
2270 | } | |
2271 | gen_reset_fpstatus(); | |
2272 | gen_helper_fcmpo(cpu_crf[crfD(ctx->opcode)], | |
2273 | cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); | |
2274 | gen_helper_float_check_status(); | |
2275 | } | |
2276 | ||
2277 | /* fcmpu */ | |
2278 | GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT) | |
2279 | { | |
2280 | if (unlikely(!ctx->fpu_enabled)) { | |
2281 | GEN_EXCP_NO_FP(ctx); | |
2282 | return; | |
2283 | } | |
2284 | gen_reset_fpstatus(); | |
2285 | gen_helper_fcmpu(cpu_crf[crfD(ctx->opcode)], | |
2286 | cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); | |
2287 | gen_helper_float_check_status(); | |
2288 | } | |
2289 | ||
2290 | /*** Floating-point move ***/ | |
2291 | /* fabs */ | |
2292 | /* XXX: beware that fabs never checks for NaNs nor update FPSCR */ | |
2293 | GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT); | |
2294 | ||
2295 | /* fmr - fmr. */ | |
2296 | /* XXX: beware that fmr never checks for NaNs nor update FPSCR */ | |
2297 | GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT) | |
2298 | { | |
2299 | if (unlikely(!ctx->fpu_enabled)) { | |
2300 | GEN_EXCP_NO_FP(ctx); | |
2301 | return; | |
2302 | } | |
2303 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); | |
2304 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
2305 | } | |
2306 | ||
2307 | /* fnabs */ | |
2308 | /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */ | |
2309 | GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT); | |
2310 | /* fneg */ | |
2311 | /* XXX: beware that fneg never checks for NaNs nor update FPSCR */ | |
2312 | GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT); | |
2313 | ||
2314 | /*** Floating-Point status & ctrl register ***/ | |
2315 | /* mcrfs */ | |
2316 | GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT) | |
2317 | { | |
2318 | int bfa; | |
2319 | ||
2320 | if (unlikely(!ctx->fpu_enabled)) { | |
2321 | GEN_EXCP_NO_FP(ctx); | |
2322 | return; | |
2323 | } | |
2324 | gen_optimize_fprf(); | |
2325 | bfa = 4 * (7 - crfS(ctx->opcode)); | |
2326 | tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa); | |
2327 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf); | |
2328 | tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa)); | |
2329 | } | |
2330 | ||
2331 | /* mffs */ | |
2332 | GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT) | |
2333 | { | |
2334 | if (unlikely(!ctx->fpu_enabled)) { | |
2335 | GEN_EXCP_NO_FP(ctx); | |
2336 | return; | |
2337 | } | |
2338 | gen_optimize_fprf(); | |
2339 | gen_reset_fpstatus(); | |
2340 | tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr); | |
2341 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
2342 | } | |
2343 | ||
2344 | /* mtfsb0 */ | |
2345 | GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT) | |
2346 | { | |
2347 | uint8_t crb; | |
2348 | ||
2349 | if (unlikely(!ctx->fpu_enabled)) { | |
2350 | GEN_EXCP_NO_FP(ctx); | |
2351 | return; | |
2352 | } | |
2353 | crb = 32 - (crbD(ctx->opcode) >> 2); | |
2354 | gen_optimize_fprf(); | |
2355 | gen_reset_fpstatus(); | |
2356 | if (likely(crb != 30 && crb != 29)) | |
2357 | tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(1 << crb)); | |
2358 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2359 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX); | |
2360 | } | |
2361 | } | |
2362 | ||
2363 | /* mtfsb1 */ | |
2364 | GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT) | |
2365 | { | |
2366 | uint8_t crb; | |
2367 | ||
2368 | if (unlikely(!ctx->fpu_enabled)) { | |
2369 | GEN_EXCP_NO_FP(ctx); | |
2370 | return; | |
2371 | } | |
2372 | crb = 32 - (crbD(ctx->opcode) >> 2); | |
2373 | gen_optimize_fprf(); | |
2374 | gen_reset_fpstatus(); | |
2375 | /* XXX: we pretend we can only do IEEE floating-point computations */ | |
2376 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) { | |
2377 | TCGv_i32 t0 = tcg_const_i32(crb); | |
2378 | gen_helper_fpscr_setbit(t0); | |
2379 | tcg_temp_free_i32(t0); | |
2380 | } | |
2381 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2382 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX); | |
2383 | } | |
2384 | /* We can raise a differed exception */ | |
2385 | gen_helper_float_check_status(); | |
2386 | } | |
2387 | ||
2388 | /* mtfsf */ | |
2389 | GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT) | |
2390 | { | |
2391 | TCGv_i32 t0; | |
2392 | ||
2393 | if (unlikely(!ctx->fpu_enabled)) { | |
2394 | GEN_EXCP_NO_FP(ctx); | |
2395 | return; | |
2396 | } | |
2397 | gen_optimize_fprf(); | |
2398 | gen_reset_fpstatus(); | |
2399 | t0 = tcg_const_i32(FM(ctx->opcode)); | |
2400 | gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0); | |
2401 | tcg_temp_free_i32(t0); | |
2402 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2403 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX); | |
2404 | } | |
2405 | /* We can raise a differed exception */ | |
2406 | gen_helper_float_check_status(); | |
2407 | } | |
2408 | ||
2409 | /* mtfsfi */ | |
2410 | GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT) | |
2411 | { | |
2412 | int bf, sh; | |
2413 | TCGv_i64 t0; | |
2414 | TCGv_i32 t1; | |
2415 | ||
2416 | if (unlikely(!ctx->fpu_enabled)) { | |
2417 | GEN_EXCP_NO_FP(ctx); | |
2418 | return; | |
2419 | } | |
2420 | bf = crbD(ctx->opcode) >> 2; | |
2421 | sh = 7 - bf; | |
2422 | gen_optimize_fprf(); | |
2423 | gen_reset_fpstatus(); | |
2424 | t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh)); | |
2425 | t1 = tcg_const_i32(1 << sh); | |
2426 | gen_helper_store_fpscr(t0, t1); | |
2427 | tcg_temp_free_i64(t0); | |
2428 | tcg_temp_free_i32(t1); | |
2429 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2430 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX); | |
2431 | } | |
2432 | /* We can raise a differed exception */ | |
2433 | gen_helper_float_check_status(); | |
2434 | } | |
2435 | ||
2436 | /*** Addressing modes ***/ | |
2437 | /* Register indirect with immediate index : EA = (rA|0) + SIMM */ | |
2438 | static always_inline void gen_addr_imm_index (TCGv EA, | |
2439 | DisasContext *ctx, | |
2440 | target_long maskl) | |
2441 | { | |
2442 | target_long simm = SIMM(ctx->opcode); | |
2443 | ||
2444 | simm &= ~maskl; | |
2445 | if (rA(ctx->opcode) == 0) | |
2446 | tcg_gen_movi_tl(EA, simm); | |
2447 | else if (likely(simm != 0)) | |
2448 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); | |
2449 | else | |
2450 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
2451 | } | |
2452 | ||
2453 | static always_inline void gen_addr_reg_index (TCGv EA, | |
2454 | DisasContext *ctx) | |
2455 | { | |
2456 | if (rA(ctx->opcode) == 0) | |
2457 | tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); | |
2458 | else | |
2459 | tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
2460 | } | |
2461 | ||
2462 | static always_inline void gen_addr_register (TCGv EA, | |
2463 | DisasContext *ctx) | |
2464 | { | |
2465 | if (rA(ctx->opcode) == 0) | |
2466 | tcg_gen_movi_tl(EA, 0); | |
2467 | else | |
2468 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
2469 | } | |
2470 | ||
2471 | #if defined(TARGET_PPC64) | |
2472 | #define _GEN_MEM_FUNCS(name, mode) \ | |
2473 | &gen_op_##name##_##mode, \ | |
2474 | &gen_op_##name##_le_##mode, \ | |
2475 | &gen_op_##name##_64_##mode, \ | |
2476 | &gen_op_##name##_le_64_##mode | |
2477 | #else | |
2478 | #define _GEN_MEM_FUNCS(name, mode) \ | |
2479 | &gen_op_##name##_##mode, \ | |
2480 | &gen_op_##name##_le_##mode | |
2481 | #endif | |
2482 | #if defined(CONFIG_USER_ONLY) | |
2483 | #if defined(TARGET_PPC64) | |
2484 | #define NB_MEM_FUNCS 4 | |
2485 | #else | |
2486 | #define NB_MEM_FUNCS 2 | |
2487 | #endif | |
2488 | #define GEN_MEM_FUNCS(name) \ | |
2489 | _GEN_MEM_FUNCS(name, raw) | |
2490 | #else | |
2491 | #if defined(TARGET_PPC64) | |
2492 | #define NB_MEM_FUNCS 12 | |
2493 | #else | |
2494 | #define NB_MEM_FUNCS 6 | |
2495 | #endif | |
2496 | #define GEN_MEM_FUNCS(name) \ | |
2497 | _GEN_MEM_FUNCS(name, user), \ | |
2498 | _GEN_MEM_FUNCS(name, kernel), \ | |
2499 | _GEN_MEM_FUNCS(name, hypv) | |
2500 | #endif | |
2501 | ||
2502 | /*** Integer load ***/ | |
2503 | #if defined(TARGET_PPC64) | |
2504 | #define GEN_QEMU_LD_PPC64(width) \ | |
2505 | static always_inline void gen_qemu_ld##width##_ppc64(TCGv t0, TCGv t1, int flags)\ | |
2506 | { \ | |
2507 | if (likely(flags & 2)) \ | |
2508 | tcg_gen_qemu_ld##width(t0, t1, flags >> 2); \ | |
2509 | else { \ | |
2510 | TCGv addr = tcg_temp_new(); \ | |
2511 | tcg_gen_ext32u_tl(addr, t1); \ | |
2512 | tcg_gen_qemu_ld##width(t0, addr, flags >> 2); \ | |
2513 | tcg_temp_free(addr); \ | |
2514 | } \ | |
2515 | } | |
2516 | GEN_QEMU_LD_PPC64(8u) | |
2517 | GEN_QEMU_LD_PPC64(8s) | |
2518 | GEN_QEMU_LD_PPC64(16u) | |
2519 | GEN_QEMU_LD_PPC64(16s) | |
2520 | GEN_QEMU_LD_PPC64(32u) | |
2521 | GEN_QEMU_LD_PPC64(32s) | |
2522 | GEN_QEMU_LD_PPC64(64) | |
2523 | ||
2524 | #define GEN_QEMU_ST_PPC64(width) \ | |
2525 | static always_inline void gen_qemu_st##width##_ppc64(TCGv t0, TCGv t1, int flags)\ | |
2526 | { \ | |
2527 | if (likely(flags & 2)) \ | |
2528 | tcg_gen_qemu_st##width(t0, t1, flags >> 2); \ | |
2529 | else { \ | |
2530 | TCGv addr = tcg_temp_new(); \ | |
2531 | tcg_gen_ext32u_tl(addr, t1); \ | |
2532 | tcg_gen_qemu_st##width(t0, addr, flags >> 2); \ | |
2533 | tcg_temp_free(addr); \ | |
2534 | } \ | |
2535 | } | |
2536 | GEN_QEMU_ST_PPC64(8) | |
2537 | GEN_QEMU_ST_PPC64(16) | |
2538 | GEN_QEMU_ST_PPC64(32) | |
2539 | GEN_QEMU_ST_PPC64(64) | |
2540 | ||
2541 | static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags) | |
2542 | { | |
2543 | gen_qemu_ld8u_ppc64(arg0, arg1, flags); | |
2544 | } | |
2545 | ||
2546 | static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags) | |
2547 | { | |
2548 | gen_qemu_ld8s_ppc64(arg0, arg1, flags); | |
2549 | } | |
2550 | ||
2551 | static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags) | |
2552 | { | |
2553 | if (unlikely(flags & 1)) { | |
2554 | TCGv_i32 t0; | |
2555 | gen_qemu_ld16u_ppc64(arg0, arg1, flags); | |
2556 | t0 = tcg_temp_new_i32(); | |
2557 | tcg_gen_trunc_tl_i32(t0, arg0); | |
2558 | tcg_gen_bswap16_i32(t0, t0); | |
2559 | tcg_gen_extu_i32_tl(arg0, t0); | |
2560 | tcg_temp_free_i32(t0); | |
2561 | } else | |
2562 | gen_qemu_ld16u_ppc64(arg0, arg1, flags); | |
2563 | } | |
2564 | ||
2565 | static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags) | |
2566 | { | |
2567 | if (unlikely(flags & 1)) { | |
2568 | TCGv_i32 t0; | |
2569 | gen_qemu_ld16u_ppc64(arg0, arg1, flags); | |
2570 | t0 = tcg_temp_new_i32(); | |
2571 | tcg_gen_trunc_tl_i32(t0, arg0); | |
2572 | tcg_gen_bswap16_i32(t0, t0); | |
2573 | tcg_gen_extu_i32_tl(arg0, t0); | |
2574 | tcg_gen_ext16s_tl(arg0, arg0); | |
2575 | tcg_temp_free_i32(t0); | |
2576 | } else | |
2577 | gen_qemu_ld16s_ppc64(arg0, arg1, flags); | |
2578 | } | |
2579 | ||
2580 | static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags) | |
2581 | { | |
2582 | if (unlikely(flags & 1)) { | |
2583 | TCGv_i32 t0; | |
2584 | gen_qemu_ld32u_ppc64(arg0, arg1, flags); | |
2585 | t0 = tcg_temp_new_i32(); | |
2586 | tcg_gen_trunc_tl_i32(t0, arg0); | |
2587 | tcg_gen_bswap_i32(t0, t0); | |
2588 | tcg_gen_extu_i32_tl(arg0, t0); | |
2589 | tcg_temp_free_i32(t0); | |
2590 | } else | |
2591 | gen_qemu_ld32u_ppc64(arg0, arg1, flags); | |
2592 | } | |
2593 | ||
2594 | static always_inline void gen_qemu_ld32s(TCGv arg0, TCGv arg1, int flags) | |
2595 | { | |
2596 | if (unlikely(flags & 1)) { | |
2597 | TCGv_i32 t0; | |
2598 | gen_qemu_ld32u_ppc64(arg0, arg1, flags); | |
2599 | t0 = tcg_temp_new_i32(); | |
2600 | tcg_gen_trunc_tl_i32(t0, arg0); | |
2601 | tcg_gen_bswap_i32(t0, t0); | |
2602 | tcg_gen_ext_i32_tl(arg0, t0); | |
2603 | tcg_temp_free_i32(t0); | |
2604 | } else | |
2605 | gen_qemu_ld32s_ppc64(arg0, arg1, flags); | |
2606 | } | |
2607 | ||
2608 | static always_inline void gen_qemu_ld64(TCGv arg0, TCGv arg1, int flags) | |
2609 | { | |
2610 | gen_qemu_ld64_ppc64(arg0, arg1, flags); | |
2611 | if (unlikely(flags & 1)) | |
2612 | tcg_gen_bswap_i64(arg0, arg0); | |
2613 | } | |
2614 | ||
2615 | static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags) | |
2616 | { | |
2617 | gen_qemu_st8_ppc64(arg0, arg1, flags); | |
2618 | } | |
2619 | ||
2620 | static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags) | |
2621 | { | |
2622 | if (unlikely(flags & 1)) { | |
2623 | TCGv_i32 t0; | |
2624 | TCGv_i64 t1; | |
2625 | t0 = tcg_temp_new_i32(); | |
2626 | tcg_gen_trunc_tl_i32(t0, arg0); | |
2627 | tcg_gen_ext16u_i32(t0, t0); | |
2628 | tcg_gen_bswap16_i32(t0, t0); | |
2629 | t1 = tcg_temp_new_i64(); | |
2630 | tcg_gen_extu_i32_tl(t1, t0); | |
2631 | tcg_temp_free_i32(t0); | |
2632 | gen_qemu_st16_ppc64(t1, arg1, flags); | |
2633 | tcg_temp_free_i64(t1); | |
2634 | } else | |
2635 | gen_qemu_st16_ppc64(arg0, arg1, flags); | |
2636 | } | |
2637 | ||
2638 | static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags) | |
2639 | { | |
2640 | if (unlikely(flags & 1)) { | |
2641 | TCGv_i32 t0; | |
2642 | TCGv_i64 t1; | |
2643 | t0 = tcg_temp_new_i32(); | |
2644 | tcg_gen_trunc_tl_i32(t0, arg0); | |
2645 | tcg_gen_bswap_i32(t0, t0); | |
2646 | t1 = tcg_temp_new_i64(); | |
2647 | tcg_gen_extu_i32_tl(t1, t0); | |
2648 | tcg_temp_free_i32(t0); | |
2649 | gen_qemu_st32_ppc64(t1, arg1, flags); | |
2650 | tcg_temp_free_i64(t1); | |
2651 | } else | |
2652 | gen_qemu_st32_ppc64(arg0, arg1, flags); | |
2653 | } | |
2654 | ||
2655 | static always_inline void gen_qemu_st64(TCGv arg0, TCGv arg1, int flags) | |
2656 | { | |
2657 | if (unlikely(flags & 1)) { | |
2658 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
2659 | tcg_gen_bswap_i64(t0, arg0); | |
2660 | gen_qemu_st64_ppc64(t0, arg1, flags); | |
2661 | tcg_temp_free_i64(t0); | |
2662 | } else | |
2663 | gen_qemu_st64_ppc64(arg0, arg1, flags); | |
2664 | } | |
2665 | ||
2666 | ||
2667 | #else /* defined(TARGET_PPC64) */ | |
2668 | #define GEN_QEMU_LD_PPC32(width) \ | |
2669 | static always_inline void gen_qemu_ld##width##_ppc32(TCGv arg0, TCGv arg1, int flags) \ | |
2670 | { \ | |
2671 | tcg_gen_qemu_ld##width(arg0, arg1, flags >> 1); \ | |
2672 | } | |
2673 | GEN_QEMU_LD_PPC32(8u) | |
2674 | GEN_QEMU_LD_PPC32(8s) | |
2675 | GEN_QEMU_LD_PPC32(16u) | |
2676 | GEN_QEMU_LD_PPC32(16s) | |
2677 | GEN_QEMU_LD_PPC32(32u) | |
2678 | GEN_QEMU_LD_PPC32(32s) | |
2679 | static always_inline void gen_qemu_ld64_ppc32(TCGv_i64 arg0, TCGv arg1, int flags) | |
2680 | { | |
2681 | tcg_gen_qemu_ld64(arg0, arg1, flags >> 1); | |
2682 | } | |
2683 | ||
2684 | #define GEN_QEMU_ST_PPC32(width) \ | |
2685 | static always_inline void gen_qemu_st##width##_ppc32(TCGv arg0, TCGv arg1, int flags) \ | |
2686 | { \ | |
2687 | tcg_gen_qemu_st##width(arg0, arg1, flags >> 1); \ | |
2688 | } | |
2689 | GEN_QEMU_ST_PPC32(8) | |
2690 | GEN_QEMU_ST_PPC32(16) | |
2691 | GEN_QEMU_ST_PPC32(32) | |
2692 | static always_inline void gen_qemu_st64_ppc32(TCGv_i64 arg0, TCGv arg1, int flags) | |
2693 | { | |
2694 | tcg_gen_qemu_st64(arg0, arg1, flags >> 1); | |
2695 | } | |
2696 | ||
2697 | static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags) | |
2698 | { | |
2699 | gen_qemu_ld8u_ppc32(arg0, arg1, flags >> 1); | |
2700 | } | |
2701 | ||
2702 | static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags) | |
2703 | { | |
2704 | gen_qemu_ld8s_ppc32(arg0, arg1, flags >> 1); | |
2705 | } | |
2706 | ||
2707 | static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags) | |
2708 | { | |
2709 | gen_qemu_ld16u_ppc32(arg0, arg1, flags >> 1); | |
2710 | if (unlikely(flags & 1)) | |
2711 | tcg_gen_bswap16_i32(arg0, arg0); | |
2712 | } | |
2713 | ||
2714 | static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags) | |
2715 | { | |
2716 | if (unlikely(flags & 1)) { | |
2717 | gen_qemu_ld16u_ppc32(arg0, arg1, flags); | |
2718 | tcg_gen_bswap16_i32(arg0, arg0); | |
2719 | tcg_gen_ext16s_i32(arg0, arg0); | |
2720 | } else | |
2721 | gen_qemu_ld16s_ppc32(arg0, arg1, flags); | |
2722 | } | |
2723 | ||
2724 | static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags) | |
2725 | { | |
2726 | gen_qemu_ld32u_ppc32(arg0, arg1, flags); | |
2727 | if (unlikely(flags & 1)) | |
2728 | tcg_gen_bswap_i32(arg0, arg0); | |
2729 | } | |
2730 | ||
2731 | static always_inline void gen_qemu_ld64(TCGv_i64 arg0, TCGv arg1, int flags) | |
2732 | { | |
2733 | gen_qemu_ld64_ppc32(arg0, arg1, flags); | |
2734 | if (unlikely(flags & 1)) | |
2735 | tcg_gen_bswap_i64(arg0, arg0); | |
2736 | } | |
2737 | ||
2738 | static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags) | |
2739 | { | |
2740 | gen_qemu_st8_ppc32(arg0, arg1, flags); | |
2741 | } | |
2742 | ||
2743 | static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags) | |
2744 | { | |
2745 | if (unlikely(flags & 1)) { | |
2746 | TCGv_i32 temp = tcg_temp_new_i32(); | |
2747 | tcg_gen_ext16u_i32(temp, arg0); | |
2748 | tcg_gen_bswap16_i32(temp, temp); | |
2749 | gen_qemu_st16_ppc32(temp, arg1, flags); | |
2750 | tcg_temp_free_i32(temp); | |
2751 | } else | |
2752 | gen_qemu_st16_ppc32(arg0, arg1, flags); | |
2753 | } | |
2754 | ||
2755 | static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags) | |
2756 | { | |
2757 | if (unlikely(flags & 1)) { | |
2758 | TCGv_i32 temp = tcg_temp_new_i32(); | |
2759 | tcg_gen_bswap_i32(temp, arg0); | |
2760 | gen_qemu_st32_ppc32(temp, arg1, flags); | |
2761 | tcg_temp_free_i32(temp); | |
2762 | } else | |
2763 | gen_qemu_st32_ppc32(arg0, arg1, flags); | |
2764 | } | |
2765 | ||
2766 | static always_inline void gen_qemu_st64(TCGv_i64 arg0, TCGv arg1, int flags) | |
2767 | { | |
2768 | if (unlikely(flags & 1)) { | |
2769 | TCGv_i64 temp = tcg_temp_new_i64(); | |
2770 | tcg_gen_bswap_i64(temp, arg0); | |
2771 | gen_qemu_st64_ppc32(temp, arg1, flags); | |
2772 | tcg_temp_free_i64(temp); | |
2773 | } else | |
2774 | gen_qemu_st64_ppc32(arg0, arg1, flags); | |
2775 | } | |
2776 | #endif | |
2777 | ||
2778 | #define GEN_LD(name, ldop, opc, type) \ | |
2779 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \ | |
2780 | { \ | |
2781 | TCGv EA = tcg_temp_new(); \ | |
2782 | gen_set_access_type(ACCESS_INT); \ | |
2783 | gen_addr_imm_index(EA, ctx, 0); \ | |
2784 | gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \ | |
2785 | tcg_temp_free(EA); \ | |
2786 | } | |
2787 | ||
2788 | #define GEN_LDU(name, ldop, opc, type) \ | |
2789 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \ | |
2790 | { \ | |
2791 | TCGv EA; \ | |
2792 | if (unlikely(rA(ctx->opcode) == 0 || \ | |
2793 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
2794 | GEN_EXCP_INVAL(ctx); \ | |
2795 | return; \ | |
2796 | } \ | |
2797 | EA = tcg_temp_new(); \ | |
2798 | gen_set_access_type(ACCESS_INT); \ | |
2799 | if (type == PPC_64B) \ | |
2800 | gen_addr_imm_index(EA, ctx, 0x03); \ | |
2801 | else \ | |
2802 | gen_addr_imm_index(EA, ctx, 0); \ | |
2803 | gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \ | |
2804 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ | |
2805 | tcg_temp_free(EA); \ | |
2806 | } | |
2807 | ||
2808 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ | |
2809 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \ | |
2810 | { \ | |
2811 | TCGv EA; \ | |
2812 | if (unlikely(rA(ctx->opcode) == 0 || \ | |
2813 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
2814 | GEN_EXCP_INVAL(ctx); \ | |
2815 | return; \ | |
2816 | } \ | |
2817 | EA = tcg_temp_new(); \ | |
2818 | gen_set_access_type(ACCESS_INT); \ | |
2819 | gen_addr_reg_index(EA, ctx); \ | |
2820 | gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \ | |
2821 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ | |
2822 | tcg_temp_free(EA); \ | |
2823 | } | |
2824 | ||
2825 | #define GEN_LDX(name, ldop, opc2, opc3, type) \ | |
2826 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \ | |
2827 | { \ | |
2828 | TCGv EA = tcg_temp_new(); \ | |
2829 | gen_set_access_type(ACCESS_INT); \ | |
2830 | gen_addr_reg_index(EA, ctx); \ | |
2831 | gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \ | |
2832 | tcg_temp_free(EA); \ | |
2833 | } | |
2834 | ||
2835 | #define GEN_LDS(name, ldop, op, type) \ | |
2836 | GEN_LD(name, ldop, op | 0x20, type); \ | |
2837 | GEN_LDU(name, ldop, op | 0x21, type); \ | |
2838 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ | |
2839 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
2840 | ||
2841 | /* lbz lbzu lbzux lbzx */ | |
2842 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); | |
2843 | /* lha lhau lhaux lhax */ | |
2844 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); | |
2845 | /* lhz lhzu lhzux lhzx */ | |
2846 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); | |
2847 | /* lwz lwzu lwzux lwzx */ | |
2848 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); | |
2849 | #if defined(TARGET_PPC64) | |
2850 | /* lwaux */ | |
2851 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); | |
2852 | /* lwax */ | |
2853 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); | |
2854 | /* ldux */ | |
2855 | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B); | |
2856 | /* ldx */ | |
2857 | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B); | |
2858 | GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B) | |
2859 | { | |
2860 | TCGv EA; | |
2861 | if (Rc(ctx->opcode)) { | |
2862 | if (unlikely(rA(ctx->opcode) == 0 || | |
2863 | rA(ctx->opcode) == rD(ctx->opcode))) { | |
2864 | GEN_EXCP_INVAL(ctx); | |
2865 | return; | |
2866 | } | |
2867 | } | |
2868 | EA = tcg_temp_new(); | |
2869 | gen_set_access_type(ACCESS_INT); | |
2870 | gen_addr_imm_index(EA, ctx, 0x03); | |
2871 | if (ctx->opcode & 0x02) { | |
2872 | /* lwa (lwau is undefined) */ | |
2873 | gen_qemu_ld32s(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); | |
2874 | } else { | |
2875 | /* ld - ldu */ | |
2876 | gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); | |
2877 | } | |
2878 | if (Rc(ctx->opcode)) | |
2879 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); | |
2880 | tcg_temp_free(EA); | |
2881 | } | |
2882 | /* lq */ | |
2883 | GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX) | |
2884 | { | |
2885 | #if defined(CONFIG_USER_ONLY) | |
2886 | GEN_EXCP_PRIVOPC(ctx); | |
2887 | #else | |
2888 | int ra, rd; | |
2889 | TCGv EA; | |
2890 | ||
2891 | /* Restore CPU state */ | |
2892 | if (unlikely(ctx->supervisor == 0)) { | |
2893 | GEN_EXCP_PRIVOPC(ctx); | |
2894 | return; | |
2895 | } | |
2896 | ra = rA(ctx->opcode); | |
2897 | rd = rD(ctx->opcode); | |
2898 | if (unlikely((rd & 1) || rd == ra)) { | |
2899 | GEN_EXCP_INVAL(ctx); | |
2900 | return; | |
2901 | } | |
2902 | if (unlikely(ctx->mem_idx & 1)) { | |
2903 | /* Little-endian mode is not handled */ | |
2904 | GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); | |
2905 | return; | |
2906 | } | |
2907 | EA = tcg_temp_new(); | |
2908 | gen_set_access_type(ACCESS_INT); | |
2909 | gen_addr_imm_index(EA, ctx, 0x0F); | |
2910 | gen_qemu_ld64(cpu_gpr[rd], EA, ctx->mem_idx); | |
2911 | tcg_gen_addi_tl(EA, EA, 8); | |
2912 | gen_qemu_ld64(cpu_gpr[rd+1], EA, ctx->mem_idx); | |
2913 | tcg_temp_free(EA); | |
2914 | #endif | |
2915 | } | |
2916 | #endif | |
2917 | ||
2918 | /*** Integer store ***/ | |
2919 | #define GEN_ST(name, stop, opc, type) \ | |
2920 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \ | |
2921 | { \ | |
2922 | TCGv EA = tcg_temp_new(); \ | |
2923 | gen_set_access_type(ACCESS_INT); \ | |
2924 | gen_addr_imm_index(EA, ctx, 0); \ | |
2925 | gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \ | |
2926 | tcg_temp_free(EA); \ | |
2927 | } | |
2928 | ||
2929 | #define GEN_STU(name, stop, opc, type) \ | |
2930 | GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \ | |
2931 | { \ | |
2932 | TCGv EA; \ | |
2933 | if (unlikely(rA(ctx->opcode) == 0)) { \ | |
2934 | GEN_EXCP_INVAL(ctx); \ | |
2935 | return; \ | |
2936 | } \ | |
2937 | EA = tcg_temp_new(); \ | |
2938 | gen_set_access_type(ACCESS_INT); \ | |
2939 | if (type == PPC_64B) \ | |
2940 | gen_addr_imm_index(EA, ctx, 0x03); \ | |
2941 | else \ | |
2942 | gen_addr_imm_index(EA, ctx, 0); \ | |
2943 | gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \ | |
2944 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ | |
2945 | tcg_temp_free(EA); \ | |
2946 | } | |
2947 | ||
2948 | #define GEN_STUX(name, stop, opc2, opc3, type) \ | |
2949 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \ | |
2950 | { \ | |
2951 | TCGv EA; \ | |
2952 | if (unlikely(rA(ctx->opcode) == 0)) { \ | |
2953 | GEN_EXCP_INVAL(ctx); \ | |
2954 | return; \ | |
2955 | } \ | |
2956 | EA = tcg_temp_new(); \ | |
2957 | gen_set_access_type(ACCESS_INT); \ | |
2958 | gen_addr_reg_index(EA, ctx); \ | |
2959 | gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \ | |
2960 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ | |
2961 | tcg_temp_free(EA); \ | |
2962 | } | |
2963 | ||
2964 | #define GEN_STX(name, stop, opc2, opc3, type) \ | |
2965 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \ | |
2966 | { \ | |
2967 | TCGv EA = tcg_temp_new(); \ | |
2968 | gen_set_access_type(ACCESS_INT); \ | |
2969 | gen_addr_reg_index(EA, ctx); \ | |
2970 | gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \ | |
2971 | tcg_temp_free(EA); \ | |
2972 | } | |
2973 | ||
2974 | #define GEN_STS(name, stop, op, type) \ | |
2975 | GEN_ST(name, stop, op | 0x20, type); \ | |
2976 | GEN_STU(name, stop, op | 0x21, type); \ | |
2977 | GEN_STUX(name, stop, 0x17, op | 0x01, type); \ | |
2978 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
2979 | ||
2980 | /* stb stbu stbux stbx */ | |
2981 | GEN_STS(stb, st8, 0x06, PPC_INTEGER); | |
2982 | /* sth sthu sthux sthx */ | |
2983 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER); | |
2984 | /* stw stwu stwux stwx */ | |
2985 | GEN_STS(stw, st32, 0x04, PPC_INTEGER); | |
2986 | #if defined(TARGET_PPC64) | |
2987 | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B); | |
2988 | GEN_STX(std, st64, 0x15, 0x04, PPC_64B); | |
2989 | GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B) | |
2990 | { | |
2991 | int rs; | |
2992 | TCGv EA; | |
2993 | ||
2994 | rs = rS(ctx->opcode); | |
2995 | if ((ctx->opcode & 0x3) == 0x2) { | |
2996 | #if defined(CONFIG_USER_ONLY) | |
2997 | GEN_EXCP_PRIVOPC(ctx); | |
2998 | #else | |
2999 | /* stq */ | |
3000 | if (unlikely(ctx->supervisor == 0)) { | |
3001 | GEN_EXCP_PRIVOPC(ctx); | |
3002 | return; | |
3003 | } | |
3004 | if (unlikely(rs & 1)) { | |
3005 | GEN_EXCP_INVAL(ctx); | |
3006 | return; | |
3007 | } | |
3008 | if (unlikely(ctx->mem_idx & 1)) { | |
3009 | /* Little-endian mode is not handled */ | |
3010 | GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); | |
3011 | return; | |
3012 | } | |
3013 | EA = tcg_temp_new(); | |
3014 | gen_set_access_type(ACCESS_INT); | |
3015 | gen_addr_imm_index(EA, ctx, 0x03); | |
3016 | gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx); | |
3017 | tcg_gen_addi_tl(EA, EA, 8); | |
3018 | gen_qemu_st64(cpu_gpr[rs+1], EA, ctx->mem_idx); | |
3019 | tcg_temp_free(EA); | |
3020 | #endif | |
3021 | } else { | |
3022 | /* std / stdu */ | |
3023 | if (Rc(ctx->opcode)) { | |
3024 | if (unlikely(rA(ctx->opcode) == 0)) { | |
3025 | GEN_EXCP_INVAL(ctx); | |
3026 | return; | |
3027 | } | |
3028 | } | |
3029 | EA = tcg_temp_new(); | |
3030 | gen_set_access_type(ACCESS_INT); | |
3031 | gen_addr_imm_index(EA, ctx, 0x03); | |
3032 | gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx); | |
3033 | if (Rc(ctx->opcode)) | |
3034 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); | |
3035 | tcg_temp_free(EA); | |
3036 | } | |
3037 | } | |
3038 | #endif | |
3039 | /*** Integer load and store with byte reverse ***/ | |
3040 | /* lhbrx */ | |
3041 | void always_inline gen_qemu_ld16ur(TCGv t0, TCGv t1, int flags) | |
3042 | { | |
3043 | TCGv_i32 temp = tcg_temp_new_i32(); | |
3044 | gen_qemu_ld16u(t0, t1, flags); | |
3045 | tcg_gen_trunc_tl_i32(temp, t0); | |
3046 | tcg_gen_bswap16_i32(temp, temp); | |
3047 | tcg_gen_extu_i32_tl(t0, temp); | |
3048 | tcg_temp_free_i32(temp); | |
3049 | } | |
3050 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); | |
3051 | ||
3052 | /* lwbrx */ | |
3053 | void always_inline gen_qemu_ld32ur(TCGv t0, TCGv t1, int flags) | |
3054 | { | |
3055 | TCGv_i32 temp = tcg_temp_new_i32(); | |
3056 | gen_qemu_ld32u(t0, t1, flags); | |
3057 | tcg_gen_trunc_tl_i32(temp, t0); | |
3058 | tcg_gen_bswap_i32(temp, temp); | |
3059 | tcg_gen_extu_i32_tl(t0, temp); | |
3060 | tcg_temp_free_i32(temp); | |
3061 | } | |
3062 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); | |
3063 | ||
3064 | /* sthbrx */ | |
3065 | void always_inline gen_qemu_st16r(TCGv t0, TCGv t1, int flags) | |
3066 | { | |
3067 | TCGv_i32 temp = tcg_temp_new_i32(); | |
3068 | TCGv t2 = tcg_temp_new(); | |
3069 | tcg_gen_trunc_tl_i32(temp, t0); | |
3070 | tcg_gen_ext16u_i32(temp, temp); | |
3071 | tcg_gen_bswap16_i32(temp, temp); | |
3072 | tcg_gen_extu_i32_tl(t2, temp); | |
3073 | tcg_temp_free_i32(temp); | |
3074 | gen_qemu_st16(t2, t1, flags); | |
3075 | tcg_temp_free(t2); | |
3076 | } | |
3077 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); | |
3078 | ||
3079 | /* stwbrx */ | |
3080 | void always_inline gen_qemu_st32r(TCGv t0, TCGv t1, int flags) | |
3081 | { | |
3082 | TCGv_i32 temp = tcg_temp_new_i32(); | |
3083 | TCGv t2 = tcg_temp_new(); | |
3084 | tcg_gen_trunc_tl_i32(temp, t0); | |
3085 | tcg_gen_bswap_i32(temp, temp); | |
3086 | tcg_gen_extu_i32_tl(t2, temp); | |
3087 | tcg_temp_free_i32(temp); | |
3088 | gen_qemu_st32(t2, t1, flags); | |
3089 | tcg_temp_free(t2); | |
3090 | } | |
3091 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); | |
3092 | ||
3093 | /*** Integer load and store multiple ***/ | |
3094 | /* lmw */ | |
3095 | GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) | |
3096 | { | |
3097 | TCGv t0 = tcg_temp_new(); | |
3098 | TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); | |
3099 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
3100 | gen_update_nip(ctx, ctx->nip - 4); | |
3101 | gen_addr_imm_index(t0, ctx, 0); | |
3102 | gen_helper_lmw(t0, t1); | |
3103 | tcg_temp_free(t0); | |
3104 | tcg_temp_free_i32(t1); | |
3105 | } | |
3106 | ||
3107 | /* stmw */ | |
3108 | GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) | |
3109 | { | |
3110 | TCGv t0 = tcg_temp_new(); | |
3111 | TCGv_i32 t1 = tcg_const_i32(rS(ctx->opcode)); | |
3112 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
3113 | gen_update_nip(ctx, ctx->nip - 4); | |
3114 | gen_addr_imm_index(t0, ctx, 0); | |
3115 | gen_helper_stmw(t0, t1); | |
3116 | tcg_temp_free(t0); | |
3117 | tcg_temp_free_i32(t1); | |
3118 | } | |
3119 | ||
3120 | /*** Integer load and store strings ***/ | |
3121 | /* lswi */ | |
3122 | /* PowerPC32 specification says we must generate an exception if | |
3123 | * rA is in the range of registers to be loaded. | |
3124 | * In an other hand, IBM says this is valid, but rA won't be loaded. | |
3125 | * For now, I'll follow the spec... | |
3126 | */ | |
3127 | GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING) | |
3128 | { | |
3129 | TCGv t0; | |
3130 | TCGv_i32 t1, t2; | |
3131 | int nb = NB(ctx->opcode); | |
3132 | int start = rD(ctx->opcode); | |
3133 | int ra = rA(ctx->opcode); | |
3134 | int nr; | |
3135 | ||
3136 | if (nb == 0) | |
3137 | nb = 32; | |
3138 | nr = nb / 4; | |
3139 | if (unlikely(((start + nr) > 32 && | |
3140 | start <= ra && (start + nr - 32) > ra) || | |
3141 | ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) { | |
3142 | GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM, | |
3143 | POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX); | |
3144 | return; | |
3145 | } | |
3146 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
3147 | gen_update_nip(ctx, ctx->nip - 4); | |
3148 | t0 = tcg_temp_new(); | |
3149 | gen_addr_register(t0, ctx); | |
3150 | t1 = tcg_const_i32(nb); | |
3151 | t2 = tcg_const_i32(start); | |
3152 | gen_helper_lsw(t0, t1, t2); | |
3153 | tcg_temp_free(t0); | |
3154 | tcg_temp_free_i32(t1); | |
3155 | tcg_temp_free_i32(t2); | |
3156 | } | |
3157 | ||
3158 | /* lswx */ | |
3159 | GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING) | |
3160 | { | |
3161 | TCGv t0 = tcg_temp_new(); | |
3162 | TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); | |
3163 | TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); | |
3164 | TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); | |
3165 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
3166 | gen_update_nip(ctx, ctx->nip - 4); | |
3167 | gen_addr_reg_index(t0, ctx); | |
3168 | gen_helper_lswx(t0, t1, t2, t3); | |
3169 | tcg_temp_free(t0); | |
3170 | tcg_temp_free_i32(t1); | |
3171 | tcg_temp_free_i32(t2); | |
3172 | tcg_temp_free_i32(t3); | |
3173 | } | |
3174 | ||
3175 | /* stswi */ | |
3176 | GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING) | |
3177 | { | |
3178 | int nb = NB(ctx->opcode); | |
3179 | TCGv t0 = tcg_temp_new(); | |
3180 | TCGv_i32 t1; | |
3181 | TCGv_i32 t2 = tcg_const_i32(rS(ctx->opcode)); | |
3182 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
3183 | gen_update_nip(ctx, ctx->nip - 4); | |
3184 | gen_addr_register(t0, ctx); | |
3185 | if (nb == 0) | |
3186 | nb = 32; | |
3187 | t1 = tcg_const_i32(nb); | |
3188 | gen_helper_stsw(t0, t1, t2); | |
3189 | tcg_temp_free(t0); | |
3190 | tcg_temp_free_i32(t1); | |
3191 | tcg_temp_free_i32(t2); | |
3192 | } | |
3193 | ||
3194 | /* stswx */ | |
3195 | GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING) | |
3196 | { | |
3197 | TCGv t0 = tcg_temp_new(); | |
3198 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
3199 | TCGv_i32 t2 = tcg_const_i32(rS(ctx->opcode)); | |
3200 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
3201 | gen_update_nip(ctx, ctx->nip - 4); | |
3202 | gen_addr_reg_index(t0, ctx); | |
3203 | tcg_gen_trunc_tl_i32(t1, cpu_xer); | |
3204 | tcg_gen_andi_i32(t1, t1, 0x7F); | |
3205 | gen_helper_stsw(t0, t1, t2); | |
3206 | tcg_temp_free(t0); | |
3207 | tcg_temp_free_i32(t1); | |
3208 | tcg_temp_free_i32(t2); | |
3209 | } | |
3210 | ||
3211 | /*** Memory synchronisation ***/ | |
3212 | /* eieio */ | |
3213 | GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO) | |
3214 | { | |
3215 | } | |
3216 | ||
3217 | /* isync */ | |
3218 | GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM) | |
3219 | { | |
3220 | GEN_STOP(ctx); | |
3221 | } | |
3222 | ||
3223 | #define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])() | |
3224 | #define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])() | |
3225 | static GenOpFunc *gen_op_lwarx[NB_MEM_FUNCS] = { | |
3226 | GEN_MEM_FUNCS(lwarx), | |
3227 | }; | |
3228 | static GenOpFunc *gen_op_stwcx[NB_MEM_FUNCS] = { | |
3229 | GEN_MEM_FUNCS(stwcx), | |
3230 | }; | |
3231 | ||
3232 | /* lwarx */ | |
3233 | GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES) | |
3234 | { | |
3235 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
3236 | gen_update_nip(ctx, ctx->nip - 4); | |
3237 | gen_set_access_type(ACCESS_RES); | |
3238 | gen_addr_reg_index(cpu_T[0], ctx); | |
3239 | op_lwarx(); | |
3240 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); | |
3241 | } | |
3242 | ||
3243 | /* stwcx. */ | |
3244 | GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES) | |
3245 | { | |
3246 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
3247 | gen_update_nip(ctx, ctx->nip - 4); | |
3248 | gen_set_access_type(ACCESS_RES); | |
3249 | gen_addr_reg_index(cpu_T[0], ctx); | |
3250 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); | |
3251 | op_stwcx(); | |
3252 | } | |
3253 | ||
3254 | #if defined(TARGET_PPC64) | |
3255 | #define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])() | |
3256 | #define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])() | |
3257 | static GenOpFunc *gen_op_ldarx[NB_MEM_FUNCS] = { | |
3258 | GEN_MEM_FUNCS(ldarx), | |
3259 | }; | |
3260 | static GenOpFunc *gen_op_stdcx[NB_MEM_FUNCS] = { | |
3261 | GEN_MEM_FUNCS(stdcx), | |
3262 | }; | |
3263 | ||
3264 | /* ldarx */ | |
3265 | GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B) | |
3266 | { | |
3267 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
3268 | gen_update_nip(ctx, ctx->nip - 4); | |
3269 | gen_set_access_type(ACCESS_RES); | |
3270 | gen_addr_reg_index(cpu_T[0], ctx); | |
3271 | op_ldarx(); | |
3272 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); | |
3273 | } | |
3274 | ||
3275 | /* stdcx. */ | |
3276 | GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B) | |
3277 | { | |
3278 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
3279 | gen_update_nip(ctx, ctx->nip - 4); | |
3280 | gen_set_access_type(ACCESS_RES); | |
3281 | gen_addr_reg_index(cpu_T[0], ctx); | |
3282 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); | |
3283 | op_stdcx(); | |
3284 | } | |
3285 | #endif /* defined(TARGET_PPC64) */ | |
3286 | ||
3287 | /* sync */ | |
3288 | GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC) | |
3289 | { | |
3290 | } | |
3291 | ||
3292 | /* wait */ | |
3293 | GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT) | |
3294 | { | |
3295 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
3296 | tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted)); | |
3297 | tcg_temp_free_i32(t0); | |
3298 | /* Stop translation, as the CPU is supposed to sleep from now */ | |
3299 | GEN_EXCP(ctx, EXCP_HLT, 1); | |
3300 | } | |
3301 | ||
3302 | /*** Floating-point load ***/ | |
3303 | #define GEN_LDF(name, ldop, opc, type) \ | |
3304 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \ | |
3305 | { \ | |
3306 | TCGv EA; \ | |
3307 | if (unlikely(!ctx->fpu_enabled)) { \ | |
3308 | GEN_EXCP_NO_FP(ctx); \ | |
3309 | return; \ | |
3310 | } \ | |
3311 | gen_set_access_type(ACCESS_FLOAT); \ | |
3312 | EA = tcg_temp_new(); \ | |
3313 | gen_addr_imm_index(EA, ctx, 0); \ | |
3314 | gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \ | |
3315 | tcg_temp_free(EA); \ | |
3316 | } | |
3317 | ||
3318 | #define GEN_LDUF(name, ldop, opc, type) \ | |
3319 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \ | |
3320 | { \ | |
3321 | TCGv EA; \ | |
3322 | if (unlikely(!ctx->fpu_enabled)) { \ | |
3323 | GEN_EXCP_NO_FP(ctx); \ | |
3324 | return; \ | |
3325 | } \ | |
3326 | if (unlikely(rA(ctx->opcode) == 0)) { \ | |
3327 | GEN_EXCP_INVAL(ctx); \ | |
3328 | return; \ | |
3329 | } \ | |
3330 | gen_set_access_type(ACCESS_FLOAT); \ | |
3331 | EA = tcg_temp_new(); \ | |
3332 | gen_addr_imm_index(EA, ctx, 0); \ | |
3333 | gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \ | |
3334 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ | |
3335 | tcg_temp_free(EA); \ | |
3336 | } | |
3337 | ||
3338 | #define GEN_LDUXF(name, ldop, opc, type) \ | |
3339 | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \ | |
3340 | { \ | |
3341 | TCGv EA; \ | |
3342 | if (unlikely(!ctx->fpu_enabled)) { \ | |
3343 | GEN_EXCP_NO_FP(ctx); \ | |
3344 | return; \ | |
3345 | } \ | |
3346 | if (unlikely(rA(ctx->opcode) == 0)) { \ | |
3347 | GEN_EXCP_INVAL(ctx); \ | |
3348 | return; \ | |
3349 | } \ | |
3350 | gen_set_access_type(ACCESS_FLOAT); \ | |
3351 | EA = tcg_temp_new(); \ | |
3352 | gen_addr_reg_index(EA, ctx); \ | |
3353 | gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \ | |
3354 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ | |
3355 | tcg_temp_free(EA); \ | |
3356 | } | |
3357 | ||
3358 | #define GEN_LDXF(name, ldop, opc2, opc3, type) \ | |
3359 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \ | |
3360 | { \ | |
3361 | TCGv EA; \ | |
3362 | if (unlikely(!ctx->fpu_enabled)) { \ | |
3363 | GEN_EXCP_NO_FP(ctx); \ | |
3364 | return; \ | |
3365 | } \ | |
3366 | gen_set_access_type(ACCESS_FLOAT); \ | |
3367 | EA = tcg_temp_new(); \ | |
3368 | gen_addr_reg_index(EA, ctx); \ | |
3369 | gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \ | |
3370 | tcg_temp_free(EA); \ | |
3371 | } | |
3372 | ||
3373 | #define GEN_LDFS(name, ldop, op, type) \ | |
3374 | GEN_LDF(name, ldop, op | 0x20, type); \ | |
3375 | GEN_LDUF(name, ldop, op | 0x21, type); \ | |
3376 | GEN_LDUXF(name, ldop, op | 0x01, type); \ | |
3377 | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) | |
3378 | ||
3379 | static always_inline void gen_qemu_ld32fs(TCGv_i64 arg1, TCGv arg2, int flags) | |
3380 | { | |
3381 | TCGv t0 = tcg_temp_new(); | |
3382 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
3383 | gen_qemu_ld32u(t0, arg2, flags); | |
3384 | tcg_gen_trunc_tl_i32(t1, t0); | |
3385 | tcg_temp_free(t0); | |
3386 | gen_helper_float32_to_float64(arg1, t1); | |
3387 | tcg_temp_free_i32(t1); | |
3388 | } | |
3389 | ||
3390 | /* lfd lfdu lfdux lfdx */ | |
3391 | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT); | |
3392 | /* lfs lfsu lfsux lfsx */ | |
3393 | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT); | |
3394 | ||
3395 | /*** Floating-point store ***/ | |
3396 | #define GEN_STF(name, stop, opc, type) \ | |
3397 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \ | |
3398 | { \ | |
3399 | TCGv EA; \ | |
3400 | if (unlikely(!ctx->fpu_enabled)) { \ | |
3401 | GEN_EXCP_NO_FP(ctx); \ | |
3402 | return; \ | |
3403 | } \ | |
3404 | gen_set_access_type(ACCESS_FLOAT); \ | |
3405 | EA = tcg_temp_new(); \ | |
3406 | gen_addr_imm_index(EA, ctx, 0); \ | |
3407 | gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \ | |
3408 | tcg_temp_free(EA); \ | |
3409 | } | |
3410 | ||
3411 | #define GEN_STUF(name, stop, opc, type) \ | |
3412 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \ | |
3413 | { \ | |
3414 | TCGv EA; \ | |
3415 | if (unlikely(!ctx->fpu_enabled)) { \ | |
3416 | GEN_EXCP_NO_FP(ctx); \ | |
3417 | return; \ | |
3418 | } \ | |
3419 | if (unlikely(rA(ctx->opcode) == 0)) { \ | |
3420 | GEN_EXCP_INVAL(ctx); \ | |
3421 | return; \ | |
3422 | } \ | |
3423 | gen_set_access_type(ACCESS_FLOAT); \ | |
3424 | EA = tcg_temp_new(); \ | |
3425 | gen_addr_imm_index(EA, ctx, 0); \ | |
3426 | gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \ | |
3427 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ | |
3428 | tcg_temp_free(EA); \ | |
3429 | } | |
3430 | ||
3431 | #define GEN_STUXF(name, stop, opc, type) \ | |
3432 | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \ | |
3433 | { \ | |
3434 | TCGv EA; \ | |
3435 | if (unlikely(!ctx->fpu_enabled)) { \ | |
3436 | GEN_EXCP_NO_FP(ctx); \ | |
3437 | return; \ | |
3438 | } \ | |
3439 | if (unlikely(rA(ctx->opcode) == 0)) { \ | |
3440 | GEN_EXCP_INVAL(ctx); \ | |
3441 | return; \ | |
3442 | } \ | |
3443 | gen_set_access_type(ACCESS_FLOAT); \ | |
3444 | EA = tcg_temp_new(); \ | |
3445 | gen_addr_reg_index(EA, ctx); \ | |
3446 | gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \ | |
3447 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ | |
3448 | tcg_temp_free(EA); \ | |
3449 | } | |
3450 | ||
3451 | #define GEN_STXF(name, stop, opc2, opc3, type) \ | |
3452 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \ | |
3453 | { \ | |
3454 | TCGv EA; \ | |
3455 | if (unlikely(!ctx->fpu_enabled)) { \ | |
3456 | GEN_EXCP_NO_FP(ctx); \ | |
3457 | return; \ | |
3458 | } \ | |
3459 | gen_set_access_type(ACCESS_FLOAT); \ | |
3460 | EA = tcg_temp_new(); \ | |
3461 | gen_addr_reg_index(EA, ctx); \ | |
3462 | gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \ | |
3463 | tcg_temp_free(EA); \ | |
3464 | } | |
3465 | ||
3466 | #define GEN_STFS(name, stop, op, type) \ | |
3467 | GEN_STF(name, stop, op | 0x20, type); \ | |
3468 | GEN_STUF(name, stop, op | 0x21, type); \ | |
3469 | GEN_STUXF(name, stop, op | 0x01, type); \ | |
3470 | GEN_STXF(name, stop, 0x17, op | 0x00, type) | |
3471 | ||
3472 | static always_inline void gen_qemu_st32fs(TCGv_i64 arg1, TCGv arg2, int flags) | |
3473 | { | |
3474 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
3475 | TCGv t1 = tcg_temp_new(); | |
3476 | gen_helper_float64_to_float32(t0, arg1); | |
3477 | tcg_gen_extu_i32_tl(t1, t0); | |
3478 | tcg_temp_free_i32(t0); | |
3479 | gen_qemu_st32(t1, arg2, flags); | |
3480 | tcg_temp_free(t1); | |
3481 | } | |
3482 | ||
3483 | /* stfd stfdu stfdux stfdx */ | |
3484 | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT); | |
3485 | /* stfs stfsu stfsux stfsx */ | |
3486 | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT); | |
3487 | ||
3488 | /* Optional: */ | |
3489 | static always_inline void gen_qemu_st32fiw(TCGv_i64 arg1, TCGv arg2, int flags) | |
3490 | { | |
3491 | TCGv t0 = tcg_temp_new(); | |
3492 | tcg_gen_trunc_i64_tl(t0, arg1), | |
3493 | gen_qemu_st32(t0, arg2, flags); | |
3494 | tcg_temp_free(t0); | |
3495 | } | |
3496 | /* stfiwx */ | |
3497 | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX); | |
3498 | ||
3499 | /*** Branch ***/ | |
3500 | static always_inline void gen_goto_tb (DisasContext *ctx, int n, | |
3501 | target_ulong dest) | |
3502 | { | |
3503 | TranslationBlock *tb; | |
3504 | tb = ctx->tb; | |
3505 | #if defined(TARGET_PPC64) | |
3506 | if (!ctx->sf_mode) | |
3507 | dest = (uint32_t) dest; | |
3508 | #endif | |
3509 | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) && | |
3510 | likely(!ctx->singlestep_enabled)) { | |
3511 | tcg_gen_goto_tb(n); | |
3512 | tcg_gen_movi_tl(cpu_nip, dest & ~3); | |
3513 | tcg_gen_exit_tb((long)tb + n); | |
3514 | } else { | |
3515 | tcg_gen_movi_tl(cpu_nip, dest & ~3); | |
3516 | if (unlikely(ctx->singlestep_enabled)) { | |
3517 | if ((ctx->singlestep_enabled & | |
3518 | (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && | |
3519 | ctx->exception == POWERPC_EXCP_BRANCH) { | |
3520 | target_ulong tmp = ctx->nip; | |
3521 | ctx->nip = dest; | |
3522 | GEN_EXCP(ctx, POWERPC_EXCP_TRACE, 0); | |
3523 | ctx->nip = tmp; | |
3524 | } | |
3525 | if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) { | |
3526 | gen_update_nip(ctx, dest); | |
3527 | gen_helper_raise_debug(); | |
3528 | } | |
3529 | } | |
3530 | tcg_gen_exit_tb(0); | |
3531 | } | |
3532 | } | |
3533 | ||
3534 | static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip) | |
3535 | { | |
3536 | #if defined(TARGET_PPC64) | |
3537 | if (ctx->sf_mode == 0) | |
3538 | tcg_gen_movi_tl(cpu_lr, (uint32_t)nip); | |
3539 | else | |
3540 | #endif | |
3541 | tcg_gen_movi_tl(cpu_lr, nip); | |
3542 | } | |
3543 | ||
3544 | /* b ba bl bla */ | |
3545 | GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW) | |
3546 | { | |
3547 | target_ulong li, target; | |
3548 | ||
3549 | ctx->exception = POWERPC_EXCP_BRANCH; | |
3550 | /* sign extend LI */ | |
3551 | #if defined(TARGET_PPC64) | |
3552 | if (ctx->sf_mode) | |
3553 | li = ((int64_t)LI(ctx->opcode) << 38) >> 38; | |
3554 | else | |
3555 | #endif | |
3556 | li = ((int32_t)LI(ctx->opcode) << 6) >> 6; | |
3557 | if (likely(AA(ctx->opcode) == 0)) | |
3558 | target = ctx->nip + li - 4; | |
3559 | else | |
3560 | target = li; | |
3561 | if (LK(ctx->opcode)) | |
3562 | gen_setlr(ctx, ctx->nip); | |
3563 | gen_goto_tb(ctx, 0, target); | |
3564 | } | |
3565 | ||
3566 | #define BCOND_IM 0 | |
3567 | #define BCOND_LR 1 | |
3568 | #define BCOND_CTR 2 | |
3569 | ||
3570 | static always_inline void gen_bcond (DisasContext *ctx, int type) | |
3571 | { | |
3572 | uint32_t bo = BO(ctx->opcode); | |
3573 | int l1 = gen_new_label(); | |
3574 | TCGv target; | |
3575 | ||
3576 | ctx->exception = POWERPC_EXCP_BRANCH; | |
3577 | if (type == BCOND_LR || type == BCOND_CTR) { | |
3578 | target = tcg_temp_local_new(); | |
3579 | if (type == BCOND_CTR) | |
3580 | tcg_gen_mov_tl(target, cpu_ctr); | |
3581 | else | |
3582 | tcg_gen_mov_tl(target, cpu_lr); | |
3583 | } | |
3584 | if (LK(ctx->opcode)) | |
3585 | gen_setlr(ctx, ctx->nip); | |
3586 | l1 = gen_new_label(); | |
3587 | if ((bo & 0x4) == 0) { | |
3588 | /* Decrement and test CTR */ | |
3589 | TCGv temp = tcg_temp_new(); | |
3590 | if (unlikely(type == BCOND_CTR)) { | |
3591 | GEN_EXCP_INVAL(ctx); | |
3592 | return; | |
3593 | } | |
3594 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); | |
3595 | #if defined(TARGET_PPC64) | |
3596 | if (!ctx->sf_mode) | |
3597 | tcg_gen_ext32u_tl(temp, cpu_ctr); | |
3598 | else | |
3599 | #endif | |
3600 | tcg_gen_mov_tl(temp, cpu_ctr); | |
3601 | if (bo & 0x2) { | |
3602 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); | |
3603 | } else { | |
3604 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); | |
3605 | } | |
3606 | tcg_temp_free(temp); | |
3607 | } | |
3608 | if ((bo & 0x10) == 0) { | |
3609 | /* Test CR */ | |
3610 | uint32_t bi = BI(ctx->opcode); | |
3611 | uint32_t mask = 1 << (3 - (bi & 0x03)); | |
3612 | TCGv_i32 temp = tcg_temp_new_i32(); | |
3613 | ||
3614 | if (bo & 0x8) { | |
3615 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); | |
3616 | tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); | |
3617 | } else { | |
3618 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); | |
3619 | tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); | |
3620 | } | |
3621 | tcg_temp_free_i32(temp); | |
3622 | } | |
3623 | if (type == BCOND_IM) { | |
3624 | target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); | |
3625 | if (likely(AA(ctx->opcode) == 0)) { | |
3626 | gen_goto_tb(ctx, 0, ctx->nip + li - 4); | |
3627 | } else { | |
3628 | gen_goto_tb(ctx, 0, li); | |
3629 | } | |
3630 | gen_set_label(l1); | |
3631 | gen_goto_tb(ctx, 1, ctx->nip); | |
3632 | } else { | |
3633 | #if defined(TARGET_PPC64) | |
3634 | if (!(ctx->sf_mode)) | |
3635 | tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); | |
3636 | else | |
3637 | #endif | |
3638 | tcg_gen_andi_tl(cpu_nip, target, ~3); | |
3639 | tcg_gen_exit_tb(0); | |
3640 | gen_set_label(l1); | |
3641 | #if defined(TARGET_PPC64) | |
3642 | if (!(ctx->sf_mode)) | |
3643 | tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip); | |
3644 | else | |
3645 | #endif | |
3646 | tcg_gen_movi_tl(cpu_nip, ctx->nip); | |
3647 | tcg_gen_exit_tb(0); | |
3648 | } | |
3649 | } | |
3650 | ||
3651 | GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW) | |
3652 | { | |
3653 | gen_bcond(ctx, BCOND_IM); | |
3654 | } | |
3655 | ||
3656 | GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW) | |
3657 | { | |
3658 | gen_bcond(ctx, BCOND_CTR); | |
3659 | } | |
3660 | ||
3661 | GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW) | |
3662 | { | |
3663 | gen_bcond(ctx, BCOND_LR); | |
3664 | } | |
3665 | ||
3666 | /*** Condition register logical ***/ | |
3667 | #define GEN_CRLOGIC(name, tcg_op, opc) \ | |
3668 | GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \ | |
3669 | { \ | |
3670 | uint8_t bitmask; \ | |
3671 | int sh; \ | |
3672 | TCGv_i32 t0, t1; \ | |
3673 | sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ | |
3674 | t0 = tcg_temp_new_i32(); \ | |
3675 | if (sh > 0) \ | |
3676 | tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ | |
3677 | else if (sh < 0) \ | |
3678 | tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ | |
3679 | else \ | |
3680 | tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ | |
3681 | t1 = tcg_temp_new_i32(); \ | |
3682 | sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ | |
3683 | if (sh > 0) \ | |
3684 | tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ | |
3685 | else if (sh < 0) \ | |
3686 | tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ | |
3687 | else \ | |
3688 | tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ | |
3689 | tcg_op(t0, t0, t1); \ | |
3690 | bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \ | |
3691 | tcg_gen_andi_i32(t0, t0, bitmask); \ | |
3692 | tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ | |
3693 | tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ | |
3694 | tcg_temp_free_i32(t0); \ | |
3695 | tcg_temp_free_i32(t1); \ | |
3696 | } | |
3697 | ||
3698 | /* crand */ | |
3699 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); | |
3700 | /* crandc */ | |
3701 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); | |
3702 | /* creqv */ | |
3703 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); | |
3704 | /* crnand */ | |
3705 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); | |
3706 | /* crnor */ | |
3707 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); | |
3708 | /* cror */ | |
3709 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); | |
3710 | /* crorc */ | |
3711 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); | |
3712 | /* crxor */ | |
3713 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); | |
3714 | /* mcrf */ | |
3715 | GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER) | |
3716 | { | |
3717 | tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); | |
3718 | } | |
3719 | ||
3720 | /*** System linkage ***/ | |
3721 | /* rfi (supervisor only) */ | |
3722 | GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW) | |
3723 | { | |
3724 | #if defined(CONFIG_USER_ONLY) | |
3725 | GEN_EXCP_PRIVOPC(ctx); | |
3726 | #else | |
3727 | /* Restore CPU state */ | |
3728 | if (unlikely(!ctx->supervisor)) { | |
3729 | GEN_EXCP_PRIVOPC(ctx); | |
3730 | return; | |
3731 | } | |
3732 | gen_op_rfi(); | |
3733 | GEN_SYNC(ctx); | |
3734 | #endif | |
3735 | } | |
3736 | ||
3737 | #if defined(TARGET_PPC64) | |
3738 | GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B) | |
3739 | { | |
3740 | #if defined(CONFIG_USER_ONLY) | |
3741 | GEN_EXCP_PRIVOPC(ctx); | |
3742 | #else | |
3743 | /* Restore CPU state */ | |
3744 | if (unlikely(!ctx->supervisor)) { | |
3745 | GEN_EXCP_PRIVOPC(ctx); | |
3746 | return; | |
3747 | } | |
3748 | gen_op_rfid(); | |
3749 | GEN_SYNC(ctx); | |
3750 | #endif | |
3751 | } | |
3752 | ||
3753 | GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H) | |
3754 | { | |
3755 | #if defined(CONFIG_USER_ONLY) | |
3756 | GEN_EXCP_PRIVOPC(ctx); | |
3757 | #else | |
3758 | /* Restore CPU state */ | |
3759 | if (unlikely(ctx->supervisor <= 1)) { | |
3760 | GEN_EXCP_PRIVOPC(ctx); | |
3761 | return; | |
3762 | } | |
3763 | gen_op_hrfid(); | |
3764 | GEN_SYNC(ctx); | |
3765 | #endif | |
3766 | } | |
3767 | #endif | |
3768 | ||
3769 | /* sc */ | |
3770 | #if defined(CONFIG_USER_ONLY) | |
3771 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER | |
3772 | #else | |
3773 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL | |
3774 | #endif | |
3775 | GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW) | |
3776 | { | |
3777 | uint32_t lev; | |
3778 | ||
3779 | lev = (ctx->opcode >> 5) & 0x7F; | |
3780 | GEN_EXCP(ctx, POWERPC_SYSCALL, lev); | |
3781 | } | |
3782 | ||
3783 | /*** Trap ***/ | |
3784 | /* tw */ | |
3785 | GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW) | |
3786 | { | |
3787 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); | |
3788 | /* Update the nip since this might generate a trap exception */ | |
3789 | gen_update_nip(ctx, ctx->nip); | |
3790 | gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); | |
3791 | tcg_temp_free_i32(t0); | |
3792 | } | |
3793 | ||
3794 | /* twi */ | |
3795 | GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW) | |
3796 | { | |
3797 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); | |
3798 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); | |
3799 | /* Update the nip since this might generate a trap exception */ | |
3800 | gen_update_nip(ctx, ctx->nip); | |
3801 | gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
3802 | tcg_temp_free(t0); | |
3803 | tcg_temp_free_i32(t1); | |
3804 | } | |
3805 | ||
3806 | #if defined(TARGET_PPC64) | |
3807 | /* td */ | |
3808 | GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B) | |
3809 | { | |
3810 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); | |
3811 | /* Update the nip since this might generate a trap exception */ | |
3812 | gen_update_nip(ctx, ctx->nip); | |
3813 | gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); | |
3814 | tcg_temp_free_i32(t0); | |
3815 | } | |
3816 | ||
3817 | /* tdi */ | |
3818 | GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B) | |
3819 | { | |
3820 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); | |
3821 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); | |
3822 | /* Update the nip since this might generate a trap exception */ | |
3823 | gen_update_nip(ctx, ctx->nip); | |
3824 | gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
3825 | tcg_temp_free(t0); | |
3826 | tcg_temp_free_i32(t1); | |
3827 | } | |
3828 | #endif | |
3829 | ||
3830 | /*** Processor control ***/ | |
3831 | /* mcrxr */ | |
3832 | GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC) | |
3833 | { | |
3834 | tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer); | |
3835 | tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA); | |
3836 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA)); | |
3837 | } | |
3838 | ||
3839 | /* mfcr */ | |
3840 | GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC) | |
3841 | { | |
3842 | uint32_t crm, crn; | |
3843 | ||
3844 | if (likely(ctx->opcode & 0x00100000)) { | |
3845 | crm = CRM(ctx->opcode); | |
3846 | if (likely((crm ^ (crm - 1)) == 0)) { | |
3847 | crn = ffs(crm); | |
3848 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); | |
3849 | } | |
3850 | } else { | |
3851 | gen_helper_load_cr(cpu_gpr[rD(ctx->opcode)]); | |
3852 | } | |
3853 | } | |
3854 | ||
3855 | /* mfmsr */ | |
3856 | GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC) | |
3857 | { | |
3858 | #if defined(CONFIG_USER_ONLY) | |
3859 | GEN_EXCP_PRIVREG(ctx); | |
3860 | #else | |
3861 | if (unlikely(!ctx->supervisor)) { | |
3862 | GEN_EXCP_PRIVREG(ctx); | |
3863 | return; | |
3864 | } | |
3865 | gen_op_load_msr(); | |
3866 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); | |
3867 | #endif | |
3868 | } | |
3869 | ||
3870 | #if 1 | |
3871 | #define SPR_NOACCESS ((void *)(-1UL)) | |
3872 | #else | |
3873 | static void spr_noaccess (void *opaque, int sprn) | |
3874 | { | |
3875 | sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); | |
3876 | printf("ERROR: try to access SPR %d !\n", sprn); | |
3877 | } | |
3878 | #define SPR_NOACCESS (&spr_noaccess) | |
3879 | #endif | |
3880 | ||
3881 | /* mfspr */ | |
3882 | static always_inline void gen_op_mfspr (DisasContext *ctx) | |
3883 | { | |
3884 | void (*read_cb)(void *opaque, int sprn); | |
3885 | uint32_t sprn = SPR(ctx->opcode); | |
3886 | ||
3887 | #if !defined(CONFIG_USER_ONLY) | |
3888 | if (ctx->supervisor == 2) | |
3889 | read_cb = ctx->spr_cb[sprn].hea_read; | |
3890 | else if (ctx->supervisor) | |
3891 | read_cb = ctx->spr_cb[sprn].oea_read; | |
3892 | else | |
3893 | #endif | |
3894 | read_cb = ctx->spr_cb[sprn].uea_read; | |
3895 | if (likely(read_cb != NULL)) { | |
3896 | if (likely(read_cb != SPR_NOACCESS)) { | |
3897 | (*read_cb)(ctx, sprn); | |
3898 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); | |
3899 | } else { | |
3900 | /* Privilege exception */ | |
3901 | /* This is a hack to avoid warnings when running Linux: | |
3902 | * this OS breaks the PowerPC virtualisation model, | |
3903 | * allowing userland application to read the PVR | |
3904 | */ | |
3905 | if (sprn != SPR_PVR) { | |
3906 | if (loglevel != 0) { | |
3907 | fprintf(logfile, "Trying to read privileged spr %d %03x at " | |
3908 | ADDRX "\n", sprn, sprn, ctx->nip); | |
3909 | } | |
3910 | printf("Trying to read privileged spr %d %03x at " ADDRX "\n", | |
3911 | sprn, sprn, ctx->nip); | |
3912 | } | |
3913 | GEN_EXCP_PRIVREG(ctx); | |
3914 | } | |
3915 | } else { | |
3916 | /* Not defined */ | |
3917 | if (loglevel != 0) { | |
3918 | fprintf(logfile, "Trying to read invalid spr %d %03x at " | |
3919 | ADDRX "\n", sprn, sprn, ctx->nip); | |
3920 | } | |
3921 | printf("Trying to read invalid spr %d %03x at " ADDRX "\n", | |
3922 | sprn, sprn, ctx->nip); | |
3923 | GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM, | |
3924 | POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR); | |
3925 | } | |
3926 | } | |
3927 | ||
3928 | GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC) | |
3929 | { | |
3930 | gen_op_mfspr(ctx); | |
3931 | } | |
3932 | ||
3933 | /* mftb */ | |
3934 | GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB) | |
3935 | { | |
3936 | gen_op_mfspr(ctx); | |
3937 | } | |
3938 | ||
3939 | /* mtcrf */ | |
3940 | GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC) | |
3941 | { | |
3942 | uint32_t crm, crn; | |
3943 | ||
3944 | crm = CRM(ctx->opcode); | |
3945 | if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) { | |
3946 | TCGv_i32 temp = tcg_temp_new_i32(); | |
3947 | crn = ffs(crm); | |
3948 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); | |
3949 | tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); | |
3950 | tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); | |
3951 | tcg_temp_free_i32(temp); | |
3952 | } else { | |
3953 | TCGv_i32 temp = tcg_const_i32(crm); | |
3954 | gen_helper_store_cr(cpu_gpr[rS(ctx->opcode)], temp); | |
3955 | tcg_temp_free_i32(temp); | |
3956 | } | |
3957 | } | |
3958 | ||
3959 | /* mtmsr */ | |
3960 | #if defined(TARGET_PPC64) | |
3961 | GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B) | |
3962 | { | |
3963 | #if defined(CONFIG_USER_ONLY) | |
3964 | GEN_EXCP_PRIVREG(ctx); | |
3965 | #else | |
3966 | if (unlikely(!ctx->supervisor)) { | |
3967 | GEN_EXCP_PRIVREG(ctx); | |
3968 | return; | |
3969 | } | |
3970 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); | |
3971 | if (ctx->opcode & 0x00010000) { | |
3972 | /* Special form that does not need any synchronisation */ | |
3973 | gen_op_update_riee(); | |
3974 | } else { | |
3975 | /* XXX: we need to update nip before the store | |
3976 | * if we enter power saving mode, we will exit the loop | |
3977 | * directly from ppc_store_msr | |
3978 | */ | |
3979 | gen_update_nip(ctx, ctx->nip); | |
3980 | gen_op_store_msr(); | |
3981 | /* Must stop the translation as machine state (may have) changed */ | |
3982 | /* Note that mtmsr is not always defined as context-synchronizing */ | |
3983 | ctx->exception = POWERPC_EXCP_STOP; | |
3984 | } | |
3985 | #endif | |
3986 | } | |
3987 | #endif | |
3988 | ||
3989 | GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC) | |
3990 | { | |
3991 | #if defined(CONFIG_USER_ONLY) | |
3992 | GEN_EXCP_PRIVREG(ctx); | |
3993 | #else | |
3994 | if (unlikely(!ctx->supervisor)) { | |
3995 | GEN_EXCP_PRIVREG(ctx); | |
3996 | return; | |
3997 | } | |
3998 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); | |
3999 | if (ctx->opcode & 0x00010000) { | |
4000 | /* Special form that does not need any synchronisation */ | |
4001 | gen_op_update_riee(); | |
4002 | } else { | |
4003 | /* XXX: we need to update nip before the store | |
4004 | * if we enter power saving mode, we will exit the loop | |
4005 | * directly from ppc_store_msr | |
4006 | */ | |
4007 | gen_update_nip(ctx, ctx->nip); | |
4008 | #if defined(TARGET_PPC64) | |
4009 | if (!ctx->sf_mode) | |
4010 | gen_op_store_msr_32(); | |
4011 | else | |
4012 | #endif | |
4013 | gen_op_store_msr(); | |
4014 | /* Must stop the translation as machine state (may have) changed */ | |
4015 | /* Note that mtmsrd is not always defined as context-synchronizing */ | |
4016 | ctx->exception = POWERPC_EXCP_STOP; | |
4017 | } | |
4018 | #endif | |
4019 | } | |
4020 | ||
4021 | /* mtspr */ | |
4022 | GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC) | |
4023 | { | |
4024 | void (*write_cb)(void *opaque, int sprn); | |
4025 | uint32_t sprn = SPR(ctx->opcode); | |
4026 | ||
4027 | #if !defined(CONFIG_USER_ONLY) | |
4028 | if (ctx->supervisor == 2) | |
4029 | write_cb = ctx->spr_cb[sprn].hea_write; | |
4030 | else if (ctx->supervisor) | |
4031 | write_cb = ctx->spr_cb[sprn].oea_write; | |
4032 | else | |
4033 | #endif | |
4034 | write_cb = ctx->spr_cb[sprn].uea_write; | |
4035 | if (likely(write_cb != NULL)) { | |
4036 | if (likely(write_cb != SPR_NOACCESS)) { | |
4037 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); | |
4038 | (*write_cb)(ctx, sprn); | |
4039 | } else { | |
4040 | /* Privilege exception */ | |
4041 | if (loglevel != 0) { | |
4042 | fprintf(logfile, "Trying to write privileged spr %d %03x at " | |
4043 | ADDRX "\n", sprn, sprn, ctx->nip); | |
4044 | } | |
4045 | printf("Trying to write privileged spr %d %03x at " ADDRX "\n", | |
4046 | sprn, sprn, ctx->nip); | |
4047 | GEN_EXCP_PRIVREG(ctx); | |
4048 | } | |
4049 | } else { | |
4050 | /* Not defined */ | |
4051 | if (loglevel != 0) { | |
4052 | fprintf(logfile, "Trying to write invalid spr %d %03x at " | |
4053 | ADDRX "\n", sprn, sprn, ctx->nip); | |
4054 | } | |
4055 | printf("Trying to write invalid spr %d %03x at " ADDRX "\n", | |
4056 | sprn, sprn, ctx->nip); | |
4057 | GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM, | |
4058 | POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR); | |
4059 | } | |
4060 | } | |
4061 | ||
4062 | /*** Cache management ***/ | |
4063 | /* dcbf */ | |
4064 | GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE) | |
4065 | { | |
4066 | /* XXX: specification says this is treated as a load by the MMU */ | |
4067 | TCGv t0 = tcg_temp_new(); | |
4068 | gen_set_access_type(ACCESS_CACHE); | |
4069 | gen_addr_reg_index(t0, ctx); | |
4070 | gen_qemu_ld8u(t0, t0, ctx->mem_idx); | |
4071 | tcg_temp_free(t0); | |
4072 | } | |
4073 | ||
4074 | /* dcbi (Supervisor only) */ | |
4075 | GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE) | |
4076 | { | |
4077 | #if defined(CONFIG_USER_ONLY) | |
4078 | GEN_EXCP_PRIVOPC(ctx); | |
4079 | #else | |
4080 | TCGv EA, val; | |
4081 | if (unlikely(!ctx->supervisor)) { | |
4082 | GEN_EXCP_PRIVOPC(ctx); | |
4083 | return; | |
4084 | } | |
4085 | EA = tcg_temp_new(); | |
4086 | gen_set_access_type(ACCESS_CACHE); | |
4087 | gen_addr_reg_index(EA, ctx); | |
4088 | val = tcg_temp_new(); | |
4089 | /* XXX: specification says this should be treated as a store by the MMU */ | |
4090 | gen_qemu_ld8u(val, EA, ctx->mem_idx); | |
4091 | gen_qemu_st8(val, EA, ctx->mem_idx); | |
4092 | tcg_temp_free(val); | |
4093 | tcg_temp_free(EA); | |
4094 | #endif | |
4095 | } | |
4096 | ||
4097 | /* dcdst */ | |
4098 | GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE) | |
4099 | { | |
4100 | /* XXX: specification say this is treated as a load by the MMU */ | |
4101 | TCGv t0 = tcg_temp_new(); | |
4102 | gen_set_access_type(ACCESS_CACHE); | |
4103 | gen_addr_reg_index(t0, ctx); | |
4104 | gen_qemu_ld8u(t0, t0, ctx->mem_idx); | |
4105 | tcg_temp_free(t0); | |
4106 | } | |
4107 | ||
4108 | /* dcbt */ | |
4109 | GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE) | |
4110 | { | |
4111 | /* interpreted as no-op */ | |
4112 | /* XXX: specification say this is treated as a load by the MMU | |
4113 | * but does not generate any exception | |
4114 | */ | |
4115 | } | |
4116 | ||
4117 | /* dcbtst */ | |
4118 | GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE) | |
4119 | { | |
4120 | /* interpreted as no-op */ | |
4121 | /* XXX: specification say this is treated as a load by the MMU | |
4122 | * but does not generate any exception | |
4123 | */ | |
4124 | } | |
4125 | ||
4126 | /* dcbz */ | |
4127 | GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ) | |
4128 | { | |
4129 | TCGv t0 = tcg_temp_new(); | |
4130 | gen_addr_reg_index(t0, ctx); | |
4131 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
4132 | gen_update_nip(ctx, ctx->nip - 4); | |
4133 | gen_helper_dcbz(t0); | |
4134 | tcg_temp_free(t0); | |
4135 | } | |
4136 | ||
4137 | GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT) | |
4138 | { | |
4139 | TCGv t0 = tcg_temp_new(); | |
4140 | gen_addr_reg_index(t0, ctx); | |
4141 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
4142 | gen_update_nip(ctx, ctx->nip - 4); | |
4143 | if (ctx->opcode & 0x00200000) | |
4144 | gen_helper_dcbz(t0); | |
4145 | else | |
4146 | gen_helper_dcbz_970(t0); | |
4147 | tcg_temp_free(t0); | |
4148 | } | |
4149 | ||
4150 | /* icbi */ | |
4151 | GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI) | |
4152 | { | |
4153 | TCGv t0 = tcg_temp_new(); | |
4154 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
4155 | gen_update_nip(ctx, ctx->nip - 4); | |
4156 | gen_addr_reg_index(t0, ctx); | |
4157 | gen_helper_icbi(t0); | |
4158 | tcg_temp_free(t0); | |
4159 | } | |
4160 | ||
4161 | /* Optional: */ | |
4162 | /* dcba */ | |
4163 | GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA) | |
4164 | { | |
4165 | /* interpreted as no-op */ | |
4166 | /* XXX: specification say this is treated as a store by the MMU | |
4167 | * but does not generate any exception | |
4168 | */ | |
4169 | } | |
4170 | ||
4171 | /*** Segment register manipulation ***/ | |
4172 | /* Supervisor only: */ | |
4173 | /* mfsr */ | |
4174 | GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT) | |
4175 | { | |
4176 | #if defined(CONFIG_USER_ONLY) | |
4177 | GEN_EXCP_PRIVREG(ctx); | |
4178 | #else | |
4179 | if (unlikely(!ctx->supervisor)) { | |
4180 | GEN_EXCP_PRIVREG(ctx); | |
4181 | return; | |
4182 | } | |
4183 | tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode)); | |
4184 | gen_op_load_sr(); | |
4185 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); | |
4186 | #endif | |
4187 | } | |
4188 | ||
4189 | /* mfsrin */ | |
4190 | GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT) | |
4191 | { | |
4192 | #if defined(CONFIG_USER_ONLY) | |
4193 | GEN_EXCP_PRIVREG(ctx); | |
4194 | #else | |
4195 | if (unlikely(!ctx->supervisor)) { | |
4196 | GEN_EXCP_PRIVREG(ctx); | |
4197 | return; | |
4198 | } | |
4199 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); | |
4200 | gen_op_srli_T1(28); | |
4201 | gen_op_load_sr(); | |
4202 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); | |
4203 | #endif | |
4204 | } | |
4205 | ||
4206 | /* mtsr */ | |
4207 | GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT) | |
4208 | { | |
4209 | #if defined(CONFIG_USER_ONLY) | |
4210 | GEN_EXCP_PRIVREG(ctx); | |
4211 | #else | |
4212 | if (unlikely(!ctx->supervisor)) { | |
4213 | GEN_EXCP_PRIVREG(ctx); | |
4214 | return; | |
4215 | } | |
4216 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); | |
4217 | tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode)); | |
4218 | gen_op_store_sr(); | |
4219 | #endif | |
4220 | } | |
4221 | ||
4222 | /* mtsrin */ | |
4223 | GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT) | |
4224 | { | |
4225 | #if defined(CONFIG_USER_ONLY) | |
4226 | GEN_EXCP_PRIVREG(ctx); | |
4227 | #else | |
4228 | if (unlikely(!ctx->supervisor)) { | |
4229 | GEN_EXCP_PRIVREG(ctx); | |
4230 | return; | |
4231 | } | |
4232 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); | |
4233 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); | |
4234 | gen_op_srli_T1(28); | |
4235 | gen_op_store_sr(); | |
4236 | #endif | |
4237 | } | |
4238 | ||
4239 | #if defined(TARGET_PPC64) | |
4240 | /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ | |
4241 | /* mfsr */ | |
4242 | GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B) | |
4243 | { | |
4244 | #if defined(CONFIG_USER_ONLY) | |
4245 | GEN_EXCP_PRIVREG(ctx); | |
4246 | #else | |
4247 | if (unlikely(!ctx->supervisor)) { | |
4248 | GEN_EXCP_PRIVREG(ctx); | |
4249 | return; | |
4250 | } | |
4251 | tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode)); | |
4252 | gen_op_load_slb(); | |
4253 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); | |
4254 | #endif | |
4255 | } | |
4256 | ||
4257 | /* mfsrin */ | |
4258 | GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, | |
4259 | PPC_SEGMENT_64B) | |
4260 | { | |
4261 | #if defined(CONFIG_USER_ONLY) | |
4262 | GEN_EXCP_PRIVREG(ctx); | |
4263 | #else | |
4264 | if (unlikely(!ctx->supervisor)) { | |
4265 | GEN_EXCP_PRIVREG(ctx); | |
4266 | return; | |
4267 | } | |
4268 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); | |
4269 | gen_op_srli_T1(28); | |
4270 | gen_op_load_slb(); | |
4271 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); | |
4272 | #endif | |
4273 | } | |
4274 | ||
4275 | /* mtsr */ | |
4276 | GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B) | |
4277 | { | |
4278 | #if defined(CONFIG_USER_ONLY) | |
4279 | GEN_EXCP_PRIVREG(ctx); | |
4280 | #else | |
4281 | if (unlikely(!ctx->supervisor)) { | |
4282 | GEN_EXCP_PRIVREG(ctx); | |
4283 | return; | |
4284 | } | |
4285 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); | |
4286 | tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode)); | |
4287 | gen_op_store_slb(); | |
4288 | #endif | |
4289 | } | |
4290 | ||
4291 | /* mtsrin */ | |
4292 | GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, | |
4293 | PPC_SEGMENT_64B) | |
4294 | { | |
4295 | #if defined(CONFIG_USER_ONLY) | |
4296 | GEN_EXCP_PRIVREG(ctx); | |
4297 | #else | |
4298 | if (unlikely(!ctx->supervisor)) { | |
4299 | GEN_EXCP_PRIVREG(ctx); | |
4300 | return; | |
4301 | } | |
4302 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); | |
4303 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); | |
4304 | gen_op_srli_T1(28); | |
4305 | gen_op_store_slb(); | |
4306 | #endif | |
4307 | } | |
4308 | #endif /* defined(TARGET_PPC64) */ | |
4309 | ||
4310 | /*** Lookaside buffer management ***/ | |
4311 | /* Optional & supervisor only: */ | |
4312 | /* tlbia */ | |
4313 | GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA) | |
4314 | { | |
4315 | #if defined(CONFIG_USER_ONLY) | |
4316 | GEN_EXCP_PRIVOPC(ctx); | |
4317 | #else | |
4318 | if (unlikely(!ctx->supervisor)) { | |
4319 | GEN_EXCP_PRIVOPC(ctx); | |
4320 | return; | |
4321 | } | |
4322 | gen_op_tlbia(); | |
4323 | #endif | |
4324 | } | |
4325 | ||
4326 | /* tlbie */ | |
4327 | GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE) | |
4328 | { | |
4329 | #if defined(CONFIG_USER_ONLY) | |
4330 | GEN_EXCP_PRIVOPC(ctx); | |
4331 | #else | |
4332 | if (unlikely(!ctx->supervisor)) { | |
4333 | GEN_EXCP_PRIVOPC(ctx); | |
4334 | return; | |
4335 | } | |
4336 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); | |
4337 | #if defined(TARGET_PPC64) | |
4338 | if (ctx->sf_mode) | |
4339 | gen_op_tlbie_64(); | |
4340 | else | |
4341 | #endif | |
4342 | gen_op_tlbie(); | |
4343 | #endif | |
4344 | } | |
4345 | ||
4346 | /* tlbsync */ | |
4347 | GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC) | |
4348 | { | |
4349 | #if defined(CONFIG_USER_ONLY) | |
4350 | GEN_EXCP_PRIVOPC(ctx); | |
4351 | #else | |
4352 | if (unlikely(!ctx->supervisor)) { | |
4353 | GEN_EXCP_PRIVOPC(ctx); | |
4354 | return; | |
4355 | } | |
4356 | /* This has no effect: it should ensure that all previous | |
4357 | * tlbie have completed | |
4358 | */ | |
4359 | GEN_STOP(ctx); | |
4360 | #endif | |
4361 | } | |
4362 | ||
4363 | #if defined(TARGET_PPC64) | |
4364 | /* slbia */ | |
4365 | GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI) | |
4366 | { | |
4367 | #if defined(CONFIG_USER_ONLY) | |
4368 | GEN_EXCP_PRIVOPC(ctx); | |
4369 | #else | |
4370 | if (unlikely(!ctx->supervisor)) { | |
4371 | GEN_EXCP_PRIVOPC(ctx); | |
4372 | return; | |
4373 | } | |
4374 | gen_op_slbia(); | |
4375 | #endif | |
4376 | } | |
4377 | ||
4378 | /* slbie */ | |
4379 | GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI) | |
4380 | { | |
4381 | #if defined(CONFIG_USER_ONLY) | |
4382 | GEN_EXCP_PRIVOPC(ctx); | |
4383 | #else | |
4384 | if (unlikely(!ctx->supervisor)) { | |
4385 | GEN_EXCP_PRIVOPC(ctx); | |
4386 | return; | |
4387 | } | |
4388 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); | |
4389 | gen_op_slbie(); | |
4390 | #endif | |
4391 | } | |
4392 | #endif | |
4393 | ||
4394 | /*** External control ***/ | |
4395 | /* Optional: */ | |
4396 | #define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])() | |
4397 | #define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])() | |
4398 | static GenOpFunc *gen_op_eciwx[NB_MEM_FUNCS] = { | |
4399 | GEN_MEM_FUNCS(eciwx), | |
4400 | }; | |
4401 | static GenOpFunc *gen_op_ecowx[NB_MEM_FUNCS] = { | |
4402 | GEN_MEM_FUNCS(ecowx), | |
4403 | }; | |
4404 | ||
4405 | /* eciwx */ | |
4406 | GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN) | |
4407 | { | |
4408 | /* Should check EAR[E] & alignment ! */ | |
4409 | gen_set_access_type(ACCESS_RES); | |
4410 | gen_addr_reg_index(cpu_T[0], ctx); | |
4411 | op_eciwx(); | |
4412 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); | |
4413 | } | |
4414 | ||
4415 | /* ecowx */ | |
4416 | GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN) | |
4417 | { | |
4418 | /* Should check EAR[E] & alignment ! */ | |
4419 | gen_addr_reg_index(cpu_T[0], ctx); | |
4420 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); | |
4421 | op_ecowx(); | |
4422 | } | |
4423 | ||
4424 | /* PowerPC 601 specific instructions */ | |
4425 | /* abs - abs. */ | |
4426 | GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR) | |
4427 | { | |
4428 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); | |
4429 | gen_op_POWER_abs(); | |
4430 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); | |
4431 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4432 | gen_set_Rc0(ctx, cpu_T[0]); | |
4433 | } | |
4434 | ||
4435 | /* abso - abso. */ | |
4436 | GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR) | |
4437 | { | |
4438 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); | |
4439 | gen_op_POWER_abso(); | |
4440 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); | |
4441 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4442 | gen_set_Rc0(ctx, cpu_T[0]); | |
4443 | } | |
4444 | ||
4445 | /* clcs */ | |
4446 | GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR) | |
4447 | { | |
4448 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); | |
4449 | gen_op_POWER_clcs(); | |
4450 | /* Rc=1 sets CR0 to an undefined state */ | |
4451 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); | |
4452 | } | |
4453 | ||
4454 | /* div - div. */ | |
4455 | GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR) | |
4456 | { | |
4457 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); | |
4458 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); | |
4459 | gen_op_POWER_div(); | |
4460 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); | |
4461 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4462 | gen_set_Rc0(ctx, cpu_T[0]); | |
4463 | } | |
4464 | ||
4465 | /* divo - divo. */ | |
4466 | GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR) | |
4467 | { | |
4468 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); | |
4469 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); | |
4470 | gen_op_POWER_divo(); | |
4471 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); | |
4472 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4473 | gen_set_Rc0(ctx, cpu_T[0]); | |
4474 | } | |
4475 | ||
4476 | /* divs - divs. */ | |
4477 | GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR) | |
4478 | { | |
4479 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); | |
4480 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); | |
4481 | gen_op_POWER_divs(); | |
4482 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); | |
4483 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4484 | gen_set_Rc0(ctx, cpu_T[0]); | |
4485 | } | |
4486 | ||
4487 | /* divso - divso. */ | |
4488 | GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR) | |
4489 | { | |
4490 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); | |
4491 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); | |
4492 | gen_op_POWER_divso(); | |
4493 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); | |
4494 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4495 | gen_set_Rc0(ctx, cpu_T[0]); | |
4496 | } | |
4497 | ||
4498 | /* doz - doz. */ | |
4499 | GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR) | |
4500 | { | |
4501 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); | |
4502 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); | |
4503 | gen_op_POWER_doz(); | |
4504 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); | |
4505 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4506 | gen_set_Rc0(ctx, cpu_T[0]); | |
4507 | } | |
4508 | ||
4509 | /* dozo - dozo. */ | |
4510 | GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR) | |
4511 | { | |
4512 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); | |
4513 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); | |
4514 | gen_op_POWER_dozo(); | |
4515 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); | |
4516 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4517 | gen_set_Rc0(ctx, cpu_T[0]); | |
4518 | } | |
4519 | ||
4520 | /* dozi */ | |
4521 | GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR) | |
4522 | { | |
4523 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); | |
4524 | tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode)); | |
4525 | gen_op_POWER_doz(); | |
4526 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); | |
4527 | } | |
4528 | ||
4529 | /* As lscbx load from memory byte after byte, it's always endian safe. | |
4530 | * Original POWER is 32 bits only, define 64 bits ops as 32 bits ones | |
4531 | */ | |
4532 | #define op_POWER_lscbx(start, ra, rb) \ | |
4533 | (*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb) | |
4534 | #define gen_op_POWER_lscbx_64_raw gen_op_POWER_lscbx_raw | |
4535 | #define gen_op_POWER_lscbx_64_user gen_op_POWER_lscbx_user | |
4536 | #define gen_op_POWER_lscbx_64_kernel gen_op_POWER_lscbx_kernel | |
4537 | #define gen_op_POWER_lscbx_64_hypv gen_op_POWER_lscbx_hypv | |
4538 | #define gen_op_POWER_lscbx_le_raw gen_op_POWER_lscbx_raw | |
4539 | #define gen_op_POWER_lscbx_le_user gen_op_POWER_lscbx_user | |
4540 | #define gen_op_POWER_lscbx_le_kernel gen_op_POWER_lscbx_kernel | |
4541 | #define gen_op_POWER_lscbx_le_hypv gen_op_POWER_lscbx_hypv | |
4542 | #define gen_op_POWER_lscbx_le_64_raw gen_op_POWER_lscbx_raw | |
4543 | #define gen_op_POWER_lscbx_le_64_user gen_op_POWER_lscbx_user | |
4544 | #define gen_op_POWER_lscbx_le_64_kernel gen_op_POWER_lscbx_kernel | |
4545 | #define gen_op_POWER_lscbx_le_64_hypv gen_op_POWER_lscbx_hypv | |
4546 | static GenOpFunc3 *gen_op_POWER_lscbx[NB_MEM_FUNCS] = { | |
4547 | GEN_MEM_FUNCS(POWER_lscbx), | |
4548 | }; | |
4549 | ||
4550 | /* lscbx - lscbx. */ | |
4551 | GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR) | |
4552 | { | |
4553 | int ra = rA(ctx->opcode); | |
4554 | int rb = rB(ctx->opcode); | |
4555 | ||
4556 | gen_addr_reg_index(cpu_T[0], ctx); | |
4557 | if (ra == 0) { | |
4558 | ra = rb; | |
4559 | } | |
4560 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
4561 | gen_update_nip(ctx, ctx->nip - 4); | |
4562 | tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F); | |
4563 | tcg_gen_shri_tl(cpu_T[2], cpu_xer, XER_CMP); | |
4564 | tcg_gen_andi_tl(cpu_T[2], cpu_T[2], 0xFF); | |
4565 | op_POWER_lscbx(rD(ctx->opcode), ra, rb); | |
4566 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); | |
4567 | tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]); | |
4568 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4569 | gen_set_Rc0(ctx, cpu_T[0]); | |
4570 | } | |
4571 | ||
4572 | /* maskg - maskg. */ | |
4573 | GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR) | |
4574 | { | |
4575 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); | |
4576 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); | |
4577 | gen_op_POWER_maskg(); | |
4578 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); | |
4579 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4580 | gen_set_Rc0(ctx, cpu_T[0]); | |
4581 | } | |
4582 | ||
4583 | /* maskir - maskir. */ | |
4584 | GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR) | |
4585 | { | |
4586 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); | |
4587 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); | |
4588 | tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]); | |
4589 | gen_op_POWER_maskir(); | |
4590 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); | |
4591 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4592 | gen_set_Rc0(ctx, cpu_T[0]); | |
4593 | } | |
4594 | ||
4595 | /* mul - mul. */ | |
4596 | GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR) | |
4597 | { | |
4598 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); | |
4599 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); | |
4600 | gen_op_POWER_mul(); | |
4601 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); | |
4602 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4603 | gen_set_Rc0(ctx, cpu_T[0]); | |
4604 | } | |
4605 | ||
4606 | /* mulo - mulo. */ | |
4607 | GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR) | |
4608 | { | |
4609 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); | |
4610 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); | |
4611 | gen_op_POWER_mulo(); | |
4612 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); | |
4613 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4614 | gen_set_Rc0(ctx, cpu_T[0]); | |
4615 | } | |
4616 | ||
4617 | /* nabs - nabs. */ | |
4618 | GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR) | |
4619 | { | |
4620 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); | |
4621 | gen_op_POWER_nabs(); | |
4622 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); | |
4623 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4624 | gen_set_Rc0(ctx, cpu_T[0]); | |
4625 | } | |
4626 | ||
4627 | /* nabso - nabso. */ | |
4628 | GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR) | |
4629 | { | |
4630 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); | |
4631 | gen_op_POWER_nabso(); | |
4632 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); | |
4633 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4634 | gen_set_Rc0(ctx, cpu_T[0]); | |
4635 | } | |
4636 | ||
4637 | /* rlmi - rlmi. */ | |
4638 | GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR) | |
4639 | { | |
4640 | uint32_t mb, me; | |
4641 | ||
4642 | mb = MB(ctx->opcode); | |
4643 | me = ME(ctx->opcode); | |
4644 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); | |
4645 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); | |
4646 | tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]); | |
4647 | gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me)); | |
4648 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); | |
4649 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4650 | gen_set_Rc0(ctx, cpu_T[0]); | |
4651 | } | |
4652 | ||
4653 | /* rrib - rrib. */ | |
4654 | GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR) | |
4655 | { | |
4656 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); | |
4657 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); | |
4658 | tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]); | |
4659 | gen_op_POWER_rrib(); | |
4660 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); | |
4661 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4662 | gen_set_Rc0(ctx, cpu_T[0]); | |
4663 | } | |
4664 | ||
4665 | /* sle - sle. */ | |
4666 | GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR) | |
4667 | { | |
4668 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); | |
4669 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); | |
4670 | gen_op_POWER_sle(); | |
4671 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); | |
4672 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4673 | gen_set_Rc0(ctx, cpu_T[0]); | |
4674 | } | |
4675 | ||
4676 | /* sleq - sleq. */ | |
4677 | GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR) | |
4678 | { | |
4679 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); | |
4680 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); | |
4681 | gen_op_POWER_sleq(); | |
4682 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); | |
4683 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4684 | gen_set_Rc0(ctx, cpu_T[0]); | |
4685 | } | |
4686 | ||
4687 | /* sliq - sliq. */ | |
4688 | GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR) | |
4689 | { | |
4690 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); | |
4691 | tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); | |
4692 | gen_op_POWER_sle(); | |
4693 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); | |
4694 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4695 | gen_set_Rc0(ctx, cpu_T[0]); | |
4696 | } | |
4697 | ||
4698 | /* slliq - slliq. */ | |
4699 | GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR) | |
4700 | { | |
4701 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); | |
4702 | tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); | |
4703 | gen_op_POWER_sleq(); | |
4704 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); | |
4705 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4706 | gen_set_Rc0(ctx, cpu_T[0]); | |
4707 | } | |
4708 | ||
4709 | /* sllq - sllq. */ | |
4710 | GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR) | |
4711 | { | |
4712 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); | |
4713 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); | |
4714 | gen_op_POWER_sllq(); | |
4715 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); | |
4716 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4717 | gen_set_Rc0(ctx, cpu_T[0]); | |
4718 | } | |
4719 | ||
4720 | /* slq - slq. */ | |
4721 | GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR) | |
4722 | { | |
4723 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); | |
4724 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); | |
4725 | gen_op_POWER_slq(); | |
4726 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); | |
4727 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4728 | gen_set_Rc0(ctx, cpu_T[0]); | |
4729 | } | |
4730 | ||
4731 | /* sraiq - sraiq. */ | |
4732 | GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR) | |
4733 | { | |
4734 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); | |
4735 | tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); | |
4736 | gen_op_POWER_sraq(); | |
4737 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); | |
4738 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4739 | gen_set_Rc0(ctx, cpu_T[0]); | |
4740 | } | |
4741 | ||
4742 | /* sraq - sraq. */ | |
4743 | GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR) | |
4744 | { | |
4745 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); | |
4746 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); | |
4747 | gen_op_POWER_sraq(); | |
4748 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); | |
4749 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4750 | gen_set_Rc0(ctx, cpu_T[0]); | |
4751 | } | |
4752 | ||
4753 | /* sre - sre. */ | |
4754 | GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR) | |
4755 | { | |
4756 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); | |
4757 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); | |
4758 | gen_op_POWER_sre(); | |
4759 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); | |
4760 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4761 | gen_set_Rc0(ctx, cpu_T[0]); | |
4762 | } | |
4763 | ||
4764 | /* srea - srea. */ | |
4765 | GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR) | |
4766 | { | |
4767 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); | |
4768 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); | |
4769 | gen_op_POWER_srea(); | |
4770 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); | |
4771 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4772 | gen_set_Rc0(ctx, cpu_T[0]); | |
4773 | } | |
4774 | ||
4775 | /* sreq */ | |
4776 | GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR) | |
4777 | { | |
4778 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); | |
4779 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); | |
4780 | gen_op_POWER_sreq(); | |
4781 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); | |
4782 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4783 | gen_set_Rc0(ctx, cpu_T[0]); | |
4784 | } | |
4785 | ||
4786 | /* sriq */ | |
4787 | GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR) | |
4788 | { | |
4789 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); | |
4790 | tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); | |
4791 | gen_op_POWER_srq(); | |
4792 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); | |
4793 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4794 | gen_set_Rc0(ctx, cpu_T[0]); | |
4795 | } | |
4796 | ||
4797 | /* srliq */ | |
4798 | GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR) | |
4799 | { | |
4800 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); | |
4801 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); | |
4802 | tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); | |
4803 | gen_op_POWER_srlq(); | |
4804 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); | |
4805 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4806 | gen_set_Rc0(ctx, cpu_T[0]); | |
4807 | } | |
4808 | ||
4809 | /* srlq */ | |
4810 | GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR) | |
4811 | { | |
4812 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); | |
4813 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); | |
4814 | gen_op_POWER_srlq(); | |
4815 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); | |
4816 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4817 | gen_set_Rc0(ctx, cpu_T[0]); | |
4818 | } | |
4819 | ||
4820 | /* srq */ | |
4821 | GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR) | |
4822 | { | |
4823 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); | |
4824 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); | |
4825 | gen_op_POWER_srq(); | |
4826 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); | |
4827 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4828 | gen_set_Rc0(ctx, cpu_T[0]); | |
4829 | } | |
4830 | ||
4831 | /* PowerPC 602 specific instructions */ | |
4832 | /* dsa */ | |
4833 | GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC) | |
4834 | { | |
4835 | /* XXX: TODO */ | |
4836 | GEN_EXCP_INVAL(ctx); | |
4837 | } | |
4838 | ||
4839 | /* esa */ | |
4840 | GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC) | |
4841 | { | |
4842 | /* XXX: TODO */ | |
4843 | GEN_EXCP_INVAL(ctx); | |
4844 | } | |
4845 | ||
4846 | /* mfrom */ | |
4847 | GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC) | |
4848 | { | |
4849 | #if defined(CONFIG_USER_ONLY) | |
4850 | GEN_EXCP_PRIVOPC(ctx); | |
4851 | #else | |
4852 | if (unlikely(!ctx->supervisor)) { | |
4853 | GEN_EXCP_PRIVOPC(ctx); | |
4854 | return; | |
4855 | } | |
4856 | gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4857 | #endif | |
4858 | } | |
4859 | ||
4860 | /* 602 - 603 - G2 TLB management */ | |
4861 | /* tlbld */ | |
4862 | GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB) | |
4863 | { | |
4864 | #if defined(CONFIG_USER_ONLY) | |
4865 | GEN_EXCP_PRIVOPC(ctx); | |
4866 | #else | |
4867 | if (unlikely(!ctx->supervisor)) { | |
4868 | GEN_EXCP_PRIVOPC(ctx); | |
4869 | return; | |
4870 | } | |
4871 | gen_helper_load_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]); | |
4872 | #endif | |
4873 | } | |
4874 | ||
4875 | /* tlbli */ | |
4876 | GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB) | |
4877 | { | |
4878 | #if defined(CONFIG_USER_ONLY) | |
4879 | GEN_EXCP_PRIVOPC(ctx); | |
4880 | #else | |
4881 | if (unlikely(!ctx->supervisor)) { | |
4882 | GEN_EXCP_PRIVOPC(ctx); | |
4883 | return; | |
4884 | } | |
4885 | gen_helper_load_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]); | |
4886 | #endif | |
4887 | } | |
4888 | ||
4889 | /* 74xx TLB management */ | |
4890 | /* tlbld */ | |
4891 | GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB) | |
4892 | { | |
4893 | #if defined(CONFIG_USER_ONLY) | |
4894 | GEN_EXCP_PRIVOPC(ctx); | |
4895 | #else | |
4896 | if (unlikely(!ctx->supervisor)) { | |
4897 | GEN_EXCP_PRIVOPC(ctx); | |
4898 | return; | |
4899 | } | |
4900 | gen_helper_load_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]); | |
4901 | #endif | |
4902 | } | |
4903 | ||
4904 | /* tlbli */ | |
4905 | GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB) | |
4906 | { | |
4907 | #if defined(CONFIG_USER_ONLY) | |
4908 | GEN_EXCP_PRIVOPC(ctx); | |
4909 | #else | |
4910 | if (unlikely(!ctx->supervisor)) { | |
4911 | GEN_EXCP_PRIVOPC(ctx); | |
4912 | return; | |
4913 | } | |
4914 | gen_helper_load_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]); | |
4915 | #endif | |
4916 | } | |
4917 | ||
4918 | /* POWER instructions not in PowerPC 601 */ | |
4919 | /* clf */ | |
4920 | GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER) | |
4921 | { | |
4922 | /* Cache line flush: implemented as no-op */ | |
4923 | } | |
4924 | ||
4925 | /* cli */ | |
4926 | GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER) | |
4927 | { | |
4928 | /* Cache line invalidate: privileged and treated as no-op */ | |
4929 | #if defined(CONFIG_USER_ONLY) | |
4930 | GEN_EXCP_PRIVOPC(ctx); | |
4931 | #else | |
4932 | if (unlikely(!ctx->supervisor)) { | |
4933 | GEN_EXCP_PRIVOPC(ctx); | |
4934 | return; | |
4935 | } | |
4936 | #endif | |
4937 | } | |
4938 | ||
4939 | /* dclst */ | |
4940 | GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER) | |
4941 | { | |
4942 | /* Data cache line store: treated as no-op */ | |
4943 | } | |
4944 | ||
4945 | GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER) | |
4946 | { | |
4947 | #if defined(CONFIG_USER_ONLY) | |
4948 | GEN_EXCP_PRIVOPC(ctx); | |
4949 | #else | |
4950 | if (unlikely(!ctx->supervisor)) { | |
4951 | GEN_EXCP_PRIVOPC(ctx); | |
4952 | return; | |
4953 | } | |
4954 | int ra = rA(ctx->opcode); | |
4955 | int rd = rD(ctx->opcode); | |
4956 | ||
4957 | gen_addr_reg_index(cpu_T[0], ctx); | |
4958 | gen_op_POWER_mfsri(); | |
4959 | tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[0]); | |
4960 | if (ra != 0 && ra != rd) | |
4961 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[1]); | |
4962 | #endif | |
4963 | } | |
4964 | ||
4965 | GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER) | |
4966 | { | |
4967 | #if defined(CONFIG_USER_ONLY) | |
4968 | GEN_EXCP_PRIVOPC(ctx); | |
4969 | #else | |
4970 | if (unlikely(!ctx->supervisor)) { | |
4971 | GEN_EXCP_PRIVOPC(ctx); | |
4972 | return; | |
4973 | } | |
4974 | gen_addr_reg_index(cpu_T[0], ctx); | |
4975 | gen_op_POWER_rac(); | |
4976 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); | |
4977 | #endif | |
4978 | } | |
4979 | ||
4980 | GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER) | |
4981 | { | |
4982 | #if defined(CONFIG_USER_ONLY) | |
4983 | GEN_EXCP_PRIVOPC(ctx); | |
4984 | #else | |
4985 | if (unlikely(!ctx->supervisor)) { | |
4986 | GEN_EXCP_PRIVOPC(ctx); | |
4987 | return; | |
4988 | } | |
4989 | gen_op_POWER_rfsvc(); | |
4990 | GEN_SYNC(ctx); | |
4991 | #endif | |
4992 | } | |
4993 | ||
4994 | /* svc is not implemented for now */ | |
4995 | ||
4996 | /* POWER2 specific instructions */ | |
4997 | /* Quad manipulation (load/store two floats at a time) */ | |
4998 | ||
4999 | /* lfq */ | |
5000 | GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2) | |
5001 | { | |
5002 | int rd = rD(ctx->opcode); | |
5003 | TCGv t0 = tcg_temp_new(); | |
5004 | gen_addr_imm_index(t0, ctx, 0); | |
5005 | gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx); | |
5006 | tcg_gen_addi_tl(t0, t0, 8); | |
5007 | gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx); | |
5008 | tcg_temp_free(t0); | |
5009 | } | |
5010 | ||
5011 | /* lfqu */ | |
5012 | GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2) | |
5013 | { | |
5014 | int ra = rA(ctx->opcode); | |
5015 | int rd = rD(ctx->opcode); | |
5016 | TCGv t0 = tcg_temp_new(); | |
5017 | TCGv t1 = tcg_temp_new(); | |
5018 | gen_addr_imm_index(t0, ctx, 0); | |
5019 | gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx); | |
5020 | tcg_gen_addi_tl(t1, t0, 8); | |
5021 | gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx); | |
5022 | if (ra != 0) | |
5023 | tcg_gen_mov_tl(cpu_gpr[ra], t0); | |
5024 | tcg_temp_free(t0); | |
5025 | tcg_temp_free(t1); | |
5026 | } | |
5027 | ||
5028 | /* lfqux */ | |
5029 | GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2) | |
5030 | { | |
5031 | int ra = rA(ctx->opcode); | |
5032 | int rd = rD(ctx->opcode); | |
5033 | TCGv t0 = tcg_temp_new(); | |
5034 | TCGv t1 = tcg_temp_new(); | |
5035 | gen_addr_reg_index(t0, ctx); | |
5036 | gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx); | |
5037 | tcg_gen_addi_tl(t1, t0, 8); | |
5038 | gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx); | |
5039 | if (ra != 0) | |
5040 | tcg_gen_mov_tl(cpu_gpr[ra], t0); | |
5041 | tcg_temp_free(t0); | |
5042 | tcg_temp_free(t1); | |
5043 | } | |
5044 | ||
5045 | /* lfqx */ | |
5046 | GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2) | |
5047 | { | |
5048 | int rd = rD(ctx->opcode); | |
5049 | TCGv t0 = tcg_temp_new(); | |
5050 | gen_addr_reg_index(t0, ctx); | |
5051 | gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx); | |
5052 | tcg_gen_addi_tl(t0, t0, 8); | |
5053 | gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx); | |
5054 | tcg_temp_free(t0); | |
5055 | } | |
5056 | ||
5057 | /* stfq */ | |
5058 | GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2) | |
5059 | { | |
5060 | int rd = rD(ctx->opcode); | |
5061 | TCGv t0 = tcg_temp_new(); | |
5062 | gen_addr_imm_index(t0, ctx, 0); | |
5063 | gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx); | |
5064 | tcg_gen_addi_tl(t0, t0, 8); | |
5065 | gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx); | |
5066 | tcg_temp_free(t0); | |
5067 | } | |
5068 | ||
5069 | /* stfqu */ | |
5070 | GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2) | |
5071 | { | |
5072 | int ra = rA(ctx->opcode); | |
5073 | int rd = rD(ctx->opcode); | |
5074 | TCGv t0 = tcg_temp_new(); | |
5075 | TCGv t1 = tcg_temp_new(); | |
5076 | gen_addr_imm_index(t0, ctx, 0); | |
5077 | gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx); | |
5078 | tcg_gen_addi_tl(t1, t0, 8); | |
5079 | gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx); | |
5080 | if (ra != 0) | |
5081 | tcg_gen_mov_tl(cpu_gpr[ra], t0); | |
5082 | tcg_temp_free(t0); | |
5083 | tcg_temp_free(t1); | |
5084 | } | |
5085 | ||
5086 | /* stfqux */ | |
5087 | GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2) | |
5088 | { | |
5089 | int ra = rA(ctx->opcode); | |
5090 | int rd = rD(ctx->opcode); | |
5091 | TCGv t0 = tcg_temp_new(); | |
5092 | TCGv t1 = tcg_temp_new(); | |
5093 | gen_addr_reg_index(t0, ctx); | |
5094 | gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx); | |
5095 | tcg_gen_addi_tl(t1, t0, 8); | |
5096 | gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx); | |
5097 | if (ra != 0) | |
5098 | tcg_gen_mov_tl(cpu_gpr[ra], t0); | |
5099 | tcg_temp_free(t0); | |
5100 | tcg_temp_free(t1); | |
5101 | } | |
5102 | ||
5103 | /* stfqx */ | |
5104 | GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2) | |
5105 | { | |
5106 | int rd = rD(ctx->opcode); | |
5107 | TCGv t0 = tcg_temp_new(); | |
5108 | gen_addr_reg_index(t0, ctx); | |
5109 | gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx); | |
5110 | tcg_gen_addi_tl(t0, t0, 8); | |
5111 | gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx); | |
5112 | tcg_temp_free(t0); | |
5113 | } | |
5114 | ||
5115 | /* BookE specific instructions */ | |
5116 | /* XXX: not implemented on 440 ? */ | |
5117 | GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI) | |
5118 | { | |
5119 | /* XXX: TODO */ | |
5120 | GEN_EXCP_INVAL(ctx); | |
5121 | } | |
5122 | ||
5123 | /* XXX: not implemented on 440 ? */ | |
5124 | GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA) | |
5125 | { | |
5126 | #if defined(CONFIG_USER_ONLY) | |
5127 | GEN_EXCP_PRIVOPC(ctx); | |
5128 | #else | |
5129 | if (unlikely(!ctx->supervisor)) { | |
5130 | GEN_EXCP_PRIVOPC(ctx); | |
5131 | return; | |
5132 | } | |
5133 | gen_addr_reg_index(cpu_T[0], ctx); | |
5134 | /* Use the same micro-ops as for tlbie */ | |
5135 | #if defined(TARGET_PPC64) | |
5136 | if (ctx->sf_mode) | |
5137 | gen_op_tlbie_64(); | |
5138 | else | |
5139 | #endif | |
5140 | gen_op_tlbie(); | |
5141 | #endif | |
5142 | } | |
5143 | ||
5144 | /* All 405 MAC instructions are translated here */ | |
5145 | static always_inline void gen_405_mulladd_insn (DisasContext *ctx, | |
5146 | int opc2, int opc3, | |
5147 | int ra, int rb, int rt, int Rc) | |
5148 | { | |
5149 | TCGv t0, t1; | |
5150 | ||
5151 | t0 = tcg_temp_local_new(); | |
5152 | t1 = tcg_temp_local_new(); | |
5153 | ||
5154 | switch (opc3 & 0x0D) { | |
5155 | case 0x05: | |
5156 | /* macchw - macchw. - macchwo - macchwo. */ | |
5157 | /* macchws - macchws. - macchwso - macchwso. */ | |
5158 | /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ | |
5159 | /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ | |
5160 | /* mulchw - mulchw. */ | |
5161 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); | |
5162 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5163 | tcg_gen_ext16s_tl(t1, t1); | |
5164 | break; | |
5165 | case 0x04: | |
5166 | /* macchwu - macchwu. - macchwuo - macchwuo. */ | |
5167 | /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ | |
5168 | /* mulchwu - mulchwu. */ | |
5169 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); | |
5170 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5171 | tcg_gen_ext16u_tl(t1, t1); | |
5172 | break; | |
5173 | case 0x01: | |
5174 | /* machhw - machhw. - machhwo - machhwo. */ | |
5175 | /* machhws - machhws. - machhwso - machhwso. */ | |
5176 | /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ | |
5177 | /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ | |
5178 | /* mulhhw - mulhhw. */ | |
5179 | tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); | |
5180 | tcg_gen_ext16s_tl(t0, t0); | |
5181 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5182 | tcg_gen_ext16s_tl(t1, t1); | |
5183 | break; | |
5184 | case 0x00: | |
5185 | /* machhwu - machhwu. - machhwuo - machhwuo. */ | |
5186 | /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ | |
5187 | /* mulhhwu - mulhhwu. */ | |
5188 | tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); | |
5189 | tcg_gen_ext16u_tl(t0, t0); | |
5190 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5191 | tcg_gen_ext16u_tl(t1, t1); | |
5192 | break; | |
5193 | case 0x0D: | |
5194 | /* maclhw - maclhw. - maclhwo - maclhwo. */ | |
5195 | /* maclhws - maclhws. - maclhwso - maclhwso. */ | |
5196 | /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ | |
5197 | /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ | |
5198 | /* mullhw - mullhw. */ | |
5199 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); | |
5200 | tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); | |
5201 | break; | |
5202 | case 0x0C: | |
5203 | /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ | |
5204 | /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ | |
5205 | /* mullhwu - mullhwu. */ | |
5206 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); | |
5207 | tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); | |
5208 | break; | |
5209 | } | |
5210 | if (opc2 & 0x04) { | |
5211 | /* (n)multiply-and-accumulate (0x0C / 0x0E) */ | |
5212 | tcg_gen_mul_tl(t1, t0, t1); | |
5213 | if (opc2 & 0x02) { | |
5214 | /* nmultiply-and-accumulate (0x0E) */ | |
5215 | tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); | |
5216 | } else { | |
5217 | /* multiply-and-accumulate (0x0C) */ | |
5218 | tcg_gen_add_tl(t0, cpu_gpr[rt], t1); | |
5219 | } | |
5220 | ||
5221 | if (opc3 & 0x12) { | |
5222 | /* Check overflow and/or saturate */ | |
5223 | int l1 = gen_new_label(); | |
5224 | ||
5225 | if (opc3 & 0x10) { | |
5226 | /* Start with XER OV disabled, the most likely case */ | |
5227 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
5228 | } | |
5229 | if (opc3 & 0x01) { | |
5230 | /* Signed */ | |
5231 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); | |
5232 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); | |
5233 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); | |
5234 | tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); | |
5235 | if (opc3 & 0x02) { | |
5236 | /* Saturate */ | |
5237 | tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); | |
5238 | tcg_gen_xori_tl(t0, t0, 0x7fffffff); | |
5239 | } | |
5240 | } else { | |
5241 | /* Unsigned */ | |
5242 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); | |
5243 | if (opc3 & 0x02) { | |
5244 | /* Saturate */ | |
5245 | tcg_gen_movi_tl(t0, UINT32_MAX); | |
5246 | } | |
5247 | } | |
5248 | if (opc3 & 0x10) { | |
5249 | /* Check overflow */ | |
5250 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
5251 | } | |
5252 | gen_set_label(l1); | |
5253 | tcg_gen_mov_tl(cpu_gpr[rt], t0); | |
5254 | } | |
5255 | } else { | |
5256 | tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); | |
5257 | } | |
5258 | tcg_temp_free(t0); | |
5259 | tcg_temp_free(t1); | |
5260 | if (unlikely(Rc) != 0) { | |
5261 | /* Update Rc0 */ | |
5262 | gen_set_Rc0(ctx, cpu_gpr[rt]); | |
5263 | } | |
5264 | } | |
5265 | ||
5266 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ | |
5267 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \ | |
5268 | { \ | |
5269 | gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ | |
5270 | rD(ctx->opcode), Rc(ctx->opcode)); \ | |
5271 | } | |
5272 | ||
5273 | /* macchw - macchw. */ | |
5274 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05); | |
5275 | /* macchwo - macchwo. */ | |
5276 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); | |
5277 | /* macchws - macchws. */ | |
5278 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07); | |
5279 | /* macchwso - macchwso. */ | |
5280 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); | |
5281 | /* macchwsu - macchwsu. */ | |
5282 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); | |
5283 | /* macchwsuo - macchwsuo. */ | |
5284 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); | |
5285 | /* macchwu - macchwu. */ | |
5286 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); | |
5287 | /* macchwuo - macchwuo. */ | |
5288 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); | |
5289 | /* machhw - machhw. */ | |
5290 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01); | |
5291 | /* machhwo - machhwo. */ | |
5292 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); | |
5293 | /* machhws - machhws. */ | |
5294 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03); | |
5295 | /* machhwso - machhwso. */ | |
5296 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); | |
5297 | /* machhwsu - machhwsu. */ | |
5298 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); | |
5299 | /* machhwsuo - machhwsuo. */ | |
5300 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); | |
5301 | /* machhwu - machhwu. */ | |
5302 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); | |
5303 | /* machhwuo - machhwuo. */ | |
5304 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); | |
5305 | /* maclhw - maclhw. */ | |
5306 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); | |
5307 | /* maclhwo - maclhwo. */ | |
5308 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); | |
5309 | /* maclhws - maclhws. */ | |
5310 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); | |
5311 | /* maclhwso - maclhwso. */ | |
5312 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); | |
5313 | /* maclhwu - maclhwu. */ | |
5314 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); | |
5315 | /* maclhwuo - maclhwuo. */ | |
5316 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); | |
5317 | /* maclhwsu - maclhwsu. */ | |
5318 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); | |
5319 | /* maclhwsuo - maclhwsuo. */ | |
5320 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); | |
5321 | /* nmacchw - nmacchw. */ | |
5322 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); | |
5323 | /* nmacchwo - nmacchwo. */ | |
5324 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); | |
5325 | /* nmacchws - nmacchws. */ | |
5326 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); | |
5327 | /* nmacchwso - nmacchwso. */ | |
5328 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); | |
5329 | /* nmachhw - nmachhw. */ | |
5330 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); | |
5331 | /* nmachhwo - nmachhwo. */ | |
5332 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); | |
5333 | /* nmachhws - nmachhws. */ | |
5334 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); | |
5335 | /* nmachhwso - nmachhwso. */ | |
5336 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); | |
5337 | /* nmaclhw - nmaclhw. */ | |
5338 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); | |
5339 | /* nmaclhwo - nmaclhwo. */ | |
5340 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); | |
5341 | /* nmaclhws - nmaclhws. */ | |
5342 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); | |
5343 | /* nmaclhwso - nmaclhwso. */ | |
5344 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); | |
5345 | ||
5346 | /* mulchw - mulchw. */ | |
5347 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05); | |
5348 | /* mulchwu - mulchwu. */ | |
5349 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); | |
5350 | /* mulhhw - mulhhw. */ | |
5351 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); | |
5352 | /* mulhhwu - mulhhwu. */ | |
5353 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); | |
5354 | /* mullhw - mullhw. */ | |
5355 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); | |
5356 | /* mullhwu - mullhwu. */ | |
5357 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); | |
5358 | ||
5359 | /* mfdcr */ | |
5360 | GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR) | |
5361 | { | |
5362 | #if defined(CONFIG_USER_ONLY) | |
5363 | GEN_EXCP_PRIVREG(ctx); | |
5364 | #else | |
5365 | uint32_t dcrn = SPR(ctx->opcode); | |
5366 | ||
5367 | if (unlikely(!ctx->supervisor)) { | |
5368 | GEN_EXCP_PRIVREG(ctx); | |
5369 | return; | |
5370 | } | |
5371 | tcg_gen_movi_tl(cpu_T[0], dcrn); | |
5372 | gen_op_load_dcr(); | |
5373 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); | |
5374 | #endif | |
5375 | } | |
5376 | ||
5377 | /* mtdcr */ | |
5378 | GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR) | |
5379 | { | |
5380 | #if defined(CONFIG_USER_ONLY) | |
5381 | GEN_EXCP_PRIVREG(ctx); | |
5382 | #else | |
5383 | uint32_t dcrn = SPR(ctx->opcode); | |
5384 | ||
5385 | if (unlikely(!ctx->supervisor)) { | |
5386 | GEN_EXCP_PRIVREG(ctx); | |
5387 | return; | |
5388 | } | |
5389 | tcg_gen_movi_tl(cpu_T[0], dcrn); | |
5390 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); | |
5391 | gen_op_store_dcr(); | |
5392 | #endif | |
5393 | } | |
5394 | ||
5395 | /* mfdcrx */ | |
5396 | /* XXX: not implemented on 440 ? */ | |
5397 | GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX) | |
5398 | { | |
5399 | #if defined(CONFIG_USER_ONLY) | |
5400 | GEN_EXCP_PRIVREG(ctx); | |
5401 | #else | |
5402 | if (unlikely(!ctx->supervisor)) { | |
5403 | GEN_EXCP_PRIVREG(ctx); | |
5404 | return; | |
5405 | } | |
5406 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); | |
5407 | gen_op_load_dcr(); | |
5408 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); | |
5409 | /* Note: Rc update flag set leads to undefined state of Rc0 */ | |
5410 | #endif | |
5411 | } | |
5412 | ||
5413 | /* mtdcrx */ | |
5414 | /* XXX: not implemented on 440 ? */ | |
5415 | GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX) | |
5416 | { | |
5417 | #if defined(CONFIG_USER_ONLY) | |
5418 | GEN_EXCP_PRIVREG(ctx); | |
5419 | #else | |
5420 | if (unlikely(!ctx->supervisor)) { | |
5421 | GEN_EXCP_PRIVREG(ctx); | |
5422 | return; | |
5423 | } | |
5424 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); | |
5425 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); | |
5426 | gen_op_store_dcr(); | |
5427 | /* Note: Rc update flag set leads to undefined state of Rc0 */ | |
5428 | #endif | |
5429 | } | |
5430 | ||
5431 | /* mfdcrux (PPC 460) : user-mode access to DCR */ | |
5432 | GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX) | |
5433 | { | |
5434 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); | |
5435 | gen_op_load_dcr(); | |
5436 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); | |
5437 | /* Note: Rc update flag set leads to undefined state of Rc0 */ | |
5438 | } | |
5439 | ||
5440 | /* mtdcrux (PPC 460) : user-mode access to DCR */ | |
5441 | GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX) | |
5442 | { | |
5443 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); | |
5444 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); | |
5445 | gen_op_store_dcr(); | |
5446 | /* Note: Rc update flag set leads to undefined state of Rc0 */ | |
5447 | } | |
5448 | ||
5449 | /* dccci */ | |
5450 | GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON) | |
5451 | { | |
5452 | #if defined(CONFIG_USER_ONLY) | |
5453 | GEN_EXCP_PRIVOPC(ctx); | |
5454 | #else | |
5455 | if (unlikely(!ctx->supervisor)) { | |
5456 | GEN_EXCP_PRIVOPC(ctx); | |
5457 | return; | |
5458 | } | |
5459 | /* interpreted as no-op */ | |
5460 | #endif | |
5461 | } | |
5462 | ||
5463 | /* dcread */ | |
5464 | GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON) | |
5465 | { | |
5466 | #if defined(CONFIG_USER_ONLY) | |
5467 | GEN_EXCP_PRIVOPC(ctx); | |
5468 | #else | |
5469 | TCGv EA, val; | |
5470 | if (unlikely(!ctx->supervisor)) { | |
5471 | GEN_EXCP_PRIVOPC(ctx); | |
5472 | return; | |
5473 | } | |
5474 | EA = tcg_temp_new(); | |
5475 | gen_set_access_type(ACCESS_CACHE); | |
5476 | gen_addr_reg_index(EA, ctx); | |
5477 | val = tcg_temp_new(); | |
5478 | gen_qemu_ld32u(val, EA, ctx->mem_idx); | |
5479 | tcg_temp_free(val); | |
5480 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); | |
5481 | tcg_temp_free(EA); | |
5482 | #endif | |
5483 | } | |
5484 | ||
5485 | /* icbt */ | |
5486 | GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT) | |
5487 | { | |
5488 | /* interpreted as no-op */ | |
5489 | /* XXX: specification say this is treated as a load by the MMU | |
5490 | * but does not generate any exception | |
5491 | */ | |
5492 | } | |
5493 | ||
5494 | /* iccci */ | |
5495 | GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON) | |
5496 | { | |
5497 | #if defined(CONFIG_USER_ONLY) | |
5498 | GEN_EXCP_PRIVOPC(ctx); | |
5499 | #else | |
5500 | if (unlikely(!ctx->supervisor)) { | |
5501 | GEN_EXCP_PRIVOPC(ctx); | |
5502 | return; | |
5503 | } | |
5504 | /* interpreted as no-op */ | |
5505 | #endif | |
5506 | } | |
5507 | ||
5508 | /* icread */ | |
5509 | GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON) | |
5510 | { | |
5511 | #if defined(CONFIG_USER_ONLY) | |
5512 | GEN_EXCP_PRIVOPC(ctx); | |
5513 | #else | |
5514 | if (unlikely(!ctx->supervisor)) { | |
5515 | GEN_EXCP_PRIVOPC(ctx); | |
5516 | return; | |
5517 | } | |
5518 | /* interpreted as no-op */ | |
5519 | #endif | |
5520 | } | |
5521 | ||
5522 | /* rfci (supervisor only) */ | |
5523 | GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP) | |
5524 | { | |
5525 | #if defined(CONFIG_USER_ONLY) | |
5526 | GEN_EXCP_PRIVOPC(ctx); | |
5527 | #else | |
5528 | if (unlikely(!ctx->supervisor)) { | |
5529 | GEN_EXCP_PRIVOPC(ctx); | |
5530 | return; | |
5531 | } | |
5532 | /* Restore CPU state */ | |
5533 | gen_op_40x_rfci(); | |
5534 | GEN_SYNC(ctx); | |
5535 | #endif | |
5536 | } | |
5537 | ||
5538 | GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE) | |
5539 | { | |
5540 | #if defined(CONFIG_USER_ONLY) | |
5541 | GEN_EXCP_PRIVOPC(ctx); | |
5542 | #else | |
5543 | if (unlikely(!ctx->supervisor)) { | |
5544 | GEN_EXCP_PRIVOPC(ctx); | |
5545 | return; | |
5546 | } | |
5547 | /* Restore CPU state */ | |
5548 | gen_op_rfci(); | |
5549 | GEN_SYNC(ctx); | |
5550 | #endif | |
5551 | } | |
5552 | ||
5553 | /* BookE specific */ | |
5554 | /* XXX: not implemented on 440 ? */ | |
5555 | GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI) | |
5556 | { | |
5557 | #if defined(CONFIG_USER_ONLY) | |
5558 | GEN_EXCP_PRIVOPC(ctx); | |
5559 | #else | |
5560 | if (unlikely(!ctx->supervisor)) { | |
5561 | GEN_EXCP_PRIVOPC(ctx); | |
5562 | return; | |
5563 | } | |
5564 | /* Restore CPU state */ | |
5565 | gen_op_rfdi(); | |
5566 | GEN_SYNC(ctx); | |
5567 | #endif | |
5568 | } | |
5569 | ||
5570 | /* XXX: not implemented on 440 ? */ | |
5571 | GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI) | |
5572 | { | |
5573 | #if defined(CONFIG_USER_ONLY) | |
5574 | GEN_EXCP_PRIVOPC(ctx); | |
5575 | #else | |
5576 | if (unlikely(!ctx->supervisor)) { | |
5577 | GEN_EXCP_PRIVOPC(ctx); | |
5578 | return; | |
5579 | } | |
5580 | /* Restore CPU state */ | |
5581 | gen_op_rfmci(); | |
5582 | GEN_SYNC(ctx); | |
5583 | #endif | |
5584 | } | |
5585 | ||
5586 | /* TLB management - PowerPC 405 implementation */ | |
5587 | /* tlbre */ | |
5588 | GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB) | |
5589 | { | |
5590 | #if defined(CONFIG_USER_ONLY) | |
5591 | GEN_EXCP_PRIVOPC(ctx); | |
5592 | #else | |
5593 | if (unlikely(!ctx->supervisor)) { | |
5594 | GEN_EXCP_PRIVOPC(ctx); | |
5595 | return; | |
5596 | } | |
5597 | switch (rB(ctx->opcode)) { | |
5598 | case 0: | |
5599 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); | |
5600 | gen_op_4xx_tlbre_hi(); | |
5601 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); | |
5602 | break; | |
5603 | case 1: | |
5604 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); | |
5605 | gen_op_4xx_tlbre_lo(); | |
5606 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); | |
5607 | break; | |
5608 | default: | |
5609 | GEN_EXCP_INVAL(ctx); | |
5610 | break; | |
5611 | } | |
5612 | #endif | |
5613 | } | |
5614 | ||
5615 | /* tlbsx - tlbsx. */ | |
5616 | GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB) | |
5617 | { | |
5618 | #if defined(CONFIG_USER_ONLY) | |
5619 | GEN_EXCP_PRIVOPC(ctx); | |
5620 | #else | |
5621 | if (unlikely(!ctx->supervisor)) { | |
5622 | GEN_EXCP_PRIVOPC(ctx); | |
5623 | return; | |
5624 | } | |
5625 | gen_addr_reg_index(cpu_T[0], ctx); | |
5626 | gen_op_4xx_tlbsx(); | |
5627 | if (Rc(ctx->opcode)) | |
5628 | gen_op_4xx_tlbsx_check(); | |
5629 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); | |
5630 | #endif | |
5631 | } | |
5632 | ||
5633 | /* tlbwe */ | |
5634 | GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB) | |
5635 | { | |
5636 | #if defined(CONFIG_USER_ONLY) | |
5637 | GEN_EXCP_PRIVOPC(ctx); | |
5638 | #else | |
5639 | if (unlikely(!ctx->supervisor)) { | |
5640 | GEN_EXCP_PRIVOPC(ctx); | |
5641 | return; | |
5642 | } | |
5643 | switch (rB(ctx->opcode)) { | |
5644 | case 0: | |
5645 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); | |
5646 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); | |
5647 | gen_op_4xx_tlbwe_hi(); | |
5648 | break; | |
5649 | case 1: | |
5650 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); | |
5651 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); | |
5652 | gen_op_4xx_tlbwe_lo(); | |
5653 | break; | |
5654 | default: | |
5655 | GEN_EXCP_INVAL(ctx); | |
5656 | break; | |
5657 | } | |
5658 | #endif | |
5659 | } | |
5660 | ||
5661 | /* TLB management - PowerPC 440 implementation */ | |
5662 | /* tlbre */ | |
5663 | GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE) | |
5664 | { | |
5665 | #if defined(CONFIG_USER_ONLY) | |
5666 | GEN_EXCP_PRIVOPC(ctx); | |
5667 | #else | |
5668 | if (unlikely(!ctx->supervisor)) { | |
5669 | GEN_EXCP_PRIVOPC(ctx); | |
5670 | return; | |
5671 | } | |
5672 | switch (rB(ctx->opcode)) { | |
5673 | case 0: | |
5674 | case 1: | |
5675 | case 2: | |
5676 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); | |
5677 | gen_op_440_tlbre(rB(ctx->opcode)); | |
5678 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); | |
5679 | break; | |
5680 | default: | |
5681 | GEN_EXCP_INVAL(ctx); | |
5682 | break; | |
5683 | } | |
5684 | #endif | |
5685 | } | |
5686 | ||
5687 | /* tlbsx - tlbsx. */ | |
5688 | GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE) | |
5689 | { | |
5690 | #if defined(CONFIG_USER_ONLY) | |
5691 | GEN_EXCP_PRIVOPC(ctx); | |
5692 | #else | |
5693 | if (unlikely(!ctx->supervisor)) { | |
5694 | GEN_EXCP_PRIVOPC(ctx); | |
5695 | return; | |
5696 | } | |
5697 | gen_addr_reg_index(cpu_T[0], ctx); | |
5698 | gen_op_440_tlbsx(); | |
5699 | if (Rc(ctx->opcode)) | |
5700 | gen_op_4xx_tlbsx_check(); | |
5701 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); | |
5702 | #endif | |
5703 | } | |
5704 | ||
5705 | /* tlbwe */ | |
5706 | GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE) | |
5707 | { | |
5708 | #if defined(CONFIG_USER_ONLY) | |
5709 | GEN_EXCP_PRIVOPC(ctx); | |
5710 | #else | |
5711 | if (unlikely(!ctx->supervisor)) { | |
5712 | GEN_EXCP_PRIVOPC(ctx); | |
5713 | return; | |
5714 | } | |
5715 | switch (rB(ctx->opcode)) { | |
5716 | case 0: | |
5717 | case 1: | |
5718 | case 2: | |
5719 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); | |
5720 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); | |
5721 | gen_op_440_tlbwe(rB(ctx->opcode)); | |
5722 | break; | |
5723 | default: | |
5724 | GEN_EXCP_INVAL(ctx); | |
5725 | break; | |
5726 | } | |
5727 | #endif | |
5728 | } | |
5729 | ||
5730 | /* wrtee */ | |
5731 | GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE) | |
5732 | { | |
5733 | #if defined(CONFIG_USER_ONLY) | |
5734 | GEN_EXCP_PRIVOPC(ctx); | |
5735 | #else | |
5736 | if (unlikely(!ctx->supervisor)) { | |
5737 | GEN_EXCP_PRIVOPC(ctx); | |
5738 | return; | |
5739 | } | |
5740 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rD(ctx->opcode)]); | |
5741 | gen_op_wrte(); | |
5742 | /* Stop translation to have a chance to raise an exception | |
5743 | * if we just set msr_ee to 1 | |
5744 | */ | |
5745 | GEN_STOP(ctx); | |
5746 | #endif | |
5747 | } | |
5748 | ||
5749 | /* wrteei */ | |
5750 | GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE) | |
5751 | { | |
5752 | #if defined(CONFIG_USER_ONLY) | |
5753 | GEN_EXCP_PRIVOPC(ctx); | |
5754 | #else | |
5755 | if (unlikely(!ctx->supervisor)) { | |
5756 | GEN_EXCP_PRIVOPC(ctx); | |
5757 | return; | |
5758 | } | |
5759 | tcg_gen_movi_tl(cpu_T[0], ctx->opcode & 0x00010000); | |
5760 | gen_op_wrte(); | |
5761 | /* Stop translation to have a chance to raise an exception | |
5762 | * if we just set msr_ee to 1 | |
5763 | */ | |
5764 | GEN_STOP(ctx); | |
5765 | #endif | |
5766 | } | |
5767 | ||
5768 | /* PowerPC 440 specific instructions */ | |
5769 | /* dlmzb */ | |
5770 | GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC) | |
5771 | { | |
5772 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); | |
5773 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); | |
5774 | gen_op_440_dlmzb(); | |
5775 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); | |
5776 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); | |
5777 | tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]); | |
5778 | if (Rc(ctx->opcode)) { | |
5779 | gen_op_440_dlmzb_update_Rc(); | |
5780 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_T[0]); | |
5781 | tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 0xf); | |
5782 | } | |
5783 | } | |
5784 | ||
5785 | /* mbar replaces eieio on 440 */ | |
5786 | GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE) | |
5787 | { | |
5788 | /* interpreted as no-op */ | |
5789 | } | |
5790 | ||
5791 | /* msync replaces sync on 440 */ | |
5792 | GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE) | |
5793 | { | |
5794 | /* interpreted as no-op */ | |
5795 | } | |
5796 | ||
5797 | /* icbt */ | |
5798 | GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE) | |
5799 | { | |
5800 | /* interpreted as no-op */ | |
5801 | /* XXX: specification say this is treated as a load by the MMU | |
5802 | * but does not generate any exception | |
5803 | */ | |
5804 | } | |
5805 | ||
5806 | /*** Altivec vector extension ***/ | |
5807 | /* Altivec registers moves */ | |
5808 | ||
5809 | #define GEN_VR_LDX(name, opc2, opc3) \ | |
5810 | GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \ | |
5811 | { \ | |
5812 | TCGv EA; \ | |
5813 | if (unlikely(!ctx->altivec_enabled)) { \ | |
5814 | GEN_EXCP_NO_VR(ctx); \ | |
5815 | return; \ | |
5816 | } \ | |
5817 | EA = tcg_temp_new(); \ | |
5818 | gen_addr_reg_index(EA, ctx); \ | |
5819 | tcg_gen_andi_tl(EA, EA, ~0xf); \ | |
5820 | if (ctx->mem_idx & 1) { \ | |
5821 | gen_qemu_ld64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \ | |
5822 | tcg_gen_addi_tl(EA, EA, 8); \ | |
5823 | gen_qemu_ld64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \ | |
5824 | } else { \ | |
5825 | gen_qemu_ld64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \ | |
5826 | tcg_gen_addi_tl(EA, EA, 8); \ | |
5827 | gen_qemu_ld64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \ | |
5828 | } \ | |
5829 | tcg_temp_free(EA); \ | |
5830 | } | |
5831 | ||
5832 | #define GEN_VR_STX(name, opc2, opc3) \ | |
5833 | GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \ | |
5834 | { \ | |
5835 | TCGv EA; \ | |
5836 | if (unlikely(!ctx->altivec_enabled)) { \ | |
5837 | GEN_EXCP_NO_VR(ctx); \ | |
5838 | return; \ | |
5839 | } \ | |
5840 | EA = tcg_temp_new(); \ | |
5841 | gen_addr_reg_index(EA, ctx); \ | |
5842 | tcg_gen_andi_tl(EA, EA, ~0xf); \ | |
5843 | if (ctx->mem_idx & 1) { \ | |
5844 | gen_qemu_st64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \ | |
5845 | tcg_gen_addi_tl(EA, EA, 8); \ | |
5846 | gen_qemu_st64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \ | |
5847 | } else { \ | |
5848 | gen_qemu_st64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \ | |
5849 | tcg_gen_addi_tl(EA, EA, 8); \ | |
5850 | gen_qemu_st64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \ | |
5851 | } \ | |
5852 | tcg_temp_free(EA); \ | |
5853 | } | |
5854 | ||
5855 | GEN_VR_LDX(lvx, 0x07, 0x03); | |
5856 | /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */ | |
5857 | GEN_VR_LDX(lvxl, 0x07, 0x0B); | |
5858 | ||
5859 | GEN_VR_STX(svx, 0x07, 0x07); | |
5860 | /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */ | |
5861 | GEN_VR_STX(svxl, 0x07, 0x0F); | |
5862 | ||
5863 | /*** SPE extension ***/ | |
5864 | /* Register moves */ | |
5865 | ||
5866 | static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) { | |
5867 | #if defined(TARGET_PPC64) | |
5868 | tcg_gen_mov_i64(t, cpu_gpr[reg]); | |
5869 | #else | |
5870 | tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]); | |
5871 | #endif | |
5872 | } | |
5873 | ||
5874 | static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) { | |
5875 | #if defined(TARGET_PPC64) | |
5876 | tcg_gen_mov_i64(cpu_gpr[reg], t); | |
5877 | #else | |
5878 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
5879 | tcg_gen_trunc_i64_i32(cpu_gpr[reg], t); | |
5880 | tcg_gen_shri_i64(tmp, t, 32); | |
5881 | tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp); | |
5882 | tcg_temp_free_i64(tmp); | |
5883 | #endif | |
5884 | } | |
5885 | ||
5886 | #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \ | |
5887 | GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \ | |
5888 | { \ | |
5889 | if (Rc(ctx->opcode)) \ | |
5890 | gen_##name1(ctx); \ | |
5891 | else \ | |
5892 | gen_##name0(ctx); \ | |
5893 | } | |
5894 | ||
5895 | /* Handler for undefined SPE opcodes */ | |
5896 | static always_inline void gen_speundef (DisasContext *ctx) | |
5897 | { | |
5898 | GEN_EXCP_INVAL(ctx); | |
5899 | } | |
5900 | ||
5901 | /* SPE logic */ | |
5902 | #if defined(TARGET_PPC64) | |
5903 | #define GEN_SPEOP_LOGIC2(name, tcg_op) \ | |
5904 | static always_inline void gen_##name (DisasContext *ctx) \ | |
5905 | { \ | |
5906 | if (unlikely(!ctx->spe_enabled)) { \ | |
5907 | GEN_EXCP_NO_AP(ctx); \ | |
5908 | return; \ | |
5909 | } \ | |
5910 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ | |
5911 | cpu_gpr[rB(ctx->opcode)]); \ | |
5912 | } | |
5913 | #else | |
5914 | #define GEN_SPEOP_LOGIC2(name, tcg_op) \ | |
5915 | static always_inline void gen_##name (DisasContext *ctx) \ | |
5916 | { \ | |
5917 | if (unlikely(!ctx->spe_enabled)) { \ | |
5918 | GEN_EXCP_NO_AP(ctx); \ | |
5919 | return; \ | |
5920 | } \ | |
5921 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ | |
5922 | cpu_gpr[rB(ctx->opcode)]); \ | |
5923 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ | |
5924 | cpu_gprh[rB(ctx->opcode)]); \ | |
5925 | } | |
5926 | #endif | |
5927 | ||
5928 | GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl); | |
5929 | GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl); | |
5930 | GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl); | |
5931 | GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl); | |
5932 | GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl); | |
5933 | GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl); | |
5934 | GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl); | |
5935 | GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl); | |
5936 | ||
5937 | /* SPE logic immediate */ | |
5938 | #if defined(TARGET_PPC64) | |
5939 | #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \ | |
5940 | static always_inline void gen_##name (DisasContext *ctx) \ | |
5941 | { \ | |
5942 | if (unlikely(!ctx->spe_enabled)) { \ | |
5943 | GEN_EXCP_NO_AP(ctx); \ | |
5944 | return; \ | |
5945 | } \ | |
5946 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ | |
5947 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
5948 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
5949 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
5950 | tcg_opi(t0, t0, rB(ctx->opcode)); \ | |
5951 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \ | |
5952 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
5953 | tcg_temp_free_i64(t2); \ | |
5954 | tcg_opi(t1, t1, rB(ctx->opcode)); \ | |
5955 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ | |
5956 | tcg_temp_free_i32(t0); \ | |
5957 | tcg_temp_free_i32(t1); \ | |
5958 | } | |
5959 | #else | |
5960 | #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \ | |
5961 | static always_inline void gen_##name (DisasContext *ctx) \ | |
5962 | { \ | |
5963 | if (unlikely(!ctx->spe_enabled)) { \ | |
5964 | GEN_EXCP_NO_AP(ctx); \ | |
5965 | return; \ | |
5966 | } \ | |
5967 | tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ | |
5968 | rB(ctx->opcode)); \ | |
5969 | tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ | |
5970 | rB(ctx->opcode)); \ | |
5971 | } | |
5972 | #endif | |
5973 | GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32); | |
5974 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32); | |
5975 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32); | |
5976 | GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32); | |
5977 | ||
5978 | /* SPE arithmetic */ | |
5979 | #if defined(TARGET_PPC64) | |
5980 | #define GEN_SPEOP_ARITH1(name, tcg_op) \ | |
5981 | static always_inline void gen_##name (DisasContext *ctx) \ | |
5982 | { \ | |
5983 | if (unlikely(!ctx->spe_enabled)) { \ | |
5984 | GEN_EXCP_NO_AP(ctx); \ | |
5985 | return; \ | |
5986 | } \ | |
5987 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ | |
5988 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
5989 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
5990 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
5991 | tcg_op(t0, t0); \ | |
5992 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \ | |
5993 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
5994 | tcg_temp_free_i64(t2); \ | |
5995 | tcg_op(t1, t1); \ | |
5996 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ | |
5997 | tcg_temp_free_i32(t0); \ | |
5998 | tcg_temp_free_i32(t1); \ | |
5999 | } | |
6000 | #else | |
6001 | #define GEN_SPEOP_ARITH1(name, tcg_op) \ | |
6002 | static always_inline void gen_##name (DisasContext *ctx) \ | |
6003 | { \ | |
6004 | if (unlikely(!ctx->spe_enabled)) { \ | |
6005 | GEN_EXCP_NO_AP(ctx); \ | |
6006 | return; \ | |
6007 | } \ | |
6008 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \ | |
6009 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \ | |
6010 | } | |
6011 | #endif | |
6012 | ||
6013 | static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1) | |
6014 | { | |
6015 | int l1 = gen_new_label(); | |
6016 | int l2 = gen_new_label(); | |
6017 | ||
6018 | tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1); | |
6019 | tcg_gen_neg_i32(ret, arg1); | |
6020 | tcg_gen_br(l2); | |
6021 | gen_set_label(l1); | |
6022 | tcg_gen_mov_i32(ret, arg1); | |
6023 | gen_set_label(l2); | |
6024 | } | |
6025 | GEN_SPEOP_ARITH1(evabs, gen_op_evabs); | |
6026 | GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32); | |
6027 | GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32); | |
6028 | GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32); | |
6029 | static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1) | |
6030 | { | |
6031 | tcg_gen_addi_i32(ret, arg1, 0x8000); | |
6032 | tcg_gen_ext16u_i32(ret, ret); | |
6033 | } | |
6034 | GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw); | |
6035 | GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32); | |
6036 | GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32); | |
6037 | ||
6038 | #if defined(TARGET_PPC64) | |
6039 | #define GEN_SPEOP_ARITH2(name, tcg_op) \ | |
6040 | static always_inline void gen_##name (DisasContext *ctx) \ | |
6041 | { \ | |
6042 | if (unlikely(!ctx->spe_enabled)) { \ | |
6043 | GEN_EXCP_NO_AP(ctx); \ | |
6044 | return; \ | |
6045 | } \ | |
6046 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ | |
6047 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
6048 | TCGv_i32 t2 = tcg_temp_local_new_i32(); \ | |
6049 | TCGv_i64 t3 = tcg_temp_local_new(TCG_TYPE_I64); \ | |
6050 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
6051 | tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \ | |
6052 | tcg_op(t0, t0, t2); \ | |
6053 | tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \ | |
6054 | tcg_gen_trunc_i64_i32(t1, t3); \ | |
6055 | tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \ | |
6056 | tcg_gen_trunc_i64_i32(t2, t3); \ | |
6057 | tcg_temp_free_i64(t3); \ | |
6058 | tcg_op(t1, t1, t2); \ | |
6059 | tcg_temp_free_i32(t2); \ | |
6060 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ | |
6061 | tcg_temp_free_i32(t0); \ | |
6062 | tcg_temp_free_i32(t1); \ | |
6063 | } | |
6064 | #else | |
6065 | #define GEN_SPEOP_ARITH2(name, tcg_op) \ | |
6066 | static always_inline void gen_##name (DisasContext *ctx) \ | |
6067 | { \ | |
6068 | if (unlikely(!ctx->spe_enabled)) { \ | |
6069 | GEN_EXCP_NO_AP(ctx); \ | |
6070 | return; \ | |
6071 | } \ | |
6072 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ | |
6073 | cpu_gpr[rB(ctx->opcode)]); \ | |
6074 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ | |
6075 | cpu_gprh[rB(ctx->opcode)]); \ | |
6076 | } | |
6077 | #endif | |
6078 | ||
6079 | static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) | |
6080 | { | |
6081 | TCGv_i32 t0; | |
6082 | int l1, l2; | |
6083 | ||
6084 | l1 = gen_new_label(); | |
6085 | l2 = gen_new_label(); | |
6086 | t0 = tcg_temp_local_new_i32(); | |
6087 | /* No error here: 6 bits are used */ | |
6088 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
6089 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
6090 | tcg_gen_shr_i32(ret, arg1, t0); | |
6091 | tcg_gen_br(l2); | |
6092 | gen_set_label(l1); | |
6093 | tcg_gen_movi_i32(ret, 0); | |
6094 | tcg_gen_br(l2); | |
6095 | tcg_temp_free_i32(t0); | |
6096 | } | |
6097 | GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu); | |
6098 | static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) | |
6099 | { | |
6100 | TCGv_i32 t0; | |
6101 | int l1, l2; | |
6102 | ||
6103 | l1 = gen_new_label(); | |
6104 | l2 = gen_new_label(); | |
6105 | t0 = tcg_temp_local_new_i32(); | |
6106 | /* No error here: 6 bits are used */ | |
6107 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
6108 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
6109 | tcg_gen_sar_i32(ret, arg1, t0); | |
6110 | tcg_gen_br(l2); | |
6111 | gen_set_label(l1); | |
6112 | tcg_gen_movi_i32(ret, 0); | |
6113 | tcg_gen_br(l2); | |
6114 | tcg_temp_free_i32(t0); | |
6115 | } | |
6116 | GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws); | |
6117 | static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) | |
6118 | { | |
6119 | TCGv_i32 t0; | |
6120 | int l1, l2; | |
6121 | ||
6122 | l1 = gen_new_label(); | |
6123 | l2 = gen_new_label(); | |
6124 | t0 = tcg_temp_local_new_i32(); | |
6125 | /* No error here: 6 bits are used */ | |
6126 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
6127 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
6128 | tcg_gen_shl_i32(ret, arg1, t0); | |
6129 | tcg_gen_br(l2); | |
6130 | gen_set_label(l1); | |
6131 | tcg_gen_movi_i32(ret, 0); | |
6132 | tcg_gen_br(l2); | |
6133 | tcg_temp_free_i32(t0); | |
6134 | } | |
6135 | GEN_SPEOP_ARITH2(evslw, gen_op_evslw); | |
6136 | static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) | |
6137 | { | |
6138 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
6139 | tcg_gen_andi_i32(t0, arg2, 0x1F); | |
6140 | tcg_gen_rotl_i32(ret, arg1, t0); | |
6141 | tcg_temp_free_i32(t0); | |
6142 | } | |
6143 | GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw); | |
6144 | static always_inline void gen_evmergehi (DisasContext *ctx) | |
6145 | { | |
6146 | if (unlikely(!ctx->spe_enabled)) { | |
6147 | GEN_EXCP_NO_AP(ctx); | |
6148 | return; | |
6149 | } | |
6150 | #if defined(TARGET_PPC64) | |
6151 | TCGv t0 = tcg_temp_new(); | |
6152 | TCGv t1 = tcg_temp_new(); | |
6153 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32); | |
6154 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL); | |
6155 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
6156 | tcg_temp_free(t0); | |
6157 | tcg_temp_free(t1); | |
6158 | #else | |
6159 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
6160 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
6161 | #endif | |
6162 | } | |
6163 | GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32); | |
6164 | static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) | |
6165 | { | |
6166 | tcg_gen_sub_i32(ret, arg2, arg1); | |
6167 | } | |
6168 | GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf); | |
6169 | ||
6170 | /* SPE arithmetic immediate */ | |
6171 | #if defined(TARGET_PPC64) | |
6172 | #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \ | |
6173 | static always_inline void gen_##name (DisasContext *ctx) \ | |
6174 | { \ | |
6175 | if (unlikely(!ctx->spe_enabled)) { \ | |
6176 | GEN_EXCP_NO_AP(ctx); \ | |
6177 | return; \ | |
6178 | } \ | |
6179 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ | |
6180 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
6181 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
6182 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ | |
6183 | tcg_op(t0, t0, rA(ctx->opcode)); \ | |
6184 | tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \ | |
6185 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
6186 | tcg_temp_free_i64(t2); \ | |
6187 | tcg_op(t1, t1, rA(ctx->opcode)); \ | |
6188 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ | |
6189 | tcg_temp_free_i32(t0); \ | |
6190 | tcg_temp_free_i32(t1); \ | |
6191 | } | |
6192 | #else | |
6193 | #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \ | |
6194 | static always_inline void gen_##name (DisasContext *ctx) \ | |
6195 | { \ | |
6196 | if (unlikely(!ctx->spe_enabled)) { \ | |
6197 | GEN_EXCP_NO_AP(ctx); \ | |
6198 | return; \ | |
6199 | } \ | |
6200 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
6201 | rA(ctx->opcode)); \ | |
6202 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \ | |
6203 | rA(ctx->opcode)); \ | |
6204 | } | |
6205 | #endif | |
6206 | GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32); | |
6207 | GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32); | |
6208 | ||
6209 | /* SPE comparison */ | |
6210 | #if defined(TARGET_PPC64) | |
6211 | #define GEN_SPEOP_COMP(name, tcg_cond) \ | |
6212 | static always_inline void gen_##name (DisasContext *ctx) \ | |
6213 | { \ | |
6214 | if (unlikely(!ctx->spe_enabled)) { \ | |
6215 | GEN_EXCP_NO_AP(ctx); \ | |
6216 | return; \ | |
6217 | } \ | |
6218 | int l1 = gen_new_label(); \ | |
6219 | int l2 = gen_new_label(); \ | |
6220 | int l3 = gen_new_label(); \ | |
6221 | int l4 = gen_new_label(); \ | |
6222 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ | |
6223 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
6224 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
6225 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
6226 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
6227 | tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \ | |
6228 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \ | |
6229 | tcg_gen_br(l2); \ | |
6230 | gen_set_label(l1); \ | |
6231 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ | |
6232 | CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ | |
6233 | gen_set_label(l2); \ | |
6234 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \ | |
6235 | tcg_gen_trunc_i64_i32(t0, t2); \ | |
6236 | tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \ | |
6237 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
6238 | tcg_temp_free_i64(t2); \ | |
6239 | tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \ | |
6240 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
6241 | ~(CRF_CH | CRF_CH_AND_CL)); \ | |
6242 | tcg_gen_br(l4); \ | |
6243 | gen_set_label(l3); \ | |
6244 | tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
6245 | CRF_CH | CRF_CH_OR_CL); \ | |
6246 | gen_set_label(l4); \ | |
6247 | tcg_temp_free_i32(t0); \ | |
6248 | tcg_temp_free_i32(t1); \ | |
6249 | } | |
6250 | #else | |
6251 | #define GEN_SPEOP_COMP(name, tcg_cond) \ | |
6252 | static always_inline void gen_##name (DisasContext *ctx) \ | |
6253 | { \ | |
6254 | if (unlikely(!ctx->spe_enabled)) { \ | |
6255 | GEN_EXCP_NO_AP(ctx); \ | |
6256 | return; \ | |
6257 | } \ | |
6258 | int l1 = gen_new_label(); \ | |
6259 | int l2 = gen_new_label(); \ | |
6260 | int l3 = gen_new_label(); \ | |
6261 | int l4 = gen_new_label(); \ | |
6262 | \ | |
6263 | tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \ | |
6264 | cpu_gpr[rB(ctx->opcode)], l1); \ | |
6265 | tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \ | |
6266 | tcg_gen_br(l2); \ | |
6267 | gen_set_label(l1); \ | |
6268 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ | |
6269 | CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ | |
6270 | gen_set_label(l2); \ | |
6271 | tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \ | |
6272 | cpu_gprh[rB(ctx->opcode)], l3); \ | |
6273 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
6274 | ~(CRF_CH | CRF_CH_AND_CL)); \ | |
6275 | tcg_gen_br(l4); \ | |
6276 | gen_set_label(l3); \ | |
6277 | tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
6278 | CRF_CH | CRF_CH_OR_CL); \ | |
6279 | gen_set_label(l4); \ | |
6280 | } | |
6281 | #endif | |
6282 | GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU); | |
6283 | GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT); | |
6284 | GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU); | |
6285 | GEN_SPEOP_COMP(evcmplts, TCG_COND_LT); | |
6286 | GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ); | |
6287 | ||
6288 | /* SPE misc */ | |
6289 | static always_inline void gen_brinc (DisasContext *ctx) | |
6290 | { | |
6291 | /* Note: brinc is usable even if SPE is disabled */ | |
6292 | gen_helper_brinc(cpu_gpr[rD(ctx->opcode)], | |
6293 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
6294 | } | |
6295 | static always_inline void gen_evmergelo (DisasContext *ctx) | |
6296 | { | |
6297 | if (unlikely(!ctx->spe_enabled)) { | |
6298 | GEN_EXCP_NO_AP(ctx); | |
6299 | return; | |
6300 | } | |
6301 | #if defined(TARGET_PPC64) | |
6302 | TCGv t0 = tcg_temp_new(); | |
6303 | TCGv t1 = tcg_temp_new(); | |
6304 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL); | |
6305 | tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32); | |
6306 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
6307 | tcg_temp_free(t0); | |
6308 | tcg_temp_free(t1); | |
6309 | #else | |
6310 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
6311 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
6312 | #endif | |
6313 | } | |
6314 | static always_inline void gen_evmergehilo (DisasContext *ctx) | |
6315 | { | |
6316 | if (unlikely(!ctx->spe_enabled)) { | |
6317 | GEN_EXCP_NO_AP(ctx); | |
6318 | return; | |
6319 | } | |
6320 | #if defined(TARGET_PPC64) | |
6321 | TCGv t0 = tcg_temp_new(); | |
6322 | TCGv t1 = tcg_temp_new(); | |
6323 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL); | |
6324 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL); | |
6325 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
6326 | tcg_temp_free(t0); | |
6327 | tcg_temp_free(t1); | |
6328 | #else | |
6329 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
6330 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
6331 | #endif | |
6332 | } | |
6333 | static always_inline void gen_evmergelohi (DisasContext *ctx) | |
6334 | { | |
6335 | if (unlikely(!ctx->spe_enabled)) { | |
6336 | GEN_EXCP_NO_AP(ctx); | |
6337 | return; | |
6338 | } | |
6339 | #if defined(TARGET_PPC64) | |
6340 | TCGv t0 = tcg_temp_new(); | |
6341 | TCGv t1 = tcg_temp_new(); | |
6342 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32); | |
6343 | tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32); | |
6344 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
6345 | tcg_temp_free(t0); | |
6346 | tcg_temp_free(t1); | |
6347 | #else | |
6348 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
6349 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
6350 | #endif | |
6351 | } | |
6352 | static always_inline void gen_evsplati (DisasContext *ctx) | |
6353 | { | |
6354 | uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27; | |
6355 | ||
6356 | #if defined(TARGET_PPC64) | |
6357 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm); | |
6358 | #else | |
6359 | tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm); | |
6360 | tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm); | |
6361 | #endif | |
6362 | } | |
6363 | static always_inline void gen_evsplatfi (DisasContext *ctx) | |
6364 | { | |
6365 | uint64_t imm = rA(ctx->opcode) << 11; | |
6366 | ||
6367 | #if defined(TARGET_PPC64) | |
6368 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm); | |
6369 | #else | |
6370 | tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm); | |
6371 | tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm); | |
6372 | #endif | |
6373 | } | |
6374 | ||
6375 | static always_inline void gen_evsel (DisasContext *ctx) | |
6376 | { | |
6377 | int l1 = gen_new_label(); | |
6378 | int l2 = gen_new_label(); | |
6379 | int l3 = gen_new_label(); | |
6380 | int l4 = gen_new_label(); | |
6381 | TCGv_i32 t0 = tcg_temp_local_new_i32(); | |
6382 | #if defined(TARGET_PPC64) | |
6383 | TCGv t1 = tcg_temp_local_new(); | |
6384 | TCGv t2 = tcg_temp_local_new(); | |
6385 | #endif | |
6386 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3); | |
6387 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); | |
6388 | #if defined(TARGET_PPC64) | |
6389 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL); | |
6390 | #else | |
6391 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
6392 | #endif | |
6393 | tcg_gen_br(l2); | |
6394 | gen_set_label(l1); | |
6395 | #if defined(TARGET_PPC64) | |
6396 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL); | |
6397 | #else | |
6398 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
6399 | #endif | |
6400 | gen_set_label(l2); | |
6401 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2); | |
6402 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3); | |
6403 | #if defined(TARGET_PPC64) | |
6404 | tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL); | |
6405 | #else | |
6406 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
6407 | #endif | |
6408 | tcg_gen_br(l4); | |
6409 | gen_set_label(l3); | |
6410 | #if defined(TARGET_PPC64) | |
6411 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL); | |
6412 | #else | |
6413 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
6414 | #endif | |
6415 | gen_set_label(l4); | |
6416 | tcg_temp_free_i32(t0); | |
6417 | #if defined(TARGET_PPC64) | |
6418 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2); | |
6419 | tcg_temp_free(t1); | |
6420 | tcg_temp_free(t2); | |
6421 | #endif | |
6422 | } | |
6423 | GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE) | |
6424 | { | |
6425 | gen_evsel(ctx); | |
6426 | } | |
6427 | GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE) | |
6428 | { | |
6429 | gen_evsel(ctx); | |
6430 | } | |
6431 | GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE) | |
6432 | { | |
6433 | gen_evsel(ctx); | |
6434 | } | |
6435 | GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE) | |
6436 | { | |
6437 | gen_evsel(ctx); | |
6438 | } | |
6439 | ||
6440 | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); //// | |
6441 | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE); | |
6442 | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); //// | |
6443 | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE); | |
6444 | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); //// | |
6445 | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); //// | |
6446 | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); //// | |
6447 | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); // | |
6448 | GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); //// | |
6449 | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); //// | |
6450 | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); //// | |
6451 | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); //// | |
6452 | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); //// | |
6453 | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); //// | |
6454 | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); //// | |
6455 | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE); | |
6456 | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); //// | |
6457 | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE); | |
6458 | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); // | |
6459 | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE); | |
6460 | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); //// | |
6461 | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); //// | |
6462 | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); //// | |
6463 | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); //// | |
6464 | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); //// | |
6465 | ||
6466 | /* SPE load and stores */ | |
6467 | static always_inline void gen_addr_spe_imm_index (TCGv EA, DisasContext *ctx, int sh) | |
6468 | { | |
6469 | target_ulong uimm = rB(ctx->opcode); | |
6470 | ||
6471 | if (rA(ctx->opcode) == 0) | |
6472 | tcg_gen_movi_tl(EA, uimm << sh); | |
6473 | else | |
6474 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh); | |
6475 | } | |
6476 | ||
6477 | static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr) | |
6478 | { | |
6479 | #if defined(TARGET_PPC64) | |
6480 | gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx); | |
6481 | #else | |
6482 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
6483 | gen_qemu_ld64(t0, addr, ctx->mem_idx); | |
6484 | tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0); | |
6485 | tcg_gen_shri_i64(t0, t0, 32); | |
6486 | tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0); | |
6487 | tcg_temp_free_i64(t0); | |
6488 | #endif | |
6489 | } | |
6490 | ||
6491 | static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr) | |
6492 | { | |
6493 | #if defined(TARGET_PPC64) | |
6494 | TCGv t0 = tcg_temp_new(); | |
6495 | gen_qemu_ld32u(t0, addr, ctx->mem_idx); | |
6496 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); | |
6497 | tcg_gen_addi_tl(addr, addr, 4); | |
6498 | gen_qemu_ld32u(t0, addr, ctx->mem_idx); | |
6499 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
6500 | tcg_temp_free(t0); | |
6501 | #else | |
6502 | gen_qemu_ld32u(cpu_gprh[rD(ctx->opcode)], addr, ctx->mem_idx); | |
6503 | tcg_gen_addi_tl(addr, addr, 4); | |
6504 | gen_qemu_ld32u(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx); | |
6505 | #endif | |
6506 | } | |
6507 | ||
6508 | static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr) | |
6509 | { | |
6510 | TCGv t0 = tcg_temp_new(); | |
6511 | #if defined(TARGET_PPC64) | |
6512 | gen_qemu_ld16u(t0, addr, ctx->mem_idx); | |
6513 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); | |
6514 | tcg_gen_addi_tl(addr, addr, 2); | |
6515 | gen_qemu_ld16u(t0, addr, ctx->mem_idx); | |
6516 | tcg_gen_shli_tl(t0, t0, 32); | |
6517 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
6518 | tcg_gen_addi_tl(addr, addr, 2); | |
6519 | gen_qemu_ld16u(t0, addr, ctx->mem_idx); | |
6520 | tcg_gen_shli_tl(t0, t0, 16); | |
6521 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
6522 | tcg_gen_addi_tl(addr, addr, 2); | |
6523 | gen_qemu_ld16u(t0, addr, ctx->mem_idx); | |
6524 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
6525 | #else | |
6526 | gen_qemu_ld16u(t0, addr, ctx->mem_idx); | |
6527 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); | |
6528 | tcg_gen_addi_tl(addr, addr, 2); | |
6529 | gen_qemu_ld16u(t0, addr, ctx->mem_idx); | |
6530 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); | |
6531 | tcg_gen_addi_tl(addr, addr, 2); | |
6532 | gen_qemu_ld16u(t0, addr, ctx->mem_idx); | |
6533 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); | |
6534 | tcg_gen_addi_tl(addr, addr, 2); | |
6535 | gen_qemu_ld16u(t0, addr, ctx->mem_idx); | |
6536 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
6537 | #endif | |
6538 | tcg_temp_free(t0); | |
6539 | } | |
6540 | ||
6541 | static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr) | |
6542 | { | |
6543 | TCGv t0 = tcg_temp_new(); | |
6544 | gen_qemu_ld16u(t0, addr, ctx->mem_idx); | |
6545 | #if defined(TARGET_PPC64) | |
6546 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); | |
6547 | tcg_gen_shli_tl(t0, t0, 16); | |
6548 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
6549 | #else | |
6550 | tcg_gen_shli_tl(t0, t0, 16); | |
6551 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
6552 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
6553 | #endif | |
6554 | tcg_temp_free(t0); | |
6555 | } | |
6556 | ||
6557 | static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr) | |
6558 | { | |
6559 | TCGv t0 = tcg_temp_new(); | |
6560 | gen_qemu_ld16u(t0, addr, ctx->mem_idx); | |
6561 | #if defined(TARGET_PPC64) | |
6562 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); | |
6563 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
6564 | #else | |
6565 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
6566 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
6567 | #endif | |
6568 | tcg_temp_free(t0); | |
6569 | } | |
6570 | ||
6571 | static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr) | |
6572 | { | |
6573 | TCGv t0 = tcg_temp_new(); | |
6574 | gen_qemu_ld16s(t0, addr, ctx->mem_idx); | |
6575 | #if defined(TARGET_PPC64) | |
6576 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); | |
6577 | tcg_gen_ext32u_tl(t0, t0); | |
6578 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
6579 | #else | |
6580 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
6581 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
6582 | #endif | |
6583 | tcg_temp_free(t0); | |
6584 | } | |
6585 | ||
6586 | static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr) | |
6587 | { | |
6588 | TCGv t0 = tcg_temp_new(); | |
6589 | #if defined(TARGET_PPC64) | |
6590 | gen_qemu_ld16u(t0, addr, ctx->mem_idx); | |
6591 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); | |
6592 | gen_qemu_ld16u(t0, addr, ctx->mem_idx); | |
6593 | tcg_gen_shli_tl(t0, t0, 16); | |
6594 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
6595 | #else | |
6596 | gen_qemu_ld16u(t0, addr, ctx->mem_idx); | |
6597 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); | |
6598 | tcg_gen_addi_tl(addr, addr, 2); | |
6599 | gen_qemu_ld16u(t0, addr, ctx->mem_idx); | |
6600 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); | |
6601 | #endif | |
6602 | tcg_temp_free(t0); | |
6603 | } | |
6604 | ||
6605 | static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr) | |
6606 | { | |
6607 | #if defined(TARGET_PPC64) | |
6608 | TCGv t0 = tcg_temp_new(); | |
6609 | gen_qemu_ld16u(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx); | |
6610 | tcg_gen_addi_tl(addr, addr, 2); | |
6611 | gen_qemu_ld16u(t0, addr, ctx->mem_idx); | |
6612 | tcg_gen_shli_tl(t0, t0, 32); | |
6613 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
6614 | tcg_temp_free(t0); | |
6615 | #else | |
6616 | gen_qemu_ld16u(cpu_gprh[rD(ctx->opcode)], addr, ctx->mem_idx); | |
6617 | tcg_gen_addi_tl(addr, addr, 2); | |
6618 | gen_qemu_ld16u(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx); | |
6619 | #endif | |
6620 | } | |
6621 | ||
6622 | static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr) | |
6623 | { | |
6624 | #if defined(TARGET_PPC64) | |
6625 | TCGv t0 = tcg_temp_new(); | |
6626 | gen_qemu_ld16s(t0, addr, ctx->mem_idx); | |
6627 | tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
6628 | tcg_gen_addi_tl(addr, addr, 2); | |
6629 | gen_qemu_ld16s(t0, addr, ctx->mem_idx); | |
6630 | tcg_gen_shli_tl(t0, t0, 32); | |
6631 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
6632 | tcg_temp_free(t0); | |
6633 | #else | |
6634 | gen_qemu_ld16s(cpu_gprh[rD(ctx->opcode)], addr, ctx->mem_idx); | |
6635 | tcg_gen_addi_tl(addr, addr, 2); | |
6636 | gen_qemu_ld16s(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx); | |
6637 | #endif | |
6638 | } | |
6639 | ||
6640 | static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr) | |
6641 | { | |
6642 | TCGv t0 = tcg_temp_new(); | |
6643 | gen_qemu_ld32u(t0, addr, ctx->mem_idx); | |
6644 | #if defined(TARGET_PPC64) | |
6645 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); | |
6646 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
6647 | #else | |
6648 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
6649 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
6650 | #endif | |
6651 | tcg_temp_free(t0); | |
6652 | } | |
6653 | ||
6654 | static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr) | |
6655 | { | |
6656 | TCGv t0 = tcg_temp_new(); | |
6657 | #if defined(TARGET_PPC64) | |
6658 | gen_qemu_ld16u(t0, addr, ctx->mem_idx); | |
6659 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); | |
6660 | tcg_gen_shli_tl(t0, t0, 32); | |
6661 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
6662 | tcg_gen_addi_tl(addr, addr, 2); | |
6663 | gen_qemu_ld16u(t0, addr, ctx->mem_idx); | |
6664 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
6665 | tcg_gen_shli_tl(t0, t0, 16); | |
6666 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
6667 | #else | |
6668 | gen_qemu_ld16u(t0, addr, ctx->mem_idx); | |
6669 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); | |
6670 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); | |
6671 | tcg_gen_addi_tl(addr, addr, 2); | |
6672 | gen_qemu_ld16u(t0, addr, ctx->mem_idx); | |
6673 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); | |
6674 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); | |
6675 | #endif | |
6676 | tcg_temp_free(t0); | |
6677 | } | |
6678 | ||
6679 | static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr) | |
6680 | { | |
6681 | #if defined(TARGET_PPC64) | |
6682 | gen_qemu_st64(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx); | |
6683 | #else | |
6684 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
6685 | tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]); | |
6686 | gen_qemu_st64(t0, addr, ctx->mem_idx); | |
6687 | tcg_temp_free_i64(t0); | |
6688 | #endif | |
6689 | } | |
6690 | ||
6691 | static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr) | |
6692 | { | |
6693 | #if defined(TARGET_PPC64) | |
6694 | TCGv t0 = tcg_temp_new(); | |
6695 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
6696 | gen_qemu_st32(t0, addr, ctx->mem_idx); | |
6697 | tcg_temp_free(t0); | |
6698 | #else | |
6699 | gen_qemu_st32(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx); | |
6700 | #endif | |
6701 | tcg_gen_addi_tl(addr, addr, 4); | |
6702 | gen_qemu_st32(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx); | |
6703 | } | |
6704 | ||
6705 | static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr) | |
6706 | { | |
6707 | TCGv t0 = tcg_temp_new(); | |
6708 | #if defined(TARGET_PPC64) | |
6709 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48); | |
6710 | #else | |
6711 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); | |
6712 | #endif | |
6713 | gen_qemu_st16(t0, addr, ctx->mem_idx); | |
6714 | tcg_gen_addi_tl(addr, addr, 2); | |
6715 | #if defined(TARGET_PPC64) | |
6716 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
6717 | gen_qemu_st16(t0, addr, ctx->mem_idx); | |
6718 | #else | |
6719 | gen_qemu_st16(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx); | |
6720 | #endif | |
6721 | tcg_gen_addi_tl(addr, addr, 2); | |
6722 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); | |
6723 | gen_qemu_st16(t0, addr, ctx->mem_idx); | |
6724 | tcg_temp_free(t0); | |
6725 | tcg_gen_addi_tl(addr, addr, 2); | |
6726 | gen_qemu_st16(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx); | |
6727 | } | |
6728 | ||
6729 | static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr) | |
6730 | { | |
6731 | TCGv t0 = tcg_temp_new(); | |
6732 | #if defined(TARGET_PPC64) | |
6733 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48); | |
6734 | #else | |
6735 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); | |
6736 | #endif | |
6737 | gen_qemu_st16(t0, addr, ctx->mem_idx); | |
6738 | tcg_gen_addi_tl(addr, addr, 2); | |
6739 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); | |
6740 | gen_qemu_st16(t0, addr, ctx->mem_idx); | |
6741 | tcg_temp_free(t0); | |
6742 | } | |
6743 | ||
6744 | static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr) | |
6745 | { | |
6746 | #if defined(TARGET_PPC64) | |
6747 | TCGv t0 = tcg_temp_new(); | |
6748 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
6749 | gen_qemu_st16(t0, addr, ctx->mem_idx); | |
6750 | tcg_temp_free(t0); | |
6751 | #else | |
6752 | gen_qemu_st16(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx); | |
6753 | #endif | |
6754 | tcg_gen_addi_tl(addr, addr, 2); | |
6755 | gen_qemu_st16(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx); | |
6756 | } | |
6757 | ||
6758 | static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr) | |
6759 | { | |
6760 | #if defined(TARGET_PPC64) | |
6761 | TCGv t0 = tcg_temp_new(); | |
6762 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
6763 | gen_qemu_st32(t0, addr, ctx->mem_idx); | |
6764 | tcg_temp_free(t0); | |
6765 | #else | |
6766 | gen_qemu_st32(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx); | |
6767 | #endif | |
6768 | } | |
6769 | ||
6770 | static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr) | |
6771 | { | |
6772 | gen_qemu_st32(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx); | |
6773 | } | |
6774 | ||
6775 | #define GEN_SPEOP_LDST(name, opc2, sh) \ | |
6776 | GEN_HANDLER(gen_##name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \ | |
6777 | { \ | |
6778 | TCGv t0; \ | |
6779 | if (unlikely(!ctx->spe_enabled)) { \ | |
6780 | GEN_EXCP_NO_AP(ctx); \ | |
6781 | return; \ | |
6782 | } \ | |
6783 | t0 = tcg_temp_new(); \ | |
6784 | if (Rc(ctx->opcode)) { \ | |
6785 | gen_addr_spe_imm_index(t0, ctx, sh); \ | |
6786 | } else { \ | |
6787 | gen_addr_reg_index(t0, ctx); \ | |
6788 | } \ | |
6789 | gen_op_##name(ctx, t0); \ | |
6790 | tcg_temp_free(t0); \ | |
6791 | } | |
6792 | ||
6793 | GEN_SPEOP_LDST(evldd, 0x00, 3); | |
6794 | GEN_SPEOP_LDST(evldw, 0x01, 3); | |
6795 | GEN_SPEOP_LDST(evldh, 0x02, 3); | |
6796 | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1); | |
6797 | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1); | |
6798 | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1); | |
6799 | GEN_SPEOP_LDST(evlwhe, 0x08, 2); | |
6800 | GEN_SPEOP_LDST(evlwhou, 0x0A, 2); | |
6801 | GEN_SPEOP_LDST(evlwhos, 0x0B, 2); | |
6802 | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2); | |
6803 | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2); | |
6804 | ||
6805 | GEN_SPEOP_LDST(evstdd, 0x10, 3); | |
6806 | GEN_SPEOP_LDST(evstdw, 0x11, 3); | |
6807 | GEN_SPEOP_LDST(evstdh, 0x12, 3); | |
6808 | GEN_SPEOP_LDST(evstwhe, 0x18, 2); | |
6809 | GEN_SPEOP_LDST(evstwho, 0x1A, 2); | |
6810 | GEN_SPEOP_LDST(evstwwe, 0x1C, 2); | |
6811 | GEN_SPEOP_LDST(evstwwo, 0x1E, 2); | |
6812 | ||
6813 | /* Multiply and add - TODO */ | |
6814 | #if 0 | |
6815 | GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE); | |
6816 | GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE); | |
6817 | GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE); | |
6818 | GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE); | |
6819 | GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE); | |
6820 | GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE); | |
6821 | GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE); | |
6822 | GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE); | |
6823 | GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE); | |
6824 | GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE); | |
6825 | GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE); | |
6826 | GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE); | |
6827 | ||
6828 | GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE); | |
6829 | GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE); | |
6830 | GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE); | |
6831 | GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE); | |
6832 | GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE); | |
6833 | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE); | |
6834 | GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE); | |
6835 | GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE); | |
6836 | GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE); | |
6837 | GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE); | |
6838 | GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE); | |
6839 | GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE); | |
6840 | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE); | |
6841 | GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE); | |
6842 | ||
6843 | GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE); | |
6844 | GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE); | |
6845 | GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE); | |
6846 | GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE); | |
6847 | GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE); | |
6848 | GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE); | |
6849 | ||
6850 | GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE); | |
6851 | GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE); | |
6852 | GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE); | |
6853 | GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE); | |
6854 | GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE); | |
6855 | GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE); | |
6856 | GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE); | |
6857 | GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE); | |
6858 | GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE); | |
6859 | GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE); | |
6860 | GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE); | |
6861 | GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE); | |
6862 | ||
6863 | GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE); | |
6864 | GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE); | |
6865 | GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE); | |
6866 | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE); | |
6867 | GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE); | |
6868 | ||
6869 | GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE); | |
6870 | GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE); | |
6871 | GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE); | |
6872 | GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE); | |
6873 | GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE); | |
6874 | GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE); | |
6875 | GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE); | |
6876 | GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE); | |
6877 | GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE); | |
6878 | GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE); | |
6879 | GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE); | |
6880 | GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE); | |
6881 | ||
6882 | GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE); | |
6883 | GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE); | |
6884 | GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE); | |
6885 | GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE); | |
6886 | GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE); | |
6887 | #endif | |
6888 | ||
6889 | /*** SPE floating-point extension ***/ | |
6890 | #if defined(TARGET_PPC64) | |
6891 | #define GEN_SPEFPUOP_CONV_32_32(name) \ | |
6892 | static always_inline void gen_##name (DisasContext *ctx) \ | |
6893 | { \ | |
6894 | TCGv_i32 t0; \ | |
6895 | TCGv t1; \ | |
6896 | t0 = tcg_temp_new_i32(); \ | |
6897 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ | |
6898 | gen_helper_##name(t0, t0); \ | |
6899 | t1 = tcg_temp_new(); \ | |
6900 | tcg_gen_extu_i32_tl(t1, t0); \ | |
6901 | tcg_temp_free_i32(t0); \ | |
6902 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ | |
6903 | 0xFFFFFFFF00000000ULL); \ | |
6904 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \ | |
6905 | tcg_temp_free(t1); \ | |
6906 | } | |
6907 | #define GEN_SPEFPUOP_CONV_32_64(name) \ | |
6908 | static always_inline void gen_##name (DisasContext *ctx) \ | |
6909 | { \ | |
6910 | TCGv_i32 t0; \ | |
6911 | TCGv t1; \ | |
6912 | t0 = tcg_temp_new_i32(); \ | |
6913 | gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \ | |
6914 | t1 = tcg_temp_new(); \ | |
6915 | tcg_gen_extu_i32_tl(t1, t0); \ | |
6916 | tcg_temp_free_i32(t0); \ | |
6917 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ | |
6918 | 0xFFFFFFFF00000000ULL); \ | |
6919 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \ | |
6920 | tcg_temp_free(t1); \ | |
6921 | } | |
6922 | #define GEN_SPEFPUOP_CONV_64_32(name) \ | |
6923 | static always_inline void gen_##name (DisasContext *ctx) \ | |
6924 | { \ | |
6925 | TCGv_i32 t0 = tcg_temp_new_i32(); \ | |
6926 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ | |
6927 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \ | |
6928 | tcg_temp_free_i32(t0); \ | |
6929 | } | |
6930 | #define GEN_SPEFPUOP_CONV_64_64(name) \ | |
6931 | static always_inline void gen_##name (DisasContext *ctx) \ | |
6932 | { \ | |
6933 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ | |
6934 | } | |
6935 | #define GEN_SPEFPUOP_ARITH2_32_32(name) \ | |
6936 | static always_inline void gen_##name (DisasContext *ctx) \ | |
6937 | { \ | |
6938 | TCGv_i32 t0, t1; \ | |
6939 | TCGv_i64 t2; \ | |
6940 | if (unlikely(!ctx->spe_enabled)) { \ | |
6941 | GEN_EXCP_NO_AP(ctx); \ | |
6942 | return; \ | |
6943 | } \ | |
6944 | t0 = tcg_temp_new_i32(); \ | |
6945 | t1 = tcg_temp_new_i32(); \ | |
6946 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
6947 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
6948 | gen_helper_##name(t0, t0, t1); \ | |
6949 | tcg_temp_free_i32(t1); \ | |
6950 | t2 = tcg_temp_new(); \ | |
6951 | tcg_gen_extu_i32_tl(t2, t0); \ | |
6952 | tcg_temp_free_i32(t0); \ | |
6953 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ | |
6954 | 0xFFFFFFFF00000000ULL); \ | |
6955 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \ | |
6956 | tcg_temp_free(t2); \ | |
6957 | } | |
6958 | #define GEN_SPEFPUOP_ARITH2_64_64(name) \ | |
6959 | static always_inline void gen_##name (DisasContext *ctx) \ | |
6960 | { \ | |
6961 | if (unlikely(!ctx->spe_enabled)) { \ | |
6962 | GEN_EXCP_NO_AP(ctx); \ | |
6963 | return; \ | |
6964 | } \ | |
6965 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ | |
6966 | cpu_gpr[rB(ctx->opcode)]); \ | |
6967 | } | |
6968 | #define GEN_SPEFPUOP_COMP_32(name) \ | |
6969 | static always_inline void gen_##name (DisasContext *ctx) \ | |
6970 | { \ | |
6971 | TCGv_i32 t0, t1; \ | |
6972 | if (unlikely(!ctx->spe_enabled)) { \ | |
6973 | GEN_EXCP_NO_AP(ctx); \ | |
6974 | return; \ | |
6975 | } \ | |
6976 | t0 = tcg_temp_new_i32(); \ | |
6977 | t1 = tcg_temp_new_i32(); \ | |
6978 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
6979 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
6980 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \ | |
6981 | tcg_temp_free_i32(t0); \ | |
6982 | tcg_temp_free_i32(t1); \ | |
6983 | } | |
6984 | #define GEN_SPEFPUOP_COMP_64(name) \ | |
6985 | static always_inline void gen_##name (DisasContext *ctx) \ | |
6986 | { \ | |
6987 | if (unlikely(!ctx->spe_enabled)) { \ | |
6988 | GEN_EXCP_NO_AP(ctx); \ | |
6989 | return; \ | |
6990 | } \ | |
6991 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ | |
6992 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ | |
6993 | } | |
6994 | #else | |
6995 | #define GEN_SPEFPUOP_CONV_32_32(name) \ | |
6996 | static always_inline void gen_##name (DisasContext *ctx) \ | |
6997 | { \ | |
6998 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ | |
6999 | } | |
7000 | #define GEN_SPEFPUOP_CONV_32_64(name) \ | |
7001 | static always_inline void gen_##name (DisasContext *ctx) \ | |
7002 | { \ | |
7003 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
7004 | gen_load_gpr64(t0, rB(ctx->opcode)); \ | |
7005 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \ | |
7006 | tcg_temp_free_i64(t0); \ | |
7007 | } | |
7008 | #define GEN_SPEFPUOP_CONV_64_32(name) \ | |
7009 | static always_inline void gen_##name (DisasContext *ctx) \ | |
7010 | { \ | |
7011 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
7012 | gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \ | |
7013 | gen_store_gpr64(rD(ctx->opcode), t0); \ | |
7014 | tcg_temp_free_i64(t0); \ | |
7015 | } | |
7016 | #define GEN_SPEFPUOP_CONV_64_64(name) \ | |
7017 | static always_inline void gen_##name (DisasContext *ctx) \ | |
7018 | { \ | |
7019 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
7020 | gen_load_gpr64(t0, rB(ctx->opcode)); \ | |
7021 | gen_helper_##name(t0, t0); \ | |
7022 | gen_store_gpr64(rD(ctx->opcode), t0); \ | |
7023 | tcg_temp_free_i64(t0); \ | |
7024 | } | |
7025 | #define GEN_SPEFPUOP_ARITH2_32_32(name) \ | |
7026 | static always_inline void gen_##name (DisasContext *ctx) \ | |
7027 | { \ | |
7028 | if (unlikely(!ctx->spe_enabled)) { \ | |
7029 | GEN_EXCP_NO_AP(ctx); \ | |
7030 | return; \ | |
7031 | } \ | |
7032 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \ | |
7033 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ | |
7034 | } | |
7035 | #define GEN_SPEFPUOP_ARITH2_64_64(name) \ | |
7036 | static always_inline void gen_##name (DisasContext *ctx) \ | |
7037 | { \ | |
7038 | TCGv_i64 t0, t1; \ | |
7039 | if (unlikely(!ctx->spe_enabled)) { \ | |
7040 | GEN_EXCP_NO_AP(ctx); \ | |
7041 | return; \ | |
7042 | } \ | |
7043 | t0 = tcg_temp_new_i64(); \ | |
7044 | t1 = tcg_temp_new_i64(); \ | |
7045 | gen_load_gpr64(t0, rA(ctx->opcode)); \ | |
7046 | gen_load_gpr64(t1, rB(ctx->opcode)); \ | |
7047 | gen_helper_##name(t0, t0, t1); \ | |
7048 | gen_store_gpr64(rD(ctx->opcode), t0); \ | |
7049 | tcg_temp_free_i64(t0); \ | |
7050 | tcg_temp_free_i64(t1); \ | |
7051 | } | |
7052 | #define GEN_SPEFPUOP_COMP_32(name) \ | |
7053 | static always_inline void gen_##name (DisasContext *ctx) \ | |
7054 | { \ | |
7055 | if (unlikely(!ctx->spe_enabled)) { \ | |
7056 | GEN_EXCP_NO_AP(ctx); \ | |
7057 | return; \ | |
7058 | } \ | |
7059 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ | |
7060 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ | |
7061 | } | |
7062 | #define GEN_SPEFPUOP_COMP_64(name) \ | |
7063 | static always_inline void gen_##name (DisasContext *ctx) \ | |
7064 | { \ | |
7065 | TCGv_i64 t0, t1; \ | |
7066 | if (unlikely(!ctx->spe_enabled)) { \ | |
7067 | GEN_EXCP_NO_AP(ctx); \ | |
7068 | return; \ | |
7069 | } \ | |
7070 | t0 = tcg_temp_new_i64(); \ | |
7071 | t1 = tcg_temp_new_i64(); \ | |
7072 | gen_load_gpr64(t0, rA(ctx->opcode)); \ | |
7073 | gen_load_gpr64(t1, rB(ctx->opcode)); \ | |
7074 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \ | |
7075 | tcg_temp_free_i64(t0); \ | |
7076 | tcg_temp_free_i64(t1); \ | |
7077 | } | |
7078 | #endif | |
7079 | ||
7080 | /* Single precision floating-point vectors operations */ | |
7081 | /* Arithmetic */ | |
7082 | GEN_SPEFPUOP_ARITH2_64_64(evfsadd); | |
7083 | GEN_SPEFPUOP_ARITH2_64_64(evfssub); | |
7084 | GEN_SPEFPUOP_ARITH2_64_64(evfsmul); | |
7085 | GEN_SPEFPUOP_ARITH2_64_64(evfsdiv); | |
7086 | static always_inline void gen_evfsabs (DisasContext *ctx) | |
7087 | { | |
7088 | if (unlikely(!ctx->spe_enabled)) { | |
7089 | GEN_EXCP_NO_AP(ctx); | |
7090 | return; | |
7091 | } | |
7092 | #if defined(TARGET_PPC64) | |
7093 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL); | |
7094 | #else | |
7095 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000); | |
7096 | tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000); | |
7097 | #endif | |
7098 | } | |
7099 | static always_inline void gen_evfsnabs (DisasContext *ctx) | |
7100 | { | |
7101 | if (unlikely(!ctx->spe_enabled)) { | |
7102 | GEN_EXCP_NO_AP(ctx); | |
7103 | return; | |
7104 | } | |
7105 | #if defined(TARGET_PPC64) | |
7106 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL); | |
7107 | #else | |
7108 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); | |
7109 | tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
7110 | #endif | |
7111 | } | |
7112 | static always_inline void gen_evfsneg (DisasContext *ctx) | |
7113 | { | |
7114 | if (unlikely(!ctx->spe_enabled)) { | |
7115 | GEN_EXCP_NO_AP(ctx); | |
7116 | return; | |
7117 | } | |
7118 | #if defined(TARGET_PPC64) | |
7119 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL); | |
7120 | #else | |
7121 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); | |
7122 | tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
7123 | #endif | |
7124 | } | |
7125 | ||
7126 | /* Conversion */ | |
7127 | GEN_SPEFPUOP_CONV_64_64(evfscfui); | |
7128 | GEN_SPEFPUOP_CONV_64_64(evfscfsi); | |
7129 | GEN_SPEFPUOP_CONV_64_64(evfscfuf); | |
7130 | GEN_SPEFPUOP_CONV_64_64(evfscfsf); | |
7131 | GEN_SPEFPUOP_CONV_64_64(evfsctui); | |
7132 | GEN_SPEFPUOP_CONV_64_64(evfsctsi); | |
7133 | GEN_SPEFPUOP_CONV_64_64(evfsctuf); | |
7134 | GEN_SPEFPUOP_CONV_64_64(evfsctsf); | |
7135 | GEN_SPEFPUOP_CONV_64_64(evfsctuiz); | |
7136 | GEN_SPEFPUOP_CONV_64_64(evfsctsiz); | |
7137 | ||
7138 | /* Comparison */ | |
7139 | GEN_SPEFPUOP_COMP_64(evfscmpgt); | |
7140 | GEN_SPEFPUOP_COMP_64(evfscmplt); | |
7141 | GEN_SPEFPUOP_COMP_64(evfscmpeq); | |
7142 | GEN_SPEFPUOP_COMP_64(evfststgt); | |
7143 | GEN_SPEFPUOP_COMP_64(evfststlt); | |
7144 | GEN_SPEFPUOP_COMP_64(evfststeq); | |
7145 | ||
7146 | /* Opcodes definitions */ | |
7147 | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); // | |
7148 | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); // | |
7149 | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); // | |
7150 | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); // | |
7151 | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); // | |
7152 | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); // | |
7153 | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); // | |
7154 | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); // | |
7155 | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); // | |
7156 | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); // | |
7157 | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); // | |
7158 | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); // | |
7159 | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); // | |
7160 | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); // | |
7161 | ||
7162 | /* Single precision floating-point operations */ | |
7163 | /* Arithmetic */ | |
7164 | GEN_SPEFPUOP_ARITH2_32_32(efsadd); | |
7165 | GEN_SPEFPUOP_ARITH2_32_32(efssub); | |
7166 | GEN_SPEFPUOP_ARITH2_32_32(efsmul); | |
7167 | GEN_SPEFPUOP_ARITH2_32_32(efsdiv); | |
7168 | static always_inline void gen_efsabs (DisasContext *ctx) | |
7169 | { | |
7170 | if (unlikely(!ctx->spe_enabled)) { | |
7171 | GEN_EXCP_NO_AP(ctx); | |
7172 | return; | |
7173 | } | |
7174 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL); | |
7175 | } | |
7176 | static always_inline void gen_efsnabs (DisasContext *ctx) | |
7177 | { | |
7178 | if (unlikely(!ctx->spe_enabled)) { | |
7179 | GEN_EXCP_NO_AP(ctx); | |
7180 | return; | |
7181 | } | |
7182 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); | |
7183 | } | |
7184 | static always_inline void gen_efsneg (DisasContext *ctx) | |
7185 | { | |
7186 | if (unlikely(!ctx->spe_enabled)) { | |
7187 | GEN_EXCP_NO_AP(ctx); | |
7188 | return; | |
7189 | } | |
7190 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); | |
7191 | } | |
7192 | ||
7193 | /* Conversion */ | |
7194 | GEN_SPEFPUOP_CONV_32_32(efscfui); | |
7195 | GEN_SPEFPUOP_CONV_32_32(efscfsi); | |
7196 | GEN_SPEFPUOP_CONV_32_32(efscfuf); | |
7197 | GEN_SPEFPUOP_CONV_32_32(efscfsf); | |
7198 | GEN_SPEFPUOP_CONV_32_32(efsctui); | |
7199 | GEN_SPEFPUOP_CONV_32_32(efsctsi); | |
7200 | GEN_SPEFPUOP_CONV_32_32(efsctuf); | |
7201 | GEN_SPEFPUOP_CONV_32_32(efsctsf); | |
7202 | GEN_SPEFPUOP_CONV_32_32(efsctuiz); | |
7203 | GEN_SPEFPUOP_CONV_32_32(efsctsiz); | |
7204 | GEN_SPEFPUOP_CONV_32_64(efscfd); | |
7205 | ||
7206 | /* Comparison */ | |
7207 | GEN_SPEFPUOP_COMP_32(efscmpgt); | |
7208 | GEN_SPEFPUOP_COMP_32(efscmplt); | |
7209 | GEN_SPEFPUOP_COMP_32(efscmpeq); | |
7210 | GEN_SPEFPUOP_COMP_32(efststgt); | |
7211 | GEN_SPEFPUOP_COMP_32(efststlt); | |
7212 | GEN_SPEFPUOP_COMP_32(efststeq); | |
7213 | ||
7214 | /* Opcodes definitions */ | |
7215 | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); // | |
7216 | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); // | |
7217 | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); // | |
7218 | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); // | |
7219 | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); // | |
7220 | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); // | |
7221 | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); // | |
7222 | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); // | |
7223 | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); // | |
7224 | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); // | |
7225 | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); // | |
7226 | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); // | |
7227 | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); // | |
7228 | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); // | |
7229 | ||
7230 | /* Double precision floating-point operations */ | |
7231 | /* Arithmetic */ | |
7232 | GEN_SPEFPUOP_ARITH2_64_64(efdadd); | |
7233 | GEN_SPEFPUOP_ARITH2_64_64(efdsub); | |
7234 | GEN_SPEFPUOP_ARITH2_64_64(efdmul); | |
7235 | GEN_SPEFPUOP_ARITH2_64_64(efddiv); | |
7236 | static always_inline void gen_efdabs (DisasContext *ctx) | |
7237 | { | |
7238 | if (unlikely(!ctx->spe_enabled)) { | |
7239 | GEN_EXCP_NO_AP(ctx); | |
7240 | return; | |
7241 | } | |
7242 | #if defined(TARGET_PPC64) | |
7243 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL); | |
7244 | #else | |
7245 | tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000); | |
7246 | #endif | |
7247 | } | |
7248 | static always_inline void gen_efdnabs (DisasContext *ctx) | |
7249 | { | |
7250 | if (unlikely(!ctx->spe_enabled)) { | |
7251 | GEN_EXCP_NO_AP(ctx); | |
7252 | return; | |
7253 | } | |
7254 | #if defined(TARGET_PPC64) | |
7255 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL); | |
7256 | #else | |
7257 | tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
7258 | #endif | |
7259 | } | |
7260 | static always_inline void gen_efdneg (DisasContext *ctx) | |
7261 | { | |
7262 | if (unlikely(!ctx->spe_enabled)) { | |
7263 | GEN_EXCP_NO_AP(ctx); | |
7264 | return; | |
7265 | } | |
7266 | #if defined(TARGET_PPC64) | |
7267 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL); | |
7268 | #else | |
7269 | tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
7270 | #endif | |
7271 | } | |
7272 | ||
7273 | /* Conversion */ | |
7274 | GEN_SPEFPUOP_CONV_64_32(efdcfui); | |
7275 | GEN_SPEFPUOP_CONV_64_32(efdcfsi); | |
7276 | GEN_SPEFPUOP_CONV_64_32(efdcfuf); | |
7277 | GEN_SPEFPUOP_CONV_64_32(efdcfsf); | |
7278 | GEN_SPEFPUOP_CONV_32_64(efdctui); | |
7279 | GEN_SPEFPUOP_CONV_32_64(efdctsi); | |
7280 | GEN_SPEFPUOP_CONV_32_64(efdctuf); | |
7281 | GEN_SPEFPUOP_CONV_32_64(efdctsf); | |
7282 | GEN_SPEFPUOP_CONV_32_64(efdctuiz); | |
7283 | GEN_SPEFPUOP_CONV_32_64(efdctsiz); | |
7284 | GEN_SPEFPUOP_CONV_64_32(efdcfs); | |
7285 | GEN_SPEFPUOP_CONV_64_64(efdcfuid); | |
7286 | GEN_SPEFPUOP_CONV_64_64(efdcfsid); | |
7287 | GEN_SPEFPUOP_CONV_64_64(efdctuidz); | |
7288 | GEN_SPEFPUOP_CONV_64_64(efdctsidz); | |
7289 | ||
7290 | /* Comparison */ | |
7291 | GEN_SPEFPUOP_COMP_64(efdcmpgt); | |
7292 | GEN_SPEFPUOP_COMP_64(efdcmplt); | |
7293 | GEN_SPEFPUOP_COMP_64(efdcmpeq); | |
7294 | GEN_SPEFPUOP_COMP_64(efdtstgt); | |
7295 | GEN_SPEFPUOP_COMP_64(efdtstlt); | |
7296 | GEN_SPEFPUOP_COMP_64(efdtsteq); | |
7297 | ||
7298 | /* Opcodes definitions */ | |
7299 | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); // | |
7300 | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); // | |
7301 | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); // | |
7302 | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); // | |
7303 | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); // | |
7304 | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); // | |
7305 | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); // | |
7306 | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); // | |
7307 | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); // | |
7308 | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); // | |
7309 | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); // | |
7310 | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); // | |
7311 | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); // | |
7312 | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); // | |
7313 | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); // | |
7314 | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); // | |
7315 | ||
7316 | /* End opcode list */ | |
7317 | GEN_OPCODE_MARK(end); | |
7318 | ||
7319 | #include "translate_init.c" | |
7320 | #include "helper_regs.h" | |
7321 | ||
7322 | /*****************************************************************************/ | |
7323 | /* Misc PowerPC helpers */ | |
7324 | void cpu_dump_state (CPUState *env, FILE *f, | |
7325 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), | |
7326 | int flags) | |
7327 | { | |
7328 | #define RGPL 4 | |
7329 | #define RFPL 4 | |
7330 | ||
7331 | int i; | |
7332 | ||
7333 | cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n", | |
7334 | env->nip, env->lr, env->ctr, env->xer); | |
7335 | cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n", | |
7336 | env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx); | |
7337 | #if !defined(NO_TIMER_DUMP) | |
7338 | cpu_fprintf(f, "TB %08x %08x " | |
7339 | #if !defined(CONFIG_USER_ONLY) | |
7340 | "DECR %08x" | |
7341 | #endif | |
7342 | "\n", | |
7343 | cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) | |
7344 | #if !defined(CONFIG_USER_ONLY) | |
7345 | , cpu_ppc_load_decr(env) | |
7346 | #endif | |
7347 | ); | |
7348 | #endif | |
7349 | for (i = 0; i < 32; i++) { | |
7350 | if ((i & (RGPL - 1)) == 0) | |
7351 | cpu_fprintf(f, "GPR%02d", i); | |
7352 | cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i)); | |
7353 | if ((i & (RGPL - 1)) == (RGPL - 1)) | |
7354 | cpu_fprintf(f, "\n"); | |
7355 | } | |
7356 | cpu_fprintf(f, "CR "); | |
7357 | for (i = 0; i < 8; i++) | |
7358 | cpu_fprintf(f, "%01x", env->crf[i]); | |
7359 | cpu_fprintf(f, " ["); | |
7360 | for (i = 0; i < 8; i++) { | |
7361 | char a = '-'; | |
7362 | if (env->crf[i] & 0x08) | |
7363 | a = 'L'; | |
7364 | else if (env->crf[i] & 0x04) | |
7365 | a = 'G'; | |
7366 | else if (env->crf[i] & 0x02) | |
7367 | a = 'E'; | |
7368 | cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); | |
7369 | } | |
7370 | cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve); | |
7371 | for (i = 0; i < 32; i++) { | |
7372 | if ((i & (RFPL - 1)) == 0) | |
7373 | cpu_fprintf(f, "FPR%02d", i); | |
7374 | cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); | |
7375 | if ((i & (RFPL - 1)) == (RFPL - 1)) | |
7376 | cpu_fprintf(f, "\n"); | |
7377 | } | |
7378 | #if !defined(CONFIG_USER_ONLY) | |
7379 | cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n", | |
7380 | env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1); | |
7381 | #endif | |
7382 | ||
7383 | #undef RGPL | |
7384 | #undef RFPL | |
7385 | } | |
7386 | ||
7387 | void cpu_dump_statistics (CPUState *env, FILE*f, | |
7388 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), | |
7389 | int flags) | |
7390 | { | |
7391 | #if defined(DO_PPC_STATISTICS) | |
7392 | opc_handler_t **t1, **t2, **t3, *handler; | |
7393 | int op1, op2, op3; | |
7394 | ||
7395 | t1 = env->opcodes; | |
7396 | for (op1 = 0; op1 < 64; op1++) { | |
7397 | handler = t1[op1]; | |
7398 | if (is_indirect_opcode(handler)) { | |
7399 | t2 = ind_table(handler); | |
7400 | for (op2 = 0; op2 < 32; op2++) { | |
7401 | handler = t2[op2]; | |
7402 | if (is_indirect_opcode(handler)) { | |
7403 | t3 = ind_table(handler); | |
7404 | for (op3 = 0; op3 < 32; op3++) { | |
7405 | handler = t3[op3]; | |
7406 | if (handler->count == 0) | |
7407 | continue; | |
7408 | cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: " | |
7409 | "%016llx %lld\n", | |
7410 | op1, op2, op3, op1, (op3 << 5) | op2, | |
7411 | handler->oname, | |
7412 | handler->count, handler->count); | |
7413 | } | |
7414 | } else { | |
7415 | if (handler->count == 0) | |
7416 | continue; | |
7417 | cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: " | |
7418 | "%016llx %lld\n", | |
7419 | op1, op2, op1, op2, handler->oname, | |
7420 | handler->count, handler->count); | |
7421 | } | |
7422 | } | |
7423 | } else { | |
7424 | if (handler->count == 0) | |
7425 | continue; | |
7426 | cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n", | |
7427 | op1, op1, handler->oname, | |
7428 | handler->count, handler->count); | |
7429 | } | |
7430 | } | |
7431 | #endif | |
7432 | } | |
7433 | ||
7434 | /*****************************************************************************/ | |
7435 | static always_inline void gen_intermediate_code_internal (CPUState *env, | |
7436 | TranslationBlock *tb, | |
7437 | int search_pc) | |
7438 | { | |
7439 | DisasContext ctx, *ctxp = &ctx; | |
7440 | opc_handler_t **table, *handler; | |
7441 | target_ulong pc_start; | |
7442 | uint16_t *gen_opc_end; | |
7443 | int supervisor, little_endian; | |
7444 | CPUBreakpoint *bp; | |
7445 | int j, lj = -1; | |
7446 | int num_insns; | |
7447 | int max_insns; | |
7448 | ||
7449 | pc_start = tb->pc; | |
7450 | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; | |
7451 | #if defined(OPTIMIZE_FPRF_UPDATE) | |
7452 | gen_fprf_ptr = gen_fprf_buf; | |
7453 | #endif | |
7454 | ctx.nip = pc_start; | |
7455 | ctx.tb = tb; | |
7456 | ctx.exception = POWERPC_EXCP_NONE; | |
7457 | ctx.spr_cb = env->spr_cb; | |
7458 | supervisor = env->mmu_idx; | |
7459 | #if !defined(CONFIG_USER_ONLY) | |
7460 | ctx.supervisor = supervisor; | |
7461 | #endif | |
7462 | little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0; | |
7463 | #if defined(TARGET_PPC64) | |
7464 | ctx.sf_mode = msr_sf; | |
7465 | ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian; | |
7466 | #else | |
7467 | ctx.mem_idx = (supervisor << 1) | little_endian; | |
7468 | #endif | |
7469 | ctx.fpu_enabled = msr_fp; | |
7470 | if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) | |
7471 | ctx.spe_enabled = msr_spe; | |
7472 | else | |
7473 | ctx.spe_enabled = 0; | |
7474 | if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) | |
7475 | ctx.altivec_enabled = msr_vr; | |
7476 | else | |
7477 | ctx.altivec_enabled = 0; | |
7478 | if ((env->flags & POWERPC_FLAG_SE) && msr_se) | |
7479 | ctx.singlestep_enabled = CPU_SINGLE_STEP; | |
7480 | else | |
7481 | ctx.singlestep_enabled = 0; | |
7482 | if ((env->flags & POWERPC_FLAG_BE) && msr_be) | |
7483 | ctx.singlestep_enabled |= CPU_BRANCH_STEP; | |
7484 | if (unlikely(env->singlestep_enabled)) | |
7485 | ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP; | |
7486 | #if defined (DO_SINGLE_STEP) && 0 | |
7487 | /* Single step trace mode */ | |
7488 | msr_se = 1; | |
7489 | #endif | |
7490 | num_insns = 0; | |
7491 | max_insns = tb->cflags & CF_COUNT_MASK; | |
7492 | if (max_insns == 0) | |
7493 | max_insns = CF_COUNT_MASK; | |
7494 | ||
7495 | gen_icount_start(); | |
7496 | /* Set env in case of segfault during code fetch */ | |
7497 | while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) { | |
7498 | if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) { | |
7499 | TAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
7500 | if (bp->pc == ctx.nip) { | |
7501 | gen_update_nip(&ctx, ctx.nip); | |
7502 | gen_helper_raise_debug(); | |
7503 | break; | |
7504 | } | |
7505 | } | |
7506 | } | |
7507 | if (unlikely(search_pc)) { | |
7508 | j = gen_opc_ptr - gen_opc_buf; | |
7509 | if (lj < j) { | |
7510 | lj++; | |
7511 | while (lj < j) | |
7512 | gen_opc_instr_start[lj++] = 0; | |
7513 | gen_opc_pc[lj] = ctx.nip; | |
7514 | gen_opc_instr_start[lj] = 1; | |
7515 | gen_opc_icount[lj] = num_insns; | |
7516 | } | |
7517 | } | |
7518 | #if defined PPC_DEBUG_DISAS | |
7519 | if (loglevel & CPU_LOG_TB_IN_ASM) { | |
7520 | fprintf(logfile, "----------------\n"); | |
7521 | fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n", | |
7522 | ctx.nip, supervisor, (int)msr_ir); | |
7523 | } | |
7524 | #endif | |
7525 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) | |
7526 | gen_io_start(); | |
7527 | if (unlikely(little_endian)) { | |
7528 | ctx.opcode = bswap32(ldl_code(ctx.nip)); | |
7529 | } else { | |
7530 | ctx.opcode = ldl_code(ctx.nip); | |
7531 | } | |
7532 | #if defined PPC_DEBUG_DISAS | |
7533 | if (loglevel & CPU_LOG_TB_IN_ASM) { | |
7534 | fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n", | |
7535 | ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), | |
7536 | opc3(ctx.opcode), little_endian ? "little" : "big"); | |
7537 | } | |
7538 | #endif | |
7539 | ctx.nip += 4; | |
7540 | table = env->opcodes; | |
7541 | num_insns++; | |
7542 | handler = table[opc1(ctx.opcode)]; | |
7543 | if (is_indirect_opcode(handler)) { | |
7544 | table = ind_table(handler); | |
7545 | handler = table[opc2(ctx.opcode)]; | |
7546 | if (is_indirect_opcode(handler)) { | |
7547 | table = ind_table(handler); | |
7548 | handler = table[opc3(ctx.opcode)]; | |
7549 | } | |
7550 | } | |
7551 | /* Is opcode *REALLY* valid ? */ | |
7552 | if (unlikely(handler->handler == &gen_invalid)) { | |
7553 | if (loglevel != 0) { | |
7554 | fprintf(logfile, "invalid/unsupported opcode: " | |
7555 | "%02x - %02x - %02x (%08x) " ADDRX " %d\n", | |
7556 | opc1(ctx.opcode), opc2(ctx.opcode), | |
7557 | opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir); | |
7558 | } else { | |
7559 | printf("invalid/unsupported opcode: " | |
7560 | "%02x - %02x - %02x (%08x) " ADDRX " %d\n", | |
7561 | opc1(ctx.opcode), opc2(ctx.opcode), | |
7562 | opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir); | |
7563 | } | |
7564 | } else { | |
7565 | if (unlikely((ctx.opcode & handler->inval) != 0)) { | |
7566 | if (loglevel != 0) { | |
7567 | fprintf(logfile, "invalid bits: %08x for opcode: " | |
7568 | "%02x - %02x - %02x (%08x) " ADDRX "\n", | |
7569 | ctx.opcode & handler->inval, opc1(ctx.opcode), | |
7570 | opc2(ctx.opcode), opc3(ctx.opcode), | |
7571 | ctx.opcode, ctx.nip - 4); | |
7572 | } else { | |
7573 | printf("invalid bits: %08x for opcode: " | |
7574 | "%02x - %02x - %02x (%08x) " ADDRX "\n", | |
7575 | ctx.opcode & handler->inval, opc1(ctx.opcode), | |
7576 | opc2(ctx.opcode), opc3(ctx.opcode), | |
7577 | ctx.opcode, ctx.nip - 4); | |
7578 | } | |
7579 | GEN_EXCP_INVAL(ctxp); | |
7580 | break; | |
7581 | } | |
7582 | } | |
7583 | (*(handler->handler))(&ctx); | |
7584 | #if defined(DO_PPC_STATISTICS) | |
7585 | handler->count++; | |
7586 | #endif | |
7587 | /* Check trace mode exceptions */ | |
7588 | if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP && | |
7589 | (ctx.nip <= 0x100 || ctx.nip > 0xF00) && | |
7590 | ctx.exception != POWERPC_SYSCALL && | |
7591 | ctx.exception != POWERPC_EXCP_TRAP && | |
7592 | ctx.exception != POWERPC_EXCP_BRANCH)) { | |
7593 | GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0); | |
7594 | } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) || | |
7595 | (env->singlestep_enabled) || | |
7596 | num_insns >= max_insns)) { | |
7597 | /* if we reach a page boundary or are single stepping, stop | |
7598 | * generation | |
7599 | */ | |
7600 | break; | |
7601 | } | |
7602 | #if defined (DO_SINGLE_STEP) | |
7603 | break; | |
7604 | #endif | |
7605 | } | |
7606 | if (tb->cflags & CF_LAST_IO) | |
7607 | gen_io_end(); | |
7608 | if (ctx.exception == POWERPC_EXCP_NONE) { | |
7609 | gen_goto_tb(&ctx, 0, ctx.nip); | |
7610 | } else if (ctx.exception != POWERPC_EXCP_BRANCH) { | |
7611 | if (unlikely(env->singlestep_enabled)) { | |
7612 | gen_update_nip(&ctx, ctx.nip); | |
7613 | gen_helper_raise_debug(); | |
7614 | } | |
7615 | /* Generate the return instruction */ | |
7616 | tcg_gen_exit_tb(0); | |
7617 | } | |
7618 | gen_icount_end(tb, num_insns); | |
7619 | *gen_opc_ptr = INDEX_op_end; | |
7620 | if (unlikely(search_pc)) { | |
7621 | j = gen_opc_ptr - gen_opc_buf; | |
7622 | lj++; | |
7623 | while (lj <= j) | |
7624 | gen_opc_instr_start[lj++] = 0; | |
7625 | } else { | |
7626 | tb->size = ctx.nip - pc_start; | |
7627 | tb->icount = num_insns; | |
7628 | } | |
7629 | #if defined(DEBUG_DISAS) | |
7630 | if (loglevel & CPU_LOG_TB_CPU) { | |
7631 | fprintf(logfile, "---------------- excp: %04x\n", ctx.exception); | |
7632 | cpu_dump_state(env, logfile, fprintf, 0); | |
7633 | } | |
7634 | if (loglevel & CPU_LOG_TB_IN_ASM) { | |
7635 | int flags; | |
7636 | flags = env->bfd_mach; | |
7637 | flags |= little_endian << 16; | |
7638 | fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start)); | |
7639 | target_disas(logfile, pc_start, ctx.nip - pc_start, flags); | |
7640 | fprintf(logfile, "\n"); | |
7641 | } | |
7642 | #endif | |
7643 | } | |
7644 | ||
7645 | void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb) | |
7646 | { | |
7647 | gen_intermediate_code_internal(env, tb, 0); | |
7648 | } | |
7649 | ||
7650 | void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb) | |
7651 | { | |
7652 | gen_intermediate_code_internal(env, tb, 1); | |
7653 | } | |
7654 | ||
7655 | void gen_pc_load(CPUState *env, TranslationBlock *tb, | |
7656 | unsigned long searched_pc, int pc_pos, void *puc) | |
7657 | { | |
7658 | env->nip = gen_opc_pc[pc_pos]; | |
7659 | } |