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1 | #ifndef CPU_SPARC_H | |
2 | #define CPU_SPARC_H | |
3 | ||
4 | #include "config.h" | |
5 | ||
6 | #if !defined(TARGET_SPARC64) | |
7 | #define TARGET_LONG_BITS 32 | |
8 | #define TARGET_FPREGS 32 | |
9 | #define TARGET_FPREG_T float | |
10 | #else | |
11 | #define TARGET_LONG_BITS 64 | |
12 | #define TARGET_FPREGS 64 | |
13 | #define TARGET_FPREG_T double | |
14 | #endif | |
15 | ||
16 | #include "cpu-defs.h" | |
17 | ||
18 | /*#define EXCP_INTERRUPT 0x100*/ | |
19 | ||
20 | /* trap definitions */ | |
21 | #define TT_TFAULT 0x01 | |
22 | #define TT_ILL_INSN 0x02 | |
23 | #define TT_PRIV_INSN 0x03 | |
24 | #define TT_NFPU_INSN 0x04 | |
25 | #define TT_WIN_OVF 0x05 | |
26 | #define TT_WIN_UNF 0x06 | |
27 | #define TT_FP_EXCP 0x08 | |
28 | #define TT_DFAULT 0x09 | |
29 | #define TT_EXTINT 0x10 | |
30 | #define TT_DIV_ZERO 0x2a | |
31 | #define TT_TRAP 0x80 | |
32 | ||
33 | #define PSR_NEG (1<<23) | |
34 | #define PSR_ZERO (1<<22) | |
35 | #define PSR_OVF (1<<21) | |
36 | #define PSR_CARRY (1<<20) | |
37 | #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY) | |
38 | #define PSR_EF (1<<12) | |
39 | #define PSR_PIL 0xf00 | |
40 | #define PSR_S (1<<7) | |
41 | #define PSR_PS (1<<6) | |
42 | #define PSR_ET (1<<5) | |
43 | #define PSR_CWP 0x1f | |
44 | ||
45 | /* Trap base register */ | |
46 | #define TBR_BASE_MASK 0xfffff000 | |
47 | ||
48 | /* Fcc */ | |
49 | #define FSR_RD1 (1<<31) | |
50 | #define FSR_RD0 (1<<30) | |
51 | #define FSR_RD_MASK (FSR_RD1 | FSR_RD0) | |
52 | #define FSR_RD_NEAREST 0 | |
53 | #define FSR_RD_ZERO FSR_RD0 | |
54 | #define FSR_RD_POS FSR_RD1 | |
55 | #define FSR_RD_NEG (FSR_RD1 | FSR_RD0) | |
56 | ||
57 | #define FSR_NVM (1<<27) | |
58 | #define FSR_OFM (1<<26) | |
59 | #define FSR_UFM (1<<25) | |
60 | #define FSR_DZM (1<<24) | |
61 | #define FSR_NXM (1<<23) | |
62 | #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM) | |
63 | ||
64 | #define FSR_NVA (1<<9) | |
65 | #define FSR_OFA (1<<8) | |
66 | #define FSR_UFA (1<<7) | |
67 | #define FSR_DZA (1<<6) | |
68 | #define FSR_NXA (1<<5) | |
69 | #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) | |
70 | ||
71 | #define FSR_NVC (1<<4) | |
72 | #define FSR_OFC (1<<3) | |
73 | #define FSR_UFC (1<<2) | |
74 | #define FSR_DZC (1<<1) | |
75 | #define FSR_NXC (1<<0) | |
76 | #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) | |
77 | ||
78 | #define FSR_FTT2 (1<<16) | |
79 | #define FSR_FTT1 (1<<15) | |
80 | #define FSR_FTT0 (1<<14) | |
81 | #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0) | |
82 | #define FSR_FTT_IEEE_EXCP (1 << 14) | |
83 | #define FSR_FTT_UNIMPFPOP (3 << 14) | |
84 | #define FSR_FTT_INVAL_FPR (6 << 14) | |
85 | ||
86 | #define FSR_FCC1 (1<<11) | |
87 | #define FSR_FCC0 (1<<10) | |
88 | ||
89 | /* MMU */ | |
90 | #define MMU_E (1<<0) | |
91 | #define MMU_NF (1<<1) | |
92 | ||
93 | #define PTE_ENTRYTYPE_MASK 3 | |
94 | #define PTE_ACCESS_MASK 0x1c | |
95 | #define PTE_ACCESS_SHIFT 2 | |
96 | #define PTE_PPN_SHIFT 7 | |
97 | #define PTE_ADDR_MASK 0xffffff00 | |
98 | ||
99 | #define PG_ACCESSED_BIT 5 | |
100 | #define PG_MODIFIED_BIT 6 | |
101 | #define PG_CACHE_BIT 7 | |
102 | ||
103 | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) | |
104 | #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT) | |
105 | #define PG_CACHE_MASK (1 << PG_CACHE_BIT) | |
106 | ||
107 | #define NWINDOWS 32 | |
108 | ||
109 | typedef struct CPUSPARCState { | |
110 | target_ulong gregs[8]; /* general registers */ | |
111 | target_ulong *regwptr; /* pointer to current register window */ | |
112 | TARGET_FPREG_T fpr[TARGET_FPREGS]; /* floating point registers */ | |
113 | target_ulong pc; /* program counter */ | |
114 | target_ulong npc; /* next program counter */ | |
115 | target_ulong y; /* multiply/divide register */ | |
116 | uint32_t psr; /* processor state register */ | |
117 | uint32_t fsr; /* FPU state register */ | |
118 | uint32_t cwp; /* index of current register window (extracted | |
119 | from PSR) */ | |
120 | uint32_t wim; /* window invalid mask */ | |
121 | uint32_t tbr; /* trap base register */ | |
122 | int psrs; /* supervisor mode (extracted from PSR) */ | |
123 | int psrps; /* previous supervisor mode */ | |
124 | int psret; /* enable traps */ | |
125 | int psrpil; /* interrupt level */ | |
126 | int psref; /* enable fpu */ | |
127 | jmp_buf jmp_env; | |
128 | int user_mode_only; | |
129 | int exception_index; | |
130 | int interrupt_index; | |
131 | int interrupt_request; | |
132 | struct TranslationBlock *current_tb; | |
133 | void *opaque; | |
134 | /* NOTE: we allow 8 more registers to handle wrapping */ | |
135 | target_ulong regbase[NWINDOWS * 16 + 8]; | |
136 | ||
137 | /* in order to avoid passing too many arguments to the memory | |
138 | write helpers, we store some rarely used information in the CPU | |
139 | context) */ | |
140 | unsigned long mem_write_pc; /* host pc at which the memory was | |
141 | written */ | |
142 | unsigned long mem_write_vaddr; /* target virtual addr at which the | |
143 | memory was written */ | |
144 | /* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */ | |
145 | CPUTLBEntry tlb_read[2][CPU_TLB_SIZE]; | |
146 | CPUTLBEntry tlb_write[2][CPU_TLB_SIZE]; | |
147 | /* MMU regs */ | |
148 | uint32_t mmuregs[16]; | |
149 | /* temporary float registers */ | |
150 | float ft0, ft1, ft2; | |
151 | double dt0, dt1, dt2; | |
152 | #if defined(TARGET_SPARC64) | |
153 | target_ulong t0, t1, t2; | |
154 | #endif | |
155 | ||
156 | /* ice debug support */ | |
157 | target_ulong breakpoints[MAX_BREAKPOINTS]; | |
158 | int nb_breakpoints; | |
159 | int singlestep_enabled; /* XXX: should use CPU single step mode instead */ | |
160 | ||
161 | } CPUSPARCState; | |
162 | ||
163 | CPUSPARCState *cpu_sparc_init(void); | |
164 | int cpu_sparc_exec(CPUSPARCState *s); | |
165 | int cpu_sparc_close(CPUSPARCState *s); | |
166 | void cpu_get_fp64(uint64_t *pmant, uint16_t *pexp, double f); | |
167 | double cpu_put_fp64(uint64_t mant, uint16_t exp); | |
168 | ||
169 | /* Fake impl 0, version 4 */ | |
170 | #define GET_PSR(env) ((0 << 28) | (4 << 24) | (env->psr & PSR_ICC) | \ | |
171 | (env->psref? PSR_EF : 0) | \ | |
172 | (env->psrpil << 8) | \ | |
173 | (env->psrs? PSR_S : 0) | \ | |
174 | (env->psrs? PSR_PS : 0) | \ | |
175 | (env->psret? PSR_ET : 0) | env->cwp) | |
176 | ||
177 | #ifndef NO_CPU_IO_DEFS | |
178 | void cpu_set_cwp(CPUSPARCState *env1, int new_cwp); | |
179 | #endif | |
180 | ||
181 | #define PUT_PSR(env, val) do { int _tmp = val; \ | |
182 | env->psr = _tmp & PSR_ICC; \ | |
183 | env->psref = (_tmp & PSR_EF)? 1 : 0; \ | |
184 | env->psrpil = (_tmp & PSR_PIL) >> 8; \ | |
185 | env->psrs = (_tmp & PSR_S)? 1 : 0; \ | |
186 | env->psrps = (_tmp & PSR_PS)? 1 : 0; \ | |
187 | env->psret = (_tmp & PSR_ET)? 1 : 0; \ | |
188 | cpu_set_cwp(env, _tmp & PSR_CWP & (NWINDOWS - 1)); \ | |
189 | } while (0) | |
190 | ||
191 | struct siginfo; | |
192 | int cpu_sparc_signal_handler(int hostsignum, struct siginfo *info, void *puc); | |
193 | ||
194 | #define TARGET_PAGE_BITS 12 /* 4k */ | |
195 | #include "cpu-all.h" | |
196 | ||
197 | #endif |