2 // Copyright (c) 2011 - 2013 ARM LTD. All rights reserved.<BR>
3 // Portion of Copyright (c) 2014 NVIDIA Corporation. All rights reserved.<BR>
5 // This program and the accompanying materials
6 // are licensed and made available under the terms and conditions of the BSD License
7 // which accompanies this distribution. The full text of the license may be found at
8 // http://opensource.org/licenses/bsd-license.php
10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 //------------------------------------------------------------------------------
15 #include <Library/PcdLib.h>
16 #include <AsmMacroIoLibV8.h>
19 This is the stack constructed by the exception handler (low address to high address).
20 X0 to FAR makes up the EFI_SYSTEM_CONTEXT for AArch64.
51 UINT64 FP; 0x0e8 // x29 - Frame Pointer
52 UINT64 LR; 0x0f0 // x30 - Link Register
53 UINT64 SP; 0x0f8 // x31 - Stack Pointer
55 // FP/SIMD Registers. 128bit if used as Q-regs.
90 UINT64 ELR; 0x300 // Exception Link Register
91 UINT64 SPSR; 0x308 // Saved Processor Status Register
92 UINT64 FPSR; 0x310 // Floating Point Status Register
93 UINT64 ESR; 0x318 // EL1 Fault Address Register
94 UINT64 FAR; 0x320 // EL1 Exception syndrome register
95 UINT64 Padding;0x328 // Required for stack alignment
98 ASM_GLOBAL ASM_PFX(ExceptionHandlersStart)
99 ASM_GLOBAL ASM_PFX(ExceptionHandlersEnd)
100 ASM_GLOBAL ASM_PFX(CommonExceptionEntry)
101 ASM_GLOBAL ASM_PFX(AsmCommonExceptionEntry)
102 ASM_GLOBAL ASM_PFX(CommonCExceptionHandler)
107 #define GP_CONTEXT_SIZE (32 * 8)
108 #define FP_CONTEXT_SIZE (32 * 16)
109 #define SYS_CONTEXT_SIZE ( 6 * 8) // 5 SYS regs + Alignment requirement (ie: the stack must be aligned on 0x10)
111 // Cannot str x31 directly
112 #define ALL_GP_REGS \
113 REG_PAIR (x0, x1, 0x000, GP_CONTEXT_SIZE); \
114 REG_PAIR (x2, x3, 0x010, GP_CONTEXT_SIZE); \
115 REG_PAIR (x4, x5, 0x020, GP_CONTEXT_SIZE); \
116 REG_PAIR (x6, x7, 0x030, GP_CONTEXT_SIZE); \
117 REG_PAIR (x8, x9, 0x040, GP_CONTEXT_SIZE); \
118 REG_PAIR (x10, x11, 0x050, GP_CONTEXT_SIZE); \
119 REG_PAIR (x12, x13, 0x060, GP_CONTEXT_SIZE); \
120 REG_PAIR (x14, x15, 0x070, GP_CONTEXT_SIZE); \
121 REG_PAIR (x16, x17, 0x080, GP_CONTEXT_SIZE); \
122 REG_PAIR (x18, x19, 0x090, GP_CONTEXT_SIZE); \
123 REG_PAIR (x20, x21, 0x0a0, GP_CONTEXT_SIZE); \
124 REG_PAIR (x22, x23, 0x0b0, GP_CONTEXT_SIZE); \
125 REG_PAIR (x24, x25, 0x0c0, GP_CONTEXT_SIZE); \
126 REG_PAIR (x26, x27, 0x0d0, GP_CONTEXT_SIZE); \
127 REG_PAIR (x28, x29, 0x0e0, GP_CONTEXT_SIZE); \
128 REG_ONE (x30, 0x0f0, GP_CONTEXT_SIZE);
130 // In order to save the SP we need to put it somwhere else first.
131 // STR only works with XZR/WZR directly
133 add x1, sp, FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE; \
134 REG_ONE (x1, 0x0f8, GP_CONTEXT_SIZE);
136 #define ALL_FP_REGS \
137 REG_PAIR (q0, q1, 0x000, FP_CONTEXT_SIZE); \
138 REG_PAIR (q2, q3, 0x020, FP_CONTEXT_SIZE); \
139 REG_PAIR (q4, q5, 0x040, FP_CONTEXT_SIZE); \
140 REG_PAIR (q6, q7, 0x060, FP_CONTEXT_SIZE); \
141 REG_PAIR (q8, q9, 0x080, FP_CONTEXT_SIZE); \
142 REG_PAIR (q10, q11, 0x0a0, FP_CONTEXT_SIZE); \
143 REG_PAIR (q12, q13, 0x0c0, FP_CONTEXT_SIZE); \
144 REG_PAIR (q14, q15, 0x0e0, FP_CONTEXT_SIZE); \
145 REG_PAIR (q16, q17, 0x100, FP_CONTEXT_SIZE); \
146 REG_PAIR (q18, q19, 0x120, FP_CONTEXT_SIZE); \
147 REG_PAIR (q20, q21, 0x140, FP_CONTEXT_SIZE); \
148 REG_PAIR (q22, q23, 0x160, FP_CONTEXT_SIZE); \
149 REG_PAIR (q24, q25, 0x180, FP_CONTEXT_SIZE); \
150 REG_PAIR (q26, q27, 0x1a0, FP_CONTEXT_SIZE); \
151 REG_PAIR (q28, q29, 0x1c0, FP_CONTEXT_SIZE); \
152 REG_PAIR (q30, q31, 0x1e0, FP_CONTEXT_SIZE);
154 #define ALL_SYS_REGS \
155 REG_PAIR (x1, x2, 0x000, SYS_CONTEXT_SIZE); \
156 REG_PAIR (x3, x4, 0x010, SYS_CONTEXT_SIZE); \
157 REG_ONE (x5, 0x020, SYS_CONTEXT_SIZE);
160 // This code gets copied to the ARM vector table
161 // VectorTableStart - VectorTableEnd gets copied
163 ASM_PFX(ExceptionHandlersStart):
166 // Current EL with SP0 : 0x0 - 0x180
169 ASM_PFX(SynchronousExceptionSP0):
170 b ASM_PFX(SynchronousExceptionEntry)
182 b ASM_PFX(SErrorEntry)
185 // Current EL with SPx: 0x200 - 0x380
188 ASM_PFX(SynchronousExceptionSPx):
189 b ASM_PFX(SynchronousExceptionEntry)
201 b ASM_PFX(SErrorEntry)
204 // Lower EL using AArch64 : 0x400 - 0x580
207 ASM_PFX(SynchronousExceptionA64):
208 b ASM_PFX(SynchronousExceptionEntry)
220 b ASM_PFX(SErrorEntry)
223 // Lower EL using AArch32 : 0x0 - 0x180
226 ASM_PFX(SynchronousExceptionA32):
227 b ASM_PFX(SynchronousExceptionEntry)
239 b ASM_PFX(SErrorEntry)
244 #define REG_PAIR(REG1, REG2, OFFSET, CONTEXT_SIZE) stp REG1, REG2, [sp, #(OFFSET-CONTEXT_SIZE)]
245 #define REG_ONE(REG1, OFFSET, CONTEXT_SIZE) str REG1, [sp, #(OFFSET-CONTEXT_SIZE)]
247 ASM_PFX(SynchronousExceptionEntry):
248 // Move the stackpointer so we can reach our structure with the str instruction.
249 sub sp, sp, FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE
251 // Save all the General regs before touching x0 and x1.
252 // This does not save r31(SP) as it is special. We do that later.
255 // Record the tipe of exception that occured.
256 mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
258 // Jump to our general handler to deal with all the common parts and process the exception.
259 ldr x1, ASM_PFX(CommonExceptionEntry)
263 sub sp, sp, FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE
265 mov x0, #EXCEPT_AARCH64_IRQ
266 ldr x1, ASM_PFX(CommonExceptionEntry)
270 sub sp, sp, FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE
272 mov x0, #EXCEPT_AARCH64_FIQ
273 ldr x1, ASM_PFX(CommonExceptionEntry)
276 ASM_PFX(SErrorEntry):
277 sub sp, sp, FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE
279 mov x0, #EXCEPT_AARCH64_SERROR
280 ldr x1, ASM_PFX(CommonExceptionEntry)
285 // This gets patched by the C code that patches in the vector table
288 ASM_PFX(CommonExceptionEntry):
289 .dword ASM_PFX(AsmCommonExceptionEntry)
291 ASM_PFX(ExceptionHandlersEnd):
296 // This code runs from CpuDxe driver loaded address. It is patched into
297 // CommonExceptionEntry.
299 ASM_PFX(AsmCommonExceptionEntry):
301 We have to break up the save code because the immidiate value to be used
302 with the SP is to big to do it all in one step so we need to shuffle the SP
303 along as we go. (we only have 9bits of immediate to work with) */
305 // Save the current Stack pointer before we start modifying it.
308 // Preserve the stack pointer we came in with before we modify it
310 1:mrs x1, elr_el1 // Exception Link Register
311 mrs x2, spsr_el1 // Saved Processor Status Register 32bit
312 mrs x3, fpsr // Floating point Status Register 32bit
313 mrs x4, esr_el1 // EL1 Exception syndrome register 32bit
314 mrs x5, far_el1 // EL1 Fault Address Register
317 2:mrs x1, elr_el2 // Exception Link Register
318 mrs x2, spsr_el2 // Saved Processor Status Register 32bit
319 mrs x3, fpsr // Floating point Status Register 32bit
320 mrs x4, esr_el2 // EL1 Exception syndrome register 32bit
321 mrs x5, far_el2 // EL1 Fault Address Register
323 // Adjust SP to save next set
324 3:add sp, sp, FP_CONTEXT_SIZE
326 // Push FP regs to Stack.
329 // Adjust SP to save next set
330 add sp, sp, SYS_CONTEXT_SIZE
335 // Point to top of struct after all regs saved
336 sub sp, sp, GP_CONTEXT_SIZE + FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE
338 // x0 still holds the exception type.
339 // Set x1 to point to the top of our struct on the Stack
342 // CommonCExceptionHandler (
343 // IN EFI_EXCEPTION_TYPE ExceptionType, R0
344 // IN OUT EFI_SYSTEM_CONTEXT SystemContext R1
347 // Call the handler as defined above
349 // For now we spin in the handler if we received an abort of some kind.
350 // We do not try to recover.
351 bl ASM_PFX(CommonCExceptionHandler) // Call exception handler
354 // Defines for popping from stack
358 #define REG_PAIR(REG1, REG2, OFFSET, CONTEXT_SIZE) ldp REG1, REG2, [sp, #(OFFSET-CONTEXT_SIZE)]
360 #define REG_ONE(REG1, OFFSET, CONTEXT_SIZE) ldr REG1, [sp, #(OFFSET-CONTEXT_SIZE)]
362 // Adjust SP to pop system registers
363 add sp, sp, GP_CONTEXT_SIZE + FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE
367 1:msr elr_el1, x1 // Exception Link Register
368 msr spsr_el1,x2 // Saved Processor Status Register 32bit
369 msr fpsr, x3 // Floating point Status Register 32bit
370 msr esr_el1, x4 // EL1 Exception syndrome register 32bit
371 msr far_el1, x5 // EL1 Fault Address Register
373 2:msr elr_el2, x1 // Exception Link Register
374 msr spsr_el2,x2 // Saved Processor Status Register 32bit
375 msr fpsr, x3 // Floating point Status Register 32bit
376 msr esr_el2, x4 // EL1 Exception syndrome register 32bit
377 msr far_el2, x5 // EL1 Fault Address Register
379 3:// pop all regs and return from exception.
380 sub sp, sp, FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE
383 // Adjust SP to pop next set
384 add sp, sp, FP_CONTEXT_SIZE
385 // Pop FP regs to Stack.
388 // Adjust SP to be where we started from when we came into the handler.
389 // The handler can not change the SP.
390 add sp, sp, SYS_CONTEXT_SIZE