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git.proxmox.com Git - mirror_edk2.git/blob - ArmPkg/Include/Chipset/AArch64.h
3 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
4 Copyright (c) 2011 - 2017, ARM Ltd. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 #include <Chipset/AArch64Mmu.h>
21 // ARM Interrupt ID in Exception Table
22 #define ARM_ARCH_EXCEPTION_IRQ EXCEPT_AARCH64_IRQ
24 // CPACR - Coprocessor Access Control Register definitions
25 #define CPACR_TTA_EN (1UL << 28)
26 #define CPACR_FPEN_EL1 (1UL << 20)
27 #define CPACR_FPEN_FULL (3UL << 20)
28 #define CPACR_CP_FULL_ACCESS 0x300000
30 // Coprocessor Trap Register (CPTR)
31 #define AARCH64_CPTR_TFP (1 << 10)
33 // ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions
34 #define AARCH64_PFR0_FP (0xF << 16)
35 #define AARCH64_PFR0_GIC (0xF << 24)
37 // SCR - Secure Configuration Register definitions
38 #define SCR_NS (1 << 0)
39 #define SCR_IRQ (1 << 1)
40 #define SCR_FIQ (1 << 2)
41 #define SCR_EA (1 << 3)
42 #define SCR_FW (1 << 4)
43 #define SCR_AW (1 << 5)
45 // MIDR - Main ID Register definitions
46 #define ARM_CPU_TYPE_SHIFT 4
47 #define ARM_CPU_TYPE_MASK 0xFFF
48 #define ARM_CPU_TYPE_AEMv8 0xD0F
49 #define ARM_CPU_TYPE_A53 0xD03
50 #define ARM_CPU_TYPE_A57 0xD07
51 #define ARM_CPU_TYPE_A72 0xD08
52 #define ARM_CPU_TYPE_A15 0xC0F
53 #define ARM_CPU_TYPE_A9 0xC09
54 #define ARM_CPU_TYPE_A7 0xC07
55 #define ARM_CPU_TYPE_A5 0xC05
57 #define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )
58 #define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))
60 // Hypervisor Configuration Register
61 #define ARM_HCR_FMO BIT3
62 #define ARM_HCR_IMO BIT4
63 #define ARM_HCR_AMO BIT5
64 #define ARM_HCR_TSC BIT19
65 #define ARM_HCR_TGE BIT27
67 // Exception Syndrome Register
68 #define AARCH64_ESR_EC(Ecr) ((0x3F << 26) & (Ecr))
69 #define AARCH64_ESR_ISS(Ecr) ((0x1FFFFFF) & (Ecr))
71 #define AARCH64_ESR_EC_SMC32 (0x13 << 26)
72 #define AARCH64_ESR_EC_SMC64 (0x17 << 26)
74 // AArch64 Exception Level
75 #define AARCH64_EL3 0xC
76 #define AARCH64_EL2 0x8
77 #define AARCH64_EL1 0x4
79 // Saved Program Status Register definitions
84 #define SPSR_AARCH32 BIT4
86 #define SPSR_AARCH32_MODE_USER 0x0
87 #define SPSR_AARCH32_MODE_FIQ 0x1
88 #define SPSR_AARCH32_MODE_IRQ 0x2
89 #define SPSR_AARCH32_MODE_SVC 0x3
90 #define SPSR_AARCH32_MODE_ABORT 0x7
91 #define SPSR_AARCH32_MODE_UNDEF 0xB
92 #define SPSR_AARCH32_MODE_SYS 0xF
94 // Counter-timer Hypervisor Control register definitions
95 #define CNTHCTL_EL2_EL1PCTEN BIT0
96 #define CNTHCTL_EL2_EL1PCEN BIT1
98 #define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1)
100 // Vector table offset definitions
101 #define ARM_VECTOR_CUR_SP0_SYNC 0x000
102 #define ARM_VECTOR_CUR_SP0_IRQ 0x080
103 #define ARM_VECTOR_CUR_SP0_FIQ 0x100
104 #define ARM_VECTOR_CUR_SP0_SERR 0x180
106 #define ARM_VECTOR_CUR_SPx_SYNC 0x200
107 #define ARM_VECTOR_CUR_SPx_IRQ 0x280
108 #define ARM_VECTOR_CUR_SPx_FIQ 0x300
109 #define ARM_VECTOR_CUR_SPx_SERR 0x380
111 #define ARM_VECTOR_LOW_A64_SYNC 0x400
112 #define ARM_VECTOR_LOW_A64_IRQ 0x480
113 #define ARM_VECTOR_LOW_A64_FIQ 0x500
114 #define ARM_VECTOR_LOW_A64_SERR 0x580
116 #define ARM_VECTOR_LOW_A32_SYNC 0x600
117 #define ARM_VECTOR_LOW_A32_IRQ 0x680
118 #define ARM_VECTOR_LOW_A32_FIQ 0x700
119 #define ARM_VECTOR_LOW_A32_SERR 0x780
121 #define VECTOR_BASE(tbl) \
122 .section .text.##tbl##,"ax"; \
125 GCC_ASM_EXPORT(tbl); \
128 #define VECTOR_ENTRY(tbl, off) \
131 #define VECTOR_END(tbl) \
137 ArmEnableSWPInstruction (
185 ArmDisableAlignmentCheck (
191 ArmEnableAlignmentCheck (
197 ArmDisableStackAlignmentCheck (
203 ArmEnableStackAlignmentCheck (
209 ArmDisableAllExceptions (
229 PageAttributeToGcdAttribute (
230 IN UINT64 PageAttributes
248 #endif // __AARCH64_H__