1 #------------------------------------------------------------------------------
3 # Copyright (c) 2008-2009 Apple Inc. All rights reserved.
5 # All rights reserved. This program and the accompanying materials
6 # are licensed and made available under the terms and conditions of the BSD License
7 # which accompanies this distribution. The full text of the license may be found at
8 # http://opensource.org/licenses/bsd-license.php
10 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 #------------------------------------------------------------------------------
17 .globl ASM_PFX(ArmCleanInvalidateDataCache)
18 .globl ASM_PFX(ArmCleanDataCache)
19 .globl ASM_PFX(ArmInvalidateDataCache)
20 .globl ASM_PFX(ArmInvalidateInstructionCache)
21 .globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
22 .globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
23 .globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA)
24 .globl ASM_PFX(ArmEnableMmu)
25 .globl ASM_PFX(ArmDisableMmu)
26 .globl ASM_PFX(ArmMmuEnabled)
27 .globl ASM_PFX(ArmEnableDataCache)
28 .globl ASM_PFX(ArmDisableDataCache)
29 .globl ASM_PFX(ArmEnableInstructionCache)
30 .globl ASM_PFX(ArmDisableInstructionCache)
31 .globl ASM_PFX(ArmEnableBranchPrediction)
32 .globl ASM_PFX(ArmDisableBranchPrediction)
33 .globl ASM_PFX(ArmDataMemoryBarrier)
34 .globl ASM_PFX(ArmDataSyncronizationBarrier)
35 .globl ASM_PFX(ArmInstructionSynchronizationBarrier)
41 #------------------------------------------------------------------------------
43 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
44 mcr p15, 0, r0, c7, c6, 1 @ invalidate single data cache line
47 ASM_PFX(ArmCleanDataCacheEntryByMVA):
48 mcr p15, 0, r0, c7, c10, 1 @ clean single data cache line
51 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
52 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate single data cache line
55 ASM_PFX(ArmEnableInstructionCache):
57 mrc p15,0,r0,c1,c0,0 @Read control register configuration data
58 orr r0,r0,r1 @Set I bit
59 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
62 ASM_PFX(ArmDisableInstructionCache):
64 mrc p15,0,r0,c1,c0,0 @Read control register configuration data
65 bic r0,r0,r1 @Clear I bit.
66 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
69 ASM_PFX(ArmInvalidateInstructionCache):
71 mcr p15,0,r0,c7,c5,0 @Invalidate entire Instruction cache.
72 @Also flushes the branch target cache.
74 mcr p15,0,r0,c7,c10,4 @Data write buffer
77 ASM_PFX(ArmEnableMmu):
83 ASM_PFX(ArmMmuEnabled):
88 ASM_PFX(ArmDisableMmu):
93 mcr p15,0,R0,c7,c10,4 @Drain write buffer
96 ASM_PFX(ArmEnableDataCache):
98 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
99 orr R0,R0,R1 @Set C bit
100 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
103 ASM_PFX(ArmDisableDataCache):
105 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
106 bic R0,R0,R1 @Clear C bit
107 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
110 ASM_PFX(ArmCleanDataCache):
111 mrc p15,0,r15,c7,c10,3
112 bne ASM_PFX(ArmCleanDataCache)
114 mcr p15,0,R0,c7,c10,4 @Drain write buffer
117 ASM_PFX(ArmInvalidateDataCache):
119 mcr p15,0,R0,c7,c6,0 @Invalidate entire data cache
121 mcr p15,0,R0,c7,c10,4 @Drain write buffer
124 ASM_PFX(ArmCleanInvalidateDataCache):
125 mrc p15,0,r15,c7,c14,3
126 bne ASM_PFX(ArmCleanInvalidateDataCache)
128 mcr p15,0,R0,c7,c10,4 @Drain write buffer
131 ASM_PFX(ArmEnableBranchPrediction):
132 bx LR @Branch prediction is not supported.
134 ASM_PFX(ArmDisableBranchPrediction):
135 bx LR @Branch prediction is not supported.
137 ASM_PFX(ArmDataMemoryBarrier):
139 mcr P15, #0, R0, C7, C10, #5 @ check if this is OK?
142 ASM_PFX(ArmDataSyncronizationBarrier):
144 mcr P15, #0, R0, C7, C10, #4 @ check if this is OK?
147 ASM_PFX(ArmInstructionSynchronizationBarrier):
149 mcr P15, #0, R0, C7, C5, #4 @ check if this is OK?
152 ASM_FUNCTION_REMOVE_IF_UNREFERENCED