1 #========================================================================================
2 # Copyright (c) 2011-2013, ARM Limited. All rights reserved.
4 # This program and the accompanying materials
5 # are licensed and made available under the terms and conditions of the BSD License
6 # which accompanies this distribution. The full text of the license may be found at
7 # http:#opensource.org/licenses/bsd-license.php
9 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12 #=======================================================================================
14 #include <AsmMacroIoLibV8.h>
15 #include <Chipset/AArch64.h>
17 #start of the code section
21 ASM_GLOBAL ASM_PFX(SwitchToNSExceptionLevel1)
22 ASM_GLOBAL ASM_PFX(enter_monitor_mode)
23 ASM_GLOBAL ASM_PFX(return_from_exception)
24 ASM_GLOBAL ASM_PFX(copy_cpsr_into_spsr)
25 ASM_GLOBAL ASM_PFX(set_non_secure_mode)
27 // Switch from EL3 to NS-EL1
28 ASM_PFX(SwitchToNSExceptionLevel1):
29 // Now setup our EL1. Controlled by EL2 config on Model
30 mrs x0, hcr_el2 // Read EL2 Hypervisor configuration Register
31 orr x0, x0, #(1 << 31) // Set EL1 to be 64bit
33 // Send all interrupts to their respective Exception levels for EL2
34 bic x0, x0, #(1 << 3) // Disable virtual FIQ
35 bic x0, x0, #(1 << 4) // Disable virtual IRQ
36 bic x0, x0, #(1 << 5) // Disable virtual SError and Abort
37 msr hcr_el2, x0 // Write back our settings
39 msr cptr_el2, xzr // Disable copro traps to EL2
43 // Enable architected timer access
45 orr x0, x0, #3 // Enable EL1 access to timers
49 orr x0, x0, #3 // EL0 access to counters
61 // EL3 on AArch64 is Secure/monitor so this funtion is reduced vs ARMv7
62 // we don't need a mode switch, just setup the Arguments and jump.
63 // x0: Monitor World EntryPoint
66 // x3: Secure Monitor mode stack
67 ASM_PFX(enter_monitor_mode):
68 mov x4, x0 // Swap EntryPoint and MpId registers
74 // Put the address in correct ELR_ELx and do a eret.
75 // We may need to do some config before we change to another Mode.
76 ASM_PFX(return_from_exception):
80 // For AArch64 we need to construct the spsr we want from individual bits and pieces.
81 ASM_PFX(copy_cpsr_into_spsr):
82 mrs x0, CurrentEl // Get the current exception level we are running at.
83 mrs x1, SPSel // Which Stack are we using
85 mrs x1, daif // Which interrupts are enabled
87 msr spsr_el3, x0 // Write to spsr
90 // Get this from platform file.
91 ASM_PFX(set_non_secure_mode):
95 ASM_FUNCTION_REMOVE_IF_UNREFERENCED