3 Copyright (c) 2017 - 2020, ARM Limited. All rights reserved.
5 SPDX-License-Identifier: BSD-2-Clause-Patent
8 - Cm or CM - Configuration Manager
10 - Std or STD - Standard
13 #ifndef ARM_NAMESPACE_OBJECTS_H_
14 #define ARM_NAMESPACE_OBJECTS_H_
16 #include <StandardNameSpaceObjects.h>
20 /** The EARM_OBJECT_ID enum describes the Object IDs
23 typedef enum ArmObjectID
{
24 EArmObjReserved
, ///< 0 - Reserved
25 EArmObjBootArchInfo
, ///< 1 - Boot Architecture Info
26 EArmObjCpuInfo
, ///< 2 - CPU Info
27 EArmObjPowerManagementProfileInfo
, ///< 3 - Power Management Profile Info
28 EArmObjGicCInfo
, ///< 4 - GIC CPU Interface Info
29 EArmObjGicDInfo
, ///< 5 - GIC Distributor Info
30 EArmObjGicMsiFrameInfo
, ///< 6 - GIC MSI Frame Info
31 EArmObjGicRedistributorInfo
, ///< 7 - GIC Redistributor Info
32 EArmObjGicItsInfo
, ///< 8 - GIC ITS Info
33 EArmObjSerialConsolePortInfo
, ///< 9 - Serial Console Port Info
34 EArmObjSerialDebugPortInfo
, ///< 10 - Serial Debug Port Info
35 EArmObjGenericTimerInfo
, ///< 11 - Generic Timer Info
36 EArmObjPlatformGTBlockInfo
, ///< 12 - Platform GT Block Info
37 EArmObjGTBlockTimerFrameInfo
, ///< 13 - Generic Timer Block Frame Info
38 EArmObjPlatformGenericWatchdogInfo
, ///< 14 - Platform Generic Watchdog
39 EArmObjPciConfigSpaceInfo
, ///< 15 - PCI Configuration Space Info
40 EArmObjHypervisorVendorIdentity
, ///< 16 - Hypervisor Vendor Id
41 EArmObjFixedFeatureFlags
, ///< 17 - Fixed feature flags for FADT
42 EArmObjItsGroup
, ///< 18 - ITS Group
43 EArmObjNamedComponent
, ///< 19 - Named Component
44 EArmObjRootComplex
, ///< 20 - Root Complex
45 EArmObjSmmuV1SmmuV2
, ///< 21 - SMMUv1 or SMMUv2
46 EArmObjSmmuV3
, ///< 22 - SMMUv3
47 EArmObjPmcg
, ///< 23 - PMCG
48 EArmObjGicItsIdentifierArray
, ///< 24 - GIC ITS Identifier Array
49 EArmObjIdMappingArray
, ///< 25 - ID Mapping Array
50 EArmObjSmmuInterruptArray
, ///< 26 - SMMU Interrupt Array
51 EArmObjProcHierarchyInfo
, ///< 27 - Processor Hierarchy Info
52 EArmObjCacheInfo
, ///< 28 - Cache Info
53 EArmObjProcNodeIdInfo
, ///< 29 - Processor Node ID Info
54 EArmObjCmRef
, ///< 30 - CM Object Reference
55 EArmObjMemoryAffinityInfo
, ///< 31 - Memory Affinity Info
56 EArmObjDeviceHandleAcpi
, ///< 32 - Device Handle Acpi
57 EArmObjDeviceHandlePci
, ///< 33 - Device Handle Pci
58 EArmObjGenericInitiatorAffinityInfo
, ///< 34 - Generic Initiator Affinity
62 /** A structure that describes the
63 ARM Boot Architecture flags.
65 ID: EArmObjBootArchInfo
67 typedef struct CmArmBootArchInfo
{
68 /** This is the ARM_BOOT_ARCH flags field of the FADT Table
69 described in the ACPI Table Specification.
72 } CM_ARM_BOOT_ARCH_INFO
;
74 /** A structure that describes the
75 Power Management Profile Information for the Platform.
77 ID: EArmObjPowerManagementProfileInfo
79 typedef struct CmArmPowerManagementProfileInfo
{
80 /** This is the Preferred_PM_Profile field of the FADT Table
81 described in the ACPI Specification
83 UINT8 PowerManagementProfile
;
84 } CM_ARM_POWER_MANAGEMENT_PROFILE_INFO
;
86 /** A structure that describes the
87 GIC CPU Interface for the Platform.
91 typedef struct CmArmGicCInfo
{
92 /// The GIC CPU Interface number.
93 UINT32 CPUInterfaceNumber
;
95 /** The ACPI Processor UID. This must match the
96 _UID of the CPU Device object information described
97 in the DSDT/SSDT for the CPU.
99 UINT32 AcpiProcessorUid
;
101 /** The flags field as described by the GICC structure
102 in the ACPI Specification.
106 /** The parking protocol version field as described by
107 the GICC structure in the ACPI Specification.
109 UINT32 ParkingProtocolVersion
;
111 /** The Performance Interrupt field as described by
112 the GICC structure in the ACPI Specification.
114 UINT32 PerformanceInterruptGsiv
;
116 /** The CPU Parked address field as described by
117 the GICC structure in the ACPI Specification.
119 UINT64 ParkedAddress
;
121 /** The base address for the GIC CPU Interface
122 as described by the GICC structure in the
125 UINT64 PhysicalBaseAddress
;
127 /** The base address for GICV interface
128 as described by the GICC structure in the
133 /** The base address for GICH interface
134 as described by the GICC structure in the
139 /** The GICV maintenance interrupt
140 as described by the GICC structure in the
143 UINT32 VGICMaintenanceInterrupt
;
145 /** The base address for GICR interface
146 as described by the GICC structure in the
149 UINT64 GICRBaseAddress
;
151 /** The MPIDR for the CPU
152 as described by the GICC structure in the
157 /** The Processor Power Efficiency class
158 as described by the GICC structure in the
161 UINT8 ProcessorPowerEfficiencyClass
;
163 /** Statistical Profiling Extension buffer overflow GSIV. Zero if
164 unsupported by this processor. This field was introduced in
165 ACPI 6.3 (MADT revision 5) and is therefore ignored when
166 generating MADT revision 4 or lower.
168 UINT16 SpeOverflowInterrupt
;
170 /** The proximity domain to which the logical processor belongs.
171 This field is used to populate the GICC affinity structure
174 UINT32 ProximityDomain
;
176 /** The clock domain to which the logical processor belongs.
177 This field is used to populate the GICC affinity structure
182 /** The GICC Affinity flags field as described by the GICC Affinity structure
185 UINT32 AffinityFlags
;
188 /** A structure that describes the
189 GIC Distributor information for the Platform.
193 typedef struct CmArmGicDInfo
{
194 /// The Physical Base address for the GIC Distributor.
195 UINT64 PhysicalBaseAddress
;
197 /** The global system interrupt
198 number where this GIC Distributor's
199 interrupt inputs start.
201 UINT32 SystemVectorBase
;
203 /** The GIC version as described
204 by the GICD structure in the
210 /** A structure that describes the
211 GIC MSI Frame information for the Platform.
213 ID: EArmObjGicMsiFrameInfo
215 typedef struct CmArmGicMsiFrameInfo
{
216 /// The GIC MSI Frame ID
217 UINT32 GicMsiFrameId
;
219 /// The Physical base address for the MSI Frame
220 UINT64 PhysicalBaseAddress
;
222 /** The GIC MSI Frame flags
223 as described by the GIC MSI frame
224 structure in the ACPI Specification.
228 /// SPI Count used by this frame
231 /// SPI Base used by this frame
233 } CM_ARM_GIC_MSI_FRAME_INFO
;
235 /** A structure that describes the
236 GIC Redistributor information for the Platform.
238 ID: EArmObjGicRedistributorInfo
240 typedef struct CmArmGicRedistInfo
{
241 /** The physical address of a page range
242 containing all GIC Redistributors.
244 UINT64 DiscoveryRangeBaseAddress
;
246 /// Length of the GIC Redistributor Discovery page range
247 UINT32 DiscoveryRangeLength
;
248 } CM_ARM_GIC_REDIST_INFO
;
250 /** A structure that describes the
251 GIC Interrupt Translation Service information for the Platform.
253 ID: EArmObjGicItsInfo
255 typedef struct CmArmGicItsInfo
{
259 /// The physical address for the Interrupt Translation Service
260 UINT64 PhysicalBaseAddress
;
262 /** The proximity domain to which the logical processor belongs.
263 This field is used to populate the GIC ITS affinity structure
266 UINT32 ProximityDomain
;
267 } CM_ARM_GIC_ITS_INFO
;
269 /** A structure that describes the
270 Serial Port information for the Platform.
272 ID: EArmObjSerialConsolePortInfo or
273 EArmObjSerialDebugPortInfo
275 typedef struct CmArmSerialPortInfo
{
276 /// The physical base address for the serial port
279 /// The serial port interrupt
282 /// The serial port baud rate
285 /// The serial port clock
288 /// Serial Port subtype
290 } CM_ARM_SERIAL_PORT_INFO
;
292 /** A structure that describes the
293 Generic Timer information for the Platform.
295 ID: EArmObjGenericTimerInfo
297 typedef struct CmArmGenericTimerInfo
{
298 /// The physical base address for the counter control frame
299 UINT64 CounterControlBaseAddress
;
301 /// The physical base address for the counter read frame
302 UINT64 CounterReadBaseAddress
;
304 /// The secure PL1 timer interrupt
305 UINT32 SecurePL1TimerGSIV
;
307 /// The secure PL1 timer flags
308 UINT32 SecurePL1TimerFlags
;
310 /// The non-secure PL1 timer interrupt
311 UINT32 NonSecurePL1TimerGSIV
;
313 /// The non-secure PL1 timer flags
314 UINT32 NonSecurePL1TimerFlags
;
316 /// The virtual timer interrupt
317 UINT32 VirtualTimerGSIV
;
319 /// The virtual timer flags
320 UINT32 VirtualTimerFlags
;
322 /// The non-secure PL2 timer interrupt
323 UINT32 NonSecurePL2TimerGSIV
;
325 /// The non-secure PL2 timer flags
326 UINT32 NonSecurePL2TimerFlags
;
328 /// GSIV for the virtual EL2 timer
329 UINT32 VirtualPL2TimerGSIV
;
331 /// Flags for the virtual EL2 timer
332 UINT32 VirtualPL2TimerFlags
;
333 } CM_ARM_GENERIC_TIMER_INFO
;
335 /** A structure that describes the
336 Platform Generic Block Timer Frame information for the Platform.
338 ID: EArmObjGTBlockTimerFrameInfo
340 typedef struct CmArmGTBlockTimerFrameInfo
{
341 /// The Generic Timer frame number
344 /// The physical base address for the CntBase block
345 UINT64 PhysicalAddressCntBase
;
347 /// The physical base address for the CntEL0Base block
348 UINT64 PhysicalAddressCntEL0Base
;
350 /// The physical timer interrupt
351 UINT32 PhysicalTimerGSIV
;
353 /** The physical timer flags as described by the GT Block
354 Timer frame Structure in the ACPI Specification.
356 UINT32 PhysicalTimerFlags
;
358 /// The virtual timer interrupt
359 UINT32 VirtualTimerGSIV
;
361 /** The virtual timer flags as described by the GT Block
362 Timer frame Structure in the ACPI Specification.
364 UINT32 VirtualTimerFlags
;
366 /** The common timer flags as described by the GT Block
367 Timer frame Structure in the ACPI Specification.
370 } CM_ARM_GTBLOCK_TIMER_FRAME_INFO
;
372 /** A structure that describes the
373 Platform Generic Block Timer information for the Platform.
375 ID: EArmObjPlatformGTBlockInfo
377 typedef struct CmArmGTBlockInfo
{
378 /// The physical base address for the GT Block Timer structure
379 UINT64 GTBlockPhysicalAddress
;
381 /// The number of timer frames implemented in the GT Block
382 UINT32 GTBlockTimerFrameCount
;
384 /// Reference token for the GT Block timer frame list
385 CM_OBJECT_TOKEN GTBlockTimerFrameToken
;
386 } CM_ARM_GTBLOCK_INFO
;
388 /** A structure that describes the
389 SBSA Generic Watchdog information for the Platform.
391 ID: EArmObjPlatformGenericWatchdogInfo
393 typedef struct CmArmGenericWatchdogInfo
{
394 /// The physical base address of the SBSA Watchdog control frame
395 UINT64 ControlFrameAddress
;
397 /// The physical base address of the SBSA Watchdog refresh frame
398 UINT64 RefreshFrameAddress
;
400 /// The watchdog interrupt
403 /** The flags for the watchdog as described by the SBSA watchdog
404 structure in the ACPI specification.
407 } CM_ARM_GENERIC_WATCHDOG_INFO
;
409 /** A structure that describes the
410 PCI Configuration Space information for the Platform.
412 ID: EArmObjPciConfigSpaceInfo
414 typedef struct CmArmPciConfigSpaceInfo
{
415 /// The physical base address for the PCI segment
418 /// The PCI segment group number
419 UINT16 PciSegmentGroupNumber
;
421 /// The start bus number
422 UINT8 StartBusNumber
;
424 /// The end bus number
426 } CM_ARM_PCI_CONFIG_SPACE_INFO
;
428 /** A structure that describes the
429 Hypervisor Vendor ID information for the Platform.
431 ID: EArmObjHypervisorVendorIdentity
433 typedef struct CmArmHypervisorVendorId
{
434 /// The hypervisor Vendor ID
435 UINT64 HypervisorVendorId
;
436 } CM_ARM_HYPERVISOR_VENDOR_ID
;
438 /** A structure that describes the
439 Fixed feature flags for the Platform.
441 ID: EArmObjFixedFeatureFlags
443 typedef struct CmArmFixedFeatureFlags
{
444 /// The Fixed feature flags
446 } CM_ARM_FIXED_FEATURE_FLAGS
;
448 /** A structure that describes the
449 ITS Group node for the Platform.
453 typedef struct CmArmItsGroupNode
{
454 /// An unique token used to identify this object
455 CM_OBJECT_TOKEN Token
;
456 /// The number of ITS identifiers in the ITS node
458 /// Reference token for the ITS identifier array
459 CM_OBJECT_TOKEN ItsIdToken
;
460 } CM_ARM_ITS_GROUP_NODE
;
462 /** A structure that describes the
463 GIC ITS Identifiers for an ITS Group node.
465 ID: EArmObjGicItsIdentifierArray
467 typedef struct CmArmGicItsIdentifier
{
468 /// The ITS Identifier
470 } CM_ARM_ITS_IDENTIFIER
;
472 /** A structure that describes the
473 Named component node for the Platform.
475 ID: EArmObjNamedComponent
477 typedef struct CmArmNamedComponentNode
{
478 /// An unique token used to identify this object
479 CM_OBJECT_TOKEN Token
;
480 /// Number of ID mappings
481 UINT32 IdMappingCount
;
482 /// Reference token for the ID mapping array
483 CM_OBJECT_TOKEN IdMappingToken
;
485 /// Flags for the named component
488 /// Memory access properties : Cache coherent attributes
489 UINT32 CacheCoherent
;
490 /// Memory access properties : Allocation hints
491 UINT8 AllocationHints
;
492 /// Memory access properties : Memory access flags
493 UINT8 MemoryAccessFlags
;
495 /// Memory access properties : Address size limit
496 UINT8 AddressSizeLimit
;
497 /** ASCII Null terminated string with the full path to
498 the entry in the namespace for this object.
501 } CM_ARM_NAMED_COMPONENT_NODE
;
503 /** A structure that describes the
504 Root complex node for the Platform.
506 ID: EArmObjRootComplex
508 typedef struct CmArmRootComplexNode
{
509 /// An unique token used to identify this object
510 CM_OBJECT_TOKEN Token
;
511 /// Number of ID mappings
512 UINT32 IdMappingCount
;
513 /// Reference token for the ID mapping array
514 CM_OBJECT_TOKEN IdMappingToken
;
516 /// Memory access properties : Cache coherent attributes
517 UINT32 CacheCoherent
;
518 /// Memory access properties : Allocation hints
519 UINT8 AllocationHints
;
520 /// Memory access properties : Memory access flags
521 UINT8 MemoryAccessFlags
;
525 /// PCI segment number
526 UINT32 PciSegmentNumber
;
527 /// Memory address size limit
528 UINT8 MemoryAddressSize
;
529 } CM_ARM_ROOT_COMPLEX_NODE
;
531 /** A structure that describes the
532 SMMUv1 or SMMUv2 node for the Platform.
534 ID: EArmObjSmmuV1SmmuV2
536 typedef struct CmArmSmmuV1SmmuV2Node
{
537 /// An unique token used to identify this object
538 CM_OBJECT_TOKEN Token
;
539 /// Number of ID mappings
540 UINT32 IdMappingCount
;
541 /// Reference token for the ID mapping array
542 CM_OBJECT_TOKEN IdMappingToken
;
544 /// SMMU Base Address
546 /// Length of the memory range covered by the SMMU
553 /// Number of context interrupts
554 UINT32 ContextInterruptCount
;
555 /// Reference token for the context interrupt array
556 CM_OBJECT_TOKEN ContextInterruptToken
;
558 /// Number of PMU interrupts
559 UINT32 PmuInterruptCount
;
560 /// Reference token for the PMU interrupt array
561 CM_OBJECT_TOKEN PmuInterruptToken
;
563 /// GSIV of the SMMU_NSgIrpt interrupt
565 /// SMMU_NSgIrpt interrupt flags
566 UINT32 SMMU_NSgIrptFlags
;
567 /// GSIV of the SMMU_NSgCfgIrpt interrupt
568 UINT32 SMMU_NSgCfgIrpt
;
569 /// SMMU_NSgCfgIrpt interrupt flags
570 UINT32 SMMU_NSgCfgIrptFlags
;
571 } CM_ARM_SMMUV1_SMMUV2_NODE
;
573 /** A structure that describes the
574 SMMUv3 node for the Platform.
578 typedef struct CmArmSmmuV3Node
{
579 /// An unique token used to identify this object
580 CM_OBJECT_TOKEN Token
;
581 /// Number of ID mappings
582 UINT32 IdMappingCount
;
583 /// Reference token for the ID mapping array
584 CM_OBJECT_TOKEN IdMappingToken
;
586 /// SMMU Base Address
594 /// GSIV of the Event interrupt if SPI based
595 UINT32 EventInterrupt
;
596 /// PRI Interrupt if SPI based
598 /// GERR interrupt if GSIV based
599 UINT32 GerrInterrupt
;
600 /// Sync interrupt if GSIV based
601 UINT32 SyncInterrupt
;
603 /// Proximity domain flag
604 UINT32 ProximityDomain
;
605 /// Index into the array of ID mapping
606 UINT32 DeviceIdMappingIndex
;
607 } CM_ARM_SMMUV3_NODE
;
609 /** A structure that describes the
610 PMCG node for the Platform.
614 typedef struct CmArmPmcgNode
{
615 /// An unique token used to identify this object
616 CM_OBJECT_TOKEN Token
;
617 /// Number of ID mappings
618 UINT32 IdMappingCount
;
619 /// Reference token for the ID mapping array
620 CM_OBJECT_TOKEN IdMappingToken
;
622 /// Base Address for performance monitor counter group
624 /// GSIV for the Overflow interrupt
625 UINT32 OverflowInterrupt
;
626 /// Page 1 Base address
627 UINT64 Page1BaseAddress
;
629 /// Reference token for the IORT node associated with this node
630 CM_OBJECT_TOKEN ReferenceToken
;
633 /** A structure that describes the
634 ID Mappings for the Platform.
636 ID: EArmObjIdMappingArray
638 typedef struct CmArmIdMapping
{
641 /// Number of input IDs
645 /// Reference token for the output node
646 CM_OBJECT_TOKEN OutputReferenceToken
;
651 /** A structure that describes the
652 SMMU interrupts for the Platform.
654 ID: EArmObjSmmuInterruptArray
656 typedef struct CmArmSmmuInterrupt
{
662 } CM_ARM_SMMU_INTERRUPT
;
664 /** A structure that describes the Processor Hierarchy Node (Type 0) in PPTT
666 ID: EArmObjProcHierarchyInfo
668 typedef struct CmArmProcHierarchyInfo
{
669 /// A unique token used to identify this object
670 CM_OBJECT_TOKEN Token
;
671 /// Processor structure flags (ACPI 6.3 - January 2019, PPTT, Table 5-155)
673 /// Token for the parent CM_ARM_PROC_HIERARCHY_INFO object in the processor
674 /// topology. A value of CM_NULL_TOKEN means this node has no parent.
675 CM_OBJECT_TOKEN ParentToken
;
676 /// Token of the associated CM_ARM_GICC_INFO object which has the
677 /// corresponding ACPI Processor ID. A value of CM_NULL_TOKEN means this
678 /// node represents a group of associated processors and it does not have an
679 /// associated GIC CPU interface.
680 CM_OBJECT_TOKEN GicCToken
;
681 /// Number of resources private to this Node
682 UINT32 NoOfPrivateResources
;
683 /// Token of the array which contains references to the resources private to
684 /// this CM_ARM_PROC_HIERARCHY_INFO instance. This field is ignored if
685 /// the NoOfPrivateResources is 0, in which case it is recommended to set
686 /// this field to CM_NULL_TOKEN.
687 CM_OBJECT_TOKEN PrivateResourcesArrayToken
;
688 } CM_ARM_PROC_HIERARCHY_INFO
;
690 /** A structure that describes the Cache Type Structure (Type 1) in PPTT
694 typedef struct CmArmCacheInfo
{
695 /// A unique token used to identify this object
696 CM_OBJECT_TOKEN Token
;
697 /// Reference token for the next level of cache that is private to the same
698 /// CM_ARM_PROC_HIERARCHY_INFO instance. A value of CM_NULL_TOKEN means this
699 /// entry represents the last cache level appropriate to the processor
700 /// hierarchy node structures using this entry.
701 CM_OBJECT_TOKEN NextLevelOfCacheToken
;
702 /// Size of the cache in bytes
704 /// Number of sets in the cache
706 /// Integer number of ways. The maximum associativity supported by
707 /// ACPI Cache type structure is limited to MAX_UINT8. However,
708 /// the maximum number of ways supported by the architecture is
709 /// PPTT_ARM_CCIDX_CACHE_ASSOCIATIVITY_MAX. Therfore this field
711 UINT32 Associativity
;
712 /// Cache attributes (ACPI 6.3 - January 2019, PPTT, Table 5-156)
714 /// Line size in bytes
718 /** A structure that describes the ID Structure (Type 2) in PPTT
720 ID: EArmObjProcNodeIdInfo
722 typedef struct CmArmProcNodeIdInfo
{
723 /// A unique token used to identify this object
724 CM_OBJECT_TOKEN Token
;
725 // Vendor ID (as described in ACPI ID registry)
727 /// First level unique node ID
729 /// Second level unique node ID
731 /// Major revision of the node
733 /// Minor revision of the node
735 /// Spin revision of the node
737 } CM_ARM_PROC_NODE_ID_INFO
;
739 /** A structure that describes a reference to another Configuration Manager
742 This is useful for creating an array of reference tokens. The framework
743 can then query the configuration manager for these arrays using the
744 object ID EArmObjCmRef.
746 This can be used is to represent one-to-many relationships between objects.
750 typedef struct CmArmObjRef
{
751 /// Token of the CM object being referenced
752 CM_OBJECT_TOKEN ReferenceToken
;
755 /** A structure that describes the Memory Affinity Structure (Type 1) in SRAT
757 ID: EArmObjMemoryAffinityInfo
759 typedef struct CmArmMemoryAffinityInfo
{
760 /// The proximity domain to which the "range of memory" belongs.
761 UINT32 ProximityDomain
;
771 } CM_ARM_MEMORY_AFFINITY_INFO
;
773 /** A structure that describes the ACPI Device Handle (Type 0) in the
774 Generic Initiator Affinity structure in SRAT
776 ID: EArmObjDeviceHandleAcpi
778 typedef struct CmArmDeviceHandleAcpi
{
784 } CM_ARM_DEVICE_HANDLE_ACPI
;
786 /** A structure that describes the PCI Device Handle (Type 1) in the
787 Generic Initiator Affinity structure in SRAT
789 ID: EArmObjDeviceHandlePci
791 typedef struct CmArmDeviceHandlePci
{
792 /// PCI Segment Number
793 UINT16 SegmentNumber
;
795 /// PCI Bus Number - Max 256 busses (Bits 15:8 of BDF)
798 /// PCI Device Number - Max 32 devices (Bits 7:3 of BDF)
801 /// PCI Function Number - Max 8 functions (Bits 2:0 of BDF)
802 UINT8 FunctionNumber
;
803 } CM_ARM_DEVICE_HANDLE_PCI
;
805 /** A structure that describes the Generic Initiator Affinity structure in SRAT
807 ID: EArmObjGenericInitiatorAffinityInfo
809 typedef struct CmArmGenericInitiatorAffinityInfo
{
810 /// The proximity domain to which the generic initiator belongs.
811 UINT32 ProximityDomain
;
816 /// Device Handle Type
817 UINT8 DeviceHandleType
;
819 /// Reference Token for the Device Handle
820 CM_OBJECT_TOKEN DeviceHandleToken
;
821 } CM_ARM_GENERIC_INITIATOR_AFFINITY_INFO
;
825 #endif // ARM_NAMESPACE_OBJECTS_H_