1 ;------------------------------------------------------------------------------
3 ; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
4 ; This program and the accompanying materials
5 ; are licensed and made available under the terms and conditions of the BSD License
6 ; which accompanies this distribution. The full text of the license may be found at
7 ; http://opensource.org/licenses/bsd-license.php.
9 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14 ;------------------------------------------------------------------------------
19 ; Float control word initial value:
20 ; all exceptions masked, double-precision, round-to-nearest
22 ASM_PFX(mFpuControlWord):
25 ; Multimedia-extensions control word:
26 ; all exceptions masked, round-to-nearest, flush to zero for masked underflow
28 ASM_PFX(mMmxControlWord):
34 ; Initializes floating point units for requirement of UEFI specification.
36 ; This function initializes floating-point control word to 0x027F (all exceptions
37 ; masked,double-precision, round-to-nearest) and multimedia-extensions control word
38 ; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
39 ; for masked underflow).
42 global ASM_PFX(InitializeFloatingPointUnits)
43 ASM_PFX(InitializeFloatingPointUnits):
49 ; Initialize floating point units
52 fldcw [ASM_PFX(mFpuControlWord)]
55 ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
56 ; whether the processor supports SSE instruction.
64 ; Set OSFXSR bit 9 in CR4
71 ; The processor should support SSE instruction and we can use
74 ldmxcsr [ASM_PFX(mMmxControlWord)]