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git.proxmox.com Git - mirror_edk2.git/blob - MdeModulePkg/Bus/Pci/PciBusDxe/PciCommand.h
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2 PCI command register operations supporting functions declaration for PCI Bus module.
4 Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
10 #ifndef _EFI_PCI_COMMAND_H_
11 #define _EFI_PCI_COMMAND_H_
14 // The PCI Command register bits owned by PCI Bus driver.
16 // They should be cleared at the beginning. The other registers
17 // are owned by chipset, we should not touch them.
19 #define EFI_PCI_COMMAND_BITS_OWNED ( \
20 EFI_PCI_COMMAND_IO_SPACE | \
21 EFI_PCI_COMMAND_MEMORY_SPACE | \
22 EFI_PCI_COMMAND_BUS_MASTER | \
23 EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE | \
24 EFI_PCI_COMMAND_VGA_PALETTE_SNOOP | \
25 EFI_PCI_COMMAND_FAST_BACK_TO_BACK \
29 // The PCI Bridge Control register bits owned by PCI Bus driver.
31 // They should be cleared at the beginning. The other registers
32 // are owned by chipset, we should not touch them.
34 #define EFI_PCI_BRIDGE_CONTROL_BITS_OWNED ( \
35 EFI_PCI_BRIDGE_CONTROL_ISA | \
36 EFI_PCI_BRIDGE_CONTROL_VGA | \
37 EFI_PCI_BRIDGE_CONTROL_VGA_16 | \
38 EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK \
42 // The PCCard Bridge Control register bits owned by PCI Bus driver.
44 // They should be cleared at the beginning. The other registers
45 // are owned by chipset, we should not touch them.
47 #define EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED ( \
48 EFI_PCI_BRIDGE_CONTROL_ISA | \
49 EFI_PCI_BRIDGE_CONTROL_VGA | \
50 EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK \
54 #define EFI_GET_REGISTER 1
55 #define EFI_SET_REGISTER 2
56 #define EFI_ENABLE_REGISTER 3
57 #define EFI_DISABLE_REGISTER 4
60 Operate the PCI register via PciIo function interface.
62 @param PciIoDevice Pointer to instance of PCI_IO_DEVICE.
63 @param Command Operator command.
64 @param Offset The address within the PCI configuration space for the PCI controller.
65 @param Operation Type of Operation.
66 @param PtrCommand Return buffer holding old PCI command, if operation is not EFI_SET_REGISTER.
68 @return Status of PciIo operation.
73 IN PCI_IO_DEVICE
*PciIoDevice
,
77 OUT UINT16
*PtrCommand
81 Check the capability supporting by given device.
83 @param PciIoDevice Pointer to instance of PCI_IO_DEVICE.
85 @retval TRUE Capability supported.
86 @retval FALSE Capability not supported.
90 PciCapabilitySupport (
91 IN PCI_IO_DEVICE
*PciIoDevice
95 Locate capability register block per capability ID.
97 @param PciIoDevice A pointer to the PCI_IO_DEVICE.
98 @param CapId The capability ID.
99 @param Offset A pointer to the offset returned.
100 @param NextRegBlock A pointer to the next block returned.
102 @retval EFI_SUCCESS Successfully located capability register block.
103 @retval EFI_UNSUPPORTED Pci device does not support capability.
104 @retval EFI_NOT_FOUND Pci device support but can not find register block.
108 LocateCapabilityRegBlock (
109 IN PCI_IO_DEVICE
*PciIoDevice
,
111 IN OUT UINT8
*Offset
,
112 OUT UINT8
*NextRegBlock OPTIONAL
116 Locate PciExpress capability register block per capability ID.
118 @param PciIoDevice A pointer to the PCI_IO_DEVICE.
119 @param CapId The capability ID.
120 @param Offset A pointer to the offset returned.
121 @param NextRegBlock A pointer to the next block returned.
123 @retval EFI_SUCCESS Successfully located capability register block.
124 @retval EFI_UNSUPPORTED Pci device does not support capability.
125 @retval EFI_NOT_FOUND Pci device support but can not find register block.
129 LocatePciExpressCapabilityRegBlock (
130 IN PCI_IO_DEVICE
*PciIoDevice
,
132 IN OUT UINT32
*Offset
,
133 OUT UINT32
*NextRegBlock OPTIONAL
137 Macro that reads command register.
139 @param a[in] Pointer to instance of PCI_IO_DEVICE.
140 @param b[out] Pointer to the 16-bit value read from command register.
142 @return status of PciIo operation
145 #define PCI_READ_COMMAND_REGISTER(a,b) \
146 PciOperateRegister (a, 0, PCI_COMMAND_OFFSET, EFI_GET_REGISTER, b)
149 Macro that writes command register.
151 @param a[in] Pointer to instance of PCI_IO_DEVICE.
152 @param b[in] The 16-bit value written into command register.
154 @return status of PciIo operation
157 #define PCI_SET_COMMAND_REGISTER(a,b) \
158 PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_SET_REGISTER, NULL)
161 Macro that enables command register.
163 @param a[in] Pointer to instance of PCI_IO_DEVICE.
164 @param b[in] The enabled value written into command register.
166 @return status of PciIo operation
169 #define PCI_ENABLE_COMMAND_REGISTER(a,b) \
170 PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_ENABLE_REGISTER, NULL)
173 Macro that disables command register.
175 @param a[in] Pointer to instance of PCI_IO_DEVICE.
176 @param b[in] The disabled value written into command register.
178 @return status of PciIo operation
181 #define PCI_DISABLE_COMMAND_REGISTER(a,b) \
182 PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_DISABLE_REGISTER, NULL)
185 Macro that reads PCI bridge control register.
187 @param a[in] Pointer to instance of PCI_IO_DEVICE.
188 @param b[out] The 16-bit value read from control register.
190 @return status of PciIo operation
193 #define PCI_READ_BRIDGE_CONTROL_REGISTER(a,b) \
194 PciOperateRegister (a, 0, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_GET_REGISTER, b)
197 Macro that writes PCI bridge control register.
199 @param a[in] Pointer to instance of PCI_IO_DEVICE.
200 @param b[in] The 16-bit value written into control register.
202 @return status of PciIo operation
205 #define PCI_SET_BRIDGE_CONTROL_REGISTER(a,b) \
206 PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_SET_REGISTER, NULL)
209 Macro that enables PCI bridge control register.
211 @param a[in] Pointer to instance of PCI_IO_DEVICE.
212 @param b[in] The enabled value written into command register.
214 @return status of PciIo operation
217 #define PCI_ENABLE_BRIDGE_CONTROL_REGISTER(a,b) \
218 PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_ENABLE_REGISTER, NULL)
221 Macro that disables PCI bridge control register.
223 @param a[in] Pointer to instance of PCI_IO_DEVICE.
224 @param b[in] The disabled value written into command register.
226 @return status of PciIo operation
229 #define PCI_DISABLE_BRIDGE_CONTROL_REGISTER(a,b) \
230 PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_DISABLE_REGISTER, NULL)