2 PCI eunmeration implementation on entire PCI bus system for PCI Bus module.
4 Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
5 (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 This routine is used to enumerate entire pci bus system
22 @param Controller Parent controller handle.
24 @retval EFI_SUCCESS PCI enumeration finished successfully.
25 @retval other Some error occurred when enumerating the pci bus system.
30 IN EFI_HANDLE Controller
33 EFI_HANDLE HostBridgeHandle
;
35 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
*PciResAlloc
;
36 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
39 // If PCI bus has already done the full enumeration, never do it again
41 if (!gFullEnumeration
) {
42 return PciEnumeratorLight (Controller
);
46 // Get the rootbridge Io protocol to find the host bridge handle
48 Status
= gBS
->OpenProtocol (
50 &gEfiPciRootBridgeIoProtocolGuid
,
51 (VOID
**) &PciRootBridgeIo
,
52 gPciBusDriverBinding
.DriverBindingHandle
,
54 EFI_OPEN_PROTOCOL_GET_PROTOCOL
57 if (EFI_ERROR (Status
)) {
62 // Get the host bridge handle
64 HostBridgeHandle
= PciRootBridgeIo
->ParentHandle
;
67 // Get the pci host bridge resource allocation protocol
69 Status
= gBS
->OpenProtocol (
71 &gEfiPciHostBridgeResourceAllocationProtocolGuid
,
72 (VOID
**) &PciResAlloc
,
73 gPciBusDriverBinding
.DriverBindingHandle
,
75 EFI_OPEN_PROTOCOL_GET_PROTOCOL
78 if (EFI_ERROR (Status
)) {
83 // Notify the pci bus enumeration is about to begin
85 Status
= NotifyPhase (PciResAlloc
, EfiPciHostBridgeBeginEnumeration
);
87 if (EFI_ERROR (Status
)) {
92 // Start the bus allocation phase
94 Status
= PciHostBridgeEnumerator (PciResAlloc
);
96 if (EFI_ERROR (Status
)) {
101 // Submit the resource request
103 Status
= PciHostBridgeResourceAllocator (PciResAlloc
);
105 if (EFI_ERROR (Status
)) {
110 // Notify the pci bus enumeration is about to complete
112 Status
= NotifyPhase (PciResAlloc
, EfiPciHostBridgeEndEnumeration
);
114 if (EFI_ERROR (Status
)) {
121 Status
= PciHostBridgeP2CProcess (PciResAlloc
);
123 if (EFI_ERROR (Status
)) {
128 // Process attributes for devices on this host bridge
130 Status
= PciHostBridgeDeviceAttribute (PciResAlloc
);
131 if (EFI_ERROR (Status
)) {
135 gFullEnumeration
= FALSE
;
137 Status
= gBS
->InstallProtocolInterface (
139 &gEfiPciEnumerationCompleteProtocolGuid
,
140 EFI_NATIVE_INTERFACE
,
143 if (EFI_ERROR (Status
)) {
151 Enumerate PCI root bridge.
153 @param PciResAlloc Pointer to protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.
154 @param RootBridgeDev Instance of root bridge device.
156 @retval EFI_SUCCESS Successfully enumerated root bridge.
157 @retval other Failed to enumerate root bridge.
161 PciRootBridgeEnumerator (
162 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
*PciResAlloc
,
163 IN PCI_IO_DEVICE
*RootBridgeDev
167 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Configuration
;
168 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Configuration1
;
169 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Configuration2
;
170 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Configuration3
;
172 UINT8 StartBusNumber
;
173 UINT8 PaddedBusRange
;
174 EFI_HANDLE RootBridgeHandle
;
184 // Get the root bridge handle
186 RootBridgeHandle
= RootBridgeDev
->Handle
;
188 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
190 EFI_IO_BUS_PCI
| EFI_IOB_PCI_BUS_ENUM
,
191 RootBridgeDev
->DevicePath
195 // Get the Bus information
197 Status
= PciResAlloc
->StartBusEnumeration (
200 (VOID
**) &Configuration
203 if (EFI_ERROR (Status
)) {
207 if (Configuration
== NULL
|| Configuration
->Desc
== ACPI_END_TAG_DESCRIPTOR
) {
208 return EFI_INVALID_PARAMETER
;
210 RootBridgeDev
->BusNumberRanges
= Configuration
;
213 // Sort the descriptors in ascending order
215 for (Configuration1
= Configuration
; Configuration1
->Desc
!= ACPI_END_TAG_DESCRIPTOR
; Configuration1
++) {
216 Configuration2
= Configuration1
;
217 for (Configuration3
= Configuration1
+ 1; Configuration3
->Desc
!= ACPI_END_TAG_DESCRIPTOR
; Configuration3
++) {
218 if (Configuration2
->AddrRangeMin
> Configuration3
->AddrRangeMin
) {
219 Configuration2
= Configuration3
;
223 // All other fields other than AddrRangeMin and AddrLen are ignored in a descriptor,
224 // so only need to swap these two fields.
226 if (Configuration2
!= Configuration1
) {
227 AddrRangeMin
= Configuration1
->AddrRangeMin
;
228 Configuration1
->AddrRangeMin
= Configuration2
->AddrRangeMin
;
229 Configuration2
->AddrRangeMin
= AddrRangeMin
;
231 AddrLen
= Configuration1
->AddrLen
;
232 Configuration1
->AddrLen
= Configuration2
->AddrLen
;
233 Configuration2
->AddrLen
= AddrLen
;
238 // Get the bus number to start with
240 StartBusNumber
= (UINT8
) (Configuration
->AddrRangeMin
);
243 // Initialize the subordinate bus number
245 SubBusNumber
= StartBusNumber
;
248 // Reset all assigned PCI bus number
250 ResetAllPpbBusNumber (
258 Status
= PciScanBus (
265 if (EFI_ERROR (Status
)) {
271 // Assign max bus number scanned
274 Status
= PciAllocateBusNumber (RootBridgeDev
, SubBusNumber
, PaddedBusRange
, &SubBusNumber
);
275 if (EFI_ERROR (Status
)) {
280 // Find the bus range which contains the higest bus number, then returns the number of buses
281 // that should be decoded.
283 while (Configuration
->AddrRangeMin
+ Configuration
->AddrLen
- 1 < SubBusNumber
) {
286 AddrLen
= Configuration
->AddrLen
;
287 Configuration
->AddrLen
= SubBusNumber
- Configuration
->AddrRangeMin
+ 1;
290 // Save the Desc field of the next descriptor. Mark the next descriptor as an END descriptor.
293 Desc
= Configuration
->Desc
;
294 Configuration
->Desc
= ACPI_END_TAG_DESCRIPTOR
;
299 Status
= PciResAlloc
->SetBusNumbers (
302 RootBridgeDev
->BusNumberRanges
306 // Restore changed fields
308 Configuration
->Desc
= Desc
;
309 (Configuration
- 1)->AddrLen
= AddrLen
;
315 This routine is used to process all PCI devices' Option Rom
316 on a certain root bridge.
318 @param Bridge Given parent's root bridge.
319 @param RomBase Base address of ROM driver loaded from.
320 @param MaxLength Maximum rom size.
325 IN PCI_IO_DEVICE
*Bridge
,
330 LIST_ENTRY
*CurrentLink
;
334 // Go through bridges to reach all devices
336 CurrentLink
= Bridge
->ChildList
.ForwardLink
;
337 while (CurrentLink
!= NULL
&& CurrentLink
!= &Bridge
->ChildList
) {
338 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
339 if (!IsListEmpty (&Temp
->ChildList
)) {
342 // Go further to process the option rom under this bridge
344 ProcessOptionRom (Temp
, RomBase
, MaxLength
);
347 if (Temp
->RomSize
!= 0 && Temp
->RomSize
<= MaxLength
) {
350 // Load and process the option rom
352 LoadOpRomImage (Temp
, RomBase
);
355 CurrentLink
= CurrentLink
->ForwardLink
;
360 This routine is used to assign bus number to the given PCI bus system
362 @param Bridge Parent root bridge instance.
363 @param StartBusNumber Number of beginning.
364 @param SubBusNumber The number of sub bus.
366 @retval EFI_SUCCESS Successfully assigned bus number.
367 @retval EFI_DEVICE_ERROR Failed to assign bus number.
372 IN PCI_IO_DEVICE
*Bridge
,
373 IN UINT8 StartBusNumber
,
374 OUT UINT8
*SubBusNumber
385 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
387 PciRootBridgeIo
= Bridge
->PciRootBridgeIo
;
392 *SubBusNumber
= StartBusNumber
;
395 // First check to see whether the parent is ppb
397 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
398 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
401 // Check to see whether a pci device is present
403 Status
= PciDevicePresent (
411 if (EFI_ERROR (Status
) && Func
== 0) {
413 // go to next device if there is no Function 0
418 if (!EFI_ERROR (Status
) &&
419 (IS_PCI_BRIDGE (&Pci
) || IS_CARDBUS_BRIDGE (&Pci
))) {
422 // Reserved one bus for cardbus bridge
424 Status
= PciAllocateBusNumber (Bridge
, *SubBusNumber
, 1, SubBusNumber
);
425 if (EFI_ERROR (Status
)) {
428 SecondBus
= *SubBusNumber
;
430 Register
= (UINT16
) ((SecondBus
<< 8) | (UINT16
) StartBusNumber
);
432 Address
= EFI_PCI_ADDRESS (StartBusNumber
, Device
, Func
, 0x18);
434 Status
= PciRootBridgeIo
->Pci
.Write (
443 // Initialize SubBusNumber to SecondBus
445 Address
= EFI_PCI_ADDRESS (StartBusNumber
, Device
, Func
, 0x1A);
446 Status
= PciRootBridgeIo
->Pci
.Write (
454 // If it is PPB, resursively search down this bridge
456 if (IS_PCI_BRIDGE (&Pci
)) {
459 Status
= PciRootBridgeIo
->Pci
.Write (
467 Status
= PciAssignBusNumber (
473 if (EFI_ERROR (Status
)) {
474 return EFI_DEVICE_ERROR
;
479 // Set the current maximum bus number under the PPB
481 Address
= EFI_PCI_ADDRESS (StartBusNumber
, Device
, Func
, 0x1A);
483 Status
= PciRootBridgeIo
->Pci
.Write (
493 if (Func
== 0 && !IS_PCI_MULTI_FUNC (&Pci
)) {
496 // Skip sub functions, this is not a multi function device
507 This routine is used to determine the root bridge attribute by interfacing
508 the host bridge resource allocation protocol.
510 @param PciResAlloc Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
511 @param RootBridgeDev Root bridge instance
513 @retval EFI_SUCCESS Successfully got root bridge's attribute.
514 @retval other Failed to get attribute.
518 DetermineRootBridgeAttributes (
519 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
*PciResAlloc
,
520 IN PCI_IO_DEVICE
*RootBridgeDev
525 EFI_HANDLE RootBridgeHandle
;
528 RootBridgeHandle
= RootBridgeDev
->Handle
;
531 // Get root bridge attribute by calling into pci host bridge resource allocation protocol
533 Status
= PciResAlloc
->GetAllocAttributes (
539 if (EFI_ERROR (Status
)) {
544 // Here is the point where PCI bus driver calls HOST bridge allocation protocol
545 // Currently we hardcoded for ea815
547 if ((Attributes
& EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM
) != 0) {
548 RootBridgeDev
->Decodes
|= EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED
;
551 if ((Attributes
& EFI_PCI_HOST_BRIDGE_MEM64_DECODE
) != 0) {
552 RootBridgeDev
->Decodes
|= EFI_BRIDGE_MEM64_DECODE_SUPPORTED
;
553 RootBridgeDev
->Decodes
|= EFI_BRIDGE_PMEM64_DECODE_SUPPORTED
;
556 RootBridgeDev
->Decodes
|= EFI_BRIDGE_MEM32_DECODE_SUPPORTED
;
557 RootBridgeDev
->Decodes
|= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED
;
558 RootBridgeDev
->Decodes
|= EFI_BRIDGE_IO16_DECODE_SUPPORTED
;
564 Get Max Option Rom size on specified bridge.
566 @param Bridge Given bridge device instance.
568 @return Max size of option rom needed.
572 GetMaxOptionRomSize (
573 IN PCI_IO_DEVICE
*Bridge
576 LIST_ENTRY
*CurrentLink
;
578 UINT64 MaxOptionRomSize
;
579 UINT64 TempOptionRomSize
;
581 MaxOptionRomSize
= 0;
584 // Go through bridges to reach all devices
586 CurrentLink
= Bridge
->ChildList
.ForwardLink
;
587 while (CurrentLink
!= NULL
&& CurrentLink
!= &Bridge
->ChildList
) {
588 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
589 if (!IsListEmpty (&Temp
->ChildList
)) {
592 // Get max option rom size under this bridge
594 TempOptionRomSize
= GetMaxOptionRomSize (Temp
);
597 // Compare with the option rom size of the bridge
598 // Get the larger one
600 if (Temp
->RomSize
> TempOptionRomSize
) {
601 TempOptionRomSize
= Temp
->RomSize
;
607 // For devices get the rom size directly
609 TempOptionRomSize
= Temp
->RomSize
;
613 // Get the largest rom size on this bridge
615 if (TempOptionRomSize
> MaxOptionRomSize
) {
616 MaxOptionRomSize
= TempOptionRomSize
;
619 CurrentLink
= CurrentLink
->ForwardLink
;
622 return MaxOptionRomSize
;
626 Process attributes of devices on this host bridge
628 @param PciResAlloc Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.
630 @retval EFI_SUCCESS Successfully process attribute.
631 @retval EFI_NOT_FOUND Can not find the specific root bridge device.
632 @retval other Failed to determine the root bridge device's attribute.
636 PciHostBridgeDeviceAttribute (
637 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
*PciResAlloc
640 EFI_HANDLE RootBridgeHandle
;
641 PCI_IO_DEVICE
*RootBridgeDev
;
644 RootBridgeHandle
= NULL
;
646 while (PciResAlloc
->GetNextRootBridge (PciResAlloc
, &RootBridgeHandle
) == EFI_SUCCESS
) {
649 // Get RootBridg Device by handle
651 RootBridgeDev
= GetRootBridgeByHandle (RootBridgeHandle
);
653 if (RootBridgeDev
== NULL
) {
654 return EFI_NOT_FOUND
;
658 // Set the attributes for devcies behind the Root Bridge
660 Status
= DetermineDeviceAttribute (RootBridgeDev
);
661 if (EFI_ERROR (Status
)) {
671 Get resource allocation status from the ACPI resource descriptor.
673 @param AcpiConfig Point to Acpi configuration table.
674 @param IoResStatus Return the status of I/O resource.
675 @param Mem32ResStatus Return the status of 32-bit Memory resource.
676 @param PMem32ResStatus Return the status of 32-bit Prefetchable Memory resource.
677 @param Mem64ResStatus Return the status of 64-bit Memory resource.
678 @param PMem64ResStatus Return the status of 64-bit Prefetchable Memory resource.
682 GetResourceAllocationStatus (
684 OUT UINT64
*IoResStatus
,
685 OUT UINT64
*Mem32ResStatus
,
686 OUT UINT64
*PMem32ResStatus
,
687 OUT UINT64
*Mem64ResStatus
,
688 OUT UINT64
*PMem64ResStatus
693 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*ACPIAddressDesc
;
695 Temp
= (UINT8
*) AcpiConfig
;
697 while (*Temp
== ACPI_ADDRESS_SPACE_DESCRIPTOR
) {
699 ACPIAddressDesc
= (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*) Temp
;
700 ResStatus
= ACPIAddressDesc
->AddrTranslationOffset
;
702 switch (ACPIAddressDesc
->ResType
) {
704 if (ACPIAddressDesc
->AddrSpaceGranularity
== 32) {
705 if (ACPIAddressDesc
->SpecificFlag
== 0x06) {
709 *PMem32ResStatus
= ResStatus
;
714 *Mem32ResStatus
= ResStatus
;
718 if (ACPIAddressDesc
->AddrSpaceGranularity
== 64) {
719 if (ACPIAddressDesc
->SpecificFlag
== 0x06) {
723 *PMem64ResStatus
= ResStatus
;
728 *Mem64ResStatus
= ResStatus
;
738 *IoResStatus
= ResStatus
;
745 Temp
+= sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
);
750 Remove a PCI device from device pool and mark its bar.
752 @param PciDevice Instance of Pci device.
754 @retval EFI_SUCCESS Successfully remove the PCI device.
755 @retval EFI_ABORTED Pci device is a root bridge or a PCI-PCI bridge.
760 IN PCI_IO_DEVICE
*PciDevice
763 PCI_IO_DEVICE
*Bridge
;
765 LIST_ENTRY
*CurrentLink
;
768 // Remove the padding resource from a bridge
770 if ( IS_PCI_BRIDGE(&PciDevice
->Pci
) &&
771 PciDevice
->ResourcePaddingDescriptors
!= NULL
) {
772 FreePool (PciDevice
->ResourcePaddingDescriptors
);
773 PciDevice
->ResourcePaddingDescriptors
= NULL
;
780 if (IS_PCI_BRIDGE (&PciDevice
->Pci
) || (PciDevice
->Parent
== NULL
)) {
784 if (IS_CARDBUS_BRIDGE (&PciDevice
->Pci
)) {
786 // Get the root bridge device
789 while (Bridge
->Parent
!= NULL
) {
790 Bridge
= Bridge
->Parent
;
793 RemoveAllPciDeviceOnBridge (Bridge
->Handle
, PciDevice
);
798 InitializeP2C (PciDevice
);
804 Bridge
= PciDevice
->Parent
;
805 CurrentLink
= Bridge
->ChildList
.ForwardLink
;
806 while (CurrentLink
!= NULL
&& CurrentLink
!= &Bridge
->ChildList
) {
807 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
808 if (Temp
== PciDevice
) {
809 InitializePciDevice (Temp
);
810 RemoveEntryList (CurrentLink
);
814 CurrentLink
= CurrentLink
->ForwardLink
;
821 Determine whethter a PCI device can be rejected.
823 @param PciResNode Pointer to Pci resource node instance.
825 @retval TRUE The PCI device can be rejected.
826 @retval TRUE The PCI device cannot be rejected.
831 IN PCI_RESOURCE_NODE
*PciResNode
836 Temp
= PciResNode
->PciDev
;
839 // Ensure the device is present
846 // PPB and RB should go ahead
848 if (IS_PCI_BRIDGE (&Temp
->Pci
) || (Temp
->Parent
== NULL
)) {
853 // Skip device on Bus0
855 if ((Temp
->Parent
!= NULL
) && (Temp
->BusNumber
== 0)) {
862 if (IS_PCI_VGA (&Temp
->Pci
)) {
870 Compare two resource nodes and get the larger resource consumer.
872 @param PciResNode1 resource node 1 want to be compared
873 @param PciResNode2 resource node 2 want to be compared
875 @return Larger resource node.
879 GetLargerConsumerDevice (
880 IN PCI_RESOURCE_NODE
*PciResNode1
,
881 IN PCI_RESOURCE_NODE
*PciResNode2
884 if (PciResNode2
== NULL
) {
888 if ((IS_PCI_BRIDGE(&(PciResNode2
->PciDev
->Pci
)) || (PciResNode2
->PciDev
->Parent
== NULL
)) \
889 && (PciResNode2
->ResourceUsage
!= PciResUsagePadding
) )
894 if (PciResNode1
== NULL
) {
898 if ((PciResNode1
->Length
) > (PciResNode2
->Length
)) {
907 Get the max resource consumer in the host resource pool.
909 @param ResPool Pointer to resource pool node.
911 @return The max resource consumer in the host resource pool.
915 GetMaxResourceConsumerDevice (
916 IN PCI_RESOURCE_NODE
*ResPool
919 PCI_RESOURCE_NODE
*Temp
;
920 LIST_ENTRY
*CurrentLink
;
921 PCI_RESOURCE_NODE
*PciResNode
;
922 PCI_RESOURCE_NODE
*PPBResNode
;
926 CurrentLink
= ResPool
->ChildList
.ForwardLink
;
927 while (CurrentLink
!= NULL
&& CurrentLink
!= &ResPool
->ChildList
) {
929 Temp
= RESOURCE_NODE_FROM_LINK (CurrentLink
);
931 if (!IsRejectiveDevice (Temp
)) {
932 CurrentLink
= CurrentLink
->ForwardLink
;
936 if ((IS_PCI_BRIDGE (&(Temp
->PciDev
->Pci
)) || (Temp
->PciDev
->Parent
== NULL
)) \
937 && (Temp
->ResourceUsage
!= PciResUsagePadding
))
939 PPBResNode
= GetMaxResourceConsumerDevice (Temp
);
940 PciResNode
= GetLargerConsumerDevice (PciResNode
, PPBResNode
);
942 PciResNode
= GetLargerConsumerDevice (PciResNode
, Temp
);
945 CurrentLink
= CurrentLink
->ForwardLink
;
952 Adjust host bridge allocation so as to reduce resource requirement
954 @param IoPool Pointer to instance of I/O resource Node.
955 @param Mem32Pool Pointer to instance of 32-bit memory resource Node.
956 @param PMem32Pool Pointer to instance of 32-bit Prefetchable memory resource node.
957 @param Mem64Pool Pointer to instance of 64-bit memory resource node.
958 @param PMem64Pool Pointer to instance of 64-bit Prefetchable memory resource node.
959 @param IoResStatus Status of I/O resource Node.
960 @param Mem32ResStatus Status of 32-bit memory resource Node.
961 @param PMem32ResStatus Status of 32-bit Prefetchable memory resource node.
962 @param Mem64ResStatus Status of 64-bit memory resource node.
963 @param PMem64ResStatus Status of 64-bit Prefetchable memory resource node.
965 @retval EFI_SUCCESS Successfully adjusted resoruce on host bridge.
966 @retval EFI_ABORTED Host bridge hasn't this resource type or no resource be adjusted.
970 PciHostBridgeAdjustAllocation (
971 IN PCI_RESOURCE_NODE
*IoPool
,
972 IN PCI_RESOURCE_NODE
*Mem32Pool
,
973 IN PCI_RESOURCE_NODE
*PMem32Pool
,
974 IN PCI_RESOURCE_NODE
*Mem64Pool
,
975 IN PCI_RESOURCE_NODE
*PMem64Pool
,
976 IN UINT64 IoResStatus
,
977 IN UINT64 Mem32ResStatus
,
978 IN UINT64 PMem32ResStatus
,
979 IN UINT64 Mem64ResStatus
,
980 IN UINT64 PMem64ResStatus
983 BOOLEAN AllocationAjusted
;
984 PCI_RESOURCE_NODE
*PciResNode
;
985 PCI_RESOURCE_NODE
*ResPool
[5];
986 PCI_IO_DEVICE
*RemovedPciDev
[5];
988 UINTN RemovedPciDevNum
;
992 EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD AllocFailExtendedData
;
995 ZeroMem (RemovedPciDev
, 5 * sizeof (PCI_IO_DEVICE
*));
996 RemovedPciDevNum
= 0;
999 ResPool
[1] = Mem32Pool
;
1000 ResPool
[2] = PMem32Pool
;
1001 ResPool
[3] = Mem64Pool
;
1002 ResPool
[4] = PMem64Pool
;
1004 ResStatus
[0] = IoResStatus
;
1005 ResStatus
[1] = Mem32ResStatus
;
1006 ResStatus
[2] = PMem32ResStatus
;
1007 ResStatus
[3] = Mem64ResStatus
;
1008 ResStatus
[4] = PMem64ResStatus
;
1010 AllocationAjusted
= FALSE
;
1012 for (ResType
= 0; ResType
< 5; ResType
++) {
1014 if (ResStatus
[ResType
] == EFI_RESOURCE_SATISFIED
) {
1018 if (ResStatus
[ResType
] == EFI_RESOURCE_NOT_SATISFIED
) {
1020 // Host bridge hasn't this resource type
1026 // Hostbridge hasn't enough resource
1028 PciResNode
= GetMaxResourceConsumerDevice (ResPool
[ResType
]);
1029 if (PciResNode
== NULL
) {
1034 // Check if the device has been removed before
1036 for (DevIndex
= 0; DevIndex
< RemovedPciDevNum
; DevIndex
++) {
1037 if (PciResNode
->PciDev
== RemovedPciDev
[DevIndex
]) {
1042 if (DevIndex
!= RemovedPciDevNum
) {
1047 // Remove the device if it isn't in the array
1049 Status
= RejectPciDevice (PciResNode
->PciDev
);
1050 if (Status
== EFI_SUCCESS
) {
1053 "PciBus: [%02x|%02x|%02x] was rejected due to resource confliction.\n",
1054 PciResNode
->PciDev
->BusNumber
, PciResNode
->PciDev
->DeviceNumber
, PciResNode
->PciDev
->FunctionNumber
1058 // Raise the EFI_IOB_EC_RESOURCE_CONFLICT status code
1061 // Have no way to get ReqRes, AllocRes & Bar here
1063 ZeroMem (&AllocFailExtendedData
, sizeof (AllocFailExtendedData
));
1064 AllocFailExtendedData
.DevicePathSize
= (UINT16
) sizeof (EFI_DEVICE_PATH_PROTOCOL
);
1065 AllocFailExtendedData
.DevicePath
= (UINT8
*) PciResNode
->PciDev
->DevicePath
;
1066 AllocFailExtendedData
.Bar
= PciResNode
->Bar
;
1068 REPORT_STATUS_CODE_WITH_EXTENDED_DATA (
1070 EFI_IO_BUS_PCI
| EFI_IOB_EC_RESOURCE_CONFLICT
,
1071 (VOID
*) &AllocFailExtendedData
,
1072 sizeof (AllocFailExtendedData
)
1076 // Add it to the array and indicate at least a device has been rejected
1078 RemovedPciDev
[RemovedPciDevNum
++] = PciResNode
->PciDev
;
1079 AllocationAjusted
= TRUE
;
1086 if (AllocationAjusted
) {
1094 Summary requests for all resource type, and contruct ACPI resource
1097 @param Bridge detecting bridge
1098 @param IoNode Pointer to instance of I/O resource Node
1099 @param Mem32Node Pointer to instance of 32-bit memory resource Node
1100 @param PMem32Node Pointer to instance of 32-bit Pmemory resource node
1101 @param Mem64Node Pointer to instance of 64-bit memory resource node
1102 @param PMem64Node Pointer to instance of 64-bit Pmemory resource node
1103 @param Config Output buffer holding new constructed APCI resource requestor
1105 @retval EFI_SUCCESS Successfully constructed ACPI resource.
1106 @retval EFI_OUT_OF_RESOURCES No memory availabe.
1110 ConstructAcpiResourceRequestor (
1111 IN PCI_IO_DEVICE
*Bridge
,
1112 IN PCI_RESOURCE_NODE
*IoNode
,
1113 IN PCI_RESOURCE_NODE
*Mem32Node
,
1114 IN PCI_RESOURCE_NODE
*PMem32Node
,
1115 IN PCI_RESOURCE_NODE
*Mem64Node
,
1116 IN PCI_RESOURCE_NODE
*PMem64Node
,
1122 UINT8
*Configuration
;
1123 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Ptr
;
1124 EFI_ACPI_END_TAG_DESCRIPTOR
*PtrEnd
;
1132 // if there is io request, add to the io aperture
1134 if (ResourceRequestExisted (IoNode
)) {
1140 // if there is mem32 request, add to the mem32 aperture
1142 if (ResourceRequestExisted (Mem32Node
)) {
1148 // if there is pmem32 request, add to the pmem32 aperture
1150 if (ResourceRequestExisted (PMem32Node
)) {
1156 // if there is mem64 request, add to the mem64 aperture
1158 if (ResourceRequestExisted (Mem64Node
)) {
1164 // if there is pmem64 request, add to the pmem64 aperture
1166 if (ResourceRequestExisted (PMem64Node
)) {
1171 if (NumConfig
!= 0) {
1174 // If there is at least one type of resource request,
1175 // allocate a acpi resource node
1177 Configuration
= AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) * NumConfig
+ sizeof (EFI_ACPI_END_TAG_DESCRIPTOR
));
1178 if (Configuration
== NULL
) {
1179 return EFI_OUT_OF_RESOURCES
;
1182 Ptr
= (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*) Configuration
;
1185 // Deal with io aperture
1187 if ((Aperture
& 0x01) != 0) {
1188 Ptr
->Desc
= ACPI_ADDRESS_SPACE_DESCRIPTOR
;
1189 Ptr
->Len
= (UINT16
) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) - 3);
1193 Ptr
->ResType
= ACPI_ADDRESS_SPACE_TYPE_IO
;
1197 Ptr
->SpecificFlag
= 1;
1198 Ptr
->AddrLen
= IoNode
->Length
;
1199 Ptr
->AddrRangeMax
= IoNode
->Alignment
;
1204 // Deal with mem32 aperture
1206 if ((Aperture
& 0x02) != 0) {
1207 Ptr
->Desc
= ACPI_ADDRESS_SPACE_DESCRIPTOR
;
1208 Ptr
->Len
= (UINT16
) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) - 3);
1212 Ptr
->ResType
= ACPI_ADDRESS_SPACE_TYPE_MEM
;
1216 Ptr
->SpecificFlag
= 0;
1220 Ptr
->AddrSpaceGranularity
= 32;
1221 Ptr
->AddrLen
= Mem32Node
->Length
;
1222 Ptr
->AddrRangeMax
= Mem32Node
->Alignment
;
1228 // Deal with Pmem32 aperture
1230 if ((Aperture
& 0x04) != 0) {
1231 Ptr
->Desc
= ACPI_ADDRESS_SPACE_DESCRIPTOR
;
1232 Ptr
->Len
= (UINT16
) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) - 3);
1236 Ptr
->ResType
= ACPI_ADDRESS_SPACE_TYPE_MEM
;
1240 Ptr
->SpecificFlag
= 0x6;
1244 Ptr
->AddrSpaceGranularity
= 32;
1245 Ptr
->AddrLen
= PMem32Node
->Length
;
1246 Ptr
->AddrRangeMax
= PMem32Node
->Alignment
;
1251 // Deal with mem64 aperture
1253 if ((Aperture
& 0x08) != 0) {
1254 Ptr
->Desc
= ACPI_ADDRESS_SPACE_DESCRIPTOR
;
1255 Ptr
->Len
= (UINT16
) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) - 3);
1259 Ptr
->ResType
= ACPI_ADDRESS_SPACE_TYPE_MEM
;
1263 Ptr
->SpecificFlag
= 0;
1267 Ptr
->AddrSpaceGranularity
= 64;
1268 Ptr
->AddrLen
= Mem64Node
->Length
;
1269 Ptr
->AddrRangeMax
= Mem64Node
->Alignment
;
1274 // Deal with Pmem64 aperture
1276 if ((Aperture
& 0x10) != 0) {
1277 Ptr
->Desc
= ACPI_ADDRESS_SPACE_DESCRIPTOR
;
1278 Ptr
->Len
= (UINT16
) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) - 3);
1282 Ptr
->ResType
= ACPI_ADDRESS_SPACE_TYPE_MEM
;
1286 Ptr
->SpecificFlag
= 0x06;
1290 Ptr
->AddrSpaceGranularity
= 64;
1291 Ptr
->AddrLen
= PMem64Node
->Length
;
1292 Ptr
->AddrRangeMax
= PMem64Node
->Alignment
;
1300 PtrEnd
= (EFI_ACPI_END_TAG_DESCRIPTOR
*) Ptr
;
1302 PtrEnd
->Desc
= ACPI_END_TAG_DESCRIPTOR
;
1303 PtrEnd
->Checksum
= 0;
1308 // If there is no resource request
1310 Configuration
= AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR
));
1311 if (Configuration
== NULL
) {
1312 return EFI_OUT_OF_RESOURCES
;
1315 Ptr
= (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*) (Configuration
);
1316 Ptr
->Desc
= ACPI_ADDRESS_SPACE_DESCRIPTOR
;
1318 PtrEnd
= (EFI_ACPI_END_TAG_DESCRIPTOR
*) (Ptr
+ 1);
1319 PtrEnd
->Desc
= ACPI_END_TAG_DESCRIPTOR
;
1320 PtrEnd
->Checksum
= 0;
1323 *Config
= Configuration
;
1329 Get resource base from an acpi configuration descriptor.
1331 @param Config An acpi configuration descriptor.
1332 @param IoBase Output of I/O resource base address.
1333 @param Mem32Base Output of 32-bit memory base address.
1334 @param PMem32Base Output of 32-bit prefetchable memory base address.
1335 @param Mem64Base Output of 64-bit memory base address.
1336 @param PMem64Base Output of 64-bit prefetchable memory base address.
1343 OUT UINT64
*Mem32Base
,
1344 OUT UINT64
*PMem32Base
,
1345 OUT UINT64
*Mem64Base
,
1346 OUT UINT64
*PMem64Base
1350 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Ptr
;
1353 ASSERT (Config
!= NULL
);
1355 *IoBase
= 0xFFFFFFFFFFFFFFFFULL
;
1356 *Mem32Base
= 0xFFFFFFFFFFFFFFFFULL
;
1357 *PMem32Base
= 0xFFFFFFFFFFFFFFFFULL
;
1358 *Mem64Base
= 0xFFFFFFFFFFFFFFFFULL
;
1359 *PMem64Base
= 0xFFFFFFFFFFFFFFFFULL
;
1361 Temp
= (UINT8
*) Config
;
1363 while (*Temp
== ACPI_ADDRESS_SPACE_DESCRIPTOR
) {
1365 Ptr
= (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*) Temp
;
1366 ResStatus
= Ptr
->AddrTranslationOffset
;
1368 if (ResStatus
== EFI_RESOURCE_SATISFIED
) {
1370 switch (Ptr
->ResType
) {
1373 // Memory type aperture
1378 // Check to see the granularity
1380 if (Ptr
->AddrSpaceGranularity
== 32) {
1381 if ((Ptr
->SpecificFlag
& 0x06) != 0) {
1382 *PMem32Base
= Ptr
->AddrRangeMin
;
1384 *Mem32Base
= Ptr
->AddrRangeMin
;
1388 if (Ptr
->AddrSpaceGranularity
== 64) {
1389 if ((Ptr
->SpecificFlag
& 0x06) != 0) {
1390 *PMem64Base
= Ptr
->AddrRangeMin
;
1392 *Mem64Base
= Ptr
->AddrRangeMin
;
1402 *IoBase
= Ptr
->AddrRangeMin
;
1416 Temp
+= sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
);
1421 Enumerate pci bridge, allocate resource and determine attribute
1422 for devices on this bridge.
1424 @param BridgeDev Pointer to instance of bridge device.
1426 @retval EFI_SUCCESS Successfully enumerated PCI bridge.
1427 @retval other Failed to enumerate.
1431 PciBridgeEnumerator (
1432 IN PCI_IO_DEVICE
*BridgeDev
1436 UINT8 StartBusNumber
;
1437 EFI_PCI_IO_PROTOCOL
*PciIo
;
1442 PciIo
= &(BridgeDev
->PciIo
);
1443 Status
= PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, 0x19, 1, &StartBusNumber
);
1445 if (EFI_ERROR (Status
)) {
1449 Status
= PciAssignBusNumber (
1455 if (EFI_ERROR (Status
)) {
1459 Status
= PciPciDeviceInfoCollector (BridgeDev
, StartBusNumber
);
1461 if (EFI_ERROR (Status
)) {
1465 Status
= PciBridgeResourceAllocator (BridgeDev
);
1467 if (EFI_ERROR (Status
)) {
1471 Status
= DetermineDeviceAttribute (BridgeDev
);
1473 if (EFI_ERROR (Status
)) {
1482 Allocate all kinds of resource for PCI bridge.
1484 @param Bridge Pointer to bridge instance.
1486 @retval EFI_SUCCESS Successfully allocated resource for PCI bridge.
1487 @retval other Failed to allocate resource for bridge.
1491 PciBridgeResourceAllocator (
1492 IN PCI_IO_DEVICE
*Bridge
1495 PCI_RESOURCE_NODE
*IoBridge
;
1496 PCI_RESOURCE_NODE
*Mem32Bridge
;
1497 PCI_RESOURCE_NODE
*PMem32Bridge
;
1498 PCI_RESOURCE_NODE
*Mem64Bridge
;
1499 PCI_RESOURCE_NODE
*PMem64Bridge
;
1507 IoBridge
= CreateResourceNode (
1510 Bridge
->BridgeIoAlignment
,
1516 Mem32Bridge
= CreateResourceNode (
1525 PMem32Bridge
= CreateResourceNode (
1534 Mem64Bridge
= CreateResourceNode (
1543 PMem64Bridge
= CreateResourceNode (
1553 // Create resourcemap by going through all the devices subject to this root bridge
1564 Status
= GetResourceBaseFromBridge (
1573 if (EFI_ERROR (Status
)) {
1578 // Program IO resources
1586 // Program Mem32 resources
1594 // Program PMem32 resources
1602 // Program Mem64 resources
1610 // Program PMem64 resources
1617 DestroyResourceTree (IoBridge
);
1618 DestroyResourceTree (Mem32Bridge
);
1619 DestroyResourceTree (PMem32Bridge
);
1620 DestroyResourceTree (PMem64Bridge
);
1621 DestroyResourceTree (Mem64Bridge
);
1623 gBS
->FreePool (IoBridge
);
1624 gBS
->FreePool (Mem32Bridge
);
1625 gBS
->FreePool (PMem32Bridge
);
1626 gBS
->FreePool (PMem64Bridge
);
1627 gBS
->FreePool (Mem64Bridge
);
1633 Get resource base address for a pci bridge device.
1635 @param Bridge Given Pci driver instance.
1636 @param IoBase Output for base address of I/O type resource.
1637 @param Mem32Base Output for base address of 32-bit memory type resource.
1638 @param PMem32Base Ooutput for base address of 32-bit Pmemory type resource.
1639 @param Mem64Base Output for base address of 64-bit memory type resource.
1640 @param PMem64Base Output for base address of 64-bit Pmemory type resource.
1642 @retval EFI_SUCCESS Successfully got resource base address.
1643 @retval EFI_OUT_OF_RESOURCES PCI bridge is not available.
1647 GetResourceBaseFromBridge (
1648 IN PCI_IO_DEVICE
*Bridge
,
1650 OUT UINT64
*Mem32Base
,
1651 OUT UINT64
*PMem32Base
,
1652 OUT UINT64
*Mem64Base
,
1653 OUT UINT64
*PMem64Base
1656 if (!Bridge
->Allocated
) {
1657 return EFI_OUT_OF_RESOURCES
;
1661 *Mem32Base
= gAllOne
;
1662 *PMem32Base
= gAllOne
;
1663 *Mem64Base
= gAllOne
;
1664 *PMem64Base
= gAllOne
;
1666 if (IS_PCI_BRIDGE (&Bridge
->Pci
)) {
1668 if (Bridge
->PciBar
[PPB_IO_RANGE
].Length
> 0) {
1669 *IoBase
= Bridge
->PciBar
[PPB_IO_RANGE
].BaseAddress
;
1672 if (Bridge
->PciBar
[PPB_MEM32_RANGE
].Length
> 0) {
1673 *Mem32Base
= Bridge
->PciBar
[PPB_MEM32_RANGE
].BaseAddress
;
1676 if (Bridge
->PciBar
[PPB_PMEM32_RANGE
].Length
> 0) {
1677 *PMem32Base
= Bridge
->PciBar
[PPB_PMEM32_RANGE
].BaseAddress
;
1680 if (Bridge
->PciBar
[PPB_PMEM64_RANGE
].Length
> 0) {
1681 *PMem64Base
= Bridge
->PciBar
[PPB_PMEM64_RANGE
].BaseAddress
;
1683 *PMem64Base
= gAllOne
;
1688 if (IS_CARDBUS_BRIDGE (&Bridge
->Pci
)) {
1689 if (Bridge
->PciBar
[P2C_IO_1
].Length
> 0) {
1690 *IoBase
= Bridge
->PciBar
[P2C_IO_1
].BaseAddress
;
1692 if (Bridge
->PciBar
[P2C_IO_2
].Length
> 0) {
1693 *IoBase
= Bridge
->PciBar
[P2C_IO_2
].BaseAddress
;
1697 if (Bridge
->PciBar
[P2C_MEM_1
].Length
> 0) {
1698 if (Bridge
->PciBar
[P2C_MEM_1
].BarType
== PciBarTypePMem32
) {
1699 *PMem32Base
= Bridge
->PciBar
[P2C_MEM_1
].BaseAddress
;
1702 if (Bridge
->PciBar
[P2C_MEM_1
].BarType
== PciBarTypeMem32
) {
1703 *Mem32Base
= Bridge
->PciBar
[P2C_MEM_1
].BaseAddress
;
1707 if (Bridge
->PciBar
[P2C_MEM_2
].Length
> 0) {
1708 if (Bridge
->PciBar
[P2C_MEM_2
].BarType
== PciBarTypePMem32
) {
1709 *PMem32Base
= Bridge
->PciBar
[P2C_MEM_2
].BaseAddress
;
1712 if (Bridge
->PciBar
[P2C_MEM_2
].BarType
== PciBarTypeMem32
) {
1713 *Mem32Base
= Bridge
->PciBar
[P2C_MEM_2
].BaseAddress
;
1722 These are the notifications from the PCI bus driver that it is about to enter a certain
1723 phase of the PCI enumeration process.
1725 This member function can be used to notify the host bridge driver to perform specific actions,
1726 including any chipset-specific initialization, so that the chipset is ready to enter the next phase.
1727 Eight notification points are defined at this time. See belows:
1728 EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures and internal data
1729 structures. The PCI enumerator should issue this notification
1730 before starting a fresh enumeration process. Enumeration cannot
1731 be restarted after sending any other notification such as
1732 EfiPciHostBridgeBeginBusAllocation.
1733 EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin. No specific action is
1734 required here. This notification can be used to perform any
1735 chipset-specific programming.
1736 EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming phase is complete. No
1737 specific action is required here. This notification can be used to
1738 perform any chipset-specific programming.
1739 EfiPciHostBridgeBeginResourceAllocation
1740 The resource allocation phase is about to begin. No specific
1741 action is required here. This notification can be used to perform
1742 any chipset-specific programming.
1743 EfiPciHostBridgeAllocateResources Allocates resources per previously submitted requests for all the PCI
1744 root bridges. These resource settings are returned on the next call to
1745 GetProposedResources(). Before calling NotifyPhase() with a Phase of
1746 EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible
1747 for gathering I/O and memory requests for
1748 all the PCI root bridges and submitting these requests using
1749 SubmitResources(). This function pads the resource amount
1750 to suit the root bridge hardware, takes care of dependencies between
1751 the PCI root bridges, and calls the Global Coherency Domain (GCD)
1752 with the allocation request. In the case of padding, the allocated range
1753 could be bigger than what was requested.
1754 EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated
1755 resources (proposed resources) for all the PCI root bridges. After the
1756 hardware is programmed, reassigning resources will not be supported.
1757 The bus settings are not affected.
1758 EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI
1759 root bridges and resets the I/O and memory apertures to their initial
1760 state. The bus settings are not affected. If the request to allocate
1761 resources fails, the PCI enumerator can use this notification to
1762 deallocate previous resources, adjust the requests, and retry
1764 EfiPciHostBridgeEndResourceAllocation The resource allocation phase is completed. No specific action is
1765 required here. This notification can be used to perform any chipsetspecific
1768 @param[in] PciResAlloc The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
1769 @param[in] Phase The phase during enumeration
1771 @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error
1772 is valid for a Phase of EfiPciHostBridgeAllocateResources if
1773 SubmitResources() has not been called for one or more
1774 PCI root bridges before this call
1775 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid
1776 for a Phase of EfiPciHostBridgeSetResources.
1777 @retval EFI_INVALID_PARAMETER Invalid phase parameter
1778 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1779 This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the
1780 previously submitted resource requests cannot be fulfilled or
1781 were only partially fulfilled.
1782 @retval EFI_SUCCESS The notification was accepted without any errors.
1787 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
*PciResAlloc
,
1788 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
1791 EFI_HANDLE HostBridgeHandle
;
1792 EFI_HANDLE RootBridgeHandle
;
1793 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
1796 HostBridgeHandle
= NULL
;
1797 RootBridgeHandle
= NULL
;
1798 if (gPciPlatformProtocol
!= NULL
) {
1800 // Get Host Bridge Handle.
1802 PciResAlloc
->GetNextRootBridge (PciResAlloc
, &RootBridgeHandle
);
1805 // Get the rootbridge Io protocol to find the host bridge handle
1807 Status
= gBS
->HandleProtocol (
1809 &gEfiPciRootBridgeIoProtocolGuid
,
1810 (VOID
**) &PciRootBridgeIo
1813 if (EFI_ERROR (Status
)) {
1814 return EFI_NOT_FOUND
;
1817 HostBridgeHandle
= PciRootBridgeIo
->ParentHandle
;
1820 // Call PlatformPci::PlatformNotify() if the protocol is present.
1822 gPciPlatformProtocol
->PlatformNotify (
1823 gPciPlatformProtocol
,
1828 } else if (gPciOverrideProtocol
!= NULL
){
1830 // Get Host Bridge Handle.
1832 PciResAlloc
->GetNextRootBridge (PciResAlloc
, &RootBridgeHandle
);
1835 // Get the rootbridge Io protocol to find the host bridge handle
1837 Status
= gBS
->HandleProtocol (
1839 &gEfiPciRootBridgeIoProtocolGuid
,
1840 (VOID
**) &PciRootBridgeIo
1843 if (EFI_ERROR (Status
)) {
1844 return EFI_NOT_FOUND
;
1847 HostBridgeHandle
= PciRootBridgeIo
->ParentHandle
;
1850 // Call PlatformPci::PhaseNotify() if the protocol is present.
1852 gPciOverrideProtocol
->PlatformNotify (
1853 gPciOverrideProtocol
,
1860 Status
= PciResAlloc
->NotifyPhase (
1865 if (gPciPlatformProtocol
!= NULL
) {
1867 // Call PlatformPci::PlatformNotify() if the protocol is present.
1869 gPciPlatformProtocol
->PlatformNotify (
1870 gPciPlatformProtocol
,
1876 } else if (gPciOverrideProtocol
!= NULL
) {
1878 // Call PlatformPci::PhaseNotify() if the protocol is present.
1880 gPciOverrideProtocol
->PlatformNotify (
1881 gPciOverrideProtocol
,
1892 Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various
1893 stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual
1894 PCI controllers before enumeration.
1896 This function is called during the PCI enumeration process. No specific action is expected from this
1897 member function. It allows the host bridge driver to preinitialize individual PCI controllers before
1900 @param Bridge Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
1901 @param Bus The bus number of the pci device.
1902 @param Device The device number of the pci device.
1903 @param Func The function number of the pci device.
1904 @param Phase The phase of the PCI device enumeration.
1906 @retval EFI_SUCCESS The requested parameters were returned.
1907 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
1908 @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in
1909 EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.
1910 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should
1911 not enumerate this device, including its child devices if it is a PCI-to-PCI
1916 PreprocessController (
1917 IN PCI_IO_DEVICE
*Bridge
,
1921 IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
1924 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS RootBridgePciAddress
;
1925 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
*PciResAlloc
;
1926 EFI_HANDLE RootBridgeHandle
;
1927 EFI_HANDLE HostBridgeHandle
;
1931 // Get the host bridge handle
1933 HostBridgeHandle
= Bridge
->PciRootBridgeIo
->ParentHandle
;
1936 // Get the pci host bridge resource allocation protocol
1938 Status
= gBS
->OpenProtocol (
1940 &gEfiPciHostBridgeResourceAllocationProtocolGuid
,
1941 (VOID
**) &PciResAlloc
,
1944 EFI_OPEN_PROTOCOL_GET_PROTOCOL
1947 if (EFI_ERROR (Status
)) {
1948 return EFI_UNSUPPORTED
;
1952 // Get Root Brige Handle
1954 while (Bridge
->Parent
!= NULL
) {
1955 Bridge
= Bridge
->Parent
;
1958 RootBridgeHandle
= Bridge
->Handle
;
1960 RootBridgePciAddress
.Register
= 0;
1961 RootBridgePciAddress
.Function
= Func
;
1962 RootBridgePciAddress
.Device
= Device
;
1963 RootBridgePciAddress
.Bus
= Bus
;
1964 RootBridgePciAddress
.ExtendedRegister
= 0;
1966 if (gPciPlatformProtocol
!= NULL
) {
1968 // Call PlatformPci::PrepController() if the protocol is present.
1970 gPciPlatformProtocol
->PlatformPrepController (
1971 gPciPlatformProtocol
,
1974 RootBridgePciAddress
,
1978 } else if (gPciOverrideProtocol
!= NULL
) {
1980 // Call PlatformPci::PrepController() if the protocol is present.
1982 gPciOverrideProtocol
->PlatformPrepController (
1983 gPciOverrideProtocol
,
1986 RootBridgePciAddress
,
1992 Status
= PciResAlloc
->PreprocessController (
1995 RootBridgePciAddress
,
1999 if (gPciPlatformProtocol
!= NULL
) {
2001 // Call PlatformPci::PrepController() if the protocol is present.
2003 gPciPlatformProtocol
->PlatformPrepController (
2004 gPciPlatformProtocol
,
2007 RootBridgePciAddress
,
2011 } else if (gPciOverrideProtocol
!= NULL
) {
2013 // Call PlatformPci::PrepController() if the protocol is present.
2015 gPciOverrideProtocol
->PlatformPrepController (
2016 gPciOverrideProtocol
,
2019 RootBridgePciAddress
,
2029 This function allows the PCI bus driver to be notified to act as requested when a hot-plug event has
2030 happened on the hot-plug controller. Currently, the operations include add operation and remove operation..
2032 @param This A pointer to the hot plug request protocol.
2033 @param Operation The operation the PCI bus driver is requested to make.
2034 @param Controller The handle of the hot-plug controller.
2035 @param RemainingDevicePath The remaining device path for the PCI-like hot-plug device.
2036 @param NumberOfChildren The number of child handles.
2037 For a add operation, it is an output parameter.
2038 For a remove operation, it's an input parameter.
2039 @param ChildHandleBuffer The buffer which contains the child handles.
2041 @retval EFI_INVALID_PARAMETER Operation is not a legal value.
2042 Controller is NULL or not a valid handle.
2043 NumberOfChildren is NULL.
2044 ChildHandleBuffer is NULL while Operation is add.
2045 @retval EFI_OUT_OF_RESOURCES There are no enough resources to start the devices.
2046 @retval EFI_NOT_FOUND Can not find bridge according to controller handle.
2047 @retval EFI_SUCCESS The handles for the specified device have been created or destroyed
2048 as requested, and for an add operation, the new handles are
2049 returned in ChildHandleBuffer.
2053 PciHotPlugRequestNotify (
2054 IN EFI_PCI_HOTPLUG_REQUEST_PROTOCOL
* This
,
2055 IN EFI_PCI_HOTPLUG_OPERATION Operation
,
2056 IN EFI_HANDLE Controller
,
2057 IN EFI_DEVICE_PATH_PROTOCOL
* RemainingDevicePath OPTIONAL
,
2058 IN OUT UINT8
*NumberOfChildren
,
2059 IN OUT EFI_HANDLE
* ChildHandleBuffer
2062 PCI_IO_DEVICE
*Bridge
;
2063 PCI_IO_DEVICE
*Temp
;
2064 EFI_PCI_IO_PROTOCOL
*PciIo
;
2066 EFI_HANDLE RootBridgeHandle
;
2070 // Check input parameter validity
2072 if ((Controller
== NULL
) || (NumberOfChildren
== NULL
)){
2073 return EFI_INVALID_PARAMETER
;
2076 if ((Operation
!= EfiPciHotPlugRequestAdd
) && (Operation
!= EfiPciHotplugRequestRemove
)) {
2077 return EFI_INVALID_PARAMETER
;
2080 if (Operation
== EfiPciHotPlugRequestAdd
){
2081 if (ChildHandleBuffer
== NULL
) {
2082 return EFI_INVALID_PARAMETER
;
2084 } else if ((Operation
== EfiPciHotplugRequestRemove
) && (*NumberOfChildren
!= 0)) {
2085 if (ChildHandleBuffer
== NULL
) {
2086 return EFI_INVALID_PARAMETER
;
2090 Status
= gBS
->OpenProtocol (
2092 &gEfiPciIoProtocolGuid
,
2094 gPciBusDriverBinding
.DriverBindingHandle
,
2096 EFI_OPEN_PROTOCOL_GET_PROTOCOL
2099 if (EFI_ERROR (Status
)) {
2100 return EFI_NOT_FOUND
;
2103 Bridge
= PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo
);
2106 // Get root bridge handle
2109 while (Temp
->Parent
!= NULL
) {
2110 Temp
= Temp
->Parent
;
2113 RootBridgeHandle
= Temp
->Handle
;
2115 if (Operation
== EfiPciHotPlugRequestAdd
) {
2117 // Report Status Code to indicate hot plug happens
2119 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
2121 (EFI_IO_BUS_PCI
| EFI_IOB_PC_HOTPLUG
),
2125 if (NumberOfChildren
!= NULL
) {
2126 *NumberOfChildren
= 0;
2129 if (IsListEmpty (&Bridge
->ChildList
)) {
2131 Status
= PciBridgeEnumerator (Bridge
);
2133 if (EFI_ERROR (Status
)) {
2138 Status
= StartPciDevicesOnBridge (
2141 RemainingDevicePath
,
2149 if (Operation
== EfiPciHotplugRequestRemove
) {
2151 if (*NumberOfChildren
== 0) {
2153 // Remove all devices on the bridge
2155 RemoveAllPciDeviceOnBridge (RootBridgeHandle
, Bridge
);
2160 for (Index
= 0; Index
< *NumberOfChildren
; Index
++) {
2162 // De register all the pci device
2164 Status
= DeRegisterPciDevice (RootBridgeHandle
, ChildHandleBuffer
[Index
]);
2166 if (EFI_ERROR (Status
)) {
2181 Search hostbridge according to given handle
2183 @param RootBridgeHandle Host bridge handle.
2185 @retval TRUE Found host bridge handle.
2186 @retval FALSE Not found hot bridge handle.
2190 SearchHostBridgeHandle (
2191 IN EFI_HANDLE RootBridgeHandle
2194 EFI_HANDLE HostBridgeHandle
;
2195 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
2200 // Get the rootbridge Io protocol to find the host bridge handle
2202 Status
= gBS
->OpenProtocol (
2204 &gEfiPciRootBridgeIoProtocolGuid
,
2205 (VOID
**) &PciRootBridgeIo
,
2206 gPciBusDriverBinding
.DriverBindingHandle
,
2208 EFI_OPEN_PROTOCOL_GET_PROTOCOL
2211 if (EFI_ERROR (Status
)) {
2215 HostBridgeHandle
= PciRootBridgeIo
->ParentHandle
;
2216 for (Index
= 0; Index
< gPciHostBridgeNumber
; Index
++) {
2217 if (HostBridgeHandle
== gPciHostBrigeHandles
[Index
]) {
2226 Add host bridge handle to global variable for enumerating.
2228 @param HostBridgeHandle Host bridge handle.
2230 @retval EFI_SUCCESS Successfully added host bridge.
2231 @retval EFI_ABORTED Host bridge is NULL, or given host bridge
2232 has been in host bridge list.
2236 AddHostBridgeEnumerator (
2237 IN EFI_HANDLE HostBridgeHandle
2242 if (HostBridgeHandle
== NULL
) {
2246 for (Index
= 0; Index
< gPciHostBridgeNumber
; Index
++) {
2247 if (HostBridgeHandle
== gPciHostBrigeHandles
[Index
]) {
2252 if (Index
< PCI_MAX_HOST_BRIDGE_NUM
) {
2253 gPciHostBrigeHandles
[Index
] = HostBridgeHandle
;
2254 gPciHostBridgeNumber
++;