2 PCI eunmeration implementation on entire PCI bus system for PCI Bus module.
4 Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 This routine is used to enumerate entire pci bus system
21 @param Controller Parent controller handle.
23 @retval EFI_SUCCESS PCI enumeration finished successfully.
24 @retval other Some error occurred when enumerating the pci bus system.
29 IN EFI_HANDLE Controller
33 EFI_HANDLE HostBridgeHandle
;
35 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
*PciResAlloc
;
36 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
39 // If PCI bus has already done the full enumeration, never do it again
41 if (!gFullEnumeration
) {
42 return PciEnumeratorLight (Controller
);
46 // Get the rootbridge Io protocol to find the host bridge handle
48 Status
= gBS
->OpenProtocol (
50 &gEfiPciRootBridgeIoProtocolGuid
,
51 (VOID
**) &PciRootBridgeIo
,
52 gPciBusDriverBinding
.DriverBindingHandle
,
54 EFI_OPEN_PROTOCOL_GET_PROTOCOL
57 if (EFI_ERROR (Status
)) {
62 // Get the host bridge handle
64 HostBridgeHandle
= PciRootBridgeIo
->ParentHandle
;
67 // Get the pci host bridge resource allocation protocol
69 Status
= gBS
->OpenProtocol (
71 &gEfiPciHostBridgeResourceAllocationProtocolGuid
,
72 (VOID
**) &PciResAlloc
,
73 gPciBusDriverBinding
.DriverBindingHandle
,
75 EFI_OPEN_PROTOCOL_GET_PROTOCOL
78 if (EFI_ERROR (Status
)) {
83 // Notify the pci bus enumeration is about to begin
85 NotifyPhase (PciResAlloc
, EfiPciHostBridgeBeginEnumeration
);
88 // Start the bus allocation phase
90 Status
= PciHostBridgeEnumerator (PciResAlloc
);
92 if (EFI_ERROR (Status
)) {
97 // Submit the resource request
99 Status
= PciHostBridgeResourceAllocator (PciResAlloc
);
101 if (EFI_ERROR (Status
)) {
106 // Notify the pci bus enumeration is about to complete
108 NotifyPhase (PciResAlloc
, EfiPciHostBridgeEndEnumeration
);
113 Status
= PciHostBridgeP2CProcess (PciResAlloc
);
115 if (EFI_ERROR (Status
)) {
120 // Process attributes for devices on this host bridge
122 Status
= PciHostBridgeDeviceAttribute (PciResAlloc
);
123 if (EFI_ERROR (Status
)) {
127 gFullEnumeration
= FALSE
;
130 Status
= gBS
->InstallProtocolInterface (
132 &gEfiPciEnumerationCompleteProtocolGuid
,
133 EFI_NATIVE_INTERFACE
,
136 if (EFI_ERROR (Status
)) {
144 Enumerate PCI root bridge.
146 @param PciResAlloc Pointer to protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.
147 @param RootBridgeDev Instance of root bridge device.
149 @retval EFI_SUCCESS Successfully enumerated root bridge.
150 @retval other Failed to enumerate root bridge.
154 PciRootBridgeEnumerator (
155 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
*PciResAlloc
,
156 IN PCI_IO_DEVICE
*RootBridgeDev
160 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Configuration
;
161 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Configuration1
;
162 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Configuration2
;
163 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Configuration3
;
165 UINT8 StartBusNumber
;
166 UINT8 PaddedBusRange
;
167 EFI_HANDLE RootBridgeHandle
;
177 // Get the root bridge handle
179 RootBridgeHandle
= RootBridgeDev
->Handle
;
181 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
183 EFI_IO_BUS_PCI
| EFI_IOB_PCI_BUS_ENUM
,
184 RootBridgeDev
->DevicePath
188 // Get the Bus information
190 Status
= PciResAlloc
->StartBusEnumeration (
193 (VOID
**) &Configuration
196 if (EFI_ERROR (Status
)) {
200 if (Configuration
== NULL
|| Configuration
->Desc
== ACPI_END_TAG_DESCRIPTOR
) {
201 return EFI_INVALID_PARAMETER
;
203 RootBridgeDev
->BusNumberRanges
= Configuration
;
206 // Sort the descriptors in ascending order
208 for (Configuration1
= Configuration
; Configuration1
->Desc
!= ACPI_END_TAG_DESCRIPTOR
; Configuration1
++) {
209 Configuration2
= Configuration1
;
210 for (Configuration3
= Configuration1
+ 1; Configuration3
->Desc
!= ACPI_END_TAG_DESCRIPTOR
; Configuration3
++) {
211 if (Configuration2
->AddrRangeMin
> Configuration3
->AddrRangeMin
) {
212 Configuration2
= Configuration3
;
216 // All other fields other than AddrRangeMin and AddrLen are ignored in a descriptor,
217 // so only need to swap these two fields.
219 if (Configuration2
!= Configuration1
) {
220 AddrRangeMin
= Configuration1
->AddrRangeMin
;
221 Configuration1
->AddrRangeMin
= Configuration2
->AddrRangeMin
;
222 Configuration2
->AddrRangeMin
= AddrRangeMin
;
224 AddrLen
= Configuration1
->AddrLen
;
225 Configuration1
->AddrLen
= Configuration2
->AddrLen
;
226 Configuration2
->AddrLen
= AddrLen
;
231 // Get the bus number to start with
233 StartBusNumber
= (UINT8
) (Configuration
->AddrRangeMin
);
236 // Initialize the subordinate bus number
238 SubBusNumber
= StartBusNumber
;
241 // Reset all assigned PCI bus number
243 ResetAllPpbBusNumber (
251 Status
= PciScanBus (
258 if (EFI_ERROR (Status
)) {
264 // Assign max bus number scanned
267 Status
= PciAllocateBusNumber (RootBridgeDev
, SubBusNumber
, PaddedBusRange
, &SubBusNumber
);
268 if (EFI_ERROR (Status
)) {
273 // Find the bus range which contains the higest bus number, then returns the number of buses
274 // that should be decoded.
276 while (Configuration
->AddrRangeMin
+ Configuration
->AddrLen
- 1 < SubBusNumber
) {
279 AddrLen
= Configuration
->AddrLen
;
280 Configuration
->AddrLen
= SubBusNumber
- Configuration
->AddrRangeMin
+ 1;
283 // Save the Desc field of the next descriptor. Mark the next descriptor as an END descriptor.
286 Desc
= Configuration
->Desc
;
287 Configuration
->Desc
= ACPI_END_TAG_DESCRIPTOR
;
292 Status
= PciResAlloc
->SetBusNumbers (
295 RootBridgeDev
->BusNumberRanges
299 // Restore changed fields
301 Configuration
->Desc
= Desc
;
302 (Configuration
- 1)->AddrLen
= AddrLen
;
308 This routine is used to process all PCI devices' Option Rom
309 on a certain root bridge.
311 @param Bridge Given parent's root bridge.
312 @param RomBase Base address of ROM driver loaded from.
313 @param MaxLength Maximum rom size.
318 IN PCI_IO_DEVICE
*Bridge
,
323 LIST_ENTRY
*CurrentLink
;
327 // Go through bridges to reach all devices
329 CurrentLink
= Bridge
->ChildList
.ForwardLink
;
330 while (CurrentLink
!= NULL
&& CurrentLink
!= &Bridge
->ChildList
) {
331 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
332 if (!IsListEmpty (&Temp
->ChildList
)) {
335 // Go further to process the option rom under this bridge
337 ProcessOptionRom (Temp
, RomBase
, MaxLength
);
340 if (Temp
->RomSize
!= 0 && Temp
->RomSize
<= MaxLength
) {
343 // Load and process the option rom
345 LoadOpRomImage (Temp
, RomBase
);
348 CurrentLink
= CurrentLink
->ForwardLink
;
353 This routine is used to assign bus number to the given PCI bus system
355 @param Bridge Parent root bridge instance.
356 @param StartBusNumber Number of beginning.
357 @param SubBusNumber The number of sub bus.
359 @retval EFI_SUCCESS Successfully assigned bus number.
360 @retval EFI_DEVICE_ERROR Failed to assign bus number.
365 IN PCI_IO_DEVICE
*Bridge
,
366 IN UINT8 StartBusNumber
,
367 OUT UINT8
*SubBusNumber
378 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
380 PciRootBridgeIo
= Bridge
->PciRootBridgeIo
;
385 *SubBusNumber
= StartBusNumber
;
388 // First check to see whether the parent is ppb
390 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
391 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
394 // Check to see whether a pci device is present
396 Status
= PciDevicePresent (
404 if (!EFI_ERROR (Status
) &&
405 (IS_PCI_BRIDGE (&Pci
) || IS_CARDBUS_BRIDGE (&Pci
))) {
408 // Reserved one bus for cardbus bridge
410 Status
= PciAllocateBusNumber (Bridge
, *SubBusNumber
, 1, SubBusNumber
);
411 if (EFI_ERROR (Status
)) {
414 SecondBus
= *SubBusNumber
;
416 Register
= (UINT16
) ((SecondBus
<< 8) | (UINT16
) StartBusNumber
);
418 Address
= EFI_PCI_ADDRESS (StartBusNumber
, Device
, Func
, 0x18);
420 Status
= PciRootBridgeIo
->Pci
.Write (
429 // Initialize SubBusNumber to SecondBus
431 Address
= EFI_PCI_ADDRESS (StartBusNumber
, Device
, Func
, 0x1A);
432 Status
= PciRootBridgeIo
->Pci
.Write (
440 // If it is PPB, resursively search down this bridge
442 if (IS_PCI_BRIDGE (&Pci
)) {
445 Status
= PciRootBridgeIo
->Pci
.Write (
453 Status
= PciAssignBusNumber (
459 if (EFI_ERROR (Status
)) {
460 return EFI_DEVICE_ERROR
;
465 // Set the current maximum bus number under the PPB
467 Address
= EFI_PCI_ADDRESS (StartBusNumber
, Device
, Func
, 0x1A);
469 Status
= PciRootBridgeIo
->Pci
.Write (
479 if (Func
== 0 && !IS_PCI_MULTI_FUNC (&Pci
)) {
482 // Skip sub functions, this is not a multi function device
493 This routine is used to determine the root bridge attribute by interfacing
494 the host bridge resource allocation protocol.
496 @param PciResAlloc Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
497 @param RootBridgeDev Root bridge instance
499 @retval EFI_SUCCESS Successfully got root bridge's attribute.
500 @retval other Failed to get attribute.
504 DetermineRootBridgeAttributes (
505 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
*PciResAlloc
,
506 IN PCI_IO_DEVICE
*RootBridgeDev
511 EFI_HANDLE RootBridgeHandle
;
514 RootBridgeHandle
= RootBridgeDev
->Handle
;
517 // Get root bridge attribute by calling into pci host bridge resource allocation protocol
519 Status
= PciResAlloc
->GetAllocAttributes (
525 if (EFI_ERROR (Status
)) {
530 // Here is the point where PCI bus driver calls HOST bridge allocation protocol
531 // Currently we hardcoded for ea815
533 if ((Attributes
& EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM
) != 0) {
534 RootBridgeDev
->Decodes
|= EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED
;
537 if ((Attributes
& EFI_PCI_HOST_BRIDGE_MEM64_DECODE
) != 0) {
538 RootBridgeDev
->Decodes
|= EFI_BRIDGE_MEM64_DECODE_SUPPORTED
;
539 RootBridgeDev
->Decodes
|= EFI_BRIDGE_PMEM64_DECODE_SUPPORTED
;
542 RootBridgeDev
->Decodes
|= EFI_BRIDGE_MEM32_DECODE_SUPPORTED
;
543 RootBridgeDev
->Decodes
|= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED
;
544 RootBridgeDev
->Decodes
|= EFI_BRIDGE_IO16_DECODE_SUPPORTED
;
550 Get Max Option Rom size on specified bridge.
552 @param Bridge Given bridge device instance.
554 @return Max size of option rom needed.
558 GetMaxOptionRomSize (
559 IN PCI_IO_DEVICE
*Bridge
562 LIST_ENTRY
*CurrentLink
;
564 UINT64 MaxOptionRomSize
;
565 UINT64 TempOptionRomSize
;
567 MaxOptionRomSize
= 0;
570 // Go through bridges to reach all devices
572 CurrentLink
= Bridge
->ChildList
.ForwardLink
;
573 while (CurrentLink
!= NULL
&& CurrentLink
!= &Bridge
->ChildList
) {
574 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
575 if (!IsListEmpty (&Temp
->ChildList
)) {
578 // Get max option rom size under this bridge
580 TempOptionRomSize
= GetMaxOptionRomSize (Temp
);
583 // Compare with the option rom size of the bridge
584 // Get the larger one
586 if (Temp
->RomSize
> TempOptionRomSize
) {
587 TempOptionRomSize
= Temp
->RomSize
;
593 // For devices get the rom size directly
595 TempOptionRomSize
= Temp
->RomSize
;
599 // Get the largest rom size on this bridge
601 if (TempOptionRomSize
> MaxOptionRomSize
) {
602 MaxOptionRomSize
= TempOptionRomSize
;
605 CurrentLink
= CurrentLink
->ForwardLink
;
608 return MaxOptionRomSize
;
612 Process attributes of devices on this host bridge
614 @param PciResAlloc Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.
616 @retval EFI_SUCCESS Successfully process attribute.
617 @retval EFI_NOT_FOUND Can not find the specific root bridge device.
618 @retval other Failed to determine the root bridge device's attribute.
622 PciHostBridgeDeviceAttribute (
623 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
*PciResAlloc
626 EFI_HANDLE RootBridgeHandle
;
627 PCI_IO_DEVICE
*RootBridgeDev
;
630 RootBridgeHandle
= NULL
;
632 while (PciResAlloc
->GetNextRootBridge (PciResAlloc
, &RootBridgeHandle
) == EFI_SUCCESS
) {
635 // Get RootBridg Device by handle
637 RootBridgeDev
= GetRootBridgeByHandle (RootBridgeHandle
);
639 if (RootBridgeDev
== NULL
) {
640 return EFI_NOT_FOUND
;
644 // Set the attributes for devcies behind the Root Bridge
646 Status
= DetermineDeviceAttribute (RootBridgeDev
);
647 if (EFI_ERROR (Status
)) {
657 Get resource allocation status from the ACPI resource descriptor.
659 @param AcpiConfig Point to Acpi configuration table.
660 @param IoResStatus Return the status of I/O resource.
661 @param Mem32ResStatus Return the status of 32-bit Memory resource.
662 @param PMem32ResStatus Return the status of 32-bit Prefetchable Memory resource.
663 @param Mem64ResStatus Return the status of 64-bit Memory resource.
664 @param PMem64ResStatus Return the status of 64-bit Prefetchable Memory resource.
668 GetResourceAllocationStatus (
670 OUT UINT64
*IoResStatus
,
671 OUT UINT64
*Mem32ResStatus
,
672 OUT UINT64
*PMem32ResStatus
,
673 OUT UINT64
*Mem64ResStatus
,
674 OUT UINT64
*PMem64ResStatus
679 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*ACPIAddressDesc
;
681 Temp
= (UINT8
*) AcpiConfig
;
683 while (*Temp
== ACPI_ADDRESS_SPACE_DESCRIPTOR
) {
685 ACPIAddressDesc
= (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*) Temp
;
686 ResStatus
= ACPIAddressDesc
->AddrTranslationOffset
;
688 switch (ACPIAddressDesc
->ResType
) {
690 if (ACPIAddressDesc
->AddrSpaceGranularity
== 32) {
691 if (ACPIAddressDesc
->SpecificFlag
== 0x06) {
695 *PMem32ResStatus
= ResStatus
;
700 *Mem32ResStatus
= ResStatus
;
704 if (ACPIAddressDesc
->AddrSpaceGranularity
== 64) {
705 if (ACPIAddressDesc
->SpecificFlag
== 0x06) {
709 *PMem64ResStatus
= ResStatus
;
714 *Mem64ResStatus
= ResStatus
;
724 *IoResStatus
= ResStatus
;
731 Temp
+= sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
);
736 Remove a PCI device from device pool and mark its bar.
738 @param PciDevice Instance of Pci device.
740 @retval EFI_SUCCESS Successfully remove the PCI device.
741 @retval EFI_ABORTED Pci device is a root bridge or a PCI-PCI bridge.
746 IN PCI_IO_DEVICE
*PciDevice
749 PCI_IO_DEVICE
*Bridge
;
751 LIST_ENTRY
*CurrentLink
;
754 // Remove the padding resource from a bridge
756 if ( IS_PCI_BRIDGE(&PciDevice
->Pci
) &&
757 PciDevice
->ResourcePaddingDescriptors
!= NULL
) {
758 FreePool (PciDevice
->ResourcePaddingDescriptors
);
759 PciDevice
->ResourcePaddingDescriptors
= NULL
;
766 if (IS_PCI_BRIDGE (&PciDevice
->Pci
) || (PciDevice
->Parent
== NULL
)) {
770 if (IS_CARDBUS_BRIDGE (&PciDevice
->Pci
)) {
772 // Get the root bridge device
775 while (Bridge
->Parent
!= NULL
) {
776 Bridge
= Bridge
->Parent
;
779 RemoveAllPciDeviceOnBridge (Bridge
->Handle
, PciDevice
);
784 InitializeP2C (PciDevice
);
790 Bridge
= PciDevice
->Parent
;
791 CurrentLink
= Bridge
->ChildList
.ForwardLink
;
792 while (CurrentLink
!= NULL
&& CurrentLink
!= &Bridge
->ChildList
) {
793 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
794 if (Temp
== PciDevice
) {
795 InitializePciDevice (Temp
);
796 RemoveEntryList (CurrentLink
);
800 CurrentLink
= CurrentLink
->ForwardLink
;
807 Determine whethter a PCI device can be rejected.
809 @param PciResNode Pointer to Pci resource node instance.
811 @retval TRUE The PCI device can be rejected.
812 @retval TRUE The PCI device cannot be rejected.
817 IN PCI_RESOURCE_NODE
*PciResNode
822 Temp
= PciResNode
->PciDev
;
825 // Ensure the device is present
832 // PPB and RB should go ahead
834 if (IS_PCI_BRIDGE (&Temp
->Pci
) || (Temp
->Parent
== NULL
)) {
839 // Skip device on Bus0
841 if ((Temp
->Parent
!= NULL
) && (Temp
->BusNumber
== 0)) {
848 if (IS_PCI_VGA (&Temp
->Pci
)) {
856 Compare two resource nodes and get the larger resource consumer.
858 @param PciResNode1 resource node 1 want to be compared
859 @param PciResNode2 resource node 2 want to be compared
861 @return Larger resource node.
865 GetLargerConsumerDevice (
866 IN PCI_RESOURCE_NODE
*PciResNode1
,
867 IN PCI_RESOURCE_NODE
*PciResNode2
870 if (PciResNode2
== NULL
) {
874 if ((IS_PCI_BRIDGE(&(PciResNode2
->PciDev
->Pci
)) || (PciResNode2
->PciDev
->Parent
== NULL
)) \
875 && (PciResNode2
->ResourceUsage
!= PciResUsagePadding
) )
880 if (PciResNode1
== NULL
) {
884 if ((PciResNode1
->Length
) > (PciResNode2
->Length
)) {
893 Get the max resource consumer in the host resource pool.
895 @param ResPool Pointer to resource pool node.
897 @return The max resource consumer in the host resource pool.
901 GetMaxResourceConsumerDevice (
902 IN PCI_RESOURCE_NODE
*ResPool
905 PCI_RESOURCE_NODE
*Temp
;
906 LIST_ENTRY
*CurrentLink
;
907 PCI_RESOURCE_NODE
*PciResNode
;
908 PCI_RESOURCE_NODE
*PPBResNode
;
912 CurrentLink
= ResPool
->ChildList
.ForwardLink
;
913 while (CurrentLink
!= NULL
&& CurrentLink
!= &ResPool
->ChildList
) {
915 Temp
= RESOURCE_NODE_FROM_LINK (CurrentLink
);
917 if (!IsRejectiveDevice (Temp
)) {
918 CurrentLink
= CurrentLink
->ForwardLink
;
922 if ((IS_PCI_BRIDGE (&(Temp
->PciDev
->Pci
)) || (Temp
->PciDev
->Parent
== NULL
)) \
923 && (Temp
->ResourceUsage
!= PciResUsagePadding
))
925 PPBResNode
= GetMaxResourceConsumerDevice (Temp
);
926 PciResNode
= GetLargerConsumerDevice (PciResNode
, PPBResNode
);
928 PciResNode
= GetLargerConsumerDevice (PciResNode
, Temp
);
931 CurrentLink
= CurrentLink
->ForwardLink
;
938 Adjust host bridge allocation so as to reduce resource requirement
940 @param IoPool Pointer to instance of I/O resource Node.
941 @param Mem32Pool Pointer to instance of 32-bit memory resource Node.
942 @param PMem32Pool Pointer to instance of 32-bit Prefetchable memory resource node.
943 @param Mem64Pool Pointer to instance of 64-bit memory resource node.
944 @param PMem64Pool Pointer to instance of 64-bit Prefetchable memory resource node.
945 @param IoResStatus Status of I/O resource Node.
946 @param Mem32ResStatus Status of 32-bit memory resource Node.
947 @param PMem32ResStatus Status of 32-bit Prefetchable memory resource node.
948 @param Mem64ResStatus Status of 64-bit memory resource node.
949 @param PMem64ResStatus Status of 64-bit Prefetchable memory resource node.
951 @retval EFI_SUCCESS Successfully adjusted resoruce on host bridge.
952 @retval EFI_ABORTED Host bridge hasn't this resource type or no resource be adjusted.
956 PciHostBridgeAdjustAllocation (
957 IN PCI_RESOURCE_NODE
*IoPool
,
958 IN PCI_RESOURCE_NODE
*Mem32Pool
,
959 IN PCI_RESOURCE_NODE
*PMem32Pool
,
960 IN PCI_RESOURCE_NODE
*Mem64Pool
,
961 IN PCI_RESOURCE_NODE
*PMem64Pool
,
962 IN UINT64 IoResStatus
,
963 IN UINT64 Mem32ResStatus
,
964 IN UINT64 PMem32ResStatus
,
965 IN UINT64 Mem64ResStatus
,
966 IN UINT64 PMem64ResStatus
969 BOOLEAN AllocationAjusted
;
970 PCI_RESOURCE_NODE
*PciResNode
;
971 PCI_RESOURCE_NODE
*ResPool
[5];
972 PCI_IO_DEVICE
*RemovedPciDev
[5];
974 UINTN RemovedPciDevNum
;
978 EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD AllocFailExtendedData
;
981 ZeroMem (RemovedPciDev
, 5 * sizeof (PCI_IO_DEVICE
*));
982 RemovedPciDevNum
= 0;
985 ResPool
[1] = Mem32Pool
;
986 ResPool
[2] = PMem32Pool
;
987 ResPool
[3] = Mem64Pool
;
988 ResPool
[4] = PMem64Pool
;
990 ResStatus
[0] = IoResStatus
;
991 ResStatus
[1] = Mem32ResStatus
;
992 ResStatus
[2] = PMem32ResStatus
;
993 ResStatus
[3] = Mem64ResStatus
;
994 ResStatus
[4] = PMem64ResStatus
;
996 AllocationAjusted
= FALSE
;
998 for (ResType
= 0; ResType
< 5; ResType
++) {
1000 if (ResStatus
[ResType
] == EFI_RESOURCE_SATISFIED
) {
1004 if (ResStatus
[ResType
] == EFI_RESOURCE_NOT_SATISFIED
) {
1006 // Host bridge hasn't this resource type
1012 // Hostbridge hasn't enough resource
1014 PciResNode
= GetMaxResourceConsumerDevice (ResPool
[ResType
]);
1015 if (PciResNode
== NULL
) {
1020 // Check if the device has been removed before
1022 for (DevIndex
= 0; DevIndex
< RemovedPciDevNum
; DevIndex
++) {
1023 if (PciResNode
->PciDev
== RemovedPciDev
[DevIndex
]) {
1028 if (DevIndex
!= RemovedPciDevNum
) {
1033 // Remove the device if it isn't in the array
1035 Status
= RejectPciDevice (PciResNode
->PciDev
);
1036 if (Status
== EFI_SUCCESS
) {
1039 "PciBus: [%02x|%02x|%02x] was rejected due to resource confliction.\n",
1040 PciResNode
->PciDev
->BusNumber
, PciResNode
->PciDev
->DeviceNumber
, PciResNode
->PciDev
->FunctionNumber
1044 // Raise the EFI_IOB_EC_RESOURCE_CONFLICT status code
1047 // Have no way to get ReqRes, AllocRes & Bar here
1049 ZeroMem (&AllocFailExtendedData
, sizeof (AllocFailExtendedData
));
1050 AllocFailExtendedData
.DevicePathSize
= (UINT16
) sizeof (EFI_DEVICE_PATH_PROTOCOL
);
1051 AllocFailExtendedData
.DevicePath
= (UINT8
*) PciResNode
->PciDev
->DevicePath
;
1052 AllocFailExtendedData
.Bar
= PciResNode
->Bar
;
1054 REPORT_STATUS_CODE_WITH_EXTENDED_DATA (
1056 EFI_IO_BUS_PCI
| EFI_IOB_EC_RESOURCE_CONFLICT
,
1057 (VOID
*) &AllocFailExtendedData
,
1058 sizeof (AllocFailExtendedData
)
1062 // Add it to the array and indicate at least a device has been rejected
1064 RemovedPciDev
[RemovedPciDevNum
++] = PciResNode
->PciDev
;
1065 AllocationAjusted
= TRUE
;
1072 if (AllocationAjusted
) {
1080 Summary requests for all resource type, and contruct ACPI resource
1083 @param Bridge detecting bridge
1084 @param IoNode Pointer to instance of I/O resource Node
1085 @param Mem32Node Pointer to instance of 32-bit memory resource Node
1086 @param PMem32Node Pointer to instance of 32-bit Pmemory resource node
1087 @param Mem64Node Pointer to instance of 64-bit memory resource node
1088 @param PMem64Node Pointer to instance of 64-bit Pmemory resource node
1089 @param Config Output buffer holding new constructed APCI resource requestor
1091 @retval EFI_SUCCESS Successfully constructed ACPI resource.
1092 @retval EFI_OUT_OF_RESOURCES No memory availabe.
1096 ConstructAcpiResourceRequestor (
1097 IN PCI_IO_DEVICE
*Bridge
,
1098 IN PCI_RESOURCE_NODE
*IoNode
,
1099 IN PCI_RESOURCE_NODE
*Mem32Node
,
1100 IN PCI_RESOURCE_NODE
*PMem32Node
,
1101 IN PCI_RESOURCE_NODE
*Mem64Node
,
1102 IN PCI_RESOURCE_NODE
*PMem64Node
,
1108 UINT8
*Configuration
;
1109 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Ptr
;
1110 EFI_ACPI_END_TAG_DESCRIPTOR
*PtrEnd
;
1118 // if there is io request, add to the io aperture
1120 if (ResourceRequestExisted (IoNode
)) {
1126 // if there is mem32 request, add to the mem32 aperture
1128 if (ResourceRequestExisted (Mem32Node
)) {
1134 // if there is pmem32 request, add to the pmem32 aperture
1136 if (ResourceRequestExisted (PMem32Node
)) {
1142 // if there is mem64 request, add to the mem64 aperture
1144 if (ResourceRequestExisted (Mem64Node
)) {
1150 // if there is pmem64 request, add to the pmem64 aperture
1152 if (ResourceRequestExisted (PMem64Node
)) {
1157 if (NumConfig
!= 0) {
1160 // If there is at least one type of resource request,
1161 // allocate a acpi resource node
1163 Configuration
= AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) * NumConfig
+ sizeof (EFI_ACPI_END_TAG_DESCRIPTOR
));
1164 if (Configuration
== NULL
) {
1165 return EFI_OUT_OF_RESOURCES
;
1168 Ptr
= (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*) Configuration
;
1171 // Deal with io aperture
1173 if ((Aperture
& 0x01) != 0) {
1174 Ptr
->Desc
= ACPI_ADDRESS_SPACE_DESCRIPTOR
;
1175 Ptr
->Len
= (UINT16
) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) - 3);
1179 Ptr
->ResType
= ACPI_ADDRESS_SPACE_TYPE_IO
;
1183 Ptr
->SpecificFlag
= 1;
1184 Ptr
->AddrLen
= IoNode
->Length
;
1185 Ptr
->AddrRangeMax
= IoNode
->Alignment
;
1190 // Deal with mem32 aperture
1192 if ((Aperture
& 0x02) != 0) {
1193 Ptr
->Desc
= ACPI_ADDRESS_SPACE_DESCRIPTOR
;
1194 Ptr
->Len
= (UINT16
) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) - 3);
1198 Ptr
->ResType
= ACPI_ADDRESS_SPACE_TYPE_MEM
;
1202 Ptr
->SpecificFlag
= 0;
1206 Ptr
->AddrSpaceGranularity
= 32;
1207 Ptr
->AddrLen
= Mem32Node
->Length
;
1208 Ptr
->AddrRangeMax
= Mem32Node
->Alignment
;
1214 // Deal with Pmem32 aperture
1216 if ((Aperture
& 0x04) != 0) {
1217 Ptr
->Desc
= ACPI_ADDRESS_SPACE_DESCRIPTOR
;
1218 Ptr
->Len
= (UINT16
) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) - 3);
1222 Ptr
->ResType
= ACPI_ADDRESS_SPACE_TYPE_MEM
;
1226 Ptr
->SpecificFlag
= 0x6;
1230 Ptr
->AddrSpaceGranularity
= 32;
1231 Ptr
->AddrLen
= PMem32Node
->Length
;
1232 Ptr
->AddrRangeMax
= PMem32Node
->Alignment
;
1237 // Deal with mem64 aperture
1239 if ((Aperture
& 0x08) != 0) {
1240 Ptr
->Desc
= ACPI_ADDRESS_SPACE_DESCRIPTOR
;
1241 Ptr
->Len
= (UINT16
) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) - 3);
1245 Ptr
->ResType
= ACPI_ADDRESS_SPACE_TYPE_MEM
;
1249 Ptr
->SpecificFlag
= 0;
1253 Ptr
->AddrSpaceGranularity
= 64;
1254 Ptr
->AddrLen
= Mem64Node
->Length
;
1255 Ptr
->AddrRangeMax
= Mem64Node
->Alignment
;
1260 // Deal with Pmem64 aperture
1262 if ((Aperture
& 0x10) != 0) {
1263 Ptr
->Desc
= ACPI_ADDRESS_SPACE_DESCRIPTOR
;
1264 Ptr
->Len
= (UINT16
) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) - 3);
1268 Ptr
->ResType
= ACPI_ADDRESS_SPACE_TYPE_MEM
;
1272 Ptr
->SpecificFlag
= 0x06;
1276 Ptr
->AddrSpaceGranularity
= 64;
1277 Ptr
->AddrLen
= PMem64Node
->Length
;
1278 Ptr
->AddrRangeMax
= PMem64Node
->Alignment
;
1286 PtrEnd
= (EFI_ACPI_END_TAG_DESCRIPTOR
*) Ptr
;
1288 PtrEnd
->Desc
= ACPI_END_TAG_DESCRIPTOR
;
1289 PtrEnd
->Checksum
= 0;
1294 // If there is no resource request
1296 Configuration
= AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR
));
1297 if (Configuration
== NULL
) {
1298 return EFI_OUT_OF_RESOURCES
;
1301 Ptr
= (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*) (Configuration
);
1302 Ptr
->Desc
= ACPI_ADDRESS_SPACE_DESCRIPTOR
;
1304 PtrEnd
= (EFI_ACPI_END_TAG_DESCRIPTOR
*) (Ptr
+ 1);
1305 PtrEnd
->Desc
= ACPI_END_TAG_DESCRIPTOR
;
1306 PtrEnd
->Checksum
= 0;
1309 *Config
= Configuration
;
1315 Get resource base from an acpi configuration descriptor.
1317 @param Config An acpi configuration descriptor.
1318 @param IoBase Output of I/O resource base address.
1319 @param Mem32Base Output of 32-bit memory base address.
1320 @param PMem32Base Output of 32-bit prefetchable memory base address.
1321 @param Mem64Base Output of 64-bit memory base address.
1322 @param PMem64Base Output of 64-bit prefetchable memory base address.
1329 OUT UINT64
*Mem32Base
,
1330 OUT UINT64
*PMem32Base
,
1331 OUT UINT64
*Mem64Base
,
1332 OUT UINT64
*PMem64Base
1336 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Ptr
;
1339 ASSERT (Config
!= NULL
);
1341 *IoBase
= 0xFFFFFFFFFFFFFFFFULL
;
1342 *Mem32Base
= 0xFFFFFFFFFFFFFFFFULL
;
1343 *PMem32Base
= 0xFFFFFFFFFFFFFFFFULL
;
1344 *Mem64Base
= 0xFFFFFFFFFFFFFFFFULL
;
1345 *PMem64Base
= 0xFFFFFFFFFFFFFFFFULL
;
1347 Temp
= (UINT8
*) Config
;
1349 while (*Temp
== ACPI_ADDRESS_SPACE_DESCRIPTOR
) {
1351 Ptr
= (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*) Temp
;
1352 ResStatus
= Ptr
->AddrTranslationOffset
;
1354 if (ResStatus
== EFI_RESOURCE_SATISFIED
) {
1356 switch (Ptr
->ResType
) {
1359 // Memory type aperture
1364 // Check to see the granularity
1366 if (Ptr
->AddrSpaceGranularity
== 32) {
1367 if ((Ptr
->SpecificFlag
& 0x06) != 0) {
1368 *PMem32Base
= Ptr
->AddrRangeMin
;
1370 *Mem32Base
= Ptr
->AddrRangeMin
;
1374 if (Ptr
->AddrSpaceGranularity
== 64) {
1375 if ((Ptr
->SpecificFlag
& 0x06) != 0) {
1376 *PMem64Base
= Ptr
->AddrRangeMin
;
1378 *Mem64Base
= Ptr
->AddrRangeMin
;
1388 *IoBase
= Ptr
->AddrRangeMin
;
1402 Temp
+= sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
);
1407 Enumerate pci bridge, allocate resource and determine attribute
1408 for devices on this bridge.
1410 @param BridgeDev Pointer to instance of bridge device.
1412 @retval EFI_SUCCESS Successfully enumerated PCI bridge.
1413 @retval other Failed to enumerate.
1417 PciBridgeEnumerator (
1418 IN PCI_IO_DEVICE
*BridgeDev
1422 UINT8 StartBusNumber
;
1423 EFI_PCI_IO_PROTOCOL
*PciIo
;
1428 PciIo
= &(BridgeDev
->PciIo
);
1429 Status
= PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, 0x19, 1, &StartBusNumber
);
1431 if (EFI_ERROR (Status
)) {
1435 Status
= PciAssignBusNumber (
1441 if (EFI_ERROR (Status
)) {
1445 Status
= PciPciDeviceInfoCollector (BridgeDev
, StartBusNumber
);
1447 if (EFI_ERROR (Status
)) {
1451 Status
= PciBridgeResourceAllocator (BridgeDev
);
1453 if (EFI_ERROR (Status
)) {
1457 Status
= DetermineDeviceAttribute (BridgeDev
);
1459 if (EFI_ERROR (Status
)) {
1468 Allocate all kinds of resource for PCI bridge.
1470 @param Bridge Pointer to bridge instance.
1472 @retval EFI_SUCCESS Successfully allocated resource for PCI bridge.
1473 @retval other Failed to allocate resource for bridge.
1477 PciBridgeResourceAllocator (
1478 IN PCI_IO_DEVICE
*Bridge
1481 PCI_RESOURCE_NODE
*IoBridge
;
1482 PCI_RESOURCE_NODE
*Mem32Bridge
;
1483 PCI_RESOURCE_NODE
*PMem32Bridge
;
1484 PCI_RESOURCE_NODE
*Mem64Bridge
;
1485 PCI_RESOURCE_NODE
*PMem64Bridge
;
1493 IoBridge
= CreateResourceNode (
1496 Bridge
->BridgeIoAlignment
,
1502 Mem32Bridge
= CreateResourceNode (
1511 PMem32Bridge
= CreateResourceNode (
1520 Mem64Bridge
= CreateResourceNode (
1529 PMem64Bridge
= CreateResourceNode (
1539 // Create resourcemap by going through all the devices subject to this root bridge
1550 Status
= GetResourceBaseFromBridge (
1559 if (EFI_ERROR (Status
)) {
1564 // Program IO resources
1572 // Program Mem32 resources
1580 // Program PMem32 resources
1588 // Program Mem64 resources
1596 // Program PMem64 resources
1603 DestroyResourceTree (IoBridge
);
1604 DestroyResourceTree (Mem32Bridge
);
1605 DestroyResourceTree (PMem32Bridge
);
1606 DestroyResourceTree (PMem64Bridge
);
1607 DestroyResourceTree (Mem64Bridge
);
1609 gBS
->FreePool (IoBridge
);
1610 gBS
->FreePool (Mem32Bridge
);
1611 gBS
->FreePool (PMem32Bridge
);
1612 gBS
->FreePool (PMem64Bridge
);
1613 gBS
->FreePool (Mem64Bridge
);
1619 Get resource base address for a pci bridge device.
1621 @param Bridge Given Pci driver instance.
1622 @param IoBase Output for base address of I/O type resource.
1623 @param Mem32Base Output for base address of 32-bit memory type resource.
1624 @param PMem32Base Ooutput for base address of 32-bit Pmemory type resource.
1625 @param Mem64Base Output for base address of 64-bit memory type resource.
1626 @param PMem64Base Output for base address of 64-bit Pmemory type resource.
1628 @retval EFI_SUCCESS Successfully got resource base address.
1629 @retval EFI_OUT_OF_RESOURCES PCI bridge is not available.
1633 GetResourceBaseFromBridge (
1634 IN PCI_IO_DEVICE
*Bridge
,
1636 OUT UINT64
*Mem32Base
,
1637 OUT UINT64
*PMem32Base
,
1638 OUT UINT64
*Mem64Base
,
1639 OUT UINT64
*PMem64Base
1642 if (!Bridge
->Allocated
) {
1643 return EFI_OUT_OF_RESOURCES
;
1647 *Mem32Base
= gAllOne
;
1648 *PMem32Base
= gAllOne
;
1649 *Mem64Base
= gAllOne
;
1650 *PMem64Base
= gAllOne
;
1652 if (IS_PCI_BRIDGE (&Bridge
->Pci
)) {
1654 if (Bridge
->PciBar
[PPB_IO_RANGE
].Length
> 0) {
1655 *IoBase
= Bridge
->PciBar
[PPB_IO_RANGE
].BaseAddress
;
1658 if (Bridge
->PciBar
[PPB_MEM32_RANGE
].Length
> 0) {
1659 *Mem32Base
= Bridge
->PciBar
[PPB_MEM32_RANGE
].BaseAddress
;
1662 if (Bridge
->PciBar
[PPB_PMEM32_RANGE
].Length
> 0) {
1663 *PMem32Base
= Bridge
->PciBar
[PPB_PMEM32_RANGE
].BaseAddress
;
1666 if (Bridge
->PciBar
[PPB_PMEM64_RANGE
].Length
> 0) {
1667 *PMem64Base
= Bridge
->PciBar
[PPB_PMEM64_RANGE
].BaseAddress
;
1669 *PMem64Base
= gAllOne
;
1674 if (IS_CARDBUS_BRIDGE (&Bridge
->Pci
)) {
1675 if (Bridge
->PciBar
[P2C_IO_1
].Length
> 0) {
1676 *IoBase
= Bridge
->PciBar
[P2C_IO_1
].BaseAddress
;
1678 if (Bridge
->PciBar
[P2C_IO_2
].Length
> 0) {
1679 *IoBase
= Bridge
->PciBar
[P2C_IO_2
].BaseAddress
;
1683 if (Bridge
->PciBar
[P2C_MEM_1
].Length
> 0) {
1684 if (Bridge
->PciBar
[P2C_MEM_1
].BarType
== PciBarTypePMem32
) {
1685 *PMem32Base
= Bridge
->PciBar
[P2C_MEM_1
].BaseAddress
;
1688 if (Bridge
->PciBar
[P2C_MEM_1
].BarType
== PciBarTypeMem32
) {
1689 *Mem32Base
= Bridge
->PciBar
[P2C_MEM_1
].BaseAddress
;
1693 if (Bridge
->PciBar
[P2C_MEM_2
].Length
> 0) {
1694 if (Bridge
->PciBar
[P2C_MEM_2
].BarType
== PciBarTypePMem32
) {
1695 *PMem32Base
= Bridge
->PciBar
[P2C_MEM_2
].BaseAddress
;
1698 if (Bridge
->PciBar
[P2C_MEM_2
].BarType
== PciBarTypeMem32
) {
1699 *Mem32Base
= Bridge
->PciBar
[P2C_MEM_2
].BaseAddress
;
1708 These are the notifications from the PCI bus driver that it is about to enter a certain
1709 phase of the PCI enumeration process.
1711 This member function can be used to notify the host bridge driver to perform specific actions,
1712 including any chipset-specific initialization, so that the chipset is ready to enter the next phase.
1713 Eight notification points are defined at this time. See belows:
1714 EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures and internal data
1715 structures. The PCI enumerator should issue this notification
1716 before starting a fresh enumeration process. Enumeration cannot
1717 be restarted after sending any other notification such as
1718 EfiPciHostBridgeBeginBusAllocation.
1719 EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin. No specific action is
1720 required here. This notification can be used to perform any
1721 chipset-specific programming.
1722 EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming phase is complete. No
1723 specific action is required here. This notification can be used to
1724 perform any chipset-specific programming.
1725 EfiPciHostBridgeBeginResourceAllocation
1726 The resource allocation phase is about to begin. No specific
1727 action is required here. This notification can be used to perform
1728 any chipset-specific programming.
1729 EfiPciHostBridgeAllocateResources Allocates resources per previously submitted requests for all the PCI
1730 root bridges. These resource settings are returned on the next call to
1731 GetProposedResources(). Before calling NotifyPhase() with a Phase of
1732 EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible
1733 for gathering I/O and memory requests for
1734 all the PCI root bridges and submitting these requests using
1735 SubmitResources(). This function pads the resource amount
1736 to suit the root bridge hardware, takes care of dependencies between
1737 the PCI root bridges, and calls the Global Coherency Domain (GCD)
1738 with the allocation request. In the case of padding, the allocated range
1739 could be bigger than what was requested.
1740 EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated
1741 resources (proposed resources) for all the PCI root bridges. After the
1742 hardware is programmed, reassigning resources will not be supported.
1743 The bus settings are not affected.
1744 EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI
1745 root bridges and resets the I/O and memory apertures to their initial
1746 state. The bus settings are not affected. If the request to allocate
1747 resources fails, the PCI enumerator can use this notification to
1748 deallocate previous resources, adjust the requests, and retry
1750 EfiPciHostBridgeEndResourceAllocation The resource allocation phase is completed. No specific action is
1751 required here. This notification can be used to perform any chipsetspecific
1754 @param[in] PciResAlloc The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
1755 @param[in] Phase The phase during enumeration
1757 @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error
1758 is valid for a Phase of EfiPciHostBridgeAllocateResources if
1759 SubmitResources() has not been called for one or more
1760 PCI root bridges before this call
1761 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid
1762 for a Phase of EfiPciHostBridgeSetResources.
1763 @retval EFI_INVALID_PARAMETER Invalid phase parameter
1764 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1765 This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the
1766 previously submitted resource requests cannot be fulfilled or
1767 were only partially fulfilled.
1768 @retval EFI_SUCCESS The notification was accepted without any errors.
1773 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
*PciResAlloc
,
1774 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
1777 EFI_HANDLE HostBridgeHandle
;
1778 EFI_HANDLE RootBridgeHandle
;
1779 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
1782 HostBridgeHandle
= NULL
;
1783 RootBridgeHandle
= NULL
;
1784 if (gPciPlatformProtocol
!= NULL
) {
1786 // Get Host Bridge Handle.
1788 PciResAlloc
->GetNextRootBridge (PciResAlloc
, &RootBridgeHandle
);
1791 // Get the rootbridge Io protocol to find the host bridge handle
1793 Status
= gBS
->HandleProtocol (
1795 &gEfiPciRootBridgeIoProtocolGuid
,
1796 (VOID
**) &PciRootBridgeIo
1799 if (EFI_ERROR (Status
)) {
1800 return EFI_NOT_FOUND
;
1803 HostBridgeHandle
= PciRootBridgeIo
->ParentHandle
;
1806 // Call PlatformPci::PlatformNotify() if the protocol is present.
1808 gPciPlatformProtocol
->PlatformNotify (
1809 gPciPlatformProtocol
,
1814 } else if (gPciOverrideProtocol
!= NULL
){
1816 // Get Host Bridge Handle.
1818 PciResAlloc
->GetNextRootBridge (PciResAlloc
, &RootBridgeHandle
);
1821 // Get the rootbridge Io protocol to find the host bridge handle
1823 Status
= gBS
->HandleProtocol (
1825 &gEfiPciRootBridgeIoProtocolGuid
,
1826 (VOID
**) &PciRootBridgeIo
1829 if (EFI_ERROR (Status
)) {
1830 return EFI_NOT_FOUND
;
1833 HostBridgeHandle
= PciRootBridgeIo
->ParentHandle
;
1836 // Call PlatformPci::PhaseNotify() if the protocol is present.
1838 gPciOverrideProtocol
->PlatformNotify (
1839 gPciOverrideProtocol
,
1846 Status
= PciResAlloc
->NotifyPhase (
1851 if (gPciPlatformProtocol
!= NULL
) {
1853 // Call PlatformPci::PlatformNotify() if the protocol is present.
1855 gPciPlatformProtocol
->PlatformNotify (
1856 gPciPlatformProtocol
,
1862 } else if (gPciOverrideProtocol
!= NULL
) {
1864 // Call PlatformPci::PhaseNotify() if the protocol is present.
1866 gPciOverrideProtocol
->PlatformNotify (
1867 gPciOverrideProtocol
,
1878 Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various
1879 stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual
1880 PCI controllers before enumeration.
1882 This function is called during the PCI enumeration process. No specific action is expected from this
1883 member function. It allows the host bridge driver to preinitialize individual PCI controllers before
1886 @param Bridge Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
1887 @param Bus The bus number of the pci device.
1888 @param Device The device number of the pci device.
1889 @param Func The function number of the pci device.
1890 @param Phase The phase of the PCI device enumeration.
1892 @retval EFI_SUCCESS The requested parameters were returned.
1893 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
1894 @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in
1895 EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.
1896 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should
1897 not enumerate this device, including its child devices if it is a PCI-to-PCI
1902 PreprocessController (
1903 IN PCI_IO_DEVICE
*Bridge
,
1907 IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
1910 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS RootBridgePciAddress
;
1911 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
*PciResAlloc
;
1912 EFI_HANDLE RootBridgeHandle
;
1913 EFI_HANDLE HostBridgeHandle
;
1917 // Get the host bridge handle
1919 HostBridgeHandle
= Bridge
->PciRootBridgeIo
->ParentHandle
;
1922 // Get the pci host bridge resource allocation protocol
1924 Status
= gBS
->OpenProtocol (
1926 &gEfiPciHostBridgeResourceAllocationProtocolGuid
,
1927 (VOID
**) &PciResAlloc
,
1930 EFI_OPEN_PROTOCOL_GET_PROTOCOL
1933 if (EFI_ERROR (Status
)) {
1934 return EFI_UNSUPPORTED
;
1938 // Get Root Brige Handle
1940 while (Bridge
->Parent
!= NULL
) {
1941 Bridge
= Bridge
->Parent
;
1944 RootBridgeHandle
= Bridge
->Handle
;
1946 RootBridgePciAddress
.Register
= 0;
1947 RootBridgePciAddress
.Function
= Func
;
1948 RootBridgePciAddress
.Device
= Device
;
1949 RootBridgePciAddress
.Bus
= Bus
;
1950 RootBridgePciAddress
.ExtendedRegister
= 0;
1952 if (gPciPlatformProtocol
!= NULL
) {
1954 // Call PlatformPci::PrepController() if the protocol is present.
1956 gPciPlatformProtocol
->PlatformPrepController (
1957 gPciPlatformProtocol
,
1960 RootBridgePciAddress
,
1964 } else if (gPciOverrideProtocol
!= NULL
) {
1966 // Call PlatformPci::PrepController() if the protocol is present.
1968 gPciOverrideProtocol
->PlatformPrepController (
1969 gPciOverrideProtocol
,
1972 RootBridgePciAddress
,
1978 Status
= PciResAlloc
->PreprocessController (
1981 RootBridgePciAddress
,
1985 if (gPciPlatformProtocol
!= NULL
) {
1987 // Call PlatformPci::PrepController() if the protocol is present.
1989 gPciPlatformProtocol
->PlatformPrepController (
1990 gPciPlatformProtocol
,
1993 RootBridgePciAddress
,
1997 } else if (gPciOverrideProtocol
!= NULL
) {
1999 // Call PlatformPci::PrepController() if the protocol is present.
2001 gPciOverrideProtocol
->PlatformPrepController (
2002 gPciOverrideProtocol
,
2005 RootBridgePciAddress
,
2015 This function allows the PCI bus driver to be notified to act as requested when a hot-plug event has
2016 happened on the hot-plug controller. Currently, the operations include add operation and remove operation..
2018 @param This A pointer to the hot plug request protocol.
2019 @param Operation The operation the PCI bus driver is requested to make.
2020 @param Controller The handle of the hot-plug controller.
2021 @param RemainingDevicePath The remaining device path for the PCI-like hot-plug device.
2022 @param NumberOfChildren The number of child handles.
2023 For a add operation, it is an output parameter.
2024 For a remove operation, it's an input parameter.
2025 @param ChildHandleBuffer The buffer which contains the child handles.
2027 @retval EFI_INVALID_PARAMETER Operation is not a legal value.
2028 Controller is NULL or not a valid handle.
2029 NumberOfChildren is NULL.
2030 ChildHandleBuffer is NULL while Operation is add.
2031 @retval EFI_OUT_OF_RESOURCES There are no enough resources to start the devices.
2032 @retval EFI_NOT_FOUND Can not find bridge according to controller handle.
2033 @retval EFI_SUCCESS The handles for the specified device have been created or destroyed
2034 as requested, and for an add operation, the new handles are
2035 returned in ChildHandleBuffer.
2039 PciHotPlugRequestNotify (
2040 IN EFI_PCI_HOTPLUG_REQUEST_PROTOCOL
* This
,
2041 IN EFI_PCI_HOTPLUG_OPERATION Operation
,
2042 IN EFI_HANDLE Controller
,
2043 IN EFI_DEVICE_PATH_PROTOCOL
* RemainingDevicePath OPTIONAL
,
2044 IN OUT UINT8
*NumberOfChildren
,
2045 IN OUT EFI_HANDLE
* ChildHandleBuffer
2048 PCI_IO_DEVICE
*Bridge
;
2049 PCI_IO_DEVICE
*Temp
;
2050 EFI_PCI_IO_PROTOCOL
*PciIo
;
2052 EFI_HANDLE RootBridgeHandle
;
2056 // Check input parameter validity
2058 if ((Controller
== NULL
) || (NumberOfChildren
== NULL
)){
2059 return EFI_INVALID_PARAMETER
;
2062 if ((Operation
!= EfiPciHotPlugRequestAdd
) && (Operation
!= EfiPciHotplugRequestRemove
)) {
2063 return EFI_INVALID_PARAMETER
;
2066 if (Operation
== EfiPciHotPlugRequestAdd
){
2067 if (ChildHandleBuffer
== NULL
) {
2068 return EFI_INVALID_PARAMETER
;
2070 } else if ((Operation
== EfiPciHotplugRequestRemove
) && (*NumberOfChildren
!= 0)) {
2071 if (ChildHandleBuffer
== NULL
) {
2072 return EFI_INVALID_PARAMETER
;
2076 Status
= gBS
->OpenProtocol (
2078 &gEfiPciIoProtocolGuid
,
2080 gPciBusDriverBinding
.DriverBindingHandle
,
2082 EFI_OPEN_PROTOCOL_GET_PROTOCOL
2085 if (EFI_ERROR (Status
)) {
2086 return EFI_NOT_FOUND
;
2089 Bridge
= PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo
);
2092 // Get root bridge handle
2095 while (Temp
->Parent
!= NULL
) {
2096 Temp
= Temp
->Parent
;
2099 RootBridgeHandle
= Temp
->Handle
;
2101 if (Operation
== EfiPciHotPlugRequestAdd
) {
2103 // Report Status Code to indicate hot plug happens
2105 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
2107 (EFI_IO_BUS_PCI
| EFI_IOB_PC_HOTPLUG
),
2111 if (NumberOfChildren
!= NULL
) {
2112 *NumberOfChildren
= 0;
2115 if (IsListEmpty (&Bridge
->ChildList
)) {
2117 Status
= PciBridgeEnumerator (Bridge
);
2119 if (EFI_ERROR (Status
)) {
2124 Status
= StartPciDevicesOnBridge (
2127 RemainingDevicePath
,
2135 if (Operation
== EfiPciHotplugRequestRemove
) {
2137 if (*NumberOfChildren
== 0) {
2139 // Remove all devices on the bridge
2141 RemoveAllPciDeviceOnBridge (RootBridgeHandle
, Bridge
);
2146 for (Index
= 0; Index
< *NumberOfChildren
; Index
++) {
2148 // De register all the pci device
2150 Status
= DeRegisterPciDevice (RootBridgeHandle
, ChildHandleBuffer
[Index
]);
2152 if (EFI_ERROR (Status
)) {
2167 Search hostbridge according to given handle
2169 @param RootBridgeHandle Host bridge handle.
2171 @retval TRUE Found host bridge handle.
2172 @retval FALSE Not found hot bridge handle.
2176 SearchHostBridgeHandle (
2177 IN EFI_HANDLE RootBridgeHandle
2180 EFI_HANDLE HostBridgeHandle
;
2181 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
2186 // Get the rootbridge Io protocol to find the host bridge handle
2188 Status
= gBS
->OpenProtocol (
2190 &gEfiPciRootBridgeIoProtocolGuid
,
2191 (VOID
**) &PciRootBridgeIo
,
2192 gPciBusDriverBinding
.DriverBindingHandle
,
2194 EFI_OPEN_PROTOCOL_GET_PROTOCOL
2197 if (EFI_ERROR (Status
)) {
2201 HostBridgeHandle
= PciRootBridgeIo
->ParentHandle
;
2202 for (Index
= 0; Index
< gPciHostBridgeNumber
; Index
++) {
2203 if (HostBridgeHandle
== gPciHostBrigeHandles
[Index
]) {
2212 Add host bridge handle to global variable for enumerating.
2214 @param HostBridgeHandle Host bridge handle.
2216 @retval EFI_SUCCESS Successfully added host bridge.
2217 @retval EFI_ABORTED Host bridge is NULL, or given host bridge
2218 has been in host bridge list.
2222 AddHostBridgeEnumerator (
2223 IN EFI_HANDLE HostBridgeHandle
2228 if (HostBridgeHandle
== NULL
) {
2232 for (Index
= 0; Index
< gPciHostBridgeNumber
; Index
++) {
2233 if (HostBridgeHandle
== gPciHostBrigeHandles
[Index
]) {
2238 if (Index
< PCI_MAX_HOST_BRIDGE_NUM
) {
2239 gPciHostBrigeHandles
[Index
] = HostBridgeHandle
;
2240 gPciHostBridgeNumber
++;