2 Support for PCI 2.2 standard.
4 Copyright (c) 2006 - 2007, Intel Corporation
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #define PCI_MAX_SEGMENT 0
20 #define PCI_MAX_BUS 255
22 #define PCI_MAX_DEVICE 31
23 #define PCI_MAX_FUNC 7
28 #define PCI_VGA_PALETTE_SNOOP_DISABLED 0x20
42 } PCI_DEVICE_INDEPENDENT_REGION
;
47 UINT16 SubsystemVendorID
;
49 UINT32 ExpansionRomBar
;
57 } PCI_DEVICE_HEADER_TYPE_REGION
;
60 PCI_DEVICE_INDEPENDENT_REGION Hdr
;
61 PCI_DEVICE_HEADER_TYPE_REGION Device
;
69 UINT8 SecondaryLatencyTimer
;
72 UINT16 SecondaryStatus
;
75 UINT16 PrefetchableMemoryBase
;
76 UINT16 PrefetchableMemoryLimit
;
77 UINT32 PrefetchableBaseUpper32
;
78 UINT32 PrefetchableLimitUpper32
;
80 UINT16 IoLimitUpper16
;
83 UINT32 ExpansionRomBAR
;
87 } PCI_BRIDGE_CONTROL_REGISTER
;
90 PCI_DEVICE_INDEPENDENT_REGION Hdr
;
91 PCI_BRIDGE_CONTROL_REGISTER Bridge
;
100 UINT32 CardBusSocketReg
; // Cardus Socket/ExCA Base
104 UINT16 SecondaryStatus
; // Secondary Status
105 UINT8 PciBusNumber
; // PCI Bus Number
106 UINT8 CardBusBusNumber
; // CardBus Bus Number
107 UINT8 SubordinateBusNumber
; // Subordinate Bus Number
108 UINT8 CardBusLatencyTimer
; // CardBus Latency Timer
109 UINT32 MemoryBase0
; // Memory Base Register 0
110 UINT32 MemoryLimit0
; // Memory Limit Register 0
114 UINT32 IoLimit0
; // I/O Base Register 0
115 UINT32 IoBase1
; // I/O Limit Register 0
117 UINT8 InterruptLine
; // Interrupt Line
118 UINT8 InterruptPin
; // Interrupt Pin
119 UINT16 BridgeControl
; // Bridge Control
120 } PCI_CARDBUS_CONTROL_REGISTER
;
123 // Definitions of PCI class bytes and manipulation macros.
125 #define PCI_CLASS_OLD 0x00
126 #define PCI_CLASS_OLD_OTHER 0x00
127 #define PCI_CLASS_OLD_VGA 0x01
129 #define PCI_CLASS_MASS_STORAGE 0x01
130 #define PCI_CLASS_MASS_STORAGE_SCSI 0x00
131 #define PCI_CLASS_MASS_STORAGE_IDE 0x01 // obsolete
132 #define PCI_CLASS_IDE 0x01
133 #define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
134 #define PCI_CLASS_MASS_STORAGE_IPI 0x03
135 #define PCI_CLASS_MASS_STORAGE_RAID 0x04
136 #define PCI_CLASS_MASS_STORAGE_OTHER 0x80
138 #define PCI_CLASS_NETWORK 0x02
139 #define PCI_CLASS_NETWORK_ETHERNET 0x00
140 #define PCI_CLASS_ETHERNET 0x00 // obsolete
141 #define PCI_CLASS_NETWORK_TOKENRING 0x01
142 #define PCI_CLASS_NETWORK_FDDI 0x02
143 #define PCI_CLASS_NETWORK_ATM 0x03
144 #define PCI_CLASS_NETWORK_ISDN 0x04
145 #define PCI_CLASS_NETWORK_OTHER 0x80
147 #define PCI_CLASS_DISPLAY 0x03
148 #define PCI_CLASS_DISPLAY_CTRL 0x03 // obsolete
149 #define PCI_CLASS_DISPLAY_VGA 0x00
150 #define PCI_CLASS_VGA 0x00 // obsolete
151 #define PCI_CLASS_DISPLAY_XGA 0x01
152 #define PCI_CLASS_DISPLAY_3D 0x02
153 #define PCI_CLASS_DISPLAY_OTHER 0x80
154 #define PCI_CLASS_DISPLAY_GFX 0x80
155 #define PCI_CLASS_GFX 0x80 // obsolete
156 #define PCI_CLASS_BRIDGE 0x06
157 #define PCI_CLASS_BRIDGE_HOST 0x00
158 #define PCI_CLASS_BRIDGE_ISA 0x01
159 #define PCI_CLASS_ISA 0x01 // obsolete
160 #define PCI_CLASS_BRIDGE_EISA 0x02
161 #define PCI_CLASS_BRIDGE_MCA 0x03
162 #define PCI_CLASS_BRIDGE_P2P 0x04
163 #define PCI_CLASS_BRIDGE_PCMCIA 0x05
164 #define PCI_CLASS_BRIDGE_NUBUS 0x06
165 #define PCI_CLASS_BRIDGE_CARDBUS 0x07
166 #define PCI_CLASS_BRIDGE_RACEWAY 0x08
167 #define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80
168 #define PCI_CLASS_ISA_POSITIVE_DECODE 0x80 // obsolete
170 #define PCI_CLASS_SCC 0x07 // Simple communications controllers
171 #define PCI_SUBCLASS_SERIAL 0x00
172 #define PCI_IF_GENERIC_XT 0x00
173 #define PCI_IF_16450 0x01
174 #define PCI_IF_16550 0x02
175 #define PCI_IF_16650 0x03
176 #define PCI_IF_16750 0x04
177 #define PCI_IF_16850 0x05
178 #define PCI_IF_16950 0x06
179 #define PCI_SUBCLASS_PARALLEL 0x01
180 #define PCI_IF_PARALLEL_PORT 0x00
181 #define PCI_IF_BI_DIR_PARALLEL_PORT 0x01
182 #define PCI_IF_ECP_PARALLEL_PORT 0x02
183 #define PCI_IF_1284_CONTROLLER 0x03
184 #define PCI_IF_1284_DEVICE 0xFE
185 #define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
186 #define PCI_SUBCLASS_MODEM 0x03
187 #define PCI_IF_GENERIC_MODEM 0x00
188 #define PCI_IF_16450_MODEM 0x01
189 #define PCI_IF_16550_MODEM 0x02
190 #define PCI_IF_16650_MODEM 0x03
191 #define PCI_IF_16750_MODEM 0x04
192 #define PCI_SUBCLASS_OTHER 0x80
194 #define PCI_CLASS_SYSTEM_PERIPHERAL 0x08
195 #define PCI_SUBCLASS_PIC 0x00
196 #define PCI_IF_8259_PIC 0x00
197 #define PCI_IF_ISA_PIC 0x01
198 #define PCI_IF_EISA_PIC 0x02
199 #define PCI_IF_APIC_CONTROLLER 0x10 // I/O APIC interrupt controller , 32 bye none-prefectable memory.
200 #define PCI_IF_APIC_CONTROLLER2 0x20
201 #define PCI_SUBCLASS_TIMER 0x02
202 #define PCI_IF_8254_TIMER 0x00
203 #define PCI_IF_ISA_TIMER 0x01
204 #define PCI_EISA_TIMER 0x02
205 #define PCI_SUBCLASS_RTC 0x03
206 #define PCI_IF_GENERIC_RTC 0x00
207 #define PCI_IF_ISA_RTC 0x00
208 #define PCI_SUBCLASS_PNP_CONTROLLER 0x04 // HotPlug Controller
210 #define PCI_CLASS_INPUT_DEVICE 0x09
211 #define PCI_SUBCLASS_KEYBOARD 0x00
212 #define PCI_SUBCLASS_PEN 0x01
213 #define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
214 #define PCI_SUBCLASS_SCAN_CONTROLLER 0x03
215 #define PCI_SUBCLASS_GAMEPORT 0x04
217 #define PCI_CLASS_DOCKING_STATION 0x0A
219 #define PCI_CLASS_PROCESSOR 0x0B
220 #define PCI_SUBCLASS_PROC_386 0x00
221 #define PCI_SUBCLASS_PROC_486 0x01
222 #define PCI_SUBCLASS_PROC_PENTIUM 0x02
223 #define PCI_SUBCLASS_PROC_ALPHA 0x10
224 #define PCI_SUBCLASS_PROC_POWERPC 0x20
225 #define PCI_SUBCLASS_PROC_MIPS 0x30
226 #define PCI_SUBCLASS_PROC_CO_PORC 0x40 // Co-Processor
228 #define PCI_CLASS_SERIAL 0x0C
229 #define PCI_CLASS_SERIAL_FIREWIRE 0x00
230 #define PCI_CLASS_SERIAL_ACCESS_BUS 0x01
231 #define PCI_CLASS_SERIAL_SSA 0x02
232 #define PCI_CLASS_SERIAL_USB 0x03
233 #define PCI_IF_EHCI 0x20
234 #define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
235 #define PCI_CLASS_SERIAL_SMB 0x05
237 #define PCI_CLASS_WIRELESS 0x0D
238 #define PCI_SUBCLASS_IRDA 0x00
239 #define PCI_SUBCLASS_IR 0x01
240 #define PCI_SUBCLASS_RF 0x02
242 #define PCI_CLASS_INTELLIGENT_IO 0x0E
244 #define PCI_CLASS_SATELLITE 0x0F
245 #define PCI_SUBCLASS_TV 0x01
246 #define PCI_SUBCLASS_AUDIO 0x02
247 #define PCI_SUBCLASS_VOICE 0x03
248 #define PCI_SUBCLASS_DATA 0x04
250 #define PCI_SECURITY_CONTROLLER 0x10 // Encryption and decryption controller
251 #define PCI_SUBCLASS_NET_COMPUT 0x00
252 #define PCI_SUBCLASS_ENTERTAINMENT 0x10
254 #define PCI_CLASS_DPIO 0x11
256 #define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))
257 #define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
258 #define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
260 #define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
261 #define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 0)
262 #define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 1)
263 #define IS_PCI_GFX(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_GFX, 0)
264 #define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)
265 #define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
266 #define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
267 #define IS_PCI_SCSI(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI, 0)
268 #define IS_PCI_RAID(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID, 0)
269 #define IS_PCI_LPC(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA, 0)
270 #define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 0)
271 #define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 1)
272 #define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
273 #define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
275 #define HEADER_TYPE_DEVICE 0x00
276 #define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
277 #define HEADER_TYPE_CARDBUS_BRIDGE 0x02
279 #define HEADER_TYPE_MULTI_FUNCTION 0x80
280 #define HEADER_LAYOUT_CODE 0x7f
282 #define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
283 #define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
284 #define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
286 #define PCI_DEVICE_ROMBAR 0x30
287 #define PCI_BRIDGE_ROMBAR 0x38
289 #define PCI_MAX_BAR 0x0006
290 #define PCI_MAX_CONFIG_OFFSET 0x0100
292 #define PCI_VENDOR_ID_OFFSET 0x00
293 #define PCI_DEVICE_ID_OFFSET 0x02
294 #define PCI_COMMAND_OFFSET 0x04
295 #define PCI_PRIMARY_STATUS_OFFSET 0x06
296 #define PCI_REVISION_ID_OFFSET 0x08
297 #define PCI_CLASSCODE_OFFSET 0x09
298 #define PCI_CACHELINE_SIZE_OFFSET 0x0C
299 #define PCI_LATENCY_TIMER_OFFSET 0x0D
300 #define PCI_HEADER_TYPE_OFFSET 0x0E
301 #define PCI_BIST_OFFSET 0x0F
302 #define PCI_BASE_ADDRESSREG_OFFSET 0x10
303 #define PCI_CARDBUS_CIS_OFFSET 0x28
304 #define PCI_SVID_OFFSET 0x2C // SubSystem Vendor id
305 #define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C
306 #define PCI_SID_OFFSET 0x2E // SubSystem ID
307 #define PCI_SUBSYSTEM_ID_OFFSET 0x2E
308 #define PCI_EXPANSION_ROM_BASE 0x30
309 #define PCI_CAPBILITY_POINTER_OFFSET 0x34
310 #define PCI_INT_LINE_OFFSET 0x3C // Interrupt Line Register
311 #define PCI_INT_PIN_OFFSET 0x3D // Interrupt Pin Register
312 #define PCI_MAXGNT_OFFSET 0x3E // Max Grant Register
313 #define PCI_MAXLAT_OFFSET 0x3F // Max Latency Register
315 #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E
316 #define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E
318 #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18
319 #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19
320 #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a
323 // Interrupt Line "Unknown" or "No connection" value defined for x86 based system
325 #define PCI_INT_LINE_UNKNOWN 0xFF
337 } PCI_CONFIG_ACCESS_CF8
;
341 #define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55
342 #define PCI_DATA_STRUCTURE_SIGNATURE EFI_SIGNATURE_32 ('P', 'C', 'I', 'R')
343 #define PCI_CODE_TYPE_PCAT_IMAGE 0x00
344 #define PCI_CODE_TYPE_EFI_IMAGE 0x03
345 #define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001
347 #define EFI_PCI_COMMAND_IO_SPACE 0x0001
348 #define EFI_PCI_COMMAND_MEMORY_SPACE 0x0002
349 #define EFI_PCI_COMMAND_BUS_MASTER 0x0004
350 #define EFI_PCI_COMMAND_SPECIAL_CYCLE 0x0008
351 #define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE 0x0010
352 #define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP 0x0020
353 #define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND 0x0040
354 #define EFI_PCI_COMMAND_STEPPING_CONTROL 0x0080
355 #define EFI_PCI_COMMAND_SERR 0x0100
356 #define EFI_PCI_COMMAND_FAST_BACK_TO_BACK 0x0200
358 #define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE 0x0001
359 #define EFI_PCI_BRIDGE_CONTROL_SERR 0x0002
360 #define EFI_PCI_BRIDGE_CONTROL_ISA 0x0004
361 #define EFI_PCI_BRIDGE_CONTROL_VGA 0x0008
362 #define EFI_PCI_BRIDGE_CONTROL_VGA_16 0x0010
363 #define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT 0x0020
364 #define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS 0x0040
365 #define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK 0x0080
366 #define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER 0x0100
367 #define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER 0x0200
368 #define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS 0x0400
369 #define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR 0x0800
372 // Following are the PCI-CARDBUS bridge control bit
374 #define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE 0x0080
375 #define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE 0x0100
376 #define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE 0x0200
377 #define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE 0x0400
380 // Following are the PCI status control bit
382 #define EFI_PCI_STATUS_CAPABILITY 0x0010
383 #define EFI_PCI_STATUS_66MZ_CAPABLE 0x0020
384 #define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE 0x0080
385 #define EFI_PCI_MASTER_DATA_PARITY_ERROR 0x0100
387 #define EFI_PCI_CAPABILITY_PTR 0x34
388 #define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
392 UINT16 Signature
; // 0xaa55
393 UINT8 Reserved
[0x16];
395 } PCI_EXPANSION_ROM_HEADER
;
398 UINT16 Signature
; // 0xaa55
400 UINT8 InitEntryPoint
[3];
401 UINT8 Reserved
[0x12];
403 } EFI_LEGACY_EXPANSION_ROM_HEADER
;
406 UINT32 Signature
; // "PCIR"
418 } PCI_DATA_STRUCTURE
;
421 // PCI Capability List IDs and records
423 #define EFI_PCI_CAPABILITY_ID_PMI 0x01
424 #define EFI_PCI_CAPABILITY_ID_AGP 0x02
425 #define EFI_PCI_CAPABILITY_ID_VPD 0x03
426 #define EFI_PCI_CAPABILITY_ID_SLOTID 0x04
427 #define EFI_PCI_CAPABILITY_ID_MSI 0x05
428 #define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
429 #define EFI_PCI_CAPABILITY_ID_PCIX 0x07
434 } EFI_PCI_CAPABILITY_HDR
;
437 // Capability EFI_PCI_CAPABILITY_ID_PMI
440 EFI_PCI_CAPABILITY_HDR Hdr
;
443 UINT8 BridgeExtention
;
445 } EFI_PCI_CAPABILITY_PMI
;
448 // Capability EFI_PCI_CAPABILITY_ID_AGP
451 EFI_PCI_CAPABILITY_HDR Hdr
;
456 } EFI_PCI_CAPABILITY_AGP
;
459 // Capability EFI_PCI_CAPABILITY_ID_VPD
462 EFI_PCI_CAPABILITY_HDR Hdr
;
465 } EFI_PCI_CAPABILITY_VPD
;
468 // Capability EFI_PCI_CAPABILITY_ID_SLOTID
471 EFI_PCI_CAPABILITY_HDR Hdr
;
474 } EFI_PCI_CAPABILITY_SLOTID
;
477 // Capability EFI_PCI_CAPABILITY_ID_MSI
480 EFI_PCI_CAPABILITY_HDR Hdr
;
484 } EFI_PCI_CAPABILITY_MSI32
;
487 EFI_PCI_CAPABILITY_HDR Hdr
;
489 UINT32 MsgAddrRegLsdw
;
490 UINT32 MsgAddrRegMsdw
;
492 } EFI_PCI_CAPABILITY_MSI64
;
495 // Capability EFI_PCI_CAPABILITY_ID_HOTPLUG
498 EFI_PCI_CAPABILITY_HDR Hdr
;
500 // not finished - fields need to go here
502 } EFI_PCI_CAPABILITY_HOTPLUG
;
505 // Capability EFI_PCI_CAPABILITY_ID_PCIX
508 EFI_PCI_CAPABILITY_HDR Hdr
;
511 } EFI_PCI_CAPABILITY_PCIX
;
514 EFI_PCI_CAPABILITY_HDR Hdr
;
517 UINT32 SplitTransCtrlRegUp
;
518 UINT32 SplitTransCtrlRegDn
;
519 } EFI_PCI_CAPABILITY_PCIX_BRDG
;
521 #define DEVICE_ID_NOCARE 0xFFFF
523 #define PCI_ACPI_UNUSED 0
524 #define PCI_BAR_NOCHANGE 0
525 #define PCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL
526 #define PCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL
527 #define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL
528 #define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL
530 #define PCI_BAR_IDX0 0x00
531 #define PCI_BAR_IDX1 0x01
532 #define PCI_BAR_IDX2 0x02
533 #define PCI_BAR_IDX3 0x03
534 #define PCI_BAR_IDX4 0x04
535 #define PCI_BAR_IDX5 0x05
536 #define PCI_BAR_ALL 0xFF
539 // EFI PCI Option ROM definitions
542 #define EFI_ROOT_BRIDGE_LIST 'eprb'
543 #define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1
554 UINT16 Signature
; // 0xaa55
555 UINT16 InitializationSize
;
556 UINT32 EfiSignature
; // 0x0EF1
558 UINT16 EfiMachineType
;
559 UINT16 CompressionType
;
561 UINT16 EfiImageHeaderOffset
;
563 } EFI_PCI_EXPANSION_ROM_HEADER
;
567 PCI_EXPANSION_ROM_HEADER
*Generic
;
568 EFI_PCI_EXPANSION_ROM_HEADER
*Efi
;
569 EFI_LEGACY_EXPANSION_ROM_HEADER
*PcAt
;
570 } EFI_PCI_ROM_HEADER
;