2 This file contains definitions for SPD LPDDR.
4 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 @par Revision Reference:
14 - Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules Document Release 2
15 http://www.jedec.org/standards-documents/docs/spd412m-2
18 #ifndef _SDRAM_SPD_LPDDR_H_
19 #define _SDRAM_SPD_LPDDR_H_
21 #pragma pack (push, 1)
25 UINT8 BytesUsed
: 4; ///< Bits 3:0
26 UINT8 BytesTotal
: 3; ///< Bits 6:4
27 UINT8 CrcCoverage
: 1; ///< Bits 7:7
30 } SPD_LPDDR_DEVICE_DESCRIPTION_STRUCT
;
34 UINT8 Minor
: 4; ///< Bits 3:0
35 UINT8 Major
: 4; ///< Bits 7:4
38 } SPD_LPDDR_REVISION_STRUCT
;
42 UINT8 Type
: 8; ///< Bits 7:0
45 } SPD_LPDDR_DRAM_DEVICE_TYPE_STRUCT
;
49 UINT8 ModuleType
: 4; ///< Bits 3:0
50 UINT8 HybridMedia
: 3; ///< Bits 6:4
51 UINT8 Hybrid
: 1; ///< Bits 7:7
54 } SPD_LPDDR_MODULE_TYPE_STRUCT
;
58 UINT8 Density
: 4; ///< Bits 3:0
59 UINT8 BankAddress
: 2; ///< Bits 5:4
60 UINT8 BankGroup
: 2; ///< Bits 7:6
63 } SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT
;
67 UINT8 ColumnAddress
: 3; ///< Bits 2:0
68 UINT8 RowAddress
: 3; ///< Bits 5:3
69 UINT8 Reserved
: 2; ///< Bits 7:6
72 } SPD_LPDDR_SDRAM_ADDRESSING_STRUCT
;
76 UINT8 SignalLoading
: 2; ///< Bits 1:0
77 UINT8 ChannelsPerDie
: 2; ///< Bits 3:2
78 UINT8 DieCount
: 3; ///< Bits 6:4
79 UINT8 SdramPackageType
: 1; ///< Bits 7:7
82 } SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT
;
86 UINT8 MaximumActivateCount
: 4; ///< Bits 3:0
87 UINT8 MaximumActivateWindow
: 2; ///< Bits 5:4
88 UINT8 Reserved
: 2; ///< Bits 7:6
91 } SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT
;
95 UINT8 Reserved
: 8; ///< Bits 7:0
98 } SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT
;
102 UINT8 Reserved
: 5; ///< Bits 4:0
103 UINT8 SoftPPR
: 1; ///< Bits 5:5
104 UINT8 PostPackageRepair
: 2; ///< Bits 7:6
107 } SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT
;
111 UINT8 OperationAt1_20
: 1; ///< Bits 0:0
112 UINT8 EndurantAt1_20
: 1; ///< Bits 1:1
113 UINT8 OperationAt1_10
: 1; ///< Bits 2:2
114 UINT8 EndurantAt1_10
: 1; ///< Bits 3:3
115 UINT8 OperationAtTBD2V
: 1; ///< Bits 4:4
116 UINT8 EndurantAtTBD2V
: 1; ///< Bits 5:5
117 UINT8 Reserved
: 2; ///< Bits 7:6
120 } SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT
;
124 UINT8 SdramDeviceWidth
: 3; ///< Bits 2:0
125 UINT8 RankCount
: 3; ///< Bits 5:3
126 UINT8 Reserved
: 2; ///< Bits 7:6
129 } SPD_LPDDR_MODULE_ORGANIZATION_STRUCT
;
133 UINT8 PrimaryBusWidth
: 3; ///< Bits 2:0
134 UINT8 BusWidthExtension
: 2; ///< Bits 4:3
135 UINT8 NumberofChannels
: 3; ///< Bits 7:5
138 } SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT
;
142 UINT8 Reserved
: 7; ///< Bits 6:0
143 UINT8 ThermalSensorPresence
: 1; ///< Bits 7:7
146 } SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT
;
150 UINT8 ExtendedBaseModuleType
: 4; ///< Bits 3:0
151 UINT8 Reserved
: 4; ///< Bits 7:4
154 } SPD_LPDDR_EXTENDED_MODULE_TYPE_STRUCT
;
158 UINT8 ChipSelectLoading
: 3; ///< Bits 2:0
159 UINT8 CommandAddressControlClockLoading
: 3; ///< Bits 5:3
160 UINT8 DataStrobeMaskLoading
: 2; ///< Bits 7:6
163 } SPD_LPDDR_SIGNAL_LOADING_STRUCT
;
167 UINT8 Fine
: 2; ///< Bits 1:0
168 UINT8 Medium
: 2; ///< Bits 3:2
169 UINT8 Reserved
: 4; ///< Bits 7:4
172 } SPD_LPDDR_TIMEBASE_STRUCT
;
176 UINT8 tCKmin
: 8; ///< Bits 7:0
179 } SPD_LPDDR_TCK_MIN_MTB_STRUCT
;
183 UINT8 tCKmax
: 8; ///< Bits 7:0
186 } SPD_LPDDR_TCK_MAX_MTB_STRUCT
;
190 UINT32 Cl3
: 1; ///< Bits 0:0
191 UINT32 Cl6
: 1; ///< Bits 1:1
192 UINT32 Cl8
: 1; ///< Bits 2:2
193 UINT32 Cl9
: 1; ///< Bits 3:3
194 UINT32 Cl10
: 1; ///< Bits 4:4
195 UINT32 Cl11
: 1; ///< Bits 5:5
196 UINT32 Cl12
: 1; ///< Bits 6:6
197 UINT32 Cl14
: 1; ///< Bits 7:7
198 UINT32 Cl16
: 1; ///< Bits 8:8
199 UINT32 Reserved0
: 1; ///< Bits 9:9
200 UINT32 Cl20
: 1; ///< Bits 10:10
201 UINT32 Cl22
: 1; ///< Bits 11:11
202 UINT32 Cl24
: 1; ///< Bits 12:12
203 UINT32 Reserved1
: 1; ///< Bits 13:13
204 UINT32 Cl28
: 1; ///< Bits 14:14
205 UINT32 Reserved2
: 1; ///< Bits 15:15
206 UINT32 Cl32
: 1; ///< Bits 16:16
207 UINT32 Reserved3
: 1; ///< Bits 17:17
208 UINT32 Cl36
: 1; ///< Bits 18:18
209 UINT32 Reserved4
: 1; ///< Bits 19:19
210 UINT32 Cl40
: 1; ///< Bits 20:20
211 UINT32 Reserved5
: 11; ///< Bits 31:21
216 } SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT
;
220 UINT8 tAAmin
: 8; ///< Bits 7:0
223 } SPD_LPDDR_TAA_MIN_MTB_STRUCT
;
227 UINT8 ReadLatencyMode
: 2; ///< Bits 1:0
228 UINT8 WriteLatencySet
: 2; ///< Bits 3:2
229 UINT8 Reserved
: 4; ///< Bits 7:4
232 } SPD_LPDDR_RW_LATENCY_OPTION_STRUCT
;
236 UINT8 tRCDmin
: 8; ///< Bits 7:0
239 } SPD_LPDDR_TRCD_MIN_MTB_STRUCT
;
243 UINT8 tRPab
: 8; ///< Bits 7:0
246 } SPD_LPDDR_TRP_AB_MTB_STRUCT
;
250 UINT8 tRPpb
: 8; ///< Bits 7:0
253 } SPD_LPDDR_TRP_PB_MTB_STRUCT
;
257 UINT16 tRFCab
: 16; ///< Bits 15:0
261 } SPD_LPDDR_TRFC_AB_MTB_STRUCT
;
265 UINT16 tRFCpb
: 16; ///< Bits 15:0
269 } SPD_LPDDR_TRFC_PB_MTB_STRUCT
;
273 UINT8 BitOrderatSDRAM
: 5; ///< Bits 4:0
274 UINT8 WiredtoUpperLowerNibble
: 1; ///< Bits 5:5
275 UINT8 PackageRankMap
: 2; ///< Bits 7:6
278 } SPD_LPDDR_CONNECTOR_BIT_MAPPING_BYTE_STRUCT
;
282 INT8 tRPpbFine
: 8; ///< Bits 7:0
285 } SPD_LPDDR_TRP_PB_FTB_STRUCT
;
289 INT8 tRPabFine
: 8; ///< Bits 7:0
292 } SPD_LPDDR_TRP_AB_FTB_STRUCT
;
296 INT8 tRCDminFine
: 8; ///< Bits 7:0
299 } SPD_LPDDR_TRCD_MIN_FTB_STRUCT
;
303 INT8 tAAminFine
: 8; ///< Bits 7:0
306 } SPD_LPDDR_TAA_MIN_FTB_STRUCT
;
310 INT8 tCKmaxFine
: 8; ///< Bits 7:0
313 } SPD_LPDDR_TCK_MAX_FTB_STRUCT
;
317 INT8 tCKminFine
: 8; ///< Bits 7:0
320 } SPD_LPDDR_TCK_MIN_FTB_STRUCT
;
324 UINT16 ContinuationCount
: 7; ///< Bits 6:0
325 UINT16 ContinuationParity
: 1; ///< Bits 7:7
326 UINT16 LastNonZeroByte
: 8; ///< Bits 15:8
330 } SPD_LPDDR_MANUFACTURER_ID_CODE
;
333 UINT8 Location
; ///< Module Manufacturing Location
334 } SPD_LPDDR_MANUFACTURING_LOCATION
;
337 UINT8 Year
; ///< Year represented in BCD (00h = 2000)
338 UINT8 Week
; ///< Year represented in BCD (47h = week 47)
339 } SPD_LPDDR_MANUFACTURING_DATE
;
343 UINT16 SerialNumber16
[2];
344 UINT8 SerialNumber8
[4];
345 } SPD_LPDDR_MANUFACTURER_SERIAL_NUMBER
;
348 SPD_LPDDR_MANUFACTURER_ID_CODE IdCode
; ///< Module Manufacturer ID Code
349 SPD_LPDDR_MANUFACTURING_LOCATION Location
; ///< Module Manufacturing Location
350 SPD_LPDDR_MANUFACTURING_DATE Date
; ///< Module Manufacturing Year, in BCD (range: 2000-2255)
351 SPD_LPDDR_MANUFACTURER_SERIAL_NUMBER SerialNumber
; ///< Module Serial Number
352 } SPD_LPDDR_UNIQUE_MODULE_ID
;
356 UINT8 FrontThickness
: 4; ///< Bits 3:0
357 UINT8 BackThickness
: 4; ///< Bits 7:4
360 } SPD_LPDDR_MODULE_MAXIMUM_THICKNESS
;
364 UINT8 Height
: 5; ///< Bits 4:0
365 UINT8 RawCardExtension
: 3; ///< Bits 7:5
368 } SPD_LPDDR_MODULE_NOMINAL_HEIGHT
;
372 UINT8 Card
: 5; ///< Bits 4:0
373 UINT8 Revision
: 2; ///< Bits 6:5
374 UINT8 Extension
: 1; ///< Bits 7:7
377 } SPD_LPDDR_REFERENCE_RAW_CARD
;
382 } SPD_LPDDR_CYCLIC_REDUNDANCY_CODE
;
385 SPD_LPDDR_DEVICE_DESCRIPTION_STRUCT Description
; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2
386 SPD_LPDDR_REVISION_STRUCT Revision
; ///< 1 SPD Revision
387 SPD_LPDDR_DRAM_DEVICE_TYPE_STRUCT DramDeviceType
; ///< 2 DRAM Device Type
388 SPD_LPDDR_MODULE_TYPE_STRUCT ModuleType
; ///< 3 Module Type
389 SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks
; ///< 4 SDRAM Density and Banks
390 SPD_LPDDR_SDRAM_ADDRESSING_STRUCT SdramAddressing
; ///< 5 SDRAM Addressing
391 SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT SdramPackageType
; ///< 6 SDRAM Package Type
392 SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures
; ///< 7 SDRAM Optional Features
393 SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions
; ///< 8 SDRAM Thermal and Refresh Options
394 SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT OtherOptionalFeatures
; ///< 9 Other SDRAM Optional Features
395 UINT8 Reserved0
; ///< 10 Reserved
396 SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage
; ///< 11 Module Nominal Voltage, VDD
397 SPD_LPDDR_MODULE_ORGANIZATION_STRUCT ModuleOrganization
; ///< 12 Module Organization
398 SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth
; ///< 13 Module Memory Bus Width
399 SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor
; ///< 14 Module Thermal Sensor
400 SPD_LPDDR_EXTENDED_MODULE_TYPE_STRUCT ExtendedModuleType
; ///< 15 Extended Module Type
401 SPD_LPDDR_SIGNAL_LOADING_STRUCT SignalLoading
; ///< 16 Signal Loading
402 SPD_LPDDR_TIMEBASE_STRUCT Timebase
; ///< 17 Timebases
403 SPD_LPDDR_TCK_MIN_MTB_STRUCT tCKmin
; ///< 18 SDRAM Minimum Cycle Time (tCKmin)
404 SPD_LPDDR_TCK_MAX_MTB_STRUCT tCKmax
; ///< 19 SDRAM Maximum Cycle Time (tCKmax)
405 SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies
; ///< 20-23 CAS Latencies Supported
406 SPD_LPDDR_TAA_MIN_MTB_STRUCT tAAmin
; ///< 24 Minimum CAS Latency Time (tAAmin)
407 SPD_LPDDR_RW_LATENCY_OPTION_STRUCT LatencySetOptions
; ///< 25 Read and Write Latency Set Options
408 SPD_LPDDR_TRCD_MIN_MTB_STRUCT tRCDmin
; ///< 26 Minimum RAS# to CAS# Delay Time (tRCDmin)
409 SPD_LPDDR_TRP_AB_MTB_STRUCT tRPab
; ///< 27 Minimum Row Precharge Delay Time (tRPab), all banks
410 SPD_LPDDR_TRP_PB_MTB_STRUCT tRPpb
; ///< 28 Minimum Row Precharge Delay Time (tRPpb), per bank
411 SPD_LPDDR_TRFC_AB_MTB_STRUCT tRFCab
; ///< 29-30 Minimum Refresh Recovery Delay Time (tRFCab), all banks
412 SPD_LPDDR_TRFC_PB_MTB_STRUCT tRFCpb
; ///< 31-32 Minimum Refresh Recovery Delay Time (tRFCpb), per bank
413 UINT8 Reserved1
[59 - 33 + 1]; ///< 33-59 Reserved
414 SPD_LPDDR_CONNECTOR_BIT_MAPPING_BYTE_STRUCT BitMapping
[77 - 60 + 1]; ///< 60-77 Connector to SDRAM Bit Mapping
415 UINT8 Reserved2
[119 - 78 + 1]; ///< 78-119 Reserved
416 SPD_LPDDR_TRP_PB_FTB_STRUCT tRPpbFine
; ///< 120 Fine Offset for Minimum Row Precharge Delay Time (tRPpbFine), per bank
417 SPD_LPDDR_TRP_AB_FTB_STRUCT tRPabFine
; ///< 121 Fine Offset for Minimum Row Precharge Delay Time (tRPabFine), all ranks
418 SPD_LPDDR_TRCD_MIN_FTB_STRUCT tRCDminFine
; ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
419 SPD_LPDDR_TAA_MIN_FTB_STRUCT tAAminFine
; ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin)
420 SPD_LPDDR_TCK_MAX_FTB_STRUCT tCKmaxFine
; ///< 124 Fine Offset for SDRAM Maximum Cycle Time (tCKmax)
421 SPD_LPDDR_TCK_MIN_FTB_STRUCT tCKminFine
; ///< 125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
422 SPD_LPDDR_CYCLIC_REDUNDANCY_CODE Crc
; ///< 126-127 Cyclical Redundancy Code (CRC)
423 } SPD_LPDDR_BASE_SECTION
;
426 SPD_LPDDR_MODULE_NOMINAL_HEIGHT ModuleNominalHeight
; ///< 128 Module Nominal Height
427 SPD_LPDDR_MODULE_MAXIMUM_THICKNESS ModuleMaximumThickness
; ///< 129 Module Maximum Thickness
428 SPD_LPDDR_REFERENCE_RAW_CARD ReferenceRawCardUsed
; ///< 130 Reference Raw Card Used
429 UINT8 Reserved
[253 - 131 + 1]; ///< 131-253 Reserved
430 SPD_LPDDR_CYCLIC_REDUNDANCY_CODE Crc
; ///< 254-255 Cyclical Redundancy Code (CRC)
431 } SPD_LPDDR_MODULE_LPDIMM
;
434 SPD_LPDDR_MODULE_LPDIMM LpDimm
; ///< 128-255 Unbuffered Memory Module Types
435 } SPD_LPDDR_MODULE_SPECIFIC
;
438 UINT8 ModulePartNumber
[348 - 329 + 1]; ///< 329-348 Module Part Number
439 } SPD_LPDDR_MODULE_PART_NUMBER
;
442 UINT8 ManufacturerSpecificData
[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data
443 } SPD_LPDDR_MANUFACTURER_SPECIFIC
;
445 typedef UINT8 SPD_LPDDR_MODULE_REVISION_CODE
;///< 349 Module Revision Code
446 typedef UINT8 SPD_LPDDR_DRAM_STEPPING
; ///< 352 Dram Stepping
449 SPD_LPDDR_UNIQUE_MODULE_ID ModuleId
; ///< 320-328 Unique Module ID
450 SPD_LPDDR_MODULE_PART_NUMBER ModulePartNumber
; ///< 329-348 Module Part Number
451 SPD_LPDDR_MODULE_REVISION_CODE ModuleRevisionCode
; ///< 349 Module Revision Code
452 SPD_LPDDR_MANUFACTURER_ID_CODE DramIdCode
; ///< 350-351 Dram Manufacturer ID Code
453 SPD_LPDDR_DRAM_STEPPING DramStepping
; ///< 352 Dram Stepping
454 SPD_LPDDR_MANUFACTURER_SPECIFIC ManufacturerSpecificData
; ///< 353-381 Manufacturer's Specific Data
455 UINT8 Reserved
[383 - 382 + 1]; ///< 382-383 Reserved
456 } SPD_LPDDR_MANUFACTURING_DATA
;
459 UINT8 Reserved
[511 - 384 + 1]; ///< 384-511 End User Programmable
460 } SPD_LPDDR_END_USER_SECTION
;
463 /// LPDDR Serial Presence Detect structure
466 SPD_LPDDR_BASE_SECTION Base
; ///< 0-127 Base Configuration and DRAM Parameters
467 SPD_LPDDR_MODULE_SPECIFIC Module
; ///< 128-255 Module-Specific Section
468 UINT8 Reserved
[319 - 256 + 1]; ///< 256-319 Hybrid Memory Parameters
469 SPD_LPDDR_MANUFACTURING_DATA ManufactureInfo
; ///< 320-383 Manufacturing Information
470 SPD_LPDDR_END_USER_SECTION EndUser
; ///< 384-511 End User Programmable