2 This file contains definitions for SPD LPDDR.
4 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
7 @par Revision Reference:
8 - Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules Document Release 2
9 http://www.jedec.org/standards-documents/docs/spd412m-2
12 #ifndef _SDRAM_SPD_LPDDR_H_
13 #define _SDRAM_SPD_LPDDR_H_
15 #pragma pack (push, 1)
19 UINT8 BytesUsed
: 4; ///< Bits 3:0
20 UINT8 BytesTotal
: 3; ///< Bits 6:4
21 UINT8 CrcCoverage
: 1; ///< Bits 7:7
24 } SPD_LPDDR_DEVICE_DESCRIPTION_STRUCT
;
28 UINT8 Minor
: 4; ///< Bits 3:0
29 UINT8 Major
: 4; ///< Bits 7:4
32 } SPD_LPDDR_REVISION_STRUCT
;
36 UINT8 Type
: 8; ///< Bits 7:0
39 } SPD_LPDDR_DRAM_DEVICE_TYPE_STRUCT
;
43 UINT8 ModuleType
: 4; ///< Bits 3:0
44 UINT8 HybridMedia
: 3; ///< Bits 6:4
45 UINT8 Hybrid
: 1; ///< Bits 7:7
48 } SPD_LPDDR_MODULE_TYPE_STRUCT
;
52 UINT8 Density
: 4; ///< Bits 3:0
53 UINT8 BankAddress
: 2; ///< Bits 5:4
54 UINT8 BankGroup
: 2; ///< Bits 7:6
57 } SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT
;
61 UINT8 ColumnAddress
: 3; ///< Bits 2:0
62 UINT8 RowAddress
: 3; ///< Bits 5:3
63 UINT8 Reserved
: 2; ///< Bits 7:6
66 } SPD_LPDDR_SDRAM_ADDRESSING_STRUCT
;
70 UINT8 SignalLoading
: 2; ///< Bits 1:0
71 UINT8 ChannelsPerDie
: 2; ///< Bits 3:2
72 UINT8 DieCount
: 3; ///< Bits 6:4
73 UINT8 SdramPackageType
: 1; ///< Bits 7:7
76 } SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT
;
80 UINT8 MaximumActivateCount
: 4; ///< Bits 3:0
81 UINT8 MaximumActivateWindow
: 2; ///< Bits 5:4
82 UINT8 Reserved
: 2; ///< Bits 7:6
85 } SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT
;
89 UINT8 Reserved
: 8; ///< Bits 7:0
92 } SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT
;
96 UINT8 Reserved
: 5; ///< Bits 4:0
97 UINT8 SoftPPR
: 1; ///< Bits 5:5
98 UINT8 PostPackageRepair
: 2; ///< Bits 7:6
101 } SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT
;
105 UINT8 OperationAt1_20
: 1; ///< Bits 0:0
106 UINT8 EndurantAt1_20
: 1; ///< Bits 1:1
107 UINT8 OperationAt1_10
: 1; ///< Bits 2:2
108 UINT8 EndurantAt1_10
: 1; ///< Bits 3:3
109 UINT8 OperationAtTBD2V
: 1; ///< Bits 4:4
110 UINT8 EndurantAtTBD2V
: 1; ///< Bits 5:5
111 UINT8 Reserved
: 2; ///< Bits 7:6
114 } SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT
;
118 UINT8 SdramDeviceWidth
: 3; ///< Bits 2:0
119 UINT8 RankCount
: 3; ///< Bits 5:3
120 UINT8 Reserved
: 2; ///< Bits 7:6
123 } SPD_LPDDR_MODULE_ORGANIZATION_STRUCT
;
127 UINT8 PrimaryBusWidth
: 3; ///< Bits 2:0
128 UINT8 BusWidthExtension
: 2; ///< Bits 4:3
129 UINT8 NumberofChannels
: 3; ///< Bits 7:5
132 } SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT
;
136 UINT8 Reserved
: 7; ///< Bits 6:0
137 UINT8 ThermalSensorPresence
: 1; ///< Bits 7:7
140 } SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT
;
144 UINT8 ExtendedBaseModuleType
: 4; ///< Bits 3:0
145 UINT8 Reserved
: 4; ///< Bits 7:4
148 } SPD_LPDDR_EXTENDED_MODULE_TYPE_STRUCT
;
152 UINT8 ChipSelectLoading
: 3; ///< Bits 2:0
153 UINT8 CommandAddressControlClockLoading
: 3; ///< Bits 5:3
154 UINT8 DataStrobeMaskLoading
: 2; ///< Bits 7:6
157 } SPD_LPDDR_SIGNAL_LOADING_STRUCT
;
161 UINT8 Fine
: 2; ///< Bits 1:0
162 UINT8 Medium
: 2; ///< Bits 3:2
163 UINT8 Reserved
: 4; ///< Bits 7:4
166 } SPD_LPDDR_TIMEBASE_STRUCT
;
170 UINT8 tCKmin
: 8; ///< Bits 7:0
173 } SPD_LPDDR_TCK_MIN_MTB_STRUCT
;
177 UINT8 tCKmax
: 8; ///< Bits 7:0
180 } SPD_LPDDR_TCK_MAX_MTB_STRUCT
;
184 UINT32 Cl3
: 1; ///< Bits 0:0
185 UINT32 Cl6
: 1; ///< Bits 1:1
186 UINT32 Cl8
: 1; ///< Bits 2:2
187 UINT32 Cl9
: 1; ///< Bits 3:3
188 UINT32 Cl10
: 1; ///< Bits 4:4
189 UINT32 Cl11
: 1; ///< Bits 5:5
190 UINT32 Cl12
: 1; ///< Bits 6:6
191 UINT32 Cl14
: 1; ///< Bits 7:7
192 UINT32 Cl16
: 1; ///< Bits 8:8
193 UINT32 Reserved0
: 1; ///< Bits 9:9
194 UINT32 Cl20
: 1; ///< Bits 10:10
195 UINT32 Cl22
: 1; ///< Bits 11:11
196 UINT32 Cl24
: 1; ///< Bits 12:12
197 UINT32 Reserved1
: 1; ///< Bits 13:13
198 UINT32 Cl28
: 1; ///< Bits 14:14
199 UINT32 Reserved2
: 1; ///< Bits 15:15
200 UINT32 Cl32
: 1; ///< Bits 16:16
201 UINT32 Reserved3
: 1; ///< Bits 17:17
202 UINT32 Cl36
: 1; ///< Bits 18:18
203 UINT32 Reserved4
: 1; ///< Bits 19:19
204 UINT32 Cl40
: 1; ///< Bits 20:20
205 UINT32 Reserved5
: 11; ///< Bits 31:21
210 } SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT
;
214 UINT8 tAAmin
: 8; ///< Bits 7:0
217 } SPD_LPDDR_TAA_MIN_MTB_STRUCT
;
221 UINT8 ReadLatencyMode
: 2; ///< Bits 1:0
222 UINT8 WriteLatencySet
: 2; ///< Bits 3:2
223 UINT8 Reserved
: 4; ///< Bits 7:4
226 } SPD_LPDDR_RW_LATENCY_OPTION_STRUCT
;
230 UINT8 tRCDmin
: 8; ///< Bits 7:0
233 } SPD_LPDDR_TRCD_MIN_MTB_STRUCT
;
237 UINT8 tRPab
: 8; ///< Bits 7:0
240 } SPD_LPDDR_TRP_AB_MTB_STRUCT
;
244 UINT8 tRPpb
: 8; ///< Bits 7:0
247 } SPD_LPDDR_TRP_PB_MTB_STRUCT
;
251 UINT16 tRFCab
: 16; ///< Bits 15:0
255 } SPD_LPDDR_TRFC_AB_MTB_STRUCT
;
259 UINT16 tRFCpb
: 16; ///< Bits 15:0
263 } SPD_LPDDR_TRFC_PB_MTB_STRUCT
;
267 UINT8 BitOrderatSDRAM
: 5; ///< Bits 4:0
268 UINT8 WiredtoUpperLowerNibble
: 1; ///< Bits 5:5
269 UINT8 PackageRankMap
: 2; ///< Bits 7:6
272 } SPD_LPDDR_CONNECTOR_BIT_MAPPING_BYTE_STRUCT
;
276 INT8 tRPpbFine
: 8; ///< Bits 7:0
279 } SPD_LPDDR_TRP_PB_FTB_STRUCT
;
283 INT8 tRPabFine
: 8; ///< Bits 7:0
286 } SPD_LPDDR_TRP_AB_FTB_STRUCT
;
290 INT8 tRCDminFine
: 8; ///< Bits 7:0
293 } SPD_LPDDR_TRCD_MIN_FTB_STRUCT
;
297 INT8 tAAminFine
: 8; ///< Bits 7:0
300 } SPD_LPDDR_TAA_MIN_FTB_STRUCT
;
304 INT8 tCKmaxFine
: 8; ///< Bits 7:0
307 } SPD_LPDDR_TCK_MAX_FTB_STRUCT
;
311 INT8 tCKminFine
: 8; ///< Bits 7:0
314 } SPD_LPDDR_TCK_MIN_FTB_STRUCT
;
318 UINT16 ContinuationCount
: 7; ///< Bits 6:0
319 UINT16 ContinuationParity
: 1; ///< Bits 7:7
320 UINT16 LastNonZeroByte
: 8; ///< Bits 15:8
324 } SPD_LPDDR_MANUFACTURER_ID_CODE
;
327 UINT8 Location
; ///< Module Manufacturing Location
328 } SPD_LPDDR_MANUFACTURING_LOCATION
;
331 UINT8 Year
; ///< Year represented in BCD (00h = 2000)
332 UINT8 Week
; ///< Year represented in BCD (47h = week 47)
333 } SPD_LPDDR_MANUFACTURING_DATE
;
337 UINT16 SerialNumber16
[2];
338 UINT8 SerialNumber8
[4];
339 } SPD_LPDDR_MANUFACTURER_SERIAL_NUMBER
;
342 SPD_LPDDR_MANUFACTURER_ID_CODE IdCode
; ///< Module Manufacturer ID Code
343 SPD_LPDDR_MANUFACTURING_LOCATION Location
; ///< Module Manufacturing Location
344 SPD_LPDDR_MANUFACTURING_DATE Date
; ///< Module Manufacturing Year, in BCD (range: 2000-2255)
345 SPD_LPDDR_MANUFACTURER_SERIAL_NUMBER SerialNumber
; ///< Module Serial Number
346 } SPD_LPDDR_UNIQUE_MODULE_ID
;
350 UINT8 FrontThickness
: 4; ///< Bits 3:0
351 UINT8 BackThickness
: 4; ///< Bits 7:4
354 } SPD_LPDDR_MODULE_MAXIMUM_THICKNESS
;
358 UINT8 Height
: 5; ///< Bits 4:0
359 UINT8 RawCardExtension
: 3; ///< Bits 7:5
362 } SPD_LPDDR_MODULE_NOMINAL_HEIGHT
;
366 UINT8 Card
: 5; ///< Bits 4:0
367 UINT8 Revision
: 2; ///< Bits 6:5
368 UINT8 Extension
: 1; ///< Bits 7:7
371 } SPD_LPDDR_REFERENCE_RAW_CARD
;
376 } SPD_LPDDR_CYCLIC_REDUNDANCY_CODE
;
379 SPD_LPDDR_DEVICE_DESCRIPTION_STRUCT Description
; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2
380 SPD_LPDDR_REVISION_STRUCT Revision
; ///< 1 SPD Revision
381 SPD_LPDDR_DRAM_DEVICE_TYPE_STRUCT DramDeviceType
; ///< 2 DRAM Device Type
382 SPD_LPDDR_MODULE_TYPE_STRUCT ModuleType
; ///< 3 Module Type
383 SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks
; ///< 4 SDRAM Density and Banks
384 SPD_LPDDR_SDRAM_ADDRESSING_STRUCT SdramAddressing
; ///< 5 SDRAM Addressing
385 SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT SdramPackageType
; ///< 6 SDRAM Package Type
386 SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures
; ///< 7 SDRAM Optional Features
387 SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions
; ///< 8 SDRAM Thermal and Refresh Options
388 SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT OtherOptionalFeatures
; ///< 9 Other SDRAM Optional Features
389 UINT8 Reserved0
; ///< 10 Reserved
390 SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage
; ///< 11 Module Nominal Voltage, VDD
391 SPD_LPDDR_MODULE_ORGANIZATION_STRUCT ModuleOrganization
; ///< 12 Module Organization
392 SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth
; ///< 13 Module Memory Bus Width
393 SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor
; ///< 14 Module Thermal Sensor
394 SPD_LPDDR_EXTENDED_MODULE_TYPE_STRUCT ExtendedModuleType
; ///< 15 Extended Module Type
395 SPD_LPDDR_SIGNAL_LOADING_STRUCT SignalLoading
; ///< 16 Signal Loading
396 SPD_LPDDR_TIMEBASE_STRUCT Timebase
; ///< 17 Timebases
397 SPD_LPDDR_TCK_MIN_MTB_STRUCT tCKmin
; ///< 18 SDRAM Minimum Cycle Time (tCKmin)
398 SPD_LPDDR_TCK_MAX_MTB_STRUCT tCKmax
; ///< 19 SDRAM Maximum Cycle Time (tCKmax)
399 SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies
; ///< 20-23 CAS Latencies Supported
400 SPD_LPDDR_TAA_MIN_MTB_STRUCT tAAmin
; ///< 24 Minimum CAS Latency Time (tAAmin)
401 SPD_LPDDR_RW_LATENCY_OPTION_STRUCT LatencySetOptions
; ///< 25 Read and Write Latency Set Options
402 SPD_LPDDR_TRCD_MIN_MTB_STRUCT tRCDmin
; ///< 26 Minimum RAS# to CAS# Delay Time (tRCDmin)
403 SPD_LPDDR_TRP_AB_MTB_STRUCT tRPab
; ///< 27 Minimum Row Precharge Delay Time (tRPab), all banks
404 SPD_LPDDR_TRP_PB_MTB_STRUCT tRPpb
; ///< 28 Minimum Row Precharge Delay Time (tRPpb), per bank
405 SPD_LPDDR_TRFC_AB_MTB_STRUCT tRFCab
; ///< 29-30 Minimum Refresh Recovery Delay Time (tRFCab), all banks
406 SPD_LPDDR_TRFC_PB_MTB_STRUCT tRFCpb
; ///< 31-32 Minimum Refresh Recovery Delay Time (tRFCpb), per bank
407 UINT8 Reserved1
[59 - 33 + 1]; ///< 33-59 Reserved
408 SPD_LPDDR_CONNECTOR_BIT_MAPPING_BYTE_STRUCT BitMapping
[77 - 60 + 1]; ///< 60-77 Connector to SDRAM Bit Mapping
409 UINT8 Reserved2
[119 - 78 + 1]; ///< 78-119 Reserved
410 SPD_LPDDR_TRP_PB_FTB_STRUCT tRPpbFine
; ///< 120 Fine Offset for Minimum Row Precharge Delay Time (tRPpbFine), per bank
411 SPD_LPDDR_TRP_AB_FTB_STRUCT tRPabFine
; ///< 121 Fine Offset for Minimum Row Precharge Delay Time (tRPabFine), all ranks
412 SPD_LPDDR_TRCD_MIN_FTB_STRUCT tRCDminFine
; ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
413 SPD_LPDDR_TAA_MIN_FTB_STRUCT tAAminFine
; ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin)
414 SPD_LPDDR_TCK_MAX_FTB_STRUCT tCKmaxFine
; ///< 124 Fine Offset for SDRAM Maximum Cycle Time (tCKmax)
415 SPD_LPDDR_TCK_MIN_FTB_STRUCT tCKminFine
; ///< 125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
416 SPD_LPDDR_CYCLIC_REDUNDANCY_CODE Crc
; ///< 126-127 Cyclical Redundancy Code (CRC)
417 } SPD_LPDDR_BASE_SECTION
;
420 SPD_LPDDR_MODULE_NOMINAL_HEIGHT ModuleNominalHeight
; ///< 128 Module Nominal Height
421 SPD_LPDDR_MODULE_MAXIMUM_THICKNESS ModuleMaximumThickness
; ///< 129 Module Maximum Thickness
422 SPD_LPDDR_REFERENCE_RAW_CARD ReferenceRawCardUsed
; ///< 130 Reference Raw Card Used
423 UINT8 Reserved
[253 - 131 + 1]; ///< 131-253 Reserved
424 SPD_LPDDR_CYCLIC_REDUNDANCY_CODE Crc
; ///< 254-255 Cyclical Redundancy Code (CRC)
425 } SPD_LPDDR_MODULE_LPDIMM
;
428 SPD_LPDDR_MODULE_LPDIMM LpDimm
; ///< 128-255 Unbuffered Memory Module Types
429 } SPD_LPDDR_MODULE_SPECIFIC
;
432 UINT8 ModulePartNumber
[348 - 329 + 1]; ///< 329-348 Module Part Number
433 } SPD_LPDDR_MODULE_PART_NUMBER
;
436 UINT8 ManufacturerSpecificData
[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data
437 } SPD_LPDDR_MANUFACTURER_SPECIFIC
;
439 typedef UINT8 SPD_LPDDR_MODULE_REVISION_CODE
;///< 349 Module Revision Code
440 typedef UINT8 SPD_LPDDR_DRAM_STEPPING
; ///< 352 Dram Stepping
443 SPD_LPDDR_UNIQUE_MODULE_ID ModuleId
; ///< 320-328 Unique Module ID
444 SPD_LPDDR_MODULE_PART_NUMBER ModulePartNumber
; ///< 329-348 Module Part Number
445 SPD_LPDDR_MODULE_REVISION_CODE ModuleRevisionCode
; ///< 349 Module Revision Code
446 SPD_LPDDR_MANUFACTURER_ID_CODE DramIdCode
; ///< 350-351 Dram Manufacturer ID Code
447 SPD_LPDDR_DRAM_STEPPING DramStepping
; ///< 352 Dram Stepping
448 SPD_LPDDR_MANUFACTURER_SPECIFIC ManufacturerSpecificData
; ///< 353-381 Manufacturer's Specific Data
449 UINT8 Reserved
[383 - 382 + 1]; ///< 382-383 Reserved
450 } SPD_LPDDR_MANUFACTURING_DATA
;
453 UINT8 Reserved
[511 - 384 + 1]; ///< 384-511 End User Programmable
454 } SPD_LPDDR_END_USER_SECTION
;
457 /// LPDDR Serial Presence Detect structure
460 SPD_LPDDR_BASE_SECTION Base
; ///< 0-127 Base Configuration and DRAM Parameters
461 SPD_LPDDR_MODULE_SPECIFIC Module
; ///< 128-255 Module-Specific Section
462 UINT8 Reserved
[319 - 256 + 1]; ///< 256-319 Hybrid Memory Parameters
463 SPD_LPDDR_MANUFACTURING_DATA ManufactureInfo
; ///< 320-383 Manufacturing Information
464 SPD_LPDDR_END_USER_SECTION EndUser
; ///< 384-511 End User Programmable