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git.proxmox.com Git - mirror_edk2.git/blob - MdePkg/Include/Library/CacheMaintenanceLib.h
2 Provides services to maintain instruction and data caches.
4 The Cache Maintenance Library provides abstractions for basic processor cache operations.
5 It removes the need to use assembly in C code.
7 Copyright (c) 2006 - 2008, Intel Corporation<BR>
8 All rights reserved. This program and the accompanying materials
9 are licensed and made available under the terms and conditions of the BSD License
10 which accompanies this distribution. The full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #ifndef __CACHE_MAINTENANCE_LIB__
19 #define __CACHE_MAINTENANCE_LIB__
22 Invalidates the entire instruction cache in cache coherency domain of the
28 InvalidateInstructionCache (
33 Invalidates a range of instruction cache lines in the cache coherency domain
36 Invalidates the instruction cache lines specified by Address and Length. If
37 Address is not aligned on a cache line boundary, then entire instruction
38 cache line containing Address is invalidated. If Address + Length is not
39 aligned on a cache line boundary, then the entire instruction cache line
40 containing Address + Length -1 is invalidated. This function may choose to
41 invalidate the entire instruction cache if that is more efficient than
42 invalidating the specified range. If Length is 0, then no instruction cache
43 lines are invalidated. Address is returned.
45 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
47 @param Address The base address of the instruction cache lines to
48 invalidate. If the CPU is in a physical addressing mode, then
49 Address is a physical address. If the CPU is in a virtual
50 addressing mode, then Address is a virtual address.
52 @param Length The number of bytes to invalidate from the instruction cache.
59 InvalidateInstructionCacheRange (
65 Writes Back and Invalidates the entire data cache in cache coherency domain
68 Writes Back and Invalidates the entire data cache in cache coherency domain
69 of the calling CPU. This function guarantees that all dirty cache lines are
70 written back to system memory, and also invalidates all the data cache lines
71 in the cache coherency domain of the calling CPU.
76 WriteBackInvalidateDataCache (
81 Writes Back and Invalidates a range of data cache lines in the cache
82 coherency domain of the calling CPU.
84 Writes Back and Invalidate the data cache lines specified by Address and
85 Length. If Address is not aligned on a cache line boundary, then entire data
86 cache line containing Address is written back and invalidated. If Address +
87 Length is not aligned on a cache line boundary, then the entire data cache
88 line containing Address + Length -1 is written back and invalidated. This
89 function may choose to write back and invalidate the entire data cache if
90 that is more efficient than writing back and invalidating the specified
91 range. If Length is 0, then no data cache lines are written back and
92 invalidated. Address is returned.
94 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
96 @param Address The base address of the data cache lines to write back and
97 invalidate. If the CPU is in a physical addressing mode, then
98 Address is a physical address. If the CPU is in a virtual
99 addressing mode, then Address is a virtual address.
100 @param Length The number of bytes to write back and invalidate from the
103 @return Address of cache invalidation.
108 WriteBackInvalidateDataCacheRange (
114 Writes Back the entire data cache in cache coherency domain of the calling
117 Writes Back the entire data cache in cache coherency domain of the calling
118 CPU. This function guarantees that all dirty cache lines are written back to
119 system memory. This function may also invalidate all the data cache lines in
120 the cache coherency domain of the calling CPU.
130 Writes Back a range of data cache lines in the cache coherency domain of the
133 Writes Back the data cache lines specified by Address and Length. If Address
134 is not aligned on a cache line boundary, then entire data cache line
135 containing Address is written back. If Address + Length is not aligned on a
136 cache line boundary, then the entire data cache line containing Address +
137 Length -1 is written back. This function may choose to write back the entire
138 data cache if that is more efficient than writing back the specified range.
139 If Length is 0, then no data cache lines are written back. This function may
140 also invalidate all the data cache lines in the specified range of the cache
141 coherency domain of the calling CPU. Address is returned.
143 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
145 @param Address The base address of the data cache lines to write back. If
146 the CPU is in a physical addressing mode, then Address is a
147 physical address. If the CPU is in a virtual addressing
148 mode, then Address is a virtual address.
149 @param Length The number of bytes to write back from the data cache.
151 @return Address of cache written in main memory.
156 WriteBackDataCacheRange (
162 Invalidates the entire data cache in cache coherency domain of the calling
165 Invalidates the entire data cache in cache coherency domain of the calling
166 CPU. This function must be used with care because dirty cache lines are not
167 written back to system memory. It is typically used for cache diagnostics. If
168 the CPU does not support invalidation of the entire data cache, then a write
169 back and invalidate operation should be performed on the entire data cache.
174 InvalidateDataCache (
179 Invalidates a range of data cache lines in the cache coherency domain of the
182 Invalidates the data cache lines specified by Address and Length. If Address
183 is not aligned on a cache line boundary, then entire data cache line
184 containing Address is invalidated. If Address + Length is not aligned on a
185 cache line boundary, then the entire data cache line containing Address +
186 Length -1 is invalidated. This function must never invalidate any cache lines
187 outside the specified range. If Length is 0, the no data cache lines are
188 invalidated. Address is returned. This function must be used with care
189 because dirty cache lines are not written back to system memory. It is
190 typically used for cache diagnostics. If the CPU does not support
191 invalidation of a data cache range, then a write back and invalidate
192 operation should be performed on the data cache range.
194 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
196 @param Address The base address of the data cache lines to invalidate. If
197 the CPU is in a physical addressing mode, then Address is a
198 physical address. If the CPU is in a virtual addressing mode,
199 then Address is a virtual address.
200 @param Length The number of bytes to invalidate from the data cache.
207 InvalidateDataCacheRange (