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2 Provides services to access PCI Configuration Space using the I/O ports 0xCF8 and 0xCFC.
4 This library is identical to the PCI Library, except the access method for performing PCI
5 configuration cycles must be through I/O ports 0xCF8 and 0xCFC. This library only allows
6 access to PCI Segment #0.
8 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
9 This program and the accompanying materials
10 are licensed and made available under the terms and conditions of the BSD License
11 which accompanies this distribution. The full text of the license may be found at
12 http://opensource.org/licenses/bsd-license.php
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 #ifndef __PCI_CF8_LIB_H__
20 #define __PCI_CF8_LIB_H__
24 Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
25 address that can be passed to the PCI Library functions.
27 Computes an address that is compatible with the PCI Library functions. The
28 unused upper bits of Bus, Device, Function and Register are stripped prior to
29 the generation of the address.
31 @param Bus PCI Bus number. Range 0..255.
32 @param Device PCI Device number. Range 0..31.
33 @param Function PCI Function number. Range 0..7.
34 @param Register PCI Register number. Range 0..255.
36 @return The encode PCI address.
39 #define PCI_CF8_LIB_ADDRESS(Bus,Device,Function,Offset) \
40 (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
43 Registers a PCI device so PCI configuration registers may be accessed after
44 SetVirtualAddressMap().
46 Registers the PCI device specified by Address so all the PCI configuration registers
47 associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
49 If Address > 0x0FFFFFFF, then ASSERT().
50 If the register specified by Address >= 0x100, then ASSERT().
52 @param Address Address that encodes the PCI Bus, Device, Function and
55 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
56 @retval RETURN_UNSUPPORTED An attempt was made to call this function
57 after ExitBootServices().
58 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
59 at runtime could not be mapped.
60 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
61 complete the registration.
66 PciCf8RegisterForRuntimeAccess (
71 Reads an 8-bit PCI configuration register.
73 Reads and returns the 8-bit PCI configuration register specified by Address.
74 This function must guarantee that all PCI read and write operations are
77 If Address > 0x0FFFFFFF, then ASSERT().
78 If the register specified by Address >= 0x100, then ASSERT().
80 @param Address Address that encodes the PCI Bus, Device, Function and
83 @return The read value from the PCI configuration register.
93 Writes an 8-bit PCI configuration register.
95 Writes the 8-bit PCI configuration register specified by Address with the
96 value specified by Value. Value is returned. This function must guarantee
97 that all PCI read and write operations are serialized.
99 If Address > 0x0FFFFFFF, then ASSERT().
100 If the register specified by Address >= 0x100, then ASSERT().
102 @param Address Address that encodes the PCI Bus, Device, Function and
104 @param Value The value to write.
106 @return The value written to the PCI configuration register.
117 Performs a bitwise OR of an 8-bit PCI configuration register with
120 Reads the 8-bit PCI configuration register specified by Address, performs a
121 bitwise OR between the read result and the value specified by
122 OrData, and writes the result to the 8-bit PCI configuration register
123 specified by Address. The value written to the PCI configuration register is
124 returned. This function must guarantee that all PCI read and write operations
127 If Address > 0x0FFFFFFF, then ASSERT().
128 If the register specified by Address >= 0x100, then ASSERT().
130 @param Address Address that encodes the PCI Bus, Device, Function and
132 @param OrData The value to OR with the PCI configuration register.
134 @return The value written back to the PCI configuration register.
145 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
148 Reads the 8-bit PCI configuration register specified by Address, performs a
149 bitwise AND between the read result and the value specified by AndData, and
150 writes the result to the 8-bit PCI configuration register specified by
151 Address. The value written to the PCI configuration register is returned.
152 This function must guarantee that all PCI read and write operations are
155 If Address > 0x0FFFFFFF, then ASSERT().
156 If the register specified by Address >= 0x100, then ASSERT().
158 @param Address Address that encodes the PCI Bus, Device, Function and
160 @param AndData The value to AND with the PCI configuration register.
162 @return The value written back to the PCI configuration register.
173 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
174 value, followed a bitwise OR with another 8-bit value.
176 Reads the 8-bit PCI configuration register specified by Address, performs a
177 bitwise AND between the read result and the value specified by AndData,
178 performs a bitwise OR between the result of the AND operation and
179 the value specified by OrData, and writes the result to the 8-bit PCI
180 configuration register specified by Address. The value written to the PCI
181 configuration register is returned. This function must guarantee that all PCI
182 read and write operations are serialized.
184 If Address > 0x0FFFFFFF, then ASSERT().
185 If the register specified by Address >= 0x100, then ASSERT().
187 @param Address Address that encodes the PCI Bus, Device, Function and
189 @param AndData The value to AND with the PCI configuration register.
190 @param OrData The value to OR with the result of the AND operation.
192 @return The value written back to the PCI configuration register.
204 Reads a bit field of a PCI configuration register.
206 Reads the bit field in an 8-bit PCI configuration register. The bit field is
207 specified by the StartBit and the EndBit. The value of the bit field is
210 If Address > 0x0FFFFFFF, then ASSERT().
211 If the register specified by Address >= 0x100, then ASSERT().
212 If StartBit is greater than 7, then ASSERT().
213 If EndBit is greater than 7, then ASSERT().
214 If EndBit is less than StartBit, then ASSERT().
216 @param Address PCI configuration register to read.
217 @param StartBit The ordinal of the least significant bit in the bit field.
219 @param EndBit The ordinal of the most significant bit in the bit field.
222 @return The value of the bit field read from the PCI configuration register.
227 PciCf8BitFieldRead8 (
234 Writes a bit field to a PCI configuration register.
236 Writes Value to the bit field of the PCI configuration register. The bit
237 field is specified by the StartBit and the EndBit. All other bits in the
238 destination PCI configuration register are preserved. The new value of the
239 8-bit register is returned.
241 If Address > 0x0FFFFFFF, then ASSERT().
242 If the register specified by Address >= 0x100, then ASSERT().
243 If StartBit is greater than 7, then ASSERT().
244 If EndBit is greater than 7, then ASSERT().
245 If EndBit is less than StartBit, then ASSERT().
246 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
248 @param Address PCI configuration register to write.
249 @param StartBit The ordinal of the least significant bit in the bit field.
251 @param EndBit The ordinal of the most significant bit in the bit field.
253 @param Value New value of the bit field.
255 @return The value written back to the PCI configuration register.
260 PciCf8BitFieldWrite8 (
268 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
269 writes the result back to the bit field in the 8-bit port.
271 Reads the 8-bit PCI configuration register specified by Address, performs a
272 bitwise OR between the read result and the value specified by
273 OrData, and writes the result to the 8-bit PCI configuration register
274 specified by Address. The value written to the PCI configuration register is
275 returned. This function must guarantee that all PCI read and write operations
276 are serialized. Extra left bits in OrData are stripped.
278 If Address > 0x0FFFFFFF, then ASSERT().
279 If the register specified by Address >= 0x100, then ASSERT().
280 If StartBit is greater than 7, then ASSERT().
281 If EndBit is greater than 7, then ASSERT().
282 If EndBit is less than StartBit, then ASSERT().
283 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
285 @param Address PCI configuration register to write.
286 @param StartBit The ordinal of the least significant bit in the bit field.
288 @param EndBit The ordinal of the most significant bit in the bit field.
290 @param OrData The value to OR with the PCI configuration register.
292 @return The value written back to the PCI configuration register.
305 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
306 AND, and writes the result back to the bit field in the 8-bit register.
308 Reads the 8-bit PCI configuration register specified by Address, performs a
309 bitwise AND between the read result and the value specified by AndData, and
310 writes the result to the 8-bit PCI configuration register specified by
311 Address. The value written to the PCI configuration register is returned.
312 This function must guarantee that all PCI read and write operations are
313 serialized. Extra left bits in AndData are stripped.
315 If Address > 0x0FFFFFFF, then ASSERT().
316 If the register specified by Address >= 0x100, then ASSERT().
317 If StartBit is greater than 7, then ASSERT().
318 If EndBit is greater than 7, then ASSERT().
319 If EndBit is less than StartBit, then ASSERT().
320 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
322 @param Address PCI configuration register to write.
323 @param StartBit The ordinal of the least significant bit in the bit field.
325 @param EndBit The ordinal of the most significant bit in the bit field.
327 @param AndData The value to AND with the PCI configuration register.
329 @return The value written back to the PCI configuration register.
342 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
343 bitwise OR, and writes the result back to the bit field in the
346 Reads the 8-bit PCI configuration register specified by Address, performs a
347 bitwise AND followed by a bitwise OR between the read result and
348 the value specified by AndData, and writes the result to the 8-bit PCI
349 configuration register specified by Address. The value written to the PCI
350 configuration register is returned. This function must guarantee that all PCI
351 read and write operations are serialized. Extra left bits in both AndData and
354 If Address > 0x0FFFFFFF, then ASSERT().
355 If the register specified by Address >= 0x100, then ASSERT().
356 If StartBit is greater than 7, then ASSERT().
357 If EndBit is greater than 7, then ASSERT().
358 If EndBit is less than StartBit, then ASSERT().
359 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
360 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
362 @param Address PCI configuration register to write.
363 @param StartBit The ordinal of the least significant bit in the bit field.
365 @param EndBit The ordinal of the most significant bit in the bit field.
367 @param AndData The value to AND with the PCI configuration register.
368 @param OrData The value to OR with the result of the AND operation.
370 @return The value written back to the PCI configuration register.
375 PciCf8BitFieldAndThenOr8 (
384 Reads a 16-bit PCI configuration register.
386 Reads and returns the 16-bit PCI configuration register specified by Address.
387 This function must guarantee that all PCI read and write operations are
390 If Address > 0x0FFFFFFF, then ASSERT().
391 If Address is not aligned on a 16-bit boundary, then ASSERT().
392 If the register specified by Address >= 0x100, then ASSERT().
394 @param Address Address that encodes the PCI Bus, Device, Function and
397 @return The read value from the PCI configuration register.
407 Writes a 16-bit PCI configuration register.
409 Writes the 16-bit PCI configuration register specified by Address with the
410 value specified by Value. Value is returned. This function must guarantee
411 that all PCI read and write operations are serialized.
413 If Address > 0x0FFFFFFF, then ASSERT().
414 If Address is not aligned on a 16-bit boundary, then ASSERT().
415 If the register specified by Address >= 0x100, then ASSERT().
417 @param Address Address that encodes the PCI Bus, Device, Function and
419 @param Value The value to write.
421 @return The value written to the PCI configuration register.
432 Performs a bitwise OR of a 16-bit PCI configuration register with
435 Reads the 16-bit PCI configuration register specified by Address, performs a
436 bitwise OR between the read result and the value specified by
437 OrData, and writes the result to the 16-bit PCI configuration register
438 specified by Address. The value written to the PCI configuration register is
439 returned. This function must guarantee that all PCI read and write operations
442 If Address > 0x0FFFFFFF, then ASSERT().
443 If Address is not aligned on a 16-bit boundary, then ASSERT().
444 If the register specified by Address >= 0x100, then ASSERT().
446 @param Address Address that encodes the PCI Bus, Device, Function and
448 @param OrData The value to OR with the PCI configuration register.
450 @return The value written back to the PCI configuration register.
461 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
464 Reads the 16-bit PCI configuration register specified by Address, performs a
465 bitwise AND between the read result and the value specified by AndData, and
466 writes the result to the 16-bit PCI configuration register specified by
467 Address. The value written to the PCI configuration register is returned.
468 This function must guarantee that all PCI read and write operations are
471 If Address > 0x0FFFFFFF, then ASSERT().
472 If Address is not aligned on a 16-bit boundary, then ASSERT().
473 If the register specified by Address >= 0x100, then ASSERT().
475 @param Address Address that encodes the PCI Bus, Device, Function and
477 @param AndData The value to AND with the PCI configuration register.
479 @return The value written back to the PCI configuration register.
490 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
491 value, followed a bitwise OR with another 16-bit value.
493 Reads the 16-bit PCI configuration register specified by Address, performs a
494 bitwise AND between the read result and the value specified by AndData,
495 performs a bitwise OR between the result of the AND operation and
496 the value specified by OrData, and writes the result to the 16-bit PCI
497 configuration register specified by Address. The value written to the PCI
498 configuration register is returned. This function must guarantee that all PCI
499 read and write operations are serialized.
501 If Address > 0x0FFFFFFF, then ASSERT().
502 If Address is not aligned on a 16-bit boundary, then ASSERT().
503 If the register specified by Address >= 0x100, then ASSERT().
505 @param Address Address that encodes the PCI Bus, Device, Function and
507 @param AndData The value to AND with the PCI configuration register.
508 @param OrData The value to OR with the result of the AND operation.
510 @return The value written back to the PCI configuration register.
522 Reads a bit field of a PCI configuration register.
524 Reads the bit field in a 16-bit PCI configuration register. The bit field is
525 specified by the StartBit and the EndBit. The value of the bit field is
528 If Address > 0x0FFFFFFF, then ASSERT().
529 If Address is not aligned on a 16-bit boundary, then ASSERT().
530 If the register specified by Address >= 0x100, then ASSERT().
531 If StartBit is greater than 15, then ASSERT().
532 If EndBit is greater than 15, then ASSERT().
533 If EndBit is less than StartBit, then ASSERT().
535 @param Address PCI configuration register to read.
536 @param StartBit The ordinal of the least significant bit in the bit field.
538 @param EndBit The ordinal of the most significant bit in the bit field.
541 @return The value of the bit field read from the PCI configuration register.
546 PciCf8BitFieldRead16 (
553 Writes a bit field to a PCI configuration register.
555 Writes Value to the bit field of the PCI configuration register. The bit
556 field is specified by the StartBit and the EndBit. All other bits in the
557 destination PCI configuration register are preserved. The new value of the
558 16-bit register is returned.
560 If Address > 0x0FFFFFFF, then ASSERT().
561 If Address is not aligned on a 16-bit boundary, then ASSERT().
562 If the register specified by Address >= 0x100, then ASSERT().
563 If StartBit is greater than 15, then ASSERT().
564 If EndBit is greater than 15, then ASSERT().
565 If EndBit is less than StartBit, then ASSERT().
566 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
568 @param Address PCI configuration register to write.
569 @param StartBit The ordinal of the least significant bit in the bit field.
571 @param EndBit The ordinal of the most significant bit in the bit field.
573 @param Value New value of the bit field.
575 @return The value written back to the PCI configuration register.
580 PciCf8BitFieldWrite16 (
588 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
589 writes the result back to the bit field in the 16-bit port.
591 Reads the 16-bit PCI configuration register specified by Address, performs a
592 bitwise OR between the read result and the value specified by
593 OrData, and writes the result to the 16-bit PCI configuration register
594 specified by Address. The value written to the PCI configuration register is
595 returned. This function must guarantee that all PCI read and write operations
596 are serialized. Extra left bits in OrData are stripped.
598 If Address > 0x0FFFFFFF, then ASSERT().
599 If Address is not aligned on a 16-bit boundary, then ASSERT().
600 If the register specified by Address >= 0x100, then ASSERT().
601 If StartBit is greater than 15, then ASSERT().
602 If EndBit is greater than 15, then ASSERT().
603 If EndBit is less than StartBit, then ASSERT().
604 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
606 @param Address PCI configuration register to write.
607 @param StartBit The ordinal of the least significant bit in the bit field.
609 @param EndBit The ordinal of the most significant bit in the bit field.
611 @param OrData The value to OR with the PCI configuration register.
613 @return The value written back to the PCI configuration register.
626 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
627 AND, and writes the result back to the bit field in the 16-bit register.
629 Reads the 16-bit PCI configuration register specified by Address, performs a
630 bitwise AND between the read result and the value specified by AndData, and
631 writes the result to the 16-bit PCI configuration register specified by
632 Address. The value written to the PCI configuration register is returned.
633 This function must guarantee that all PCI read and write operations are
634 serialized. Extra left bits in AndData are stripped.
636 If Address > 0x0FFFFFFF, then ASSERT().
637 If Address is not aligned on a 16-bit boundary, then ASSERT().
638 If the register specified by Address >= 0x100, then ASSERT().
639 If StartBit is greater than 15, then ASSERT().
640 If EndBit is greater than 15, then ASSERT().
641 If EndBit is less than StartBit, then ASSERT().
642 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
644 @param Address PCI configuration register to write.
645 @param StartBit The ordinal of the least significant bit in the bit field.
647 @param EndBit The ordinal of the most significant bit in the bit field.
649 @param AndData The value to AND with the PCI configuration register.
651 @return The value written back to the PCI configuration register.
656 PciCf8BitFieldAnd16 (
664 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
665 bitwise OR, and writes the result back to the bit field in the
668 Reads the 16-bit PCI configuration register specified by Address, performs a
669 bitwise AND followed by a bitwise OR between the read result and
670 the value specified by AndData, and writes the result to the 16-bit PCI
671 configuration register specified by Address. The value written to the PCI
672 configuration register is returned. This function must guarantee that all PCI
673 read and write operations are serialized. Extra left bits in both AndData and
676 If Address > 0x0FFFFFFF, then ASSERT().
677 If Address is not aligned on a 16-bit boundary, then ASSERT().
678 If the register specified by Address >= 0x100, then ASSERT().
679 If StartBit is greater than 15, then ASSERT().
680 If EndBit is greater than 15, then ASSERT().
681 If EndBit is less than StartBit, then ASSERT().
682 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
683 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
685 @param Address PCI configuration register to write.
686 @param StartBit The ordinal of the least significant bit in the bit field.
688 @param EndBit The ordinal of the most significant bit in the bit field.
690 @param AndData The value to AND with the PCI configuration register.
691 @param OrData The value to OR with the result of the AND operation.
693 @return The value written back to the PCI configuration register.
698 PciCf8BitFieldAndThenOr16 (
707 Reads a 32-bit PCI configuration register.
709 Reads and returns the 32-bit PCI configuration register specified by Address.
710 This function must guarantee that all PCI read and write operations are
713 If Address > 0x0FFFFFFF, then ASSERT().
714 If Address is not aligned on a 32-bit boundary, then ASSERT().
715 If the register specified by Address >= 0x100, then ASSERT().
717 @param Address Address that encodes the PCI Bus, Device, Function and
720 @return The read value from the PCI configuration register.
730 Writes a 32-bit PCI configuration register.
732 Writes the 32-bit PCI configuration register specified by Address with the
733 value specified by Value. Value is returned. This function must guarantee
734 that all PCI read and write operations are serialized.
736 If Address > 0x0FFFFFFF, then ASSERT().
737 If Address is not aligned on a 32-bit boundary, then ASSERT().
738 If the register specified by Address >= 0x100, then ASSERT().
740 @param Address Address that encodes the PCI Bus, Device, Function and
742 @param Value The value to write.
744 @return The value written to the PCI configuration register.
755 Performs a bitwise OR of a 32-bit PCI configuration register with
758 Reads the 32-bit PCI configuration register specified by Address, performs a
759 bitwise OR between the read result and the value specified by
760 OrData, and writes the result to the 32-bit PCI configuration register
761 specified by Address. The value written to the PCI configuration register is
762 returned. This function must guarantee that all PCI read and write operations
765 If Address > 0x0FFFFFFF, then ASSERT().
766 If Address is not aligned on a 32-bit boundary, then ASSERT().
767 If the register specified by Address >= 0x100, then ASSERT().
769 @param Address Address that encodes the PCI Bus, Device, Function and
771 @param OrData The value to OR with the PCI configuration register.
773 @return The value written back to the PCI configuration register.
784 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
787 Reads the 32-bit PCI configuration register specified by Address, performs a
788 bitwise AND between the read result and the value specified by AndData, and
789 writes the result to the 32-bit PCI configuration register specified by
790 Address. The value written to the PCI configuration register is returned.
791 This function must guarantee that all PCI read and write operations are
794 If Address > 0x0FFFFFFF, then ASSERT().
795 If Address is not aligned on a 32-bit boundary, then ASSERT().
796 If the register specified by Address >= 0x100, then ASSERT().
798 @param Address Address that encodes the PCI Bus, Device, Function and
800 @param AndData The value to AND with the PCI configuration register.
802 @return The value written back to the PCI configuration register.
813 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
814 value, followed a bitwise OR with another 32-bit value.
816 Reads the 32-bit PCI configuration register specified by Address, performs a
817 bitwise AND between the read result and the value specified by AndData,
818 performs a bitwise OR between the result of the AND operation and
819 the value specified by OrData, and writes the result to the 32-bit PCI
820 configuration register specified by Address. The value written to the PCI
821 configuration register is returned. This function must guarantee that all PCI
822 read and write operations are serialized.
824 If Address > 0x0FFFFFFF, then ASSERT().
825 If Address is not aligned on a 32-bit boundary, then ASSERT().
826 If the register specified by Address >= 0x100, then ASSERT().
828 @param Address Address that encodes the PCI Bus, Device, Function and
830 @param AndData The value to AND with the PCI configuration register.
831 @param OrData The value to OR with the result of the AND operation.
833 @return The value written back to the PCI configuration register.
845 Reads a bit field of a PCI configuration register.
847 Reads the bit field in a 32-bit PCI configuration register. The bit field is
848 specified by the StartBit and the EndBit. The value of the bit field is
851 If Address > 0x0FFFFFFF, then ASSERT().
852 If Address is not aligned on a 32-bit boundary, then ASSERT().
853 If the register specified by Address >= 0x100, then ASSERT().
854 If StartBit is greater than 31, then ASSERT().
855 If EndBit is greater than 31, then ASSERT().
856 If EndBit is less than StartBit, then ASSERT().
858 @param Address PCI configuration register to read.
859 @param StartBit The ordinal of the least significant bit in the bit field.
861 @param EndBit The ordinal of the most significant bit in the bit field.
864 @return The value of the bit field read from the PCI configuration register.
869 PciCf8BitFieldRead32 (
876 Writes a bit field to a PCI configuration register.
878 Writes Value to the bit field of the PCI configuration register. The bit
879 field is specified by the StartBit and the EndBit. All other bits in the
880 destination PCI configuration register are preserved. The new value of the
881 32-bit register is returned.
883 If Address > 0x0FFFFFFF, then ASSERT().
884 If Address is not aligned on a 32-bit boundary, then ASSERT().
885 If the register specified by Address >= 0x100, then ASSERT().
886 If StartBit is greater than 31, then ASSERT().
887 If EndBit is greater than 31, then ASSERT().
888 If EndBit is less than StartBit, then ASSERT().
889 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
891 @param Address PCI configuration register to write.
892 @param StartBit The ordinal of the least significant bit in the bit field.
894 @param EndBit The ordinal of the most significant bit in the bit field.
896 @param Value New value of the bit field.
898 @return The value written back to the PCI configuration register.
903 PciCf8BitFieldWrite32 (
911 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
912 writes the result back to the bit field in the 32-bit port.
914 Reads the 32-bit PCI configuration register specified by Address, performs a
915 bitwise OR between the read result and the value specified by
916 OrData, and writes the result to the 32-bit PCI configuration register
917 specified by Address. The value written to the PCI configuration register is
918 returned. This function must guarantee that all PCI read and write operations
919 are serialized. Extra left bits in OrData are stripped.
921 If Address > 0x0FFFFFFF, then ASSERT().
922 If Address is not aligned on a 32-bit boundary, then ASSERT().
923 If the register specified by Address >= 0x100, then ASSERT().
924 If StartBit is greater than 31, then ASSERT().
925 If EndBit is greater than 31, then ASSERT().
926 If EndBit is less than StartBit, then ASSERT().
927 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
929 @param Address PCI configuration register to write.
930 @param StartBit The ordinal of the least significant bit in the bit field.
932 @param EndBit The ordinal of the most significant bit in the bit field.
934 @param OrData The value to OR with the PCI configuration register.
936 @return The value written back to the PCI configuration register.
949 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
950 AND, and writes the result back to the bit field in the 32-bit register.
952 Reads the 32-bit PCI configuration register specified by Address, performs a
953 bitwise AND between the read result and the value specified by AndData, and
954 writes the result to the 32-bit PCI configuration register specified by
955 Address. The value written to the PCI configuration register is returned.
956 This function must guarantee that all PCI read and write operations are
957 serialized. Extra left bits in AndData are stripped.
959 If Address > 0x0FFFFFFF, then ASSERT().
960 If Address is not aligned on a 32-bit boundary, then ASSERT().
961 If the register specified by Address >= 0x100, then ASSERT().
962 If StartBit is greater than 31, then ASSERT().
963 If EndBit is greater than 31, then ASSERT().
964 If EndBit is less than StartBit, then ASSERT().
965 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
967 @param Address PCI configuration register to write.
968 @param StartBit The ordinal of the least significant bit in the bit field.
970 @param EndBit The ordinal of the most significant bit in the bit field.
972 @param AndData The value to AND with the PCI configuration register.
974 @return The value written back to the PCI configuration register.
979 PciCf8BitFieldAnd32 (
987 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
988 bitwise OR, and writes the result back to the bit field in the
991 Reads the 32-bit PCI configuration register specified by Address, performs a
992 bitwise AND followed by a bitwise OR between the read result and
993 the value specified by AndData, and writes the result to the 32-bit PCI
994 configuration register specified by Address. The value written to the PCI
995 configuration register is returned. This function must guarantee that all PCI
996 read and write operations are serialized. Extra left bits in both AndData and
999 If Address > 0x0FFFFFFF, then ASSERT().
1000 If Address is not aligned on a 32-bit boundary, then ASSERT().
1001 If the register specified by Address >= 0x100, then ASSERT().
1002 If StartBit is greater than 31, then ASSERT().
1003 If EndBit is greater than 31, then ASSERT().
1004 If EndBit is less than StartBit, then ASSERT().
1005 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1006 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1008 @param Address PCI configuration register to write.
1009 @param StartBit The ordinal of the least significant bit in the bit field.
1011 @param EndBit The ordinal of the most significant bit in the bit field.
1013 @param AndData The value to AND with the PCI configuration register.
1014 @param OrData The value to OR with the result of the AND operation.
1016 @return The value written back to the PCI configuration register.
1021 PciCf8BitFieldAndThenOr32 (
1030 Reads a range of PCI configuration registers into a caller supplied buffer.
1032 Reads the range of PCI configuration registers specified by StartAddress and
1033 Size into the buffer specified by Buffer. This function only allows the PCI
1034 configuration registers from a single PCI function to be read. Size is
1035 returned. When possible 32-bit PCI configuration read cycles are used to read
1036 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1037 and 16-bit PCI configuration read cycles may be used at the beginning and the
1040 If StartAddress > 0x0FFFFFFF, then ASSERT().
1041 If the register specified by StartAddress >= 0x100, then ASSERT().
1042 If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
1043 If Size > 0 and Buffer is NULL, then ASSERT().
1045 @param StartAddress Starting address that encodes the PCI Bus, Device,
1046 Function and Register.
1047 @param Size Size in bytes of the transfer.
1048 @param Buffer Pointer to a buffer receiving the data read.
1050 @return Size read from StartAddress.
1056 IN UINTN StartAddress
,
1062 Copies the data in a caller supplied buffer to a specified range of PCI
1063 configuration space.
1065 Writes the range of PCI configuration registers specified by StartAddress and
1066 Size from the buffer specified by Buffer. This function only allows the PCI
1067 configuration registers from a single PCI function to be written. Size is
1068 returned. When possible 32-bit PCI configuration write cycles are used to
1069 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1070 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1071 and the end of the range.
1073 If StartAddress > 0x0FFFFFFF, then ASSERT().
1074 If the register specified by StartAddress >= 0x100, then ASSERT().
1075 If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
1076 If Size > 0 and Buffer is NULL, then ASSERT().
1078 @param StartAddress Starting address that encodes the PCI Bus, Device,
1079 Function and Register.
1080 @param Size Size in bytes of the transfer.
1081 @param Buffer Pointer to a buffer containing the data to write.
1083 @return Size written to StartAddress.
1089 IN UINTN StartAddress
,