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2 Provides services to access PCI Configuration Space.
4 These functions perform PCI configuration cycles using the default PCI configuration
5 access method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses,
6 or it may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some
7 alternate access method. Modules will typically use the PCI Library for its PCI configuration
8 accesses. However, if a module requires a mix of PCI access methods, the PCI CF8 Library or
9 PCI Express Library may be used in conjunction with the PCI Library. The functionality of
10 these three libraries is identical. The PCI CF8 Library and PCI Express Library simply use
11 explicit access methods.
13 Copyright (c) 2006 - 2009, Intel Corporation<BR>
14 All rights reserved. This program and the accompanying materials
15 are licensed and made available under the terms and conditions of the BSD License
16 which accompanies this distribution. The full text of the license may be found at
17 http://opensource.org/licenses/bsd-license.php
19 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
20 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
28 Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
29 address that can be passed to the PCI Library functions.
31 @param Bus PCI Bus number. Range 0..255.
32 @param Device PCI Device number. Range 0..31.
33 @param Function PCI Function number. Range 0..7.
34 @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095
37 @return The encoded PCI address.
40 #define PCI_LIB_ADDRESS(Bus,Device,Function,Register) \
41 (((Register) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
44 Registers a PCI device so PCI configuration registers may be accessed after
45 SetVirtualAddressMap().
47 Registers the PCI device specified by Address so all the PCI configuration registers
48 associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
50 If Address > 0x0FFFFFFF, then ASSERT().
52 @param Address Address that encodes the PCI Bus, Device, Function and
55 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
56 @retval RETURN_UNSUPPORTED An attempt was made to call this function
57 after ExitBootServices().
58 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
59 at runtime could not be mapped.
60 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
61 complete the registration.
66 PciRegisterForRuntimeAccess (
71 Reads an 8-bit PCI configuration register.
73 Reads and returns the 8-bit PCI configuration register specified by Address.
74 This function must guarantee that all PCI read and write operations are
77 If Address > 0x0FFFFFFF, then ASSERT().
79 @param Address Address that encodes the PCI Bus, Device, Function and
82 @return The read value from the PCI configuration register.
92 Writes an 8-bit PCI configuration register.
94 Writes the 8-bit PCI configuration register specified by Address with the
95 value specified by Value. Value is returned. This function must guarantee
96 that all PCI read and write operations are serialized.
98 If Address > 0x0FFFFFFF, then ASSERT().
100 @param Address Address that encodes the PCI Bus, Device, Function and
102 @param Value The value to write.
104 @return The value written to the PCI configuration register.
115 Performs a bitwise OR of an 8-bit PCI configuration register with
118 Reads the 8-bit PCI configuration register specified by Address, performs a
119 bitwise OR between the read result and the value specified by
120 OrData, and writes the result to the 8-bit PCI configuration register
121 specified by Address. The value written to the PCI configuration register is
122 returned. This function must guarantee that all PCI read and write operations
125 If Address > 0x0FFFFFFF, then ASSERT().
127 @param Address Address that encodes the PCI Bus, Device, Function and
129 @param OrData The value to OR with the PCI configuration register.
131 @return The value written back to the PCI configuration register.
142 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
145 Reads the 8-bit PCI configuration register specified by Address, performs a
146 bitwise AND between the read result and the value specified by AndData, and
147 writes the result to the 8-bit PCI configuration register specified by
148 Address. The value written to the PCI configuration register is returned.
149 This function must guarantee that all PCI read and write operations are
152 If Address > 0x0FFFFFFF, then ASSERT().
154 @param Address Address that encodes the PCI Bus, Device, Function and
156 @param AndData The value to AND with the PCI configuration register.
158 @return The value written back to the PCI configuration register.
169 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
170 value, followed by a bitwise OR with another 8-bit value.
172 Reads the 8-bit PCI configuration register specified by Address, performs a
173 bitwise AND between the read result and the value specified by AndData,
174 performs a bitwise OR between the result of the AND operation and
175 the value specified by OrData, and writes the result to the 8-bit PCI
176 configuration register specified by Address. The value written to the PCI
177 configuration register is returned. This function must guarantee that all PCI
178 read and write operations are serialized.
180 If Address > 0x0FFFFFFF, then ASSERT().
182 @param Address Address that encodes the PCI Bus, Device, Function and
184 @param AndData The value to AND with the PCI configuration register.
185 @param OrData The value to OR with the result of the AND operation.
187 @return The value written back to the PCI configuration register.
199 Reads a bit field of a PCI configuration register.
201 Reads the bit field in an 8-bit PCI configuration register. The bit field is
202 specified by the StartBit and the EndBit. The value of the bit field is
205 If Address > 0x0FFFFFFF, then ASSERT().
206 If StartBit is greater than 7, then ASSERT().
207 If EndBit is greater than 7, then ASSERT().
208 If EndBit is less than StartBit, then ASSERT().
210 @param Address PCI configuration register to read.
211 @param StartBit The ordinal of the least significant bit in the bit field.
213 @param EndBit The ordinal of the most significant bit in the bit field.
216 @return The value of the bit field read from the PCI configuration register.
228 Writes a bit field to a PCI configuration register.
230 Writes Value to the bit field of the PCI configuration register. The bit
231 field is specified by the StartBit and the EndBit. All other bits in the
232 destination PCI configuration register are preserved. The new value of the
233 8-bit register is returned.
235 If Address > 0x0FFFFFFF, then ASSERT().
236 If StartBit is greater than 7, then ASSERT().
237 If EndBit is greater than 7, then ASSERT().
238 If EndBit is less than StartBit, then ASSERT().
240 @param Address PCI configuration register to write.
241 @param StartBit The ordinal of the least significant bit in the bit field.
243 @param EndBit The ordinal of the most significant bit in the bit field.
245 @param Value New value of the bit field.
247 @return The value written back to the PCI configuration register.
260 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
261 writes the result back to the bit field in the 8-bit port.
263 Reads the 8-bit PCI configuration register specified by Address, performs a
264 bitwise OR between the read result and the value specified by
265 OrData, and writes the result to the 8-bit PCI configuration register
266 specified by Address. The value written to the PCI configuration register is
267 returned. This function must guarantee that all PCI read and write operations
268 are serialized. Extra left bits in OrData are stripped.
270 If Address > 0x0FFFFFFF, then ASSERT().
271 If StartBit is greater than 7, then ASSERT().
272 If EndBit is greater than 7, then ASSERT().
273 If EndBit is less than StartBit, then ASSERT().
275 @param Address PCI configuration register to write.
276 @param StartBit The ordinal of the least significant bit in the bit field.
278 @param EndBit The ordinal of the most significant bit in the bit field.
280 @param OrData The value to OR with the PCI configuration register.
282 @return The value written back to the PCI configuration register.
295 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
296 AND, and writes the result back to the bit field in the 8-bit register.
298 Reads the 8-bit PCI configuration register specified by Address, performs a
299 bitwise AND between the read result and the value specified by AndData, and
300 writes the result to the 8-bit PCI configuration register specified by
301 Address. The value written to the PCI configuration register is returned.
302 This function must guarantee that all PCI read and write operations are
303 serialized. Extra left bits in AndData are stripped.
305 If Address > 0x0FFFFFFF, then ASSERT().
306 If StartBit is greater than 7, then ASSERT().
307 If EndBit is greater than 7, then ASSERT().
308 If EndBit is less than StartBit, then ASSERT().
310 @param Address PCI configuration register to write.
311 @param StartBit The ordinal of the least significant bit in the bit field.
313 @param EndBit The ordinal of the most significant bit in the bit field.
315 @param AndData The value to AND with the PCI configuration register.
317 @return The value written back to the PCI configuration register.
330 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
331 bitwise OR, and writes the result back to the bit field in the
334 Reads the 8-bit PCI configuration register specified by Address, performs a
335 bitwise AND followed by a bitwise OR between the read result and
336 the value specified by AndData, and writes the result to the 8-bit PCI
337 configuration register specified by Address. The value written to the PCI
338 configuration register is returned. This function must guarantee that all PCI
339 read and write operations are serialized. Extra left bits in both AndData and
342 If Address > 0x0FFFFFFF, then ASSERT().
343 If StartBit is greater than 7, then ASSERT().
344 If EndBit is greater than 7, then ASSERT().
345 If EndBit is less than StartBit, then ASSERT().
347 @param Address PCI configuration register to write.
348 @param StartBit The ordinal of the least significant bit in the bit field.
350 @param EndBit The ordinal of the most significant bit in the bit field.
352 @param AndData The value to AND with the PCI configuration register.
353 @param OrData The value to OR with the result of the AND operation.
355 @return The value written back to the PCI configuration register.
360 PciBitFieldAndThenOr8 (
369 Reads a 16-bit PCI configuration register.
371 Reads and returns the 16-bit PCI configuration register specified by Address.
372 This function must guarantee that all PCI read and write operations are
375 If Address > 0x0FFFFFFF, then ASSERT().
376 If Address is not aligned on a 16-bit boundary, then ASSERT().
378 @param Address Address that encodes the PCI Bus, Device, Function and
381 @return The read value from the PCI configuration register.
391 Writes a 16-bit PCI configuration register.
393 Writes the 16-bit PCI configuration register specified by Address with the
394 value specified by Value. Value is returned. This function must guarantee
395 that all PCI read and write operations are serialized.
397 If Address > 0x0FFFFFFF, then ASSERT().
398 If Address is not aligned on a 16-bit boundary, then ASSERT().
400 @param Address Address that encodes the PCI Bus, Device, Function and
402 @param Value The value to write.
404 @return The value written to the PCI configuration register.
415 Performs a bitwise OR of a 16-bit PCI configuration register with
418 Reads the 16-bit PCI configuration register specified by Address, performs a
419 bitwise OR between the read result and the value specified by
420 OrData, and writes the result to the 16-bit PCI configuration register
421 specified by Address. The value written to the PCI configuration register is
422 returned. This function must guarantee that all PCI read and write operations
425 If Address > 0x0FFFFFFF, then ASSERT().
426 If Address is not aligned on a 16-bit boundary, then ASSERT().
428 @param Address Address that encodes the PCI Bus, Device, Function and
430 @param OrData The value to OR with the PCI configuration register.
432 @return The value written back to the PCI configuration register.
443 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
446 Reads the 16-bit PCI configuration register specified by Address, performs a
447 bitwise AND between the read result and the value specified by AndData, and
448 writes the result to the 16-bit PCI configuration register specified by
449 Address. The value written to the PCI configuration register is returned.
450 This function must guarantee that all PCI read and write operations are
453 If Address > 0x0FFFFFFF, then ASSERT().
454 If Address is not aligned on a 16-bit boundary, then ASSERT().
456 @param Address Address that encodes the PCI Bus, Device, Function and
458 @param AndData The value to AND with the PCI configuration register.
460 @return The value written back to the PCI configuration register.
471 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
472 value, followed a bitwise OR with another 16-bit value.
474 Reads the 16-bit PCI configuration register specified by Address, performs a
475 bitwise AND between the read result and the value specified by AndData,
476 performs a bitwise OR between the result of the AND operation and
477 the value specified by OrData, and writes the result to the 16-bit PCI
478 configuration register specified by Address. The value written to the PCI
479 configuration register is returned. This function must guarantee that all PCI
480 read and write operations are serialized.
482 If Address > 0x0FFFFFFF, then ASSERT().
483 If Address is not aligned on a 16-bit boundary, then ASSERT().
485 @param Address Address that encodes the PCI Bus, Device, Function and
487 @param AndData The value to AND with the PCI configuration register.
488 @param OrData The value to OR with the result of the AND operation.
490 @return The value written back to the PCI configuration register.
502 Reads a bit field of a PCI configuration register.
504 Reads the bit field in a 16-bit PCI configuration register. The bit field is
505 specified by the StartBit and the EndBit. The value of the bit field is
508 If Address > 0x0FFFFFFF, then ASSERT().
509 If Address is not aligned on a 16-bit boundary, then ASSERT().
510 If StartBit is greater than 15, then ASSERT().
511 If EndBit is greater than 15, then ASSERT().
512 If EndBit is less than StartBit, then ASSERT().
514 @param Address PCI configuration register to read.
515 @param StartBit The ordinal of the least significant bit in the bit field.
517 @param EndBit The ordinal of the most significant bit in the bit field.
520 @return The value of the bit field read from the PCI configuration register.
532 Writes a bit field to a PCI configuration register.
534 Writes Value to the bit field of the PCI configuration register. The bit
535 field is specified by the StartBit and the EndBit. All other bits in the
536 destination PCI configuration register are preserved. The new value of the
537 16-bit register is returned.
539 If Address > 0x0FFFFFFF, then ASSERT().
540 If Address is not aligned on a 16-bit boundary, then ASSERT().
541 If StartBit is greater than 15, then ASSERT().
542 If EndBit is greater than 15, then ASSERT().
543 If EndBit is less than StartBit, then ASSERT().
545 @param Address PCI configuration register to write.
546 @param StartBit The ordinal of the least significant bit in the bit field.
548 @param EndBit The ordinal of the most significant bit in the bit field.
550 @param Value New value of the bit field.
552 @return The value written back to the PCI configuration register.
565 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
566 writes the result back to the bit field in the 16-bit port.
568 Reads the 16-bit PCI configuration register specified by Address, performs a
569 bitwise OR between the read result and the value specified by
570 OrData, and writes the result to the 16-bit PCI configuration register
571 specified by Address. The value written to the PCI configuration register is
572 returned. This function must guarantee that all PCI read and write operations
573 are serialized. Extra left bits in OrData are stripped.
575 If Address > 0x0FFFFFFF, then ASSERT().
576 If Address is not aligned on a 16-bit boundary, then ASSERT().
577 If StartBit is greater than 15, then ASSERT().
578 If EndBit is greater than 15, then ASSERT().
579 If EndBit is less than StartBit, then ASSERT().
581 @param Address PCI configuration register to write.
582 @param StartBit The ordinal of the least significant bit in the bit field.
584 @param EndBit The ordinal of the most significant bit in the bit field.
586 @param OrData The value to OR with the PCI configuration register.
588 @return The value written back to the PCI configuration register.
601 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
602 AND, and writes the result back to the bit field in the 16-bit register.
604 Reads the 16-bit PCI configuration register specified by Address, performs a
605 bitwise AND between the read result and the value specified by AndData, and
606 writes the result to the 16-bit PCI configuration register specified by
607 Address. The value written to the PCI configuration register is returned.
608 This function must guarantee that all PCI read and write operations are
609 serialized. Extra left bits in AndData are stripped.
611 If Address > 0x0FFFFFFF, then ASSERT().
612 If Address is not aligned on a 16-bit boundary, then ASSERT().
613 If StartBit is greater than 15, then ASSERT().
614 If EndBit is greater than 15, then ASSERT().
615 If EndBit is less than StartBit, then ASSERT().
617 @param Address PCI configuration register to write.
618 @param StartBit The ordinal of the least significant bit in the bit field.
620 @param EndBit The ordinal of the most significant bit in the bit field.
622 @param AndData The value to AND with the PCI configuration register.
624 @return The value written back to the PCI configuration register.
637 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
638 bitwise OR, and writes the result back to the bit field in the
641 Reads the 16-bit PCI configuration register specified by Address, performs a
642 bitwise AND followed by a bitwise OR between the read result and
643 the value specified by AndData, and writes the result to the 16-bit PCI
644 configuration register specified by Address. The value written to the PCI
645 configuration register is returned. This function must guarantee that all PCI
646 read and write operations are serialized. Extra left bits in both AndData and
649 If Address > 0x0FFFFFFF, then ASSERT().
650 If Address is not aligned on a 16-bit boundary, then ASSERT().
651 If StartBit is greater than 15, then ASSERT().
652 If EndBit is greater than 15, then ASSERT().
653 If EndBit is less than StartBit, then ASSERT().
655 @param Address PCI configuration register to write.
656 @param StartBit The ordinal of the least significant bit in the bit field.
658 @param EndBit The ordinal of the most significant bit in the bit field.
660 @param AndData The value to AND with the PCI configuration register.
661 @param OrData The value to OR with the result of the AND operation.
663 @return The value written back to the PCI configuration register.
668 PciBitFieldAndThenOr16 (
677 Reads a 32-bit PCI configuration register.
679 Reads and returns the 32-bit PCI configuration register specified by Address.
680 This function must guarantee that all PCI read and write operations are
683 If Address > 0x0FFFFFFF, then ASSERT().
684 If Address is not aligned on a 32-bit boundary, then ASSERT().
686 @param Address Address that encodes the PCI Bus, Device, Function and
689 @return The read value from the PCI configuration register.
699 Writes a 32-bit PCI configuration register.
701 Writes the 32-bit PCI configuration register specified by Address with the
702 value specified by Value. Value is returned. This function must guarantee
703 that all PCI read and write operations are serialized.
705 If Address > 0x0FFFFFFF, then ASSERT().
706 If Address is not aligned on a 32-bit boundary, then ASSERT().
708 @param Address Address that encodes the PCI Bus, Device, Function and
710 @param Value The value to write.
712 @return The value written to the PCI configuration register.
723 Performs a bitwise OR of a 32-bit PCI configuration register with
726 Reads the 32-bit PCI configuration register specified by Address, performs a
727 bitwise OR between the read result and the value specified by
728 OrData, and writes the result to the 32-bit PCI configuration register
729 specified by Address. The value written to the PCI configuration register is
730 returned. This function must guarantee that all PCI read and write operations
733 If Address > 0x0FFFFFFF, then ASSERT().
734 If Address is not aligned on a 32-bit boundary, then ASSERT().
736 @param Address Address that encodes the PCI Bus, Device, Function and
738 @param OrData The value to OR with the PCI configuration register.
740 @return The value written back to the PCI configuration register.
751 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
754 Reads the 32-bit PCI configuration register specified by Address, performs a
755 bitwise AND between the read result and the value specified by AndData, and
756 writes the result to the 32-bit PCI configuration register specified by
757 Address. The value written to the PCI configuration register is returned.
758 This function must guarantee that all PCI read and write operations are
761 If Address > 0x0FFFFFFF, then ASSERT().
762 If Address is not aligned on a 32-bit boundary, then ASSERT().
764 @param Address Address that encodes the PCI Bus, Device, Function and
766 @param AndData The value to AND with the PCI configuration register.
768 @return The value written back to the PCI configuration register.
779 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
780 value, followed a bitwise OR with another 32-bit value.
782 Reads the 32-bit PCI configuration register specified by Address, performs a
783 bitwise AND between the read result and the value specified by AndData,
784 performs a bitwise OR between the result of the AND operation and
785 the value specified by OrData, and writes the result to the 32-bit PCI
786 configuration register specified by Address. The value written to the PCI
787 configuration register is returned. This function must guarantee that all PCI
788 read and write operations are serialized.
790 If Address > 0x0FFFFFFF, then ASSERT().
791 If Address is not aligned on a 32-bit boundary, then ASSERT().
793 @param Address Address that encodes the PCI Bus, Device, Function and
795 @param AndData The value to AND with the PCI configuration register.
796 @param OrData The value to OR with the result of the AND operation.
798 @return The value written back to the PCI configuration register.
810 Reads a bit field of a PCI configuration register.
812 Reads the bit field in a 32-bit PCI configuration register. The bit field is
813 specified by the StartBit and the EndBit. The value of the bit field is
816 If Address > 0x0FFFFFFF, then ASSERT().
817 If Address is not aligned on a 32-bit boundary, then ASSERT().
818 If StartBit is greater than 31, then ASSERT().
819 If EndBit is greater than 31, then ASSERT().
820 If EndBit is less than StartBit, then ASSERT().
822 @param Address PCI configuration register to read.
823 @param StartBit The ordinal of the least significant bit in the bit field.
825 @param EndBit The ordinal of the most significant bit in the bit field.
828 @return The value of the bit field read from the PCI configuration register.
840 Writes a bit field to a PCI configuration register.
842 Writes Value to the bit field of the PCI configuration register. The bit
843 field is specified by the StartBit and the EndBit. All other bits in the
844 destination PCI configuration register are preserved. The new value of the
845 32-bit register is returned.
847 If Address > 0x0FFFFFFF, then ASSERT().
848 If Address is not aligned on a 32-bit boundary, then ASSERT().
849 If StartBit is greater than 31, then ASSERT().
850 If EndBit is greater than 31, then ASSERT().
851 If EndBit is less than StartBit, then ASSERT().
853 @param Address PCI configuration register to write.
854 @param StartBit The ordinal of the least significant bit in the bit field.
856 @param EndBit The ordinal of the most significant bit in the bit field.
858 @param Value New value of the bit field.
860 @return The value written back to the PCI configuration register.
873 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
874 writes the result back to the bit field in the 32-bit port.
876 Reads the 32-bit PCI configuration register specified by Address, performs a
877 bitwise OR between the read result and the value specified by
878 OrData, and writes the result to the 32-bit PCI configuration register
879 specified by Address. The value written to the PCI configuration register is
880 returned. This function must guarantee that all PCI read and write operations
881 are serialized. Extra left bits in OrData are stripped.
883 If Address > 0x0FFFFFFF, then ASSERT().
884 If Address is not aligned on a 32-bit boundary, then ASSERT().
885 If StartBit is greater than 31, then ASSERT().
886 If EndBit is greater than 31, then ASSERT().
887 If EndBit is less than StartBit, then ASSERT().
889 @param Address PCI configuration register to write.
890 @param StartBit The ordinal of the least significant bit in the bit field.
892 @param EndBit The ordinal of the most significant bit in the bit field.
894 @param OrData The value to OR with the PCI configuration register.
896 @return The value written back to the PCI configuration register.
909 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
910 AND, and writes the result back to the bit field in the 32-bit register.
912 Reads the 32-bit PCI configuration register specified by Address, performs a
913 bitwise AND between the read result and the value specified by AndData, and
914 writes the result to the 32-bit PCI configuration register specified by
915 Address. The value written to the PCI configuration register is returned.
916 This function must guarantee that all PCI read and write operations are
917 serialized. Extra left bits in AndData are stripped.
919 If Address > 0x0FFFFFFF, then ASSERT().
920 If Address is not aligned on a 32-bit boundary, then ASSERT().
921 If StartBit is greater than 31, then ASSERT().
922 If EndBit is greater than 31, then ASSERT().
923 If EndBit is less than StartBit, then ASSERT().
925 @param Address PCI configuration register to write.
926 @param StartBit The ordinal of the least significant bit in the bit field.
928 @param EndBit The ordinal of the most significant bit in the bit field.
930 @param AndData The value to AND with the PCI configuration register.
932 @return The value written back to the PCI configuration register.
945 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
946 bitwise OR, and writes the result back to the bit field in the
949 Reads the 32-bit PCI configuration register specified by Address, performs a
950 bitwise AND followed by a bitwise OR between the read result and
951 the value specified by AndData, and writes the result to the 32-bit PCI
952 configuration register specified by Address. The value written to the PCI
953 configuration register is returned. This function must guarantee that all PCI
954 read and write operations are serialized. Extra left bits in both AndData and
957 If Address > 0x0FFFFFFF, then ASSERT().
958 If Address is not aligned on a 32-bit boundary, then ASSERT().
959 If StartBit is greater than 31, then ASSERT().
960 If EndBit is greater than 31, then ASSERT().
961 If EndBit is less than StartBit, then ASSERT().
963 @param Address PCI configuration register to write.
964 @param StartBit The ordinal of the least significant bit in the bit field.
966 @param EndBit The ordinal of the most significant bit in the bit field.
968 @param AndData The value to AND with the PCI configuration register.
969 @param OrData The value to OR with the result of the AND operation.
971 @return The value written back to the PCI configuration register.
976 PciBitFieldAndThenOr32 (
985 Reads a range of PCI configuration registers into a caller supplied buffer.
987 Reads the range of PCI configuration registers specified by StartAddress and
988 Size into the buffer specified by Buffer. This function only allows the PCI
989 configuration registers from a single PCI function to be read. Size is
990 returned. When possible 32-bit PCI configuration read cycles are used to read
991 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
992 and 16-bit PCI configuration read cycles may be used at the beginning and the
995 If StartAddress > 0x0FFFFFFF, then ASSERT().
996 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
997 If Size > 0 and Buffer is NULL, then ASSERT().
999 @param StartAddress Starting address that encodes the PCI Bus, Device,
1000 Function and Register.
1001 @param Size Size in bytes of the transfer.
1002 @param Buffer Pointer to a buffer receiving the data read.
1010 IN UINTN StartAddress
,
1016 Copies the data in a caller supplied buffer to a specified range of PCI
1017 configuration space.
1019 Writes the range of PCI configuration registers specified by StartAddress and
1020 Size from the buffer specified by Buffer. This function only allows the PCI
1021 configuration registers from a single PCI function to be written. Size is
1022 returned. When possible 32-bit PCI configuration write cycles are used to
1023 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1024 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1025 and the end of the range.
1027 If StartAddress > 0x0FFFFFFF, then ASSERT().
1028 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1029 If Size > 0 and Buffer is NULL, then ASSERT().
1031 @param StartAddress Starting address that encodes the PCI Bus, Device,
1032 Function and Register.
1033 @param Size Size in bytes of the transfer.
1034 @param Buffer Pointer to a buffer containing the data to write.
1036 @return Size written to StartAddress.
1042 IN UINTN StartAddress
,