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git.proxmox.com Git - mirror_edk2.git/blob - MdePkg/Include/Library/S3PciLib.h
2 The PCI configuration Library Services that carry out PCI configuration and enable
3 the PCI operations to be replayed during an S3 resume. This library class
4 maps directly on top of the PciLib class.
6 Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
8 This program and the accompanying materials
9 are licensed and made available under the terms and conditions
10 of the BSD License which accompanies this distribution. The
11 full text of the license may be found at
12 http://opensource.org/licenses/bsd-license.php
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 #ifndef __S3_PCI_LIB_H__
20 #define __S3_PCI_LIB_H__
23 Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
24 address that can be passed to the S3 PCI Library functions.
26 @param Bus The PCI Bus number. Range 0..255.
27 @param Device The PCI Device number. Range 0..31.
28 @param Function The PCI Function number. Range 0..7.
29 @param Register The PCI Register number. Range 0..255 for PCI. Range 0..4095
32 @return The encoded PCI address.
35 #define S3_PCI_LIB_ADDRESS(Bus,Device,Function,Register) \
36 (((Register) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
40 Reads and returns the 8-bit PCI configuration register specified by Address,
41 and saves the value in the S3 script to be replayed on S3 resume.
42 This function must guarantee that all PCI read and write operations are
45 If Address > 0x0FFFFFFF, then ASSERT().
47 @param[in] Address The address that encodes the PCI Bus, Device, Function and
50 @return The value read from the PCI configuration register.
60 Writes an 8-bit PCI configuration register, and saves the value in the S3
61 script to be replayed on S3 resume.
63 Writes the 8-bit PCI configuration register specified by Address with the
64 value specified by Value. Value is returned. This function must guarantee
65 that all PCI read and write operations are serialized.
67 If Address > 0x0FFFFFFF, then ASSERT().
69 @param[in] Address The address that encodes the PCI Bus, Device, Function and
71 @param[in] Value The value to write.
73 @return The value written to the PCI configuration register.
84 Performs a bitwise OR of an 8-bit PCI configuration register with
85 an 8-bit value, and saves the value in the S3 script to be replayed on S3 resume.
87 Reads the 8-bit PCI configuration register specified by Address, performs a
88 bitwise OR between the read result and the value specified by
89 OrData, and writes the result to the 8-bit PCI configuration register
90 specified by Address. The value written to the PCI configuration register is
91 returned. This function must guarantee that all PCI read and write operations
94 If Address > 0x0FFFFFFF, then ASSERT().
96 @param[in] Address The address that encodes the PCI Bus, Device, Function and
98 @param[in] OrData The value to OR with the PCI configuration register.
100 @return The value written back to the PCI configuration register.
111 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
112 value, and saves the value in the S3 script to be replayed on S3 resume.
114 Reads the 8-bit PCI configuration register specified by Address, performs a
115 bitwise AND between the read result and the value specified by AndData, and
116 writes the result to the 8-bit PCI configuration register specified by
117 Address. The value written to the PCI configuration register is returned.
118 This function must guarantee that all PCI read and write operations are
121 If Address > 0x0FFFFFFF, then ASSERT().
123 @param[in] Address The address that encodes the PCI Bus, Device, Function and
125 @param[in] AndData The value to AND with the PCI configuration register.
127 @return The value written back to the PCI configuration register.
138 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
139 value, followed a bitwise OR with another 8-bit value, and saves
140 the value in the S3 script to be replayed on S3 resume.
142 Reads the 8-bit PCI configuration register specified by Address, performs a
143 bitwise AND between the read result and the value specified by AndData,
144 performs a bitwise OR between the result of the AND operation and
145 the value specified by OrData, and writes the result to the 8-bit PCI
146 configuration register specified by Address. The value written to the PCI
147 configuration register is returned. This function must guarantee that all PCI
148 read and write operations are serialized.
150 If Address > 0x0FFFFFFF, then ASSERT().
152 @param[in] Address The address that encodes the PCI Bus, Device, Function and
154 @param[in] AndData The value to AND with the PCI configuration register.
155 @param[in] OrData The value to OR with the result of the AND operation.
157 @return The value written back to the PCI configuration register.
169 Reads a bit field of a PCI configuration register, and saves the value in
170 the S3 script to be replayed on S3 resume.
172 Reads the bit field in an 8-bit PCI configuration register. The bit field is
173 specified by the StartBit and the EndBit. The value of the bit field is
176 If Address > 0x0FFFFFFF, then ASSERT().
177 If StartBit is greater than 7, then ASSERT().
178 If EndBit is greater than 7, then ASSERT().
179 If EndBit is less than StartBit, then ASSERT().
181 @param[in] Address The PCI configuration register to read.
182 @param[in] StartBit The ordinal of the least significant bit in the bit field.
184 @param[in] EndBit The ordinal of the most significant bit in the bit field.
187 @return The value of the bit field read from the PCI configuration register.
199 Writes a bit field to a PCI configuration register, and saves the value in
200 the S3 script to be replayed on S3 resume.
202 Writes Value to the bit field of the PCI configuration register. The bit
203 field is specified by the StartBit and the EndBit. All other bits in the
204 destination PCI configuration register are preserved. The new value of the
205 8-bit register is returned.
207 If Address > 0x0FFFFFFF, then ASSERT().
208 If StartBit is greater than 7, then ASSERT().
209 If EndBit is greater than 7, then ASSERT().
210 If EndBit is less than StartBit, then ASSERT().
211 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
213 @param[in] Address The PCI configuration register to write.
214 @param[in] StartBit The ordinal of the least significant bit in the bit field.
216 @param[in] EndBit The ordinal of the most significant bit in the bit field.
218 @param[in] Value New value of the bit field.
220 @return The value written back to the PCI configuration register.
225 S3PciBitFieldWrite8 (
233 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
234 writes the result back to the bit field in the 8-bit port, and saves the value
235 in the S3 script to be replayed on S3 resume.
237 Reads the 8-bit PCI configuration register specified by Address, performs a
238 bitwise OR between the read result and the value specified by
239 OrData, and writes the result to the 8-bit PCI configuration register
240 specified by Address. The value written to the PCI configuration register is
241 returned. This function must guarantee that all PCI read and write operations
242 are serialized. Extra left bits in OrData are stripped.
244 If Address > 0x0FFFFFFF, then ASSERT().
245 If StartBit is greater than 7, then ASSERT().
246 If EndBit is greater than 7, then ASSERT().
247 If EndBit is less than StartBit, then ASSERT().
248 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
250 @param[in] Address The PCI configuration register to write.
251 @param[in] StartBit The ordinal of the least significant bit in the bit field.
253 @param[in] EndBit The ordinal of the most significant bit in the bit field.
255 @param[in] OrData The value to OR with the PCI configuration register.
257 @return The value written back to the PCI configuration register.
270 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
271 AND, and writes the result back to the bit field in the 8-bit register and
272 saves the value in the S3 script to be replayed on S3 resume.
274 Reads the 8-bit PCI configuration register specified by Address, performs a
275 bitwise AND between the read result and the value specified by AndData, and
276 writes the result to the 8-bit PCI configuration register specified by
277 Address. The value written to the PCI configuration register is returned.
278 This function must guarantee that all PCI read and write operations are
279 serialized. Extra left bits in AndData are stripped.
281 If Address > 0x0FFFFFFF, then ASSERT().
282 If StartBit is greater than 7, then ASSERT().
283 If EndBit is greater than 7, then ASSERT().
284 If EndBit is less than StartBit, then ASSERT().
285 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
287 @param[in] Address The PCI configuration register to write.
288 @param[in] StartBit The ordinal of the least significant bit in the bit field.
290 @param[in] EndBit The ordinal of the most significant bit in the bit field.
292 @param[in] AndData The value to AND with the PCI configuration register.
294 @return The value written back to the PCI configuration register.
307 Reads a bit field in an 8-bit Address, performs a bitwise AND followed by a
308 bitwise OR, and writes the result back to the bit field in the
309 8-bit port, and saves the value in the S3 script to be replayed on S3 resume.
311 Reads the 8-bit PCI configuration register specified by Address, performs a
312 bitwise AND followed by a bitwise OR between the read result and
313 the value specified by AndData, and writes the result to the 8-bit PCI
314 configuration register specified by Address. The value written to the PCI
315 configuration register is returned. This function must guarantee that all PCI
316 read and write operations are serialized. Extra left bits in both AndData and
319 If Address > 0x0FFFFFFF, then ASSERT().
320 If StartBit is greater than 7, then ASSERT().
321 If EndBit is greater than 7, then ASSERT().
322 If EndBit is less than StartBit, then ASSERT().
323 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
324 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
326 @param[in] Address The PCI configuration register to write.
327 @param[in] StartBit The ordinal of the least significant bit in the bit field.
329 @param[in] EndBit The ordinal of the most significant bit in the bit field.
331 @param[in] AndData The value to AND with the PCI configuration register.
332 @param[in] OrData The value to OR with the result of the AND operation.
334 @return The value written back to the PCI configuration register.
339 S3PciBitFieldAndThenOr8 (
348 Reads a 16-bit PCI configuration register, and saves the value in the S3
349 script to be replayed on S3 resume.
351 Reads and returns the 16-bit PCI configuration register specified by Address.
352 This function must guarantee that all PCI read and write operations are
355 If Address > 0x0FFFFFFF, then ASSERT().
356 If Address is not aligned on a 16-bit boundary, then ASSERT().
358 @param[in] Address The address that encodes the PCI Bus, Device, Function and
361 @return The read value from the PCI configuration register.
371 Writes a 16-bit PCI configuration register, and saves the value in the S3
372 script to be replayed on S3 resume.
374 Writes the 16-bit PCI configuration register specified by Address with the
375 value specified by Value. Value is returned. This function must guarantee
376 that all PCI read and write operations are serialized.
378 If Address > 0x0FFFFFFF, then ASSERT().
379 If Address is not aligned on a 16-bit boundary, then ASSERT().
381 @param[in] Address The address that encodes the PCI Bus, Device, Function and
383 @param[in] Value The value to write.
385 @return The value written to the PCI configuration register.
396 Performs a bitwise OR of a 16-bit PCI configuration register with
397 a 16-bit value, and saves the value in the S3 script to be replayed on S3 resume.
399 Reads the 16-bit PCI configuration register specified by Address, performs a
400 bitwise OR between the read result and the value specified by
401 OrData, and writes the result to the 16-bit PCI configuration register
402 specified by Address. The value written to the PCI configuration register is
403 returned. This function must guarantee that all PCI read and write operations
406 If Address > 0x0FFFFFFF, then ASSERT().
407 If Address is not aligned on a 16-bit boundary, then ASSERT().
409 @param[in] Address The address that encodes the PCI Bus, Device, Function and
411 @param[in] OrData The value to OR with the PCI configuration register.
413 @return The value written back to the PCI configuration register.
424 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
425 value, and saves the value in the S3 script to be replayed on S3 resume.
427 Reads the 16-bit PCI configuration register specified by Address, performs a
428 bitwise AND between the read result and the value specified by AndData, and
429 writes the result to the 16-bit PCI configuration register specified by
430 Address. The value written to the PCI configuration register is returned.
431 This function must guarantee that all PCI read and write operations are
434 If Address > 0x0FFFFFFF, then ASSERT().
435 If Address is not aligned on a 16-bit boundary, then ASSERT().
437 @param[in] Address The address that encodes the PCI Bus, Device, Function and
439 @param[in] AndData The value to AND with the PCI configuration register.
441 @return The value written back to the PCI configuration register.
452 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
453 value, followed a bitwise OR with another 16-bit value, and saves
454 the value in the S3 script to be replayed on S3 resume.
456 Reads the 16-bit PCI configuration register specified by Address, performs a
457 bitwise AND between the read result and the value specified by AndData,
458 performs a bitwise OR between the result of the AND operation and
459 the value specified by OrData, and writes the result to the 16-bit PCI
460 configuration register specified by Address. The value written to the PCI
461 configuration register is returned. This function must guarantee that all PCI
462 read and write operations are serialized.
464 If Address > 0x0FFFFFFF, then ASSERT().
465 If Address is not aligned on a 16-bit boundary, then ASSERT().
467 @param[in] Address The address that encodes the PCI Bus, Device, Function and
469 @param[in] AndData The value to AND with the PCI configuration register.
470 @param[in] OrData The value to OR with the result of the AND operation.
472 @return The value written back to the PCI configuration register.
484 Reads a bit field of a PCI configuration register, and saves the value in
485 the S3 script to be replayed on S3 resume.
487 Reads the bit field in a 16-bit PCI configuration register. The bit field is
488 specified by the StartBit and the EndBit. The value of the bit field is
491 If Address > 0x0FFFFFFF, then ASSERT().
492 If Address is not aligned on a 16-bit boundary, then ASSERT().
493 If StartBit is greater than 15, then ASSERT().
494 If EndBit is greater than 15, then ASSERT().
495 If EndBit is less than StartBit, then ASSERT().
497 @param[in] Address The PCI configuration register to read.
498 @param[in] StartBit The ordinal of the least significant bit in the bit field.
500 @param[in] EndBit The ordinal of the most significant bit in the bit field.
503 @return The value of the bit field read from the PCI configuration register.
508 S3PciBitFieldRead16 (
515 Writes a bit field to a PCI configuration register, and saves the value in
516 the S3 script to be replayed on S3 resume.
518 Writes Value to the bit field of the PCI configuration register. The bit
519 field is specified by the StartBit and the EndBit. All other bits in the
520 destination PCI configuration register are preserved. The new value of the
521 16-bit register is returned.
523 If Address > 0x0FFFFFFF, then ASSERT().
524 If Address is not aligned on a 16-bit boundary, then ASSERT().
525 If StartBit is greater than 15, then ASSERT().
526 If EndBit is greater than 15, then ASSERT().
527 If EndBit is less than StartBit, then ASSERT().
528 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
530 @param[in] Address The PCI configuration register to write.
531 @param[in] StartBit The ordinal of the least significant bit in the bit field.
533 @param[in] EndBit The ordinal of the most significant bit in the bit field.
535 @param[in] Value New value of the bit field.
537 @return The value written back to the PCI configuration register.
542 S3PciBitFieldWrite16 (
550 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
551 writes the result back to the bit field in the 16-bit port, and saves the value
552 in the S3 script to be replayed on S3 resume.
554 Reads the 16-bit PCI configuration register specified by Address, performs a
555 bitwise OR between the read result and the value specified by
556 OrData, and writes the result to the 16-bit PCI configuration register
557 specified by Address. The value written to the PCI configuration register is
558 returned. This function must guarantee that all PCI read and write operations
559 are serialized. Extra left bits in OrData are stripped.
561 If Address > 0x0FFFFFFF, then ASSERT().
562 If Address is not aligned on a 16-bit boundary, then ASSERT().
563 If StartBit is greater than 15, then ASSERT().
564 If EndBit is greater than 15, then ASSERT().
565 If EndBit is less than StartBit, then ASSERT().
566 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
568 @param[in] Address The PCI configuration register to write.
569 @param[in] StartBit The ordinal of the least significant bit in the bit field.
571 @param[in] EndBit The ordinal of the most significant bit in the bit field.
573 @param[in] OrData The value to OR with the PCI configuration register.
575 @return The value written back to the PCI configuration register.
588 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
589 AND, and writes the result back to the bit field in the 16-bit register and
590 saves the value in the S3 script to be replayed on S3 resume.
592 Reads the 16-bit PCI configuration register specified by Address, performs a
593 bitwise AND between the read result and the value specified by AndData, and
594 writes the result to the 16-bit PCI configuration register specified by
595 Address. The value written to the PCI configuration register is returned.
596 This function must guarantee that all PCI read and write operations are
597 serialized. Extra left bits in AndData are stripped.
599 If Address > 0x0FFFFFFF, then ASSERT().
600 If Address is not aligned on a 16-bit boundary, then ASSERT().
601 If StartBit is greater than 15, then ASSERT().
602 If EndBit is greater than 15, then ASSERT().
603 If EndBit is less than StartBit, then ASSERT().
604 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
606 @param[in] Address The PCI configuration register to write.
607 @param[in] StartBit The ordinal of the least significant bit in the bit field.
609 @param[in] EndBit The ordinal of the most significant bit in the bit field.
611 @param[in] AndData The value to AND with the PCI configuration register.
613 @return The value written back to the PCI configuration register.
626 Reads a bit field in a 16-bit Address, performs a bitwise AND followed by a
627 bitwise OR, and writes the result back to the bit field in the
628 16-bit port, and saves the value in the S3 script to be replayed on S3 resume.
630 Reads the 16-bit PCI configuration register specified by Address, performs a
631 bitwise AND followed by a bitwise OR between the read result and
632 the value specified by AndData, and writes the result to the 16-bit PCI
633 configuration register specified by Address. The value written to the PCI
634 configuration register is returned. This function must guarantee that all PCI
635 read and write operations are serialized. Extra left bits in both AndData and
638 If Address > 0x0FFFFFFF, then ASSERT().
639 If Address is not aligned on a 16-bit boundary, then ASSERT().
640 If StartBit is greater than 15, then ASSERT().
641 If EndBit is greater than 15, then ASSERT().
642 If EndBit is less than StartBit, then ASSERT().
643 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
644 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
646 @param[in] Address The PCI configuration register to write.
647 @param[in] StartBit The ordinal of the least significant bit in the bit field.
649 @param[in] EndBit The ordinal of the most significant bit in the bit field.
651 @param[in] AndData The value to AND with the PCI configuration register.
652 @param[in] OrData The value to OR with the result of the AND operation.
654 @return The value written back to the PCI configuration register.
659 S3PciBitFieldAndThenOr16 (
668 Reads a 32-bit PCI configuration register, and saves the value in the S3
669 script to be replayed on S3 resume.
671 Reads and returns the 32-bit PCI configuration register specified by Address.
672 This function must guarantee that all PCI read and write operations are
675 If Address > 0x0FFFFFFF, then ASSERT().
676 If Address is not aligned on a 32-bit boundary, then ASSERT().
678 @param[in] Address The address that encodes the PCI Bus, Device, Function and
681 @return The read value from the PCI configuration register.
691 Writes a 32-bit PCI configuration register, and saves the value in the S3
692 script to be replayed on S3 resume.
694 Writes the 32-bit PCI configuration register specified by Address with the
695 value specified by Value. Value is returned. This function must guarantee
696 that all PCI read and write operations are serialized.
698 If Address > 0x0FFFFFFF, then ASSERT().
699 If Address is not aligned on a 32-bit boundary, then ASSERT().
701 @param[in] Address The address that encodes the PCI Bus, Device, Function and
703 @param[in] Value The value to write.
705 @return The value written to the PCI configuration register.
716 Performs a bitwise OR of a 32-bit PCI configuration register with
717 a 32-bit value, and saves the value in the S3 script to be replayed on S3 resume.
719 Reads the 32-bit PCI configuration register specified by Address, performs a
720 bitwise OR between the read result and the value specified by
721 OrData, and writes the result to the 32-bit PCI configuration register
722 specified by Address. The value written to the PCI configuration register is
723 returned. This function must guarantee that all PCI read and write operations
726 If Address > 0x0FFFFFFF, then ASSERT().
727 If Address is not aligned on a 32-bit boundary, then ASSERT().
729 @param[in] Address The address that encodes the PCI Bus, Device, Function and
731 @param[in] OrData The value to OR with the PCI configuration register.
733 @return The value written back to the PCI configuration register.
744 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
745 value, and saves the value in the S3 script to be replayed on S3 resume.
747 Reads the 32-bit PCI configuration register specified by Address, performs a
748 bitwise AND between the read result and the value specified by AndData, and
749 writes the result to the 32-bit PCI configuration register specified by
750 Address. The value written to the PCI configuration register is returned.
751 This function must guarantee that all PCI read and write operations are
754 If Address > 0x0FFFFFFF, then ASSERT().
755 If Address is not aligned on a 32-bit boundary, then ASSERT().
757 @param[in] Address The address that encodes the PCI Bus, Device, Function and
759 @param[in] AndData The value to AND with the PCI configuration register.
761 @return The value written back to the PCI configuration register.
772 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
773 value, followed a bitwise OR with another 32-bit value, and saves
774 the value in the S3 script to be replayed on S3 resume.
776 Reads the 32-bit PCI configuration register specified by Address, performs a
777 bitwise AND between the read result and the value specified by AndData,
778 performs a bitwise OR between the result of the AND operation and
779 the value specified by OrData, and writes the result to the 32-bit PCI
780 configuration register specified by Address. The value written to the PCI
781 configuration register is returned. This function must guarantee that all PCI
782 read and write operations are serialized.
784 If Address > 0x0FFFFFFF, then ASSERT().
785 If Address is not aligned on a 32-bit boundary, then ASSERT().
787 @param[in] Address The address that encodes the PCI Bus, Device, Function and
789 @param[in] AndData The value to AND with the PCI configuration register.
790 @param[in] OrData The value to OR with the result of the AND operation.
792 @return The value written back to the PCI configuration register.
804 Reads a bit field of a PCI configuration register, and saves the value in
805 the S3 script to be replayed on S3 resume.
807 Reads the bit field in a 32-bit PCI configuration register. The bit field is
808 specified by the StartBit and the EndBit. The value of the bit field is
811 If Address > 0x0FFFFFFF, then ASSERT().
812 If Address is not aligned on a 32-bit boundary, then ASSERT().
813 If StartBit is greater than 31, then ASSERT().
814 If EndBit is greater than 31, then ASSERT().
815 If EndBit is less than StartBit, then ASSERT().
817 @param[in] Address The PCI configuration register to read.
818 @param[in] StartBit The ordinal of the least significant bit in the bit field.
820 @param[in] EndBit The ordinal of the most significant bit in the bit field.
823 @return The value of the bit field read from the PCI configuration register.
828 S3PciBitFieldRead32 (
835 Writes a bit field to a PCI configuration register, and saves the value in
836 the S3 script to be replayed on S3 resume.
838 Writes Value to the bit field of the PCI configuration register. The bit
839 field is specified by the StartBit and the EndBit. All other bits in the
840 destination PCI configuration register are preserved. The new value of the
841 32-bit register is returned.
843 If Address > 0x0FFFFFFF, then ASSERT().
844 If Address is not aligned on a 32-bit boundary, then ASSERT().
845 If StartBit is greater than 31, then ASSERT().
846 If EndBit is greater than 31, then ASSERT().
847 If EndBit is less than StartBit, then ASSERT().
848 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
850 @param[in] Address The PCI configuration register to write.
851 @param[in] StartBit The ordinal of the least significant bit in the bit field.
853 @param[in] EndBit The ordinal of the most significant bit in the bit field.
855 @param[in] Value New value of the bit field.
857 @return The value written back to the PCI configuration register.
862 S3PciBitFieldWrite32 (
870 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
871 writes the result back to the bit field in the 32-bit port, and saves the value
872 in the S3 script to be replayed on S3 resume.
874 Reads the 32-bit PCI configuration register specified by Address, performs a
875 bitwise OR between the read result and the value specified by
876 OrData, and writes the result to the 32-bit PCI configuration register
877 specified by Address. The value written to the PCI configuration register is
878 returned. This function must guarantee that all PCI read and write operations
879 are serialized. Extra left bits in OrData are stripped.
881 If Address > 0x0FFFFFFF, then ASSERT().
882 If Address is not aligned on a 32-bit boundary, then ASSERT().
883 If StartBit is greater than 31, then ASSERT().
884 If EndBit is greater than 31, then ASSERT().
885 If EndBit is less than StartBit, then ASSERT().
886 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
888 @param[in] Address The PCI configuration register to write.
889 @param[in] StartBit The ordinal of the least significant bit in the bit field.
891 @param[in] EndBit The ordinal of the most significant bit in the bit field.
893 @param[in] OrData The value to OR with the PCI configuration register.
895 @return The value written back to the PCI configuration register.
908 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
909 AND, and writes the result back to the bit field in the 32-bit register and
910 saves the value in the S3 script to be replayed on S3 resume.
912 Reads the 32-bit PCI configuration register specified by Address, performs a
913 bitwise AND between the read result and the value specified by AndData, and
914 writes the result to the 32-bit PCI configuration register specified by
915 Address. The value written to the PCI configuration register is returned.
916 This function must guarantee that all PCI read and write operations are
917 serialized. Extra left bits in AndData are stripped.
919 If Address > 0x0FFFFFFF, then ASSERT().
920 If Address is not aligned on a 32-bit boundary, then ASSERT().
921 If StartBit is greater than 31, then ASSERT().
922 If EndBit is greater than 31, then ASSERT().
923 If EndBit is less than StartBit, then ASSERT().
924 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
926 @param[in] Address The PCI configuration register to write.
927 @param[in] StartBit The ordinal of the least significant bit in the bit field.
929 @param[in] EndBit The ordinal of the most significant bit in the bit field.
931 @param[in] AndData The value to AND with the PCI configuration register.
933 @return The value written back to the PCI configuration register.
946 Reads a bit field in a 32-bit Address, performs a bitwise AND followed by a
947 bitwise OR, and writes the result back to the bit field in the
948 32-bit port, and saves the value in the S3 script to be replayed on S3 resume.
950 Reads the 32-bit PCI configuration register specified by Address, performs a
951 bitwise AND followed by a bitwise OR between the read result and
952 the value specified by AndData, and writes the result to the 32-bit PCI
953 configuration register specified by Address. The value written to the PCI
954 configuration register is returned. This function must guarantee that all PCI
955 read and write operations are serialized. Extra left bits in both AndData and
958 If Address > 0x0FFFFFFF, then ASSERT().
959 If Address is not aligned on a 32-bit boundary, then ASSERT().
960 If StartBit is greater than 31, then ASSERT().
961 If EndBit is greater than 31, then ASSERT().
962 If EndBit is less than StartBit, then ASSERT().
963 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
964 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
966 @param[in] Address The PCI configuration register to write.
967 @param[in] StartBit The ordinal of the least significant bit in the bit field.
969 @param[in] EndBit The ordinal of the most significant bit in the bit field.
971 @param[in] AndData The value to AND with the PCI configuration register.
972 @param[in] OrData The value to OR with the result of the AND operation.
974 @return The value written back to the PCI configuration register.
979 S3PciBitFieldAndThenOr32 (
988 Reads a range of PCI configuration registers into a caller supplied buffer,
989 and saves the value in the S3 script to be replayed on S3 resume.
991 Reads the range of PCI configuration registers specified by StartAddress and
992 Size into the buffer specified by Buffer. This function only allows the PCI
993 configuration registers from a single PCI function to be read. Size is
994 returned. When possible 32-bit PCI configuration read cycles are used to read
995 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
996 and 16-bit PCI configuration read cycles may be used at the beginning and the
999 If StartAddress > 0x0FFFFFFF, then ASSERT().
1000 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1001 If Size > 0 and Buffer is NULL, then ASSERT().
1003 @param[in] StartAddress Starting address that encodes the PCI Bus, Device,
1004 Function and Register.
1005 @param[in] Size Size in bytes of the transfer.
1006 @param[out] Buffer The pointer to a buffer receiving the data read.
1014 IN UINTN StartAddress
,
1020 Copies the data in a caller supplied buffer to a specified range of PCI
1021 configuration space, and saves the value in the S3 script to be replayed on S3
1024 Writes the range of PCI configuration registers specified by StartAddress and
1025 Size from the buffer specified by Buffer. This function only allows the PCI
1026 configuration registers from a single PCI function to be written. Size is
1027 returned. When possible 32-bit PCI configuration write cycles are used to
1028 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1029 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1030 and the end of the range.
1032 If StartAddress > 0x0FFFFFFF, then ASSERT().
1033 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1034 If Size > 0 and Buffer is NULL, then ASSERT().
1036 @param[in] StartAddress Starting address that encodes the PCI Bus, Device,
1037 Function and Register.
1038 @param[in] Size Size in bytes of the transfer.
1039 @param[in] Buffer The pointer to a buffer containing the data to write.
1047 IN UINTN StartAddress
,